Index: sys/mips/atheros/ar531x/ar5315_machdep.c
===================================================================
--- sys/mips/atheros/ar531x/ar5315_machdep.c
+++ sys/mips/atheros/ar531x/ar5315_machdep.c
@@ -146,6 +146,8 @@
 	   "Board revision");
 #endif
 
+extern char cpu_model[];
+
 void
 platform_start(__register_t a0 __unused, __register_t a1 __unused, 
     __register_t a2 __unused, __register_t a3 __unused)
@@ -260,6 +262,8 @@
 	printf("  a2 = %08x\n", a2);
 	printf("  a3 = %08x\n", a3);
 
+	strcpy(cpu_model, ar5315_get_system_type());
+
 	/*
 	 * XXX this code is very redboot specific.
 	 */
Index: sys/mips/mediatek/mtk_machdep.c
===================================================================
--- sys/mips/mediatek/mtk_machdep.c
+++ sys/mips/mediatek/mtk_machdep.c
@@ -245,6 +245,8 @@
 
 	init_static_kenv(boot1_env, sizeof(boot1_env));
 
+	mtk_soc_set_cpu_model();
+
 	/*
 	 * Get bsdbootargs from FDT if specified.
 	 */
Index: sys/mips/mediatek/mtk_soc.h
===================================================================
--- sys/mips/mediatek/mtk_soc.h
+++ sys/mips/mediatek/mtk_soc.h
@@ -121,6 +121,7 @@
 #define MTK_MT7621_BASE		0x1e000000
 #define MTK_DEFAULT_SIZE	0x6000
 
+extern void     mtk_soc_set_cpu_model(void);
 extern void     mtk_soc_try_early_detect(void);
 extern uint32_t mtk_soc_get_uartclk(void);
 extern uint32_t mtk_soc_get_cpuclk(void);
Index: sys/mips/mediatek/mtk_soc.c
===================================================================
--- sys/mips/mediatek/mtk_soc.c
+++ sys/mips/mediatek/mtk_soc.c
@@ -47,6 +47,8 @@
 #include <mips/mediatek/mtk_sysctl.h>
 #include <mips/mediatek/mtk_soc.h>
 
+extern char    cpu_model[];
+
 static uint32_t mtk_soc_socid = MTK_SOC_UNKNOWN;
 static uint32_t mtk_soc_uartclk = 0;
 static uint32_t mtk_soc_cpuclk = MTK_CPU_CLK_880MHZ;
@@ -77,6 +79,34 @@
 	{ NULL,				MTK_SOC_UNKNOWN },
 };
 
+void
+mtk_soc_set_cpu_model(void)
+{
+	bus_space_tag_t bst;
+	bus_space_handle_t bsh;
+	uint32_t base;
+	uint32_t chipid0, chipid1;
+
+	bst = fdtbus_bs_tag;
+	if (mtk_soc_socid == MTK_SOC_RT2880)
+		base = MTK_RT2880_BASE;
+	else if (mtk_soc_socid == MTK_SOC_MT7621)
+		base = MTK_MT7621_BASE;
+	else
+		base = MTK_DEFAULT_BASE;
+
+	if (bus_space_map(bst, base, MTK_DEFAULT_SIZE, 0, &bsh))
+		return;
+
+	/* First, figure out the CPU clock */
+	chipid0 = bus_space_read_4(bst, bsh, SYSCTL_CHIPID0_3);
+	chipid1 = bus_space_read_4(bst, bsh, SYSCTL_CHIPID4_7);
+
+	*((uint32_t *)cpu_model) = chipid0;
+	*((uint32_t *)cpu_model + 1) = chipid1;
+	cpu_model[8] = '\0';
+}
+
 static uint32_t
 mtk_detect_cpuclk_rt2880(bus_space_tag_t bst, bus_space_handle_t bsh)
 {
Index: sys/mips/mips/machdep.c
===================================================================
--- sys/mips/mips/machdep.c
+++ sys/mips/mips/machdep.c
@@ -186,6 +186,8 @@
 	if (boothowto & RB_VERBOSE)
 		bootverbose++;
 
+	printf("CPU model: %s\n", cpu_model);
+
 	printf("real memory  = %ju (%juK bytes)\n", ptoa((uintmax_t)realmem),
 	    ptoa((uintmax_t)realmem) / 1024);