Index: sys/dev/drm2/drm_pciids.h
===================================================================
--- sys/dev/drm2/drm_pciids.h
+++ sys/dev/drm2/drm_pciids.h
@@ -48,13 +48,6 @@
 	{0x8086, 0x0162, CHIP_I9XX|CHIP_I915, "Intel IvyBridge"}, \
 	{0x8086, 0x0166, CHIP_I9XX|CHIP_I915, "Intel IvyBridge (M)"}, \
 	{0x8086, 0x016A, CHIP_I9XX|CHIP_I915, "Intel IvyBridge (S)"}, \
-	{0x8086, 0x0402, CHIP_I9XX|CHIP_I915, "Intel Haswell"}, \
-	{0x8086, 0x0412, CHIP_I9XX|CHIP_I915, "Intel Haswell"}, \
-	{0x8086, 0x040a, CHIP_I9XX|CHIP_I915, "Intel Haswell (S)"}, \
-	{0x8086, 0x041a, CHIP_I9XX|CHIP_I915, "Intel Haswell (S)"}, \
-	{0x8086, 0x0406, CHIP_I9XX|CHIP_I915, "Intel Haswell (M)"}, \
-	{0x8086, 0x0416, CHIP_I9XX|CHIP_I915, "Intel Haswell (M)"}, \
-	{0x8086, 0x0c16, CHIP_I9XX|CHIP_I915, "Intel Haswell (SDV)"}, \
 	{0x8086, 0x2562, CHIP_I8XX, "Intel i845G GMCH"}, \
 	{0x8086, 0x2572, CHIP_I8XX, "Intel i865G GMCH"}, \
 	{0x8086, 0x2582, CHIP_I9XX|CHIP_I915, "Intel i915G"}, \
@@ -86,6 +79,15 @@
 	{0x8086, 0xA011, CHIP_I9XX|CHIP_I965, "Intel Pineview (M)"}, \
 	{0, 0, 0, NULL}
 
+#define i915_HASWELL_PCI_IDS \
+	{0x8086, 0x0402, CHIP_I9XX|CHIP_I915, "Intel Haswell"}, \
+	{0x8086, 0x0412, CHIP_I9XX|CHIP_I915, "Intel Haswell"}, \
+	{0x8086, 0x040a, CHIP_I9XX|CHIP_I915, "Intel Haswell (S)"}, \
+	{0x8086, 0x041a, CHIP_I9XX|CHIP_I915, "Intel Haswell (S)"}, \
+	{0x8086, 0x0406, CHIP_I9XX|CHIP_I915, "Intel Haswell (M)"}, \
+	{0x8086, 0x0416, CHIP_I9XX|CHIP_I915, "Intel Haswell (M)"}, \
+	{0x8086, 0x0c16, CHIP_I9XX|CHIP_I915, "Intel Haswell (SDV)"}
+
 #define imagine_PCI_IDS \
 	{0x105D, 0x2309, IMAGINE_128, "Imagine 128"}, \
 	{0x105D, 0x2339, IMAGINE_128_2, "Imagine 128-II"}, \
Index: sys/dev/drm2/i915/i915_drv.c
===================================================================
--- sys/dev/drm2/i915/i915_drv.c
+++ sys/dev/drm2/i915/i915_drv.c
@@ -42,10 +42,17 @@
 
 #include "fb_if.h"
 
+/* For the drm.i915.enable_haswell tunable. Disable by default. */
+int i915_enable_haswell = 0;
+
 /* drv_PCI_IDs comes from drm_pciids.h, generated from drm_pciids.txt. */
 static drm_pci_id_list_t i915_pciidlist[] = {
 	i915_PCI_IDS
 };
+static drm_pci_id_list_t i915_haswell_pciidlist[] = {
+	i915_HASWELL_PCI_IDS,
+	i915_PCI_IDS
+};
 
 static const struct intel_device_info intel_i830_info = {
 	.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
@@ -413,8 +420,14 @@
 static int
 i915_probe(device_t kdev)
 {
+	drm_pci_id_list_t *list;
 
-	return drm_probe(kdev, i915_pciidlist);
+	if (i915_enable_haswell)
+		list = i915_haswell_pciidlist;
+	else
+		list = i915_pciidlist;
+
+	return drm_probe(kdev, list);
 }
 
 int i915_modeset;
@@ -423,12 +436,18 @@
 i915_attach(device_t kdev)
 {
 	struct drm_device *dev;
+	drm_pci_id_list_t *list;
+
+	if (i915_enable_haswell)
+		list = i915_haswell_pciidlist;
+	else
+		list = i915_pciidlist;
 
 	dev = device_get_softc(kdev);
 	if (i915_modeset == 1)
 		i915_driver_info.driver_features |= DRIVER_MODESET;
 	dev->driver = &i915_driver_info;
-	return (drm_attach(kdev, i915_pciidlist));
+	return (drm_attach(kdev, list));
 }
 
 static struct fb_info *
@@ -527,6 +546,7 @@
 TUNABLE_INT("drm.i915.enable_ppgtt", &i915_enable_ppgtt);
 int i915_enable_hangcheck = 1;
 TUNABLE_INT("drm.i915.enable_hangcheck", &i915_enable_hangcheck);
+TUNABLE_INT("drm.i915.enable_haswell", &i915_enable_haswell);
 
 #define	PCI_VENDOR_INTEL		0x8086
 #define INTEL_PCH_DEVICE_ID_MASK	0xff00