Index: lib/libc/gen/getosreldate.3 =================================================================== --- lib/libc/gen/getosreldate.3 +++ lib/libc/gen/getosreldate.3 @@ -24,7 +24,7 @@ .\" .\" $FreeBSD$ .\" -.Dd September 30, 2008 +.Dd June 13, 2018 .Dt GETOSRELDATE 3 .Os .Sh NAME @@ -45,9 +45,9 @@ .Fx kernel. Definitions of the values can be found in -.%B "The Porter's Handbook" -which is usually installed at -.Pa /usr/share/doc/en_US.ISO8859-1/books/porters-handbook/ . +.%B "The Porter's Handbook": +.Pp +.Lk https://www.FreeBSD.org/doc/en/books/porters-handbook/ .Sh RETURN VALUES Upon successful completion, .Fn getosreldate @@ -77,7 +77,6 @@ .Sh SEE ALSO .Rs .%B "The Porter's Handbook" -.%O /usr/share/doc/en_US.ISO8859-1/books/porters\-handbook/ .Re .Sh HISTORY The Index: lib/libvmmapi/vmmapi.c =================================================================== --- lib/libvmmapi/vmmapi.c +++ lib/libvmmapi/vmmapi.c @@ -85,19 +85,19 @@ static int vm_device_open(const char *name) { - int fd, len; - char *vmfile; + int fd, len; + char *vmfile; len = strlen("/dev/vmm/") + strlen(name) + 1; vmfile = malloc(len); assert(vmfile != NULL); snprintf(vmfile, len, "/dev/vmm/%s", name); - /* Open the device file */ - fd = open(vmfile, O_RDWR, 0); + /* Open the device file */ + fd = open(vmfile, O_RDWR, 0); free(vmfile); - return (fd); + return (fd); } int @@ -876,7 +876,7 @@ vmcap.cpuid = vcpu; vmcap.captype = cap; vmcap.capval = val; - + return (ioctl(ctx->fd, VM_SET_CAPABILITY, &vmcap)); } @@ -1580,4 +1580,3 @@ *len = nitems(vm_ioctl_cmds); return (NULL); } - Index: sbin/Makefile =================================================================== --- sbin/Makefile +++ sbin/Makefile @@ -82,6 +82,7 @@ SUBDIR.${MK_ISCSI}+= iscontrol SUBDIR.${MK_NAND}+= nandfs SUBDIR.${MK_NAND}+= newfs_nandfs +SUBDIR.${MK_NVME}+= nvmecontrol SUBDIR.${MK_OPENSSL}+= decryptcore SUBDIR.${MK_PF}+= pfctl SUBDIR.${MK_PF}+= pflogd Index: sbin/Makefile.amd64 =================================================================== --- sbin/Makefile.amd64 +++ sbin/Makefile.amd64 @@ -2,4 +2,3 @@ SUBDIR += bsdlabel SUBDIR += fdisk -SUBDIR += nvmecontrol Index: sbin/Makefile.i386 =================================================================== --- sbin/Makefile.i386 +++ sbin/Makefile.i386 @@ -2,5 +2,4 @@ SUBDIR += bsdlabel SUBDIR += fdisk -SUBDIR += nvmecontrol SUBDIR += sconfig Index: sbin/Makefile.powerpc64 =================================================================== --- sbin/Makefile.powerpc64 +++ sbin/Makefile.powerpc64 @@ -2,4 +2,3 @@ SUBDIR += bsdlabel SUBDIR += fdisk -SUBDIR += nvmecontrol Index: sbin/camcontrol/Makefile =================================================================== --- sbin/camcontrol/Makefile +++ sbin/camcontrol/Makefile @@ -1,5 +1,7 @@ # $FreeBSD$ +.include + PACKAGE=runtime PROG= camcontrol SRCS= camcontrol.c util.c @@ -8,6 +10,13 @@ .else CFLAGS+= -DMINIMALISTIC .endif +.if ${MK_NVME} != "no" +.PATH: ${SRCTOP}/sbin/nvmecontrol +CFLAGS+= -I${SRCTOP}/sbin/nvmecontrol -DWITH_NVME +SRCS+= identify_ext.c nc_util.c +.PATH: ${SRCTOP}/sys/dev/nvme +SRCS+= nvme_util.c +.endif # This is verboten .if ${MACHINE_CPUARCH} == "arm" WARNS?= 3 Index: sbin/camcontrol/camcontrol.c =================================================================== --- sbin/camcontrol/camcontrol.c +++ sbin/camcontrol/camcontrol.c @@ -63,6 +63,9 @@ #include #include #include "camcontrol.h" +#ifdef WITH_NVME +#include "nvmecontrol_ext.h" +#endif typedef enum { CAM_CMD_NONE = 0x00000000, @@ -280,7 +283,9 @@ static int print_dev_semb(struct device_match_result *dev_result, char *tmpstr); static int print_dev_mmcsd(struct device_match_result *dev_result, char *tmpstr); +#ifdef WITH_NVME static int print_dev_nvme(struct device_match_result *dev_result, char *tmpstr); +#endif #ifndef MINIMALISTIC static int testunitready(struct cam_device *device, int task_attr, int retry_count, int timeout, int quiet); @@ -601,12 +606,14 @@ skip_device = 1; break; } +#ifdef WITH_NVME } else if (dev_result->protocol == PROTO_NVME) { if (print_dev_nvme(dev_result, &tmpstr[0]) != 0) { skip_device = 1; break; } +#endif } else { sprintf(tmpstr, "<>"); } @@ -762,22 +769,13 @@ return (0); } +#ifdef WITH_NVME static int -print_dev_nvme(struct device_match_result *dev_result, char *tmpstr) +nvme_get_cdata(struct cam_device *dev, struct nvme_controller_data *cdata) { union ccb *ccb; struct ccb_dev_advinfo *advi; - struct cam_device *dev; - struct nvme_controller_data cdata; - char vendor[64], product[64]; - dev = cam_open_btl(dev_result->path_id, dev_result->target_id, - dev_result->target_lun, O_RDWR, NULL); - if (dev == NULL) { - warnx("%s", cam_errbuf); - return (1); - } - ccb = cam_getccb(dev); if (ccb == NULL) { warnx("couldn't allocate CCB"); @@ -791,7 +789,7 @@ advi->flags = CDAI_FLAG_NONE; advi->buftype = CDAI_TYPE_NVME_CNTRL; advi->bufsiz = sizeof(struct nvme_controller_data); - advi->buf = (uint8_t *)&cdata; + advi->buf = (uint8_t *)cdata; if (cam_send_ccb(dev, ccb) < 0) { warn("error sending CAMIOCOMMAND ioctl"); @@ -805,14 +803,35 @@ cam_close_device(dev); return(1); } + cam_freeccb(ccb); + return 0; +} + +static int +print_dev_nvme(struct device_match_result *dev_result, char *tmpstr) +{ + struct cam_device *dev; + struct nvme_controller_data cdata; + char vendor[64], product[64]; + + dev = cam_open_btl(dev_result->path_id, dev_result->target_id, + dev_result->target_lun, O_RDWR, NULL); + if (dev == NULL) { + warnx("%s", cam_errbuf); + return (1); + } + + if (nvme_get_cdata(dev, &cdata)) + return (1); + cam_strvis(vendor, cdata.mn, sizeof(cdata.mn), sizeof(vendor)); cam_strvis(product, cdata.fr, sizeof(cdata.fr), sizeof(product)); sprintf(tmpstr, "<%s %s>", vendor, product); - cam_freeccb(ccb); cam_close_device(dev); return (0); } +#endif #ifndef MINIMALISTIC static int @@ -2390,6 +2409,38 @@ return (0); } + +#ifdef WITH_NVME +static int +nvmeidentify(struct cam_device *device, int retry_count __unused, int timeout __unused) +{ + struct nvme_controller_data cdata; + + if (nvme_get_cdata(device, &cdata)) + return (1); + nvme_print_controller(&cdata); + + return (0); +} +#endif + +static int +identify(struct cam_device *device, int retry_count, int timeout) +{ +#ifdef WITH_NVME + struct ccb_pathinq cpi; + + if (get_cpi(device, &cpi) != 0) { + warnx("couldn't get CPI"); + return (-1); + } + + if (cpi.protocol == PROTO_NVME) { + return (nvmeidentify(device, retry_count, timeout)); + } +#endif + return (ataidentify(device, retry_count, timeout)); +} #endif /* MINIMALISTIC */ @@ -5167,6 +5218,7 @@ "enabled" : "disabled"); } } +#ifdef WITH_NVME if (cts->protocol == PROTO_NVME) { struct ccb_trans_settings_nvme *nvmex = &cts->xport_specific.nvme; @@ -5183,6 +5235,7 @@ nvmex->speed, nvmex->max_speed); } } +#endif } /* @@ -10058,7 +10111,7 @@ task_attr, retry_count, timeout); break; case CAM_CMD_IDENTIFY: - error = ataidentify(cam_dev, retry_count, timeout); + error = identify(cam_dev, retry_count, timeout); break; case CAM_CMD_STARTSTOP: error = scsistart(cam_dev, arglist & CAM_ARG_START_UNIT, Index: sbin/nvmecontrol/Makefile =================================================================== --- sbin/nvmecontrol/Makefile +++ sbin/nvmecontrol/Makefile @@ -2,8 +2,8 @@ PACKAGE=runtime PROG= nvmecontrol -SRCS= nvmecontrol.c devlist.c firmware.c format.c identify.c logpage.c \ - perftest.c reset.c ns.c nvme_util.c power.c util.c wdc.c +SRCS= nvmecontrol.c devlist.c firmware.c format.c identify.c identify_ext.c logpage.c \ + perftest.c reset.c ns.c nvme_util.c power.c nc_util.c wdc.c MAN= nvmecontrol.8 .PATH: ${SRCTOP}/sys/dev/nvme Index: sbin/nvmecontrol/identify.c =================================================================== --- sbin/nvmecontrol/identify.c +++ sbin/nvmecontrol/identify.c @@ -41,185 +41,7 @@ #include #include "nvmecontrol.h" - -static void -print_controller(struct nvme_controller_data *cdata) -{ - uint8_t str[128]; - char cbuf[UINT128_DIG + 1]; - uint16_t oncs, oacs; - uint8_t compare, write_unc, dsm, vwc_present; - uint8_t security, fmt, fw, nsmgmt; - uint8_t fw_slot1_ro, fw_num_slots; - uint8_t ns_smart; - uint8_t sqes_max, sqes_min; - uint8_t cqes_max, cqes_min; - - oncs = cdata->oncs; - compare = (oncs >> NVME_CTRLR_DATA_ONCS_COMPARE_SHIFT) & - NVME_CTRLR_DATA_ONCS_COMPARE_MASK; - write_unc = (oncs >> NVME_CTRLR_DATA_ONCS_WRITE_UNC_SHIFT) & - NVME_CTRLR_DATA_ONCS_WRITE_UNC_MASK; - dsm = (oncs >> NVME_CTRLR_DATA_ONCS_DSM_SHIFT) & - NVME_CTRLR_DATA_ONCS_DSM_MASK; - vwc_present = (cdata->vwc >> NVME_CTRLR_DATA_VWC_PRESENT_SHIFT) & - NVME_CTRLR_DATA_VWC_PRESENT_MASK; - - oacs = cdata->oacs; - security = (oacs >> NVME_CTRLR_DATA_OACS_SECURITY_SHIFT) & - NVME_CTRLR_DATA_OACS_SECURITY_MASK; - fmt = (oacs >> NVME_CTRLR_DATA_OACS_FORMAT_SHIFT) & - NVME_CTRLR_DATA_OACS_FORMAT_MASK; - fw = (oacs >> NVME_CTRLR_DATA_OACS_FIRMWARE_SHIFT) & - NVME_CTRLR_DATA_OACS_FIRMWARE_MASK; - nsmgmt = (oacs >> NVME_CTRLR_DATA_OACS_NSMGMT_SHIFT) & - NVME_CTRLR_DATA_OACS_NSMGMT_MASK; - - fw_num_slots = (cdata->frmw >> NVME_CTRLR_DATA_FRMW_NUM_SLOTS_SHIFT) & - NVME_CTRLR_DATA_FRMW_NUM_SLOTS_MASK; - fw_slot1_ro = (cdata->frmw >> NVME_CTRLR_DATA_FRMW_SLOT1_RO_SHIFT) & - NVME_CTRLR_DATA_FRMW_SLOT1_RO_MASK; - - ns_smart = (cdata->lpa >> NVME_CTRLR_DATA_LPA_NS_SMART_SHIFT) & - NVME_CTRLR_DATA_LPA_NS_SMART_MASK; - - sqes_min = (cdata->sqes >> NVME_CTRLR_DATA_SQES_MIN_SHIFT) & - NVME_CTRLR_DATA_SQES_MIN_MASK; - sqes_max = (cdata->sqes >> NVME_CTRLR_DATA_SQES_MAX_SHIFT) & - NVME_CTRLR_DATA_SQES_MAX_MASK; - - cqes_min = (cdata->cqes >> NVME_CTRLR_DATA_CQES_MIN_SHIFT) & - NVME_CTRLR_DATA_CQES_MIN_MASK; - cqes_max = (cdata->cqes >> NVME_CTRLR_DATA_CQES_MAX_SHIFT) & - NVME_CTRLR_DATA_CQES_MAX_MASK; - - printf("Controller Capabilities/Features\n"); - printf("================================\n"); - printf("Vendor ID: %04x\n", cdata->vid); - printf("Subsystem Vendor ID: %04x\n", cdata->ssvid); - nvme_strvis(str, cdata->sn, sizeof(str), NVME_SERIAL_NUMBER_LENGTH); - printf("Serial Number: %s\n", str); - nvme_strvis(str, cdata->mn, sizeof(str), NVME_MODEL_NUMBER_LENGTH); - printf("Model Number: %s\n", str); - nvme_strvis(str, cdata->fr, sizeof(str), NVME_FIRMWARE_REVISION_LENGTH); - printf("Firmware Version: %s\n", str); - printf("Recommended Arb Burst: %d\n", cdata->rab); - printf("IEEE OUI Identifier: %02x %02x %02x\n", - cdata->ieee[0], cdata->ieee[1], cdata->ieee[2]); - printf("Multi-Path I/O Capabilities: %s%s%s%s\n", - (cdata->mic == 0) ? "Not Supported" : "", - ((cdata->mic >> NVME_CTRLR_DATA_MIC_SRIOVVF_SHIFT) & - NVME_CTRLR_DATA_MIC_SRIOVVF_MASK) ? "SR-IOV VF, " : "", - ((cdata->mic >> NVME_CTRLR_DATA_MIC_MCTRLRS_SHIFT) & - NVME_CTRLR_DATA_MIC_MCTRLRS_MASK) ? "Multiple controllers, " : "", - ((cdata->mic >> NVME_CTRLR_DATA_MIC_MPORTS_SHIFT) & - NVME_CTRLR_DATA_MIC_MPORTS_MASK) ? "Multiple ports" : ""); - /* TODO: Use CAP.MPSMIN to determine true memory page size. */ - printf("Max Data Transfer Size: "); - if (cdata->mdts == 0) - printf("Unlimited\n"); - else - printf("%ld\n", PAGE_SIZE * (1L << cdata->mdts)); - printf("Controller ID: 0x%02x\n", cdata->ctrlr_id); - printf("Version: %d.%d.%d\n", - (cdata->ver >> 16) & 0xffff, (cdata->ver >> 8) & 0xff, - cdata->ver & 0xff); - printf("\n"); - - printf("Admin Command Set Attributes\n"); - printf("============================\n"); - printf("Security Send/Receive: %s\n", - security ? "Supported" : "Not Supported"); - printf("Format NVM: %s\n", - fmt ? "Supported" : "Not Supported"); - printf("Firmware Activate/Download: %s\n", - fw ? "Supported" : "Not Supported"); - printf("Namespace Managment: %s\n", - nsmgmt ? "Supported" : "Not Supported"); - printf("Device Self-test: %sSupported\n", - ((oacs >> NVME_CTRLR_DATA_OACS_SELFTEST_SHIFT) & - NVME_CTRLR_DATA_OACS_SELFTEST_MASK) ? "" : "Not "); - printf("Directives: %sSupported\n", - ((oacs >> NVME_CTRLR_DATA_OACS_DIRECTIVES_SHIFT) & - NVME_CTRLR_DATA_OACS_DIRECTIVES_MASK) ? "" : "Not "); - printf("NVMe-MI Send/Receive: %sSupported\n", - ((oacs >> NVME_CTRLR_DATA_OACS_NVMEMI_SHIFT) & - NVME_CTRLR_DATA_OACS_NVMEMI_MASK) ? "" : "Not "); - printf("Virtualization Management: %sSupported\n", - ((oacs >> NVME_CTRLR_DATA_OACS_VM_SHIFT) & - NVME_CTRLR_DATA_OACS_VM_MASK) ? "" : "Not "); - printf("Doorbell Buffer Config %sSupported\n", - ((oacs >> NVME_CTRLR_DATA_OACS_DBBUFFER_SHIFT) & - NVME_CTRLR_DATA_OACS_DBBUFFER_MASK) ? "" : "Not "); - printf("Abort Command Limit: %d\n", cdata->acl+1); - printf("Async Event Request Limit: %d\n", cdata->aerl+1); - printf("Number of Firmware Slots: "); - if (fw != 0) - printf("%d\n", fw_num_slots); - else - printf("N/A\n"); - printf("Firmware Slot 1 Read-Only: "); - if (fw != 0) - printf("%s\n", fw_slot1_ro ? "Yes" : "No"); - else - printf("N/A\n"); - printf("Per-Namespace SMART Log: %s\n", - ns_smart ? "Yes" : "No"); - printf("Error Log Page Entries: %d\n", cdata->elpe+1); - printf("Number of Power States: %d\n", cdata->npss+1); - - printf("\n"); - printf("NVM Command Set Attributes\n"); - printf("==========================\n"); - printf("Submission Queue Entry Size\n"); - printf(" Max: %d\n", 1 << sqes_max); - printf(" Min: %d\n", 1 << sqes_min); - printf("Completion Queue Entry Size\n"); - printf(" Max: %d\n", 1 << cqes_max); - printf(" Min: %d\n", 1 << cqes_min); - printf("Number of Namespaces: %d\n", cdata->nn); - printf("Compare Command: %s\n", - compare ? "Supported" : "Not Supported"); - printf("Write Uncorrectable Command: %s\n", - write_unc ? "Supported" : "Not Supported"); - printf("Dataset Management Command: %s\n", - dsm ? "Supported" : "Not Supported"); - printf("Write Zeroes Command: %sSupported\n", - ((oncs >> NVME_CTRLR_DATA_ONCS_WRZERO_SHIFT) & - NVME_CTRLR_DATA_ONCS_WRZERO_MASK) ? "" : "Not "); - printf("Save Features: %sSupported\n", - ((oncs >> NVME_CTRLR_DATA_ONCS_SAVEFEAT_SHIFT) & - NVME_CTRLR_DATA_ONCS_SAVEFEAT_MASK) ? "" : "Not "); - printf("Reservations: %sSupported\n", - ((oncs >> NVME_CTRLR_DATA_ONCS_RESERV_SHIFT) & - NVME_CTRLR_DATA_ONCS_RESERV_MASK) ? "" : "Not "); - printf("Timestamp feature: %sSupported\n", - ((oncs >> NVME_CTRLR_DATA_ONCS_TIMESTAMP_SHIFT) & - NVME_CTRLR_DATA_ONCS_TIMESTAMP_MASK) ? "" : "Not "); - printf("Fused Operation Support: %s%s\n", - (cdata->fuses == 0) ? "Not Supported" : "", - ((cdata->fuses >> NVME_CTRLR_DATA_FUSES_CNW_SHIFT) & - NVME_CTRLR_DATA_FUSES_CNW_MASK) ? "Compare and Write" : ""); - printf("Format NVM Attributes: %s%s Erase, %s Format\n", - ((cdata->fna >> NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_SHIFT) & - NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_MASK) ? "Crypto Erase, " : "", - ((cdata->fna >> NVME_CTRLR_DATA_FNA_ERASE_ALL_SHIFT) & - NVME_CTRLR_DATA_FNA_ERASE_ALL_MASK) ? "All-NVM" : "Per-NS", - ((cdata->fna >> NVME_CTRLR_DATA_FNA_FORMAT_ALL_SHIFT) & - NVME_CTRLR_DATA_FNA_FORMAT_ALL_MASK) ? "All-NVM" : "Per-NS"); - printf("Volatile Write Cache: %s\n", - vwc_present ? "Present" : "Not Present"); - - if (nsmgmt) { - printf("\n"); - printf("Namespace Drive Attributes\n"); - printf("==========================\n"); - printf("NVM total cap: %s\n", - uint128_to_str(to128(cdata->untncap.tnvmcap), cbuf, sizeof(cbuf))); - printf("NVM unallocated cap: %s\n", - uint128_to_str(to128(cdata->untncap.unvmcap), cbuf, sizeof(cbuf))); - } -} +#include "nvmecontrol_ext.h" static void print_namespace(struct nvme_namespace_data *nsdata) @@ -375,7 +197,7 @@ identify_usage(); } - print_controller(&cdata); + nvme_print_controller(&cdata); exit(0); } Index: sbin/nvmecontrol/identify_ext.c =================================================================== --- sbin/nvmecontrol/identify_ext.c +++ sbin/nvmecontrol/identify_ext.c @@ -41,9 +41,10 @@ #include #include "nvmecontrol.h" +#include "nvmecontrol_ext.h" -static void -print_controller(struct nvme_controller_data *cdata) +void +nvme_print_controller(struct nvme_controller_data *cdata) { uint8_t str[128]; char cbuf[UINT128_DIG + 1]; @@ -220,254 +221,3 @@ uint128_to_str(to128(cdata->untncap.unvmcap), cbuf, sizeof(cbuf))); } } - -static void -print_namespace(struct nvme_namespace_data *nsdata) -{ - uint32_t i; - uint32_t lbaf, lbads, ms, rp; - uint8_t thin_prov, ptype; - uint8_t flbas_fmt; - - thin_prov = (nsdata->nsfeat >> NVME_NS_DATA_NSFEAT_THIN_PROV_SHIFT) & - NVME_NS_DATA_NSFEAT_THIN_PROV_MASK; - - flbas_fmt = (nsdata->flbas >> NVME_NS_DATA_FLBAS_FORMAT_SHIFT) & - NVME_NS_DATA_FLBAS_FORMAT_MASK; - - printf("Size (in LBAs): %lld (%lldM)\n", - (long long)nsdata->nsze, - (long long)nsdata->nsze / 1024 / 1024); - printf("Capacity (in LBAs): %lld (%lldM)\n", - (long long)nsdata->ncap, - (long long)nsdata->ncap / 1024 / 1024); - printf("Utilization (in LBAs): %lld (%lldM)\n", - (long long)nsdata->nuse, - (long long)nsdata->nuse / 1024 / 1024); - printf("Thin Provisioning: %s\n", - thin_prov ? "Supported" : "Not Supported"); - printf("Number of LBA Formats: %d\n", nsdata->nlbaf+1); - printf("Current LBA Format: LBA Format #%02d\n", flbas_fmt); - printf("Data Protection Caps: %s%s%s%s%s%s\n", - (nsdata->dpc == 0) ? "Not Supported" : "", - ((nsdata->dpc >> NVME_NS_DATA_DPC_MD_END_SHIFT) & - NVME_NS_DATA_DPC_MD_END_MASK) ? "Last Bytes, " : "", - ((nsdata->dpc >> NVME_NS_DATA_DPC_MD_START_SHIFT) & - NVME_NS_DATA_DPC_MD_START_MASK) ? "First Bytes, " : "", - ((nsdata->dpc >> NVME_NS_DATA_DPC_PIT3_SHIFT) & - NVME_NS_DATA_DPC_PIT3_MASK) ? "Type 3, " : "", - ((nsdata->dpc >> NVME_NS_DATA_DPC_PIT2_SHIFT) & - NVME_NS_DATA_DPC_PIT2_MASK) ? "Type 2, " : "", - ((nsdata->dpc >> NVME_NS_DATA_DPC_PIT2_MASK) & - NVME_NS_DATA_DPC_PIT1_MASK) ? "Type 1" : ""); - printf("Data Protection Settings: "); - ptype = (nsdata->dps >> NVME_NS_DATA_DPS_PIT_SHIFT) & - NVME_NS_DATA_DPS_PIT_MASK; - if (ptype) { - printf("Type %d, %s Bytes\n", ptype, - ((nsdata->dps >> NVME_NS_DATA_DPS_MD_START_SHIFT) & - NVME_NS_DATA_DPS_MD_START_MASK) ? "First" : "Last"); - } else { - printf("Not Enabled\n"); - } - printf("Multi-Path I/O Capabilities: %s%s\n", - (nsdata->nmic == 0) ? "Not Supported" : "", - ((nsdata->nmic >> NVME_NS_DATA_NMIC_MAY_BE_SHARED_SHIFT) & - NVME_NS_DATA_NMIC_MAY_BE_SHARED_MASK) ? "May be shared" : ""); - printf("Reservation Capabilities: %s%s%s%s%s%s%s%s%s\n", - (nsdata->rescap == 0) ? "Not Supported" : "", - ((nsdata->rescap >> NVME_NS_DATA_RESCAP_IEKEY13_SHIFT) & - NVME_NS_DATA_RESCAP_IEKEY13_MASK) ? "IEKEY13, " : "", - ((nsdata->rescap >> NVME_NS_DATA_RESCAP_EX_AC_AR_SHIFT) & - NVME_NS_DATA_RESCAP_EX_AC_AR_MASK) ? "EX_AC_AR, " : "", - ((nsdata->rescap >> NVME_NS_DATA_RESCAP_WR_EX_AR_SHIFT) & - NVME_NS_DATA_RESCAP_WR_EX_AR_MASK) ? "WR_EX_AR, " : "", - ((nsdata->rescap >> NVME_NS_DATA_RESCAP_EX_AC_RO_SHIFT) & - NVME_NS_DATA_RESCAP_EX_AC_RO_MASK) ? "EX_AC_RO, " : "", - ((nsdata->rescap >> NVME_NS_DATA_RESCAP_WR_EX_RO_SHIFT) & - NVME_NS_DATA_RESCAP_WR_EX_RO_MASK) ? "WR_EX_RO, " : "", - ((nsdata->rescap >> NVME_NS_DATA_RESCAP_EX_AC_SHIFT) & - NVME_NS_DATA_RESCAP_EX_AC_MASK) ? "EX_AC, " : "", - ((nsdata->rescap >> NVME_NS_DATA_RESCAP_WR_EX_SHIFT) & - NVME_NS_DATA_RESCAP_WR_EX_MASK) ? "WR_EX, " : "", - ((nsdata->rescap >> NVME_NS_DATA_RESCAP_PTPL_SHIFT) & - NVME_NS_DATA_RESCAP_PTPL_MASK) ? "PTPL" : ""); - printf("Format Progress Indicator: "); - if ((nsdata->fpi >> NVME_NS_DATA_FPI_SUPP_SHIFT) & - NVME_NS_DATA_FPI_SUPP_MASK) { - printf("%u%% remains\n", - (nsdata->fpi >> NVME_NS_DATA_FPI_PERC_SHIFT) & - NVME_NS_DATA_FPI_PERC_MASK); - } else - printf("Not Supported\n"); - printf("Optimal I/O Boundary (LBAs): %u\n", nsdata->noiob); - printf("Globally Unique Identifier: "); - for (i = 0; i < sizeof(nsdata->nguid); i++) - printf("%02x", nsdata->nguid[i]); - printf("\n"); - printf("IEEE EUI64: "); - for (i = 0; i < sizeof(nsdata->eui64); i++) - printf("%02x", nsdata->eui64[i]); - printf("\n"); - for (i = 0; i <= nsdata->nlbaf; i++) { - lbaf = nsdata->lbaf[i]; - lbads = (lbaf >> NVME_NS_DATA_LBAF_LBADS_SHIFT) & - NVME_NS_DATA_LBAF_LBADS_MASK; - ms = (lbaf >> NVME_NS_DATA_LBAF_MS_SHIFT) & - NVME_NS_DATA_LBAF_MS_MASK; - rp = (lbaf >> NVME_NS_DATA_LBAF_RP_SHIFT) & - NVME_NS_DATA_LBAF_RP_MASK; - printf("LBA Format #%02d: Data Size: %5d Metadata Size: %5d" - " Performance: %s\n", - i, 1 << lbads, ms, (rp == 0) ? "Best" : - (rp == 1) ? "Better" : (rp == 2) ? "Good" : "Degraded"); - } -} - -static void -identify_usage(void) -{ - fprintf(stderr, "usage:\n"); - fprintf(stderr, IDENTIFY_USAGE); - exit(1); -} - -static void -identify_ctrlr(int argc, char *argv[]) -{ - struct nvme_controller_data cdata; - int ch, fd, hexflag = 0, hexlength; - int verboseflag = 0; - - while ((ch = getopt(argc, argv, "vx")) != -1) { - switch ((char)ch) { - case 'v': - verboseflag = 1; - break; - case 'x': - hexflag = 1; - break; - default: - identify_usage(); - } - } - - /* Check that a controller was specified. */ - if (optind >= argc) - identify_usage(); - - open_dev(argv[optind], &fd, 1, 1); - read_controller_data(fd, &cdata); - close(fd); - - if (hexflag == 1) { - if (verboseflag == 1) - hexlength = sizeof(struct nvme_controller_data); - else - hexlength = offsetof(struct nvme_controller_data, - reserved8); - print_hex(&cdata, hexlength); - exit(0); - } - - if (verboseflag == 1) { - fprintf(stderr, "-v not currently supported without -x\n"); - identify_usage(); - } - - print_controller(&cdata); - exit(0); -} - -static void -identify_ns(int argc, char *argv[]) -{ - struct nvme_namespace_data nsdata; - char path[64]; - int ch, fd, hexflag = 0, hexlength; - int verboseflag = 0; - uint32_t nsid; - - while ((ch = getopt(argc, argv, "vx")) != -1) { - switch ((char)ch) { - case 'v': - verboseflag = 1; - break; - case 'x': - hexflag = 1; - break; - default: - identify_usage(); - } - } - - /* Check that a namespace was specified. */ - if (optind >= argc) - identify_usage(); - - /* - * Check if the specified device node exists before continuing. - * This is a cleaner check for cases where the correct controller - * is specified, but an invalid namespace on that controller. - */ - open_dev(argv[optind], &fd, 1, 1); - close(fd); - - /* - * We send IDENTIFY commands to the controller, not the namespace, - * since it is an admin cmd. The namespace ID will be specified in - * the IDENTIFY command itself. So parse the namespace's device node - * string to get the controller substring and namespace ID. - */ - parse_ns_str(argv[optind], path, &nsid); - open_dev(path, &fd, 1, 1); - read_namespace_data(fd, nsid, &nsdata); - close(fd); - - if (hexflag == 1) { - if (verboseflag == 1) - hexlength = sizeof(struct nvme_namespace_data); - else - hexlength = offsetof(struct nvme_namespace_data, - reserved6); - print_hex(&nsdata, hexlength); - exit(0); - } - - if (verboseflag == 1) { - fprintf(stderr, "-v not currently supported without -x\n"); - identify_usage(); - } - - print_namespace(&nsdata); - exit(0); -} - -void -identify(int argc, char *argv[]) -{ - char *target; - - if (argc < 2) - identify_usage(); - - while (getopt(argc, argv, "vx") != -1) ; - - /* Check that a controller or namespace was specified. */ - if (optind >= argc) - identify_usage(); - - target = argv[optind]; - - optreset = 1; - optind = 1; - - /* - * If device node contains "ns", we consider it a namespace, - * otherwise, consider it a controller. - */ - if (strstr(target, NVME_NS_PREFIX) == NULL) - identify_ctrlr(argc, argv); - else - identify_ns(argc, argv); -} Index: sbin/nvmecontrol/nvmecontrol_ext.h =================================================================== --- sbin/nvmecontrol/nvmecontrol_ext.h +++ sbin/nvmecontrol/nvmecontrol_ext.h @@ -1,8 +1,7 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * - * Copyright (c) 2015 Neel Natu - * All rights reserved. + * Copyright (C) 2018 Netflix * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -13,7 +12,7 @@ * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE @@ -28,13 +27,4 @@ * $FreeBSD$ */ -#ifndef _BOOTROM_H_ -#define _BOOTROM_H_ - -#include - -struct vmctx; - -int bootrom_init(struct vmctx *ctx, const char *romfile); - -#endif +void nvme_print_controller(struct nvme_controller_data *cdata); Index: sbin/nvmecontrol/util.c =================================================================== --- /dev/null +++ sbin/nvmecontrol/util.c @@ -1,59 +0,0 @@ -/*- - * Copyright (c) 2017 Netflix, Inc - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include "nvmecontrol.h" - -char * -uint128_to_str(uint128_t u, char *buf, size_t buflen) -{ - char *end = buf + buflen - 1; - - *end-- = '\0'; - if (u == 0) - *end-- = '0'; - while (u && end >= buf) { - *end-- = u % 10 + '0'; - u /= 10; - } - end++; - if (u != 0) - return NULL; - - return end; -} - -/* "Missing" from endian.h */ -uint64_t -le48dec(const void *pp) -{ - uint8_t const *p = (uint8_t const *)pp; - - return (((uint64_t)le16dec(p + 4) << 32) | le32dec(p)); -} Index: share/man/man4/Makefile =================================================================== --- share/man/man4/Makefile +++ share/man/man4/Makefile @@ -446,6 +446,7 @@ rights.4 \ ${_rk_gpio.4} \ ${_rk_grf.4} \ + ${_rk_i2c.4} \ ${_rk_pinctrl.4} \ rl.4 \ rndtest.4 \ @@ -765,6 +766,7 @@ _armv8crypto.4= armv8crypto.4 _rk_gpio.4= rk_gpio.4 _rk_grf.4= rk_grf.4 +_rk_i2c.4= rk_i2c.4 _rk_pinctrl.4= rk_pinctrl.4 .endif Index: share/man/man4/rk_i2c.4 =================================================================== --- share/man/man4/rk_i2c.4 +++ share/man/man4/rk_i2c.4 @@ -1,5 +1,7 @@ -.\" Copyright (c) 2002 The FreeBSD Project. -.\" All rights reserved. +.\"- +.\" SPDX-License-Identifier: BSD-2-Clause-FreeBSD +.\" +.\" Copyright (c) 2018 Emmanuel Vadot .\" .\" Redistribution and use in source and binary forms, with or without .\" modification, are permitted provided that the following conditions @@ -24,63 +26,39 @@ .\" .\" $FreeBSD$ .\" -.Dd September 30, 2008 -.Dt GETOSRELDATE 3 +.Dd June 14, 2018 +.Dt RK_I2C 4 .Os .Sh NAME -.Nm getosreldate -.Nd get the value of -.Dv __FreeBSD_version -.Sh LIBRARY -.Lb libc +.Nm rk_i2c +.Nd driver for the i2c controller on RockChip SoCs .Sh SYNOPSIS -.In unistd.h -.Ft int -.Fn getosreldate void +.Cd "options SOC_ROCKCHIP_RK3328" .Sh DESCRIPTION The -.Fn getosreldate -function returns an integer showing the version of the -currently running -.Fx -kernel. -Definitions of the values can be found in -.%B "The Porter's Handbook" -which is usually installed at -.Pa /usr/share/doc/en_US.ISO8859-1/books/porters-handbook/ . -.Sh RETURN VALUES -Upon successful completion, -.Fn getosreldate -returns the value requested; -otherwise the value \-1 is returned and the global variable -.Va errno -is set to indicate the error. -.Sh ENVIRONMENT -.Bl -tag -width ".Ev OSVERSION" -.It Ev OSVERSION -If the environment variable -.Ev OSVERSION -is set, it will override the -.Fn getosreldate -return value. +.Nm +device driver provides support for the i2c controller device present +on RockChip SoC. +.Sh HARDWARE +The current version of the +.Nm +driver supports the i2c controller with one of the following +compatible strings : +.Pp +.Bl -bullet -compact +.It +rockchip,rk3328-i2c .El -.Sh EXAMPLES -An example can be found in -.Pa /usr/share/examples/FreeBSD_version . -.Sh ERRORS -The -.Fn getosreldate -function may fail and set -.Va errno -for any of the errors specified for the library function -.Xr sysctl 3 . .Sh SEE ALSO -.Rs -.%B "The Porter's Handbook" -.%O /usr/share/doc/en_US.ISO8859-1/books/porters\-handbook/ -.Re +.Xr iic 4 , +.Xr iicbus 4 , .Sh HISTORY The -.Fn getosreldate -function appeared in -.Fx 2.0 . +.Nm +device driver first appeared in +.Fx 12.0 . +.Sh AUTHORS +The +.Nm +device driver and manpage was written by +.An Emmanuel Vadot Aq Mt manu@freebsd.org . Index: share/man/man7/ports.7 =================================================================== --- share/man/man7/ports.7 +++ share/man/man7/ports.7 @@ -25,7 +25,7 @@ .\" .\" $FreeBSD$ .\" -.Dd June 6, 2014 +.Dd June 13, 2018 .Dt PORTS 7 .Os .Sh NAME @@ -37,6 +37,8 @@ Ports Collection offers a simple way for users and administrators to install applications. +It is also used to build the packages, to be installed using +.Xr pkg 8 . Each .Em port contains any patches necessary to make the original @@ -56,18 +58,17 @@ .Nm make Cm install to install the application. .Pp -For more information about using ports, see -.Dq "Packages and Ports" +For more information about using ports, see the +.Dq "Packages and Ports" section in -.%B "The FreeBSD Handbook" , -.Pa ( file:/usr/share/doc/en_US.ISO8859-1/books/handbook/ports.html -or -.Pa https://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/ports.html ) . -For information about creating new ports, see -.%B "The Porter's Handbook" -.Pa ( file:/usr/share/doc/en_US.ISO8859-1/books/porters-handbook/index.html -or -.Pa https://www.FreeBSD.org/doc/en_US.ISO8859-1/books/porters-handbook/ ) . +.%B "The FreeBSD Handbook": +.Pp +.Lk https://www.FreeBSD.org/doc/en/books/handbook/ports.html +.Pp +For information about creating new ports, see: +.%B "The Porter's Handbook": +.Pp +.Lk https://www.FreeBSD.org/doc/en/books/porters-handbook/ .Sh TARGETS Some of the targets work recursively through subdirectories. This lets you, for example, install all of the Index: share/man/man9/malloc.9 =================================================================== --- share/man/man9/malloc.9 +++ share/man/man9/malloc.9 @@ -29,7 +29,7 @@ .\" $NetBSD: malloc.9,v 1.3 1996/11/11 00:05:11 lukem Exp $ .\" $FreeBSD$ .\" -.Dd January 24, 2018 +.Dd June 13, 2018 .Dt MALLOC 9 .Os .Sh NAME @@ -189,6 +189,11 @@ .Dv M_NOWAIT when an allocation failure cannot be tolerated by the caller without catastrophic effects on the system. +.It Dv M_EXEC +Indicates that the system should allocate executable memory. +If this flag is not set, the system will not allocate executable memory. +Not all platforms enforce a distinction between executable and +non-executable memory. .El .Pp Exactly one of either Index: share/man/man9/zone.9 =================================================================== --- share/man/man9/zone.9 +++ share/man/man9/zone.9 @@ -25,7 +25,7 @@ .\" .\" $FreeBSD$ .\" -.Dd April 26, 2017 +.Dd June 13, 2018 .Dt ZONE 9 .Os .Sh NAME @@ -375,6 +375,15 @@ and .Dv M_NOWAIT was specified. +.Sh IMPLEMENTATION NOTES +The memory that these allocation calls return is not executable. +The +.Fn uma_zalloc +function does not support the +.Dv M_EXEC +flag to allocate executable memory. +Not all platforms enforce a distinction between executable and +non-executable memory. .Sh SEE ALSO .Xr malloc 9 .Sh HISTORY Index: share/mk/src.opts.mk =================================================================== --- share/mk/src.opts.mk +++ share/mk/src.opts.mk @@ -322,6 +322,13 @@ __DEFAULT_NO_OPTIONS+=MLX5TOOL .endif +# NVME is only x86 and powerpc64 +.if ${__T} == "amd64" || ${__T} == "i386" || ${__T} == "powerpc64" +__DEFAULT_YES_OPTIONS+=NVME +.else +__DEFAULT_NO_OPTIONS+=NVME +.endif + .include # Index: stand/common/bootstrap.h =================================================================== --- stand/common/bootstrap.h +++ stand/common/bootstrap.h @@ -161,6 +161,11 @@ extern int isapnp_readport; /* + * Version information + */ +extern char bootprog_info[]; + +/* * Preloaded file metadata header. * * Metadata are allocated on our heap, and copied into kernel space Index: stand/efi/loader/main.c =================================================================== --- stand/efi/loader/main.c +++ stand/efi/loader/main.c @@ -53,8 +53,6 @@ #include "loader_efi.h" -extern char bootprog_info[]; - struct arch_switch archsw; /* MI/MD interface boundary */ EFI_GUID acpi = ACPI_TABLE_GUID; @@ -415,7 +413,8 @@ { char var[128]; EFI_GUID *guid; - int i, j, vargood, howto; + int i, j, howto; + bool vargood; UINTN k; int has_kbd; char *s; @@ -532,14 +531,14 @@ } } } else { - vargood = 0; + vargood = false; for (j = 0; argv[i][j] != 0; j++) { if (j == sizeof(var)) { - vargood = 0; + vargood = false; break; } if (j > 0 && argv[i][j] == '=') - vargood = 1; + vargood = true; var[j] = (char)argv[i][j]; } if (vargood) { Index: stand/ficl.mk =================================================================== --- stand/ficl.mk +++ stand/ficl.mk @@ -2,8 +2,6 @@ # Common flags to build FICL related files -.include "defs.mk" - .if ${MACHINE_CPUARCH} == "amd64" && ${DO32:U0} == 1 FICL_CPUARCH= i386 .elif ${MACHINE_ARCH:Mmips64*} != "" Index: stand/i386/loader/main.c =================================================================== --- stand/i386/loader/main.c +++ stand/i386/loader/main.c @@ -79,9 +79,6 @@ static void i386_zfs_probe(void); #endif -/* from vers.c */ -extern char bootprog_info[]; - /* XXX debugging */ extern char end[]; Index: stand/libsa/close.c =================================================================== --- stand/libsa/close.c +++ stand/libsa/close.c @@ -32,30 +32,30 @@ * SUCH DAMAGE. * * @(#)close.c 8.1 (Berkeley) 6/11/93 - * + * * * Copyright (c) 1989, 1990, 1991 Carnegie Mellon University * All Rights Reserved. * * Author: Alessandro Forin - * + * * Permission to use, copy, modify and distribute this software and its * documentation is hereby granted, provided that both the copyright * notice and this permission notice appear in all copies of the * software, derivative works or modified versions, and any portions * thereof, and that both notices appear in supporting documentation. - * + * * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. - * + * * Carnegie Mellon requests users of this software to return to - * + * * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU * School of Computer Science * Carnegie Mellon University * Pittsburgh PA 15213-3890 - * + * * any improvements or extensions that they make and grant Carnegie the * rights to redistribute these changes. */ @@ -68,31 +68,30 @@ int close(int fd) { - struct open_file *f = &files[fd]; - int err1 = 0, err2 = 0; + struct open_file *f = &files[fd]; + int err1 = 0, err2 = 0; - if ((unsigned)fd >= SOPEN_MAX || f->f_flags == 0) { - errno = EBADF; - return (-1); - } - if (f->f_rabuf != NULL) { + if ((unsigned)fd >= SOPEN_MAX || f->f_flags == 0) { + errno = EBADF; + return (-1); + } free(f->f_rabuf); f->f_rabuf = NULL; - } - if (!(f->f_flags & F_RAW) && f->f_ops) - err1 = (f->f_ops->fo_close)(f); - if (!(f->f_flags & F_NODEV) && f->f_dev) - err2 = (f->f_dev->dv_close)(f); - if (f->f_devdata != NULL) - devclose(f); - f->f_flags = 0; - if (err1) { - errno = err1; - return (-1); - } - if (err2) { - errno = err2; - return (-1); - } - return (0); + + if (!(f->f_flags & F_RAW) && f->f_ops) + err1 = (f->f_ops->fo_close)(f); + if (!(f->f_flags & F_NODEV) && f->f_dev) + err2 = (f->f_dev->dv_close)(f); + if (f->f_devdata != NULL) + devclose(f); + f->f_flags = 0; + if (err1) { + errno = err1; + return (-1); + } + if (err2) { + errno = err2; + return (-1); + } + return (0); } Index: stand/libsa/nfs.c =================================================================== --- stand/libsa/nfs.c +++ stand/libsa/nfs.c @@ -249,7 +249,7 @@ nfs_lookupfh(struct nfs_iodesc *d, const char *name, struct nfs_iodesc *newfd) { void *pkt = NULL; - int len, rlen, pos; + int len, pos; struct args { uint32_t fhsize; uint32_t fhplusname[1 + @@ -465,14 +465,13 @@ nfs_open(const char *upath, struct open_file *f) { struct iodesc *desc; - struct nfs_iodesc *currfd; + struct nfs_iodesc *currfd = NULL; char buf[2 * NFS_V3MAXFHSIZE + 3]; u_char *fh; char *cp; int i; #ifndef NFS_NOSYMLINK - struct nfs_iodesc *newfd; - struct nfsv3_fattrs *fa; + struct nfs_iodesc *newfd = NULL; char *ncp; int c; char namebuf[NFS_MAXPATHLEN + 1]; @@ -480,7 +479,7 @@ int nlinks = 0; #endif int error; - char *path; + char *path = NULL; if (netproto != NET_NFS) return (EINVAL); Index: stand/libsa/open.c =================================================================== --- stand/libsa/open.c +++ stand/libsa/open.c @@ -32,30 +32,30 @@ * SUCH DAMAGE. * * @(#)open.c 8.1 (Berkeley) 6/11/93 - * + * * * Copyright (c) 1989, 1990, 1991 Carnegie Mellon University * All Rights Reserved. * * Author: Alessandro Forin - * + * * Permission to use, copy, modify and distribute this software and its * documentation is hereby granted, provided that both the copyright * notice and this permission notice appear in all copies of the * software, derivative works or modified versions, and any portions * thereof, and that both notices appear in supporting documentation. - * + * * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. - * + * * Carnegie Mellon requests users of this software to return to - * + * * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU * School of Computer Science * Carnegie Mellon University * Pittsburgh PA 15213-3890 - * + * * any improvements or extensions that they make and grant Carnegie the * rights to redistribute these changes. */ @@ -70,90 +70,89 @@ struct open_file files[SOPEN_MAX]; static int -o_gethandle(void) +o_gethandle(void) { - int fd; - - for (fd = 0; fd < SOPEN_MAX; fd++) - if (files[fd].f_flags == 0) - return(fd); - return(-1); + int fd; + + for (fd = 0; fd < SOPEN_MAX; fd++) + if (files[fd].f_flags == 0) + return (fd); + return (-1); } static void o_rainit(struct open_file *f) { - f->f_rabuf = malloc(SOPEN_RASIZE); - f->f_ralen = 0; - f->f_raoffset = 0; + f->f_rabuf = malloc(SOPEN_RASIZE); + f->f_ralen = 0; + f->f_raoffset = 0; } int open(const char *fname, int mode) { - struct fs_ops *fs; - struct open_file *f; - int fd, i, error, besterror; - const char *file; - - if ((fd = o_gethandle()) == -1) { - errno = EMFILE; - return(-1); - } - - f = &files[fd]; - f->f_flags = mode + 1; - f->f_dev = (struct devsw *)0; - f->f_ops = (struct fs_ops *)0; - f->f_offset = 0; - f->f_devdata = NULL; - file = (char *)0; - - if (exclusive_file_system != NULL) { - fs = exclusive_file_system; - error = (fs->fo_open)(fname, f); - if (error == 0) - goto ok; - goto err; - } - - error = devopen(f, fname, &file); - if (error || - (((f->f_flags & F_NODEV) == 0) && f->f_dev == (struct devsw *)0)) - goto err; - - /* see if we opened a raw device; otherwise, 'file' is the file name. */ - if (file == (char *)0 || *file == '\0') { - f->f_flags |= F_RAW; - f->f_rabuf = NULL; + struct fs_ops *fs; + struct open_file *f; + int fd, i, error, besterror; + const char *file; + + if ((fd = o_gethandle()) == -1) { + errno = EMFILE; + return (-1); + } + + f = &files[fd]; + f->f_flags = mode + 1; + f->f_dev = (struct devsw *)0; + f->f_ops = (struct fs_ops *)0; + f->f_offset = 0; + f->f_devdata = NULL; + file = (char *)0; + + if (exclusive_file_system != NULL) { + fs = exclusive_file_system; + error = (fs->fo_open)(fname, f); + if (error == 0) + goto ok; + goto err; + } + + error = devopen(f, fname, &file); + if (error || + (((f->f_flags & F_NODEV) == 0) && f->f_dev == (struct devsw *)0)) + goto err; + + /* see if we opened a raw device; otherwise, 'file' is the file name. */ + if (file == (char *)0 || *file == '\0') { + f->f_flags |= F_RAW; + f->f_rabuf = NULL; + return (fd); + } + + /* pass file name to the different filesystem open routines */ + besterror = ENOENT; + for (i = 0; file_system[i] != NULL; i++) { + fs = file_system[i]; + error = (fs->fo_open)(file, f); + if (error == 0) + goto ok; + if (error != EINVAL) + besterror = error; + } + error = besterror; + + if ((f->f_flags & F_NODEV) == 0 && f->f_dev != NULL) + f->f_dev->dv_close(f); + if (error) + devclose(f); + +err: + f->f_flags = 0; + errno = error; + return (-1); + +ok: + f->f_ops = fs; + o_rainit(f); return (fd); - } - - /* pass file name to the different filesystem open routines */ - besterror = ENOENT; - for (i = 0; file_system[i] != NULL; i++) { - fs = file_system[i]; - error = (fs->fo_open)(file, f); - if (error == 0) - goto ok; - if (error != EINVAL) - besterror = error; - } - error = besterror; - - fail: - if ((f->f_flags & F_NODEV) == 0 && f->f_dev != NULL) - f->f_dev->dv_close(f); - if (error) - devclose(f); - - err: - f->f_flags = 0; - errno = error; - return (-1); - - ok: - f->f_ops = fs; - o_rainit(f); - return (fd); } Index: stand/libsa/read.c =================================================================== --- stand/libsa/read.c +++ stand/libsa/read.c @@ -32,30 +32,30 @@ * SUCH DAMAGE. * * @(#)read.c 8.1 (Berkeley) 6/11/93 - * + * * * Copyright (c) 1989, 1990, 1991 Carnegie Mellon University * All Rights Reserved. * * Author: Alessandro Forin - * + * * Permission to use, copy, modify and distribute this software and its * documentation is hereby granted, provided that both the copyright * notice and this permission notice appear in all copies of the * software, derivative works or modified versions, and any portions * thereof, and that both notices appear in supporting documentation. - * + * * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. - * + * * Carnegie Mellon requests users of this software to return to - * + * * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU * School of Computer Science * Carnegie Mellon University * Pittsburgh PA 15213-3890 - * + * * any improvements or extensions that they make and grant Carnegie the * rights to redistribute these changes. */ @@ -69,59 +69,65 @@ ssize_t read(int fd, void *dest, size_t bcount) { - struct open_file *f = &files[fd]; - size_t resid; + struct open_file *f = &files[fd]; + size_t resid; - if ((unsigned)fd >= SOPEN_MAX || !(f->f_flags & F_READ)) { - errno = EBADF; - return (-1); - } - if (f->f_flags & F_RAW) { - twiddle(4); - errno = (f->f_dev->dv_strategy)(f->f_devdata, F_READ, - btodb(f->f_offset), bcount, dest, &resid); - if (errno) - return (-1); - f->f_offset += resid; - return (resid); - } - - /* - * Optimise reads from regular files using a readahead buffer. - * If the request can't be satisfied from the current buffer contents, - * check to see if it should be bypassed, or refill the buffer and complete - * the request. - */ - resid = bcount; - for (;;) { - size_t ccount, cresid; - /* how much can we supply? */ - ccount = imin(f->f_ralen, resid); - if (ccount > 0) { - bcopy(f->f_rabuf + f->f_raoffset, dest, ccount); - f->f_raoffset += ccount; - f->f_ralen -= ccount; - resid -= ccount; - if (resid == 0) - return(bcount); - dest = (char *)dest + ccount; + if ((unsigned)fd >= SOPEN_MAX || !(f->f_flags & F_READ)) { + errno = EBADF; + return (-1); } - - /* will filling the readahead buffer again not help? */ - if (resid >= SOPEN_RASIZE) { - /* bypass the rest of the request and leave the buffer empty */ - if ((errno = (f->f_ops->fo_read)(f, dest, resid, &cresid))) - return (-1); - return(bcount - cresid); + if (f->f_flags & F_RAW) { + twiddle(4); + errno = (f->f_dev->dv_strategy)(f->f_devdata, F_READ, + btodb(f->f_offset), bcount, dest, &resid); + if (errno) + return (-1); + f->f_offset += resid; + return (resid); } - /* fetch more data */ - if ((errno = (f->f_ops->fo_read)(f, f->f_rabuf, SOPEN_RASIZE, &cresid))) - return (-1); - f->f_raoffset = 0; - f->f_ralen = SOPEN_RASIZE - cresid; - /* no more data, return what we had */ - if (f->f_ralen == 0) - return(bcount - resid); - } + /* + * Optimise reads from regular files using a readahead buffer. + * If the request can't be satisfied from the current buffer contents, + * check to see if it should be bypassed, or refill the buffer and + * complete the request. + */ + resid = bcount; + for (;;) { + size_t ccount, cresid; + /* how much can we supply? */ + ccount = imin(f->f_ralen, resid); + if (ccount > 0) { + bcopy(f->f_rabuf + f->f_raoffset, dest, ccount); + f->f_raoffset += ccount; + f->f_ralen -= ccount; + resid -= ccount; + if (resid == 0) + return (bcount); + dest = (char *)dest + ccount; + } + + /* will filling the readahead buffer again not help? */ + if (f->f_rabuf == NULL || resid >= SOPEN_RASIZE) { + /* + * bypass the rest of the request and leave the + * buffer empty + */ + errno = (f->f_ops->fo_read)(f, dest, resid, &cresid); + if (errno != 0) + return (-1); + return (bcount - cresid); + } + + /* fetch more data */ + errno = (f->f_ops->fo_read)(f, f->f_rabuf, SOPEN_RASIZE, + &cresid); + if (errno != 0) + return (-1); + f->f_raoffset = 0; + f->f_ralen = SOPEN_RASIZE - cresid; + /* no more data, return what we had */ + if (f->f_ralen == 0) + return (bcount - resid); + } } Index: stand/libsa/tftp.c =================================================================== --- stand/libsa/tftp.c +++ stand/libsa/tftp.c @@ -186,7 +186,6 @@ struct tftprecv_extra *extra; struct tftp_handle *h; struct tftphdr *t; - unsigned short *rtype; void *ptr = NULL; ssize_t len; Index: stand/libsa/ufs.c =================================================================== --- stand/libsa/ufs.c +++ stand/libsa/ufs.c @@ -506,8 +506,7 @@ ino_t inumber, parent_inumber; struct file *fp; struct fs *fs; - int i, rc; - size_t buf_size; + int rc; int nlinks = 0; char namebuf[MAXPATHLEN+1]; char *buf = NULL; Index: stand/libsa/write.c =================================================================== --- stand/libsa/write.c +++ stand/libsa/write.c @@ -32,30 +32,30 @@ * SUCH DAMAGE. * * @(#)write.c 8.1 (Berkeley) 6/11/93 - * + * * * Copyright (c) 1989, 1990, 1991 Carnegie Mellon University * All Rights Reserved. * * Author: Alessandro Forin - * + * * Permission to use, copy, modify and distribute this software and its * documentation is hereby granted, provided that both the copyright * notice and this permission notice appear in all copies of the * software, derivative works or modified versions, and any portions * thereof, and that both notices appear in supporting documentation. - * + * * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. - * + * * Carnegie Mellon requests users of this software to return to - * + * * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU * School of Computer Science * Carnegie Mellon University * Pittsburgh PA 15213-3890 - * + * * any improvements or extensions that they make and grant Carnegie the * rights to redistribute these changes. */ @@ -67,10 +67,7 @@ #include "stand.h" ssize_t -write(fd, dest, bcount) - int fd; - const void *dest; - size_t bcount; +write(int fd, const void *dest, size_t bcount) { struct open_file *f = &files[fd]; size_t resid; @@ -82,8 +79,8 @@ if (f->f_flags & F_RAW) { twiddle(4); errno = (f->f_dev->dv_strategy)(f->f_devdata, F_WRITE, - btodb(f->f_offset), bcount, __DECONST(void *, dest), - &resid); + btodb(f->f_offset), bcount, __DECONST(void *, dest), + &resid); if (errno) return (-1); f->f_offset += resid; Index: stand/loader.mk =================================================================== --- stand/loader.mk +++ stand/loader.mk @@ -1,7 +1,5 @@ # $FreeBSD$ -.include "defs.mk" - .PATH: ${LDRSRC} ${BOOTSRC}/libsa CFLAGS+=-I${LDRSRC} Index: stand/mips/beri/loader/loader.h =================================================================== --- stand/mips/beri/loader/loader.h +++ stand/mips/beri/loader/loader.h @@ -58,7 +58,4 @@ /* metadata.c */ int md_load64(char *args, vm_offset_t *modulep, vm_offset_t *dtbp); -/* vers.c */ -extern char bootprog_info[]; - #endif /* !_BOOT_LOADER_H_ */ Index: stand/powerpc/kboot/main.c =================================================================== --- stand/powerpc/kboot/main.c +++ stand/powerpc/kboot/main.c @@ -40,8 +40,6 @@ struct arch_switch archsw; extern void *_end; -extern char bootprog_info[]; - int kboot_getdev(void **vdev, const char *devspec, const char **path); ssize_t kboot_copyin(const void *src, vm_offset_t dest, const size_t len); ssize_t kboot_copyout(vm_offset_t src, void *dest, const size_t len); Index: stand/powerpc/ofw/main.c =================================================================== --- stand/powerpc/ofw/main.c +++ stand/powerpc/ofw/main.c @@ -38,7 +38,6 @@ struct arch_switch archsw; /* MI/MD interface boundary */ extern char end[]; -extern char bootprog_info[]; uint32_t acells, scells; Index: stand/sparc64/loader/main.c =================================================================== --- stand/sparc64/loader/main.c +++ stand/sparc64/loader/main.c @@ -75,8 +75,6 @@ #include "libofw.h" #include "dev_net.h" -extern char bootprog_info[]; - enum { HEAPVA = 0x800000, HEAPSZ = 0x1000000, Index: stand/uboot/common/main.c =================================================================== --- stand/uboot/common/main.c +++ stand/uboot/common/main.c @@ -66,7 +66,6 @@ }; extern char end[]; -extern char bootprog_info[]; extern unsigned char _etext[]; extern unsigned char _edata[]; Index: stand/userboot/userboot/main.c =================================================================== --- stand/userboot/userboot/main.c +++ stand/userboot/userboot/main.c @@ -52,7 +52,6 @@ struct loader_callbacks *callbacks; void *callbacks_arg; -extern char bootprog_info[]; static jmp_buf jb; struct arch_switch archsw; /* MI/MD interface boundary */ Index: sys/amd64/amd64/bpf_jit_machdep.c =================================================================== --- sys/amd64/amd64/bpf_jit_machdep.c +++ sys/amd64/amd64/bpf_jit_machdep.c @@ -44,9 +44,6 @@ #include #include -#include -#include -#include #else #include #include @@ -605,11 +602,7 @@ *size = stream.cur_ip; #ifdef _KERNEL - /* - * We cannot use malloc(9) because DMAP is mapped as NX. - */ - stream.ibuf = (void *)kmem_malloc(kernel_arena, *size, - M_NOWAIT); + stream.ibuf = malloc(*size, M_BPFJIT, M_EXEC | M_NOWAIT); if (stream.ibuf == NULL) break; #else @@ -658,14 +651,3 @@ return ((bpf_filter_func)(void *)stream.ibuf); } - -void -bpf_jit_free(void *func, size_t size) -{ - -#ifdef _KERNEL - kmem_free(kernel_arena, (vm_offset_t)func, size); -#else - munmap(func, size); -#endif -} Index: sys/amd64/amd64/cpu_switch.S =================================================================== --- sys/amd64/amd64/cpu_switch.S +++ sys/amd64/amd64/cpu_switch.S @@ -128,10 +128,10 @@ /* have we used fp, and need a save? */ cmpq %rdi,PCPU(FPCURTHREAD) - jne 3f + jne 2f movq PCB_SAVEFPU(%r8),%r8 clts - cmpl $0,use_xsave + cmpl $0,use_xsave(%rip) jne 1f fxsave (%r8) jmp 2f @@ -143,12 +143,7 @@ /* This is patched to xsaveopt if supported, see fpuinit_bsp1() */ xsave (%r8) movq %rcx,%rdx -2: smsw %ax - orb $CR0_TS,%al - lmsw %ax - xorl %eax,%eax - movq %rax,PCPU(FPCURTHREAD) -3: +2: /* Save is done. Now fire up new thread. Leave old vmspace. */ movq %rsi,%r12 movq %rdi,%r13 @@ -238,6 +233,8 @@ movq PCB_RBX(%r8),%rbx movq PCB_RIP(%r8),%rax movq %rax,(%rsp) + movq PCPU(CURTHREAD),%rdi + call fpu_activate_sw ret /* Index: sys/amd64/amd64/fpu.c =================================================================== --- sys/amd64/amd64/fpu.c +++ sys/amd64/amd64/fpu.c @@ -142,6 +142,11 @@ SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD, SYSCTL_NULL_INT_PTR, 1, "Floating point instructions executed in hardware"); +int lazy_fpu_switch = 0; +SYSCTL_INT(_hw, OID_AUTO, lazy_fpu_switch, CTLFLAG_RWTUN | CTLFLAG_NOFETCH, + &lazy_fpu_switch, 0, + "Lazily load FPU context after context switch"); + int use_xsave; /* non-static for cpu_switch.S */ uint64_t xsave_mask; /* the same */ static uma_zone_t fpu_save_area_zone; @@ -242,6 +247,7 @@ uint64_t xsave_mask_user; bool old_wp; + TUNABLE_INT_FETCH("hw.lazy_fpu_switch", &lazy_fpu_switch); if (!use_xsave) return; cpuid_count(0xd, 0x0, cp); @@ -651,6 +657,45 @@ return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]); } +static void +restore_fpu_curthread(struct thread *td) +{ + struct pcb *pcb; + + /* + * Record new context early in case frstor causes a trap. + */ + PCPU_SET(fpcurthread, td); + + stop_emulating(); + fpu_clean_state(); + pcb = td->td_pcb; + + if ((pcb->pcb_flags & PCB_FPUINITDONE) == 0) { + /* + * This is the first time this thread has used the FPU or + * the PCB doesn't contain a clean FPU state. Explicitly + * load an initial state. + * + * We prefer to restore the state from the actual save + * area in PCB instead of directly loading from + * fpu_initialstate, to ignite the XSAVEOPT + * tracking engine. + */ + bcopy(fpu_initialstate, pcb->pcb_save, + cpu_max_ext_state_size); + fpurestore(pcb->pcb_save); + if (pcb->pcb_initial_fpucw != __INITIAL_FPUCW__) + fldcw(pcb->pcb_initial_fpucw); + if (PCB_USER_FPU(pcb)) + set_pcb_flags(pcb, PCB_FPUINITDONE | + PCB_USERFPUINITDONE); + else + set_pcb_flags(pcb, PCB_FPUINITDONE); + } else + fpurestore(pcb->pcb_save); +} + /* * Device Not Available (DNA, #NM) exception handler. * @@ -661,7 +706,9 @@ void fpudna(void) { + struct thread *td; + td = curthread; /* * This handler is entered with interrupts enabled, so context * switches may occur before critical_enter() is executed. If @@ -675,49 +722,38 @@ KASSERT((curpcb->pcb_flags & PCB_FPUNOSAVE) == 0, ("fpudna while in fpu_kern_enter(FPU_KERN_NOCTX)")); - if (PCPU_GET(fpcurthread) == curthread) { - printf("fpudna: fpcurthread == curthread\n"); + if (__predict_false(PCPU_GET(fpcurthread) == td)) { + /* + * Some virtual machines seems to set %cr0.TS at + * arbitrary moments. Silently clear the TS bit + * regardless of the eager/lazy FPU context switch + * mode. + */ stop_emulating(); - critical_exit(); - return; - } - if (PCPU_GET(fpcurthread) != NULL) { - panic("fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n", - PCPU_GET(fpcurthread), PCPU_GET(fpcurthread)->td_tid, - curthread, curthread->td_tid); + } else { + if (__predict_false(PCPU_GET(fpcurthread) != NULL)) { + panic( + "fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n", + PCPU_GET(fpcurthread), + PCPU_GET(fpcurthread)->td_tid, td, td->td_tid); + } + restore_fpu_curthread(td); } - stop_emulating(); - /* - * Record new context early in case frstor causes a trap. - */ - PCPU_SET(fpcurthread, curthread); + critical_exit(); +} - fpu_clean_state(); +void fpu_activate_sw(struct thread *td); /* Called from the context switch */ +void +fpu_activate_sw(struct thread *td) +{ - if ((curpcb->pcb_flags & PCB_FPUINITDONE) == 0) { - /* - * This is the first time this thread has used the FPU or - * the PCB doesn't contain a clean FPU state. Explicitly - * load an initial state. - * - * We prefer to restore the state from the actual save - * area in PCB instead of directly loading from - * fpu_initialstate, to ignite the XSAVEOPT - * tracking engine. - */ - bcopy(fpu_initialstate, curpcb->pcb_save, - cpu_max_ext_state_size); - fpurestore(curpcb->pcb_save); - if (curpcb->pcb_initial_fpucw != __INITIAL_FPUCW__) - fldcw(curpcb->pcb_initial_fpucw); - if (PCB_USER_FPU(curpcb)) - set_pcb_flags(curpcb, - PCB_FPUINITDONE | PCB_USERFPUINITDONE); - else - set_pcb_flags(curpcb, PCB_FPUINITDONE); - } else - fpurestore(curpcb->pcb_save); - critical_exit(); + if (lazy_fpu_switch || (td->td_pflags & TDP_KTHREAD) != 0 || + !PCB_USER_FPU(td->td_pcb)) { + PCPU_SET(fpcurthread, NULL); + start_emulating(); + } else if (PCPU_GET(fpcurthread) != td) { + restore_fpu_curthread(td); + } } void Index: sys/arm64/arm64/cpu_errata.c =================================================================== --- sys/arm64/arm64/cpu_errata.c +++ sys/arm64/arm64/cpu_errata.c @@ -41,7 +41,7 @@ #include -#include +#include typedef void (cpu_quirk_install)(void); struct cpu_quirks { @@ -73,13 +73,22 @@ .midr_value = CPU_ID_RAW(CPU_IMPL_ARM, CPU_PART_CORTEX_A75,0,0), .quirk_install = install_psci_bp_hardening, }, + { + .midr_mask = CPU_IMPL_MASK | CPU_PART_MASK, + .midr_value = + CPU_ID_RAW(CPU_IMPL_CAVIUM, CPU_PART_THUNDERX2, 0,0), + .quirk_install = install_psci_bp_hardening, + }, }; static void install_psci_bp_hardening(void) { - PCPU_SET(bp_harden, psci_get_version); + if (smccc_arch_features(SMCCC_ARCH_WORKAROUND_1) != SMCCC_RET_SUCCESS) + return; + + PCPU_SET(bp_harden, smccc_arch_workaround_1); } void Index: sys/arm64/arm64/gic_v3.c =================================================================== --- sys/arm64/arm64/gic_v3.c +++ sys/arm64/arm64/gic_v3.c @@ -418,7 +418,7 @@ pic = sc->gic_pic; while (1) { - if (CPU_MATCH_ERRATA_CAVIUM_THUNDER_1_1) { + if (CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1) { /* * Hardware: Cavium ThunderX * Chip revision: Pass 1.0 (early version) Index: sys/arm64/arm64/identcpu.c =================================================================== --- sys/arm64/arm64/identcpu.c +++ sys/arm64/arm64/identcpu.c @@ -133,7 +133,7 @@ }; /* Cavium */ static const struct cpu_parts cpu_parts_cavium[] = { - { CPU_PART_THUNDER, "Thunder" }, + { CPU_PART_THUNDERX, "ThunderX" }, CPU_PART_NONE, }; @@ -212,11 +212,11 @@ * https://lkml.org/lkml/2016/8/4/722 */ /* - * XXX: CPU_MATCH_ERRATA_CAVIUM_THUNDER_1_1 on its own also + * XXX: CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 on its own also * triggers on pass 2.0+. */ if (cpu == 0 && CPU_VAR(PCPU_GET(midr)) == 0 && - CPU_MATCH_ERRATA_CAVIUM_THUNDER_1_1) + CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1) printf("WARNING: ThunderX Pass 1.1 detected.\nThis has known " "hardware bugs that may cause the incorrect operation of " "atomic operations.\n"); Index: sys/arm64/cavium/thunder_pcie_common.c =================================================================== --- sys/arm64/cavium/thunder_pcie_common.c +++ sys/arm64/cavium/thunder_pcie_common.c @@ -159,7 +159,7 @@ /* Check if we're running on Cavium ThunderX */ if (!CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK, - CPU_IMPL_CAVIUM, CPU_PART_THUNDER, 0, 0)) + CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, 0)) return (EINVAL); start = bus_get_resource_start(dev, SYS_RES_MEMORY, 0); Index: sys/arm64/cavium/thunder_pcie_fdt.c =================================================================== --- sys/arm64/cavium/thunder_pcie_fdt.c +++ sys/arm64/cavium/thunder_pcie_fdt.c @@ -97,7 +97,7 @@ /* Check if we're running on Cavium ThunderX */ if (!CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK, - CPU_IMPL_CAVIUM, CPU_PART_THUNDER, 0, 0)) + CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, 0)) return (ENXIO); if (!ofw_bus_status_okay(dev)) Index: sys/arm64/conf/GENERIC =================================================================== --- sys/arm64/conf/GENERIC +++ sys/arm64/conf/GENERIC @@ -146,6 +146,7 @@ device smc # SMSC LAN91C111 device vnic # Cavium ThunderX NIC device al_eth # Annapurna Alpine Ethernet NIC +device dwc_rk # Rockchip Designware # Block devices device ahci Index: sys/arm64/include/cpu.h =================================================================== --- sys/arm64/include/cpu.h +++ sys/arm64/include/cpu.h @@ -78,7 +78,7 @@ #define CPU_IMPL_MARVELL 0x56 #define CPU_IMPL_INTEL 0x69 -#define CPU_PART_THUNDER 0x0A1 +/* ARM Part numbers */ #define CPU_PART_FOUNDATION 0xD00 #define CPU_PART_CORTEX_A35 0xD04 #define CPU_PART_CORTEX_A53 0xD03 @@ -88,8 +88,14 @@ #define CPU_PART_CORTEX_A73 0xD09 #define CPU_PART_CORTEX_A75 0xD0A -#define CPU_REV_THUNDER_1_0 0x00 -#define CPU_REV_THUNDER_1_1 0x01 +/* Cavium Part numbers */ +#define CPU_PART_THUNDERX 0x0A1 +#define CPU_PART_THUNDERX_81XX 0x0A2 +#define CPU_PART_THUNDERX_83XX 0x0A3 +#define CPU_PART_THUNDERX2 0x0AF + +#define CPU_REV_THUNDERX_1_0 0x00 +#define CPU_REV_THUNDERX_1_1 0x01 #define CPU_IMPL(midr) (((midr) >> 24) & 0xff) #define CPU_PART(midr) (((midr) >> 4) & 0xfff) @@ -131,13 +137,13 @@ * Revision(s): Pass 1.0, Pass 1.1 */ #ifdef THUNDERX_PASS_1_1_ERRATA -#define CPU_MATCH_ERRATA_CAVIUM_THUNDER_1_1 \ +#define CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 \ (CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK | CPU_REV_MASK, \ - CPU_IMPL_CAVIUM, CPU_PART_THUNDER, 0, CPU_REV_THUNDER_1_0) || \ + CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, CPU_REV_THUNDERX_1_0) || \ CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK | CPU_REV_MASK, \ - CPU_IMPL_CAVIUM, CPU_PART_THUNDER, 0, CPU_REV_THUNDER_1_1)) + CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, CPU_REV_THUNDERX_1_1)) #else -#define CPU_MATCH_ERRATA_CAVIUM_THUNDER_1_1 0 +#define CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 0 #endif Index: sys/arm64/rockchip/clk/rk3328_cru.c =================================================================== --- sys/arm64/rockchip/clk/rk3328_cru.c +++ sys/arm64/rockchip/clk/rk3328_cru.c @@ -57,6 +57,10 @@ #define PCLK_GPIO1 201 #define PCLK_GPIO2 202 #define PCLK_GPIO3 203 +#define PCLK_I2C0 205 +#define PCLK_I2C1 206 +#define PCLK_I2C2 207 +#define PCLK_I2C3 208 #define HCLK_SDMMC 317 #define HCLK_SDIO 318 #define HCLK_EMMC 319 @@ -80,7 +84,13 @@ /* CRU_CLKGATE_CON10 */ CRU_GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", 0x228, 0) + /* CRU_CLKGATE_CON15*/ + CRU_GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0x23C, 10) + /* CRU_CLKGATE_CON16 */ + CRU_GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0x23C, 0) + CRU_GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0x23C, 1) + CRU_GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0x23C, 2) CRU_GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_bus", 0x240, 7) CRU_GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0x240, 8) CRU_GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0x240, 9) @@ -512,6 +522,8 @@ .base_offset = 0x00, .gate_offset = 0x200, .gate_shift = 0, + .mode_reg = 0x80, + .mode_val = 0x1, .flags = RK_CLK_PLL_HAVE_GATE, .frac_rates = rk3328_pll_frac_rates, }; @@ -526,6 +538,8 @@ .base_offset = 0x20, .gate_offset = 0x200, .gate_shift = 1, + .mode_reg = 0x80, + .mode_val = 0x8, .flags = RK_CLK_PLL_HAVE_GATE, }; @@ -537,6 +551,8 @@ .parent_cnt = nitems(pll_parents), }, .base_offset = 0x40, + .mode_reg = 0x80, + .mode_val = 0x80, .rates = rk3328_pll_rates, }; @@ -550,6 +566,8 @@ .base_offset = 0x60, .gate_offset = 0x200, .gate_shift = 2, + .mode_reg = 0x80, + .mode_val = 0x800, .flags = RK_CLK_PLL_HAVE_GATE, .frac_rates = rk3328_pll_frac_rates, }; @@ -564,6 +582,8 @@ .base_offset = 0xa0, .gate_offset = 0x200, .gate_shift = 12, + .mode_reg = 0x80, + .mode_val = 0x2, .flags = RK_CLK_PLL_HAVE_GATE, .rates = rk3328_pll_rates, }; @@ -853,6 +873,104 @@ .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; +/* CRU_CLKSEL_CON34 */ +#define SCLK_I2C0 55 +#define SCLK_I2C1 56 + +static const char *i2c_parents[] = {"cpll", "gpll"}; + +static struct rk_clk_composite_def i2c0 = { + .clkdef = { + .id = SCLK_I2C0, + .name = "clk_i2c0", + .parent_names = i2c_parents, + .parent_cnt = nitems(i2c_parents), + }, + .muxdiv_offset = 0x188, + + .mux_shift = 7, + .mux_width = 1, + + .div_shift = 0, + .div_width = 6, + + /* CRU_CLKGATE_CON2 */ + .gate_offset = 0x208, + .gate_shift = 9, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, +}; + +static struct rk_clk_composite_def i2c1 = { + .clkdef = { + .id = SCLK_I2C1, + .name = "clk_i2c1", + .parent_names = i2c_parents, + .parent_cnt = nitems(i2c_parents), + }, + .muxdiv_offset = 0x188, + + .mux_shift = 15, + .mux_width = 1, + + .div_shift = 8, + .div_width = 6, + + /* CRU_CLKGATE_CON2 */ + .gate_offset = 0x208, + .gate_shift = 10, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, +}; + +/* CRU_CLKSEL_CON35 */ +#define SCLK_I2C2 57 +#define SCLK_I2C3 58 + +static struct rk_clk_composite_def i2c2 = { + .clkdef = { + .id = SCLK_I2C2, + .name = "clk_i2c2", + .parent_names = i2c_parents, + .parent_cnt = nitems(i2c_parents), + }, + .muxdiv_offset = 0x18C, + + .mux_shift = 7, + .mux_width = 1, + + .div_shift = 0, + .div_width = 6, + + /* CRU_CLKGATE_CON2 */ + .gate_offset = 0x208, + .gate_shift = 11, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, +}; + +static struct rk_clk_composite_def i2c3 = { + .clkdef = { + .id = SCLK_I2C3, + .name = "clk_i2c3", + .parent_names = i2c_parents, + .parent_cnt = nitems(i2c_parents), + }, + .muxdiv_offset = 0x18C, + + .mux_shift = 15, + .mux_width = 1, + + .div_shift = 8, + .div_width = 6, + + /* CRU_CLKGATE_CON2 */ + .gate_offset = 0x208, + .gate_shift = 12, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, +}; + static struct rk_clk rk3328_clks[] = { { .type = RK_CLK_PLL, @@ -917,6 +1035,23 @@ .type = RK_CLK_COMPOSITE, .clk.composite = &emmc }, + + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &i2c0 + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &i2c1 + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &i2c2 + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &i2c3 + }, }; static int Index: sys/arm64/rockchip/clk/rk_clk_armclk.c =================================================================== --- sys/arm64/rockchip/clk/rk_clk_armclk.c +++ sys/arm64/rockchip/clk/rk_clk_armclk.c @@ -105,7 +105,7 @@ DEVICE_LOCK(clk); READ4(clk, sc->muxdiv_offset, &val); val &= ~(sc->mux_mask >> sc->mux_shift); - val |= index << sc->mux_shift; + val |= index << sc->mux_shift | RK_ARMCLK_WRITE_MASK; WRITE4(clk, sc->muxdiv_offset, val); DEVICE_UNLOCK(clk); Index: sys/arm64/rockchip/clk/rk_clk_pll.h =================================================================== --- sys/arm64/rockchip/clk/rk_clk_pll.h +++ sys/arm64/rockchip/clk/rk_clk_pll.h @@ -50,6 +50,9 @@ uint32_t gate_offset; uint32_t gate_shift; + uint32_t mode_reg; + uint32_t mode_val; + uint32_t flags; struct rk_clk_pll_rate *rates; Index: sys/arm64/rockchip/clk/rk_clk_pll.c =================================================================== --- sys/arm64/rockchip/clk/rk_clk_pll.c +++ sys/arm64/rockchip/clk/rk_clk_pll.c @@ -47,6 +47,9 @@ uint32_t gate_offset; uint32_t gate_shift; + uint32_t mode_reg; + uint32_t mode_val; + uint32_t flags; struct rk_clk_pll_rate *rates; @@ -221,6 +224,11 @@ reg |= rates->frac << RK_CLK_PLL_FRAC_SHIFT; WRITE4(clk, sc->base_offset + 0x8, reg); + /* Setting to normal mode */ + READ4(clk, sc->mode_reg, ®); + reg |= sc->mode_val << 16 | sc->mode_val; + WRITE4(clk, sc->mode_reg, reg); + /* Reading lock */ for (timeout = 1000; timeout; timeout--) { READ4(clk, sc->base_offset + 0x4, ®); @@ -263,6 +271,8 @@ sc->base_offset = clkdef->base_offset; sc->gate_offset = clkdef->gate_offset; sc->gate_shift = clkdef->gate_shift; + sc->mode_reg = clkdef->mode_reg; + sc->mode_val = clkdef->mode_val; sc->flags = clkdef->flags; sc->rates = clkdef->rates; sc->frac_rates = clkdef->frac_rates; Index: sys/arm64/rockchip/if_dwc_rk.c =================================================================== --- /dev/null +++ sys/arm64/rockchip/if_dwc_rk.c @@ -0,0 +1,151 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2018 Emmanuel Vadot + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include +#include + +#include + +#include "syscon_if.h" + +#include "if_dwc_if.h" + +#define RK3328_GRF_MAC_CON0 0x0900 +#define RK3328_GRF_MAC_CON0_TX_MASK 0x7F +#define RK3328_GRF_MAC_CON0_TX_SHIFT 0 +#define RK3328_GRF_MAC_CON0_RX_MASK 0x7F +#define RK3328_GRF_MAC_CON0_RX_SHIFT 7 + +#define RK3328_GRF_MAC_CON1 0x0904 +#define RK3328_GRF_MAC_CON2 0x0908 +#define RK3328_GRF_MACPHY_CON0 0x0B00 +#define RK3328_GRF_MACPHY_CON1 0x0B04 +#define RK3328_GRF_MACPHY_CON2 0x0B08 +#define RK3328_GRF_MACPHY_CON3 0x0B0C +#define RK3328_GRF_MACPHY_STATUS 0x0B10 + +static void +rk3328_set_delays(struct syscon *grf, phandle_t node) +{ + uint32_t tx, rx; + + if (OF_getencprop(node, "tx-delay", &tx, sizeof(tx)) >= 0) + tx = 0x30; + if (OF_getencprop(node, "rx-delay", &rx, sizeof(rx)) >= 0) + rx = 0x10; + + tx = ((tx & RK3328_GRF_MAC_CON0_TX_MASK) << + RK3328_GRF_MAC_CON0_TX_SHIFT); + rx = ((rx & RK3328_GRF_MAC_CON0_TX_MASK) << + RK3328_GRF_MAC_CON0_RX_SHIFT); + SYSCON_WRITE_4(grf, RK3328_GRF_MAC_CON0, tx | rx); +} + +static int +if_dwc_rk_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + if (!ofw_bus_is_compatible(dev, "rockchip,rk3328-gmac")) + return (ENXIO); + device_set_desc(dev, "Rockchip Gigabit Ethernet Controller"); + + return (BUS_PROBE_DEFAULT); +} + +static int +if_dwc_rk_init(device_t dev) +{ + phandle_t node; + struct syscon *grf = NULL; + + node = ofw_bus_get_node(dev); + if (OF_hasprop(node, "rockchip,grf") && + syscon_get_by_ofw_property(dev, node, + "rockchip,grf", &grf) != 0) { + device_printf(dev, "cannot get grf driver handle\n"); + return (ENXIO); + } + + rk3328_set_delays(grf, node); + + /* Mode should be set according to dtb property */ + + return (0); +} + +static int +if_dwc_rk_mac_type(device_t dev) +{ + + return (DWC_GMAC_ALT_DESC); +} + +static int +if_dwc_rk_mii_clk(device_t dev) +{ + + /* Should be calculated from the clock */ + return (GMAC_MII_CLK_150_250M_DIV102); +} + +static device_method_t if_dwc_rk_methods[] = { + DEVMETHOD(device_probe, if_dwc_rk_probe), + + DEVMETHOD(if_dwc_init, if_dwc_rk_init), + DEVMETHOD(if_dwc_mac_type, if_dwc_rk_mac_type), + DEVMETHOD(if_dwc_mii_clk, if_dwc_rk_mii_clk), + + DEVMETHOD_END +}; + +static devclass_t dwc_rk_devclass; + +extern driver_t dwc_driver; + +DEFINE_CLASS_1(dwc, dwc_rk_driver, if_dwc_rk_methods, + sizeof(struct dwc_softc), dwc_driver); +DRIVER_MODULE(dwc_rk, simplebus, dwc_rk_driver, dwc_rk_devclass, 0, 0); +MODULE_DEPEND(dwc_rk, dwc, 1, 1, 1); Index: sys/arm64/rockchip/rk_i2c.c =================================================================== --- /dev/null +++ sys/arm64/rockchip/rk_i2c.c @@ -0,0 +1,607 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2018 Emmanuel Vadot + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include + +#include "iicbus_if.h" + +#include "opt_soc.h" + + +#define RK_I2C_CON 0x00 +#define RK_I2C_CON_EN (1 << 0) +#define RK_I2C_CON_MODE_SHIFT 1 +#define RK_I2C_CON_MODE_TX 0 +#define RK_I2C_CON_MODE_RRX 1 +#define RK_I2C_CON_MODE_RX 2 +#define RK_I2C_CON_MODE_RTX 3 +#define RK_I2C_CON_MODE_MASK 0x6 +#define RK_I2C_CON_START (1 << 3) +#define RK_I2C_CON_STOP (1 << 4) +#define RK_I2C_CON_LASTACK (1 << 5) +#define RK_I2C_CON_NAKSTOP (1 << 6) + +#define RK_I2C_CLKDIV 0x04 +#define RK_I2C_CLKDIVL_MASK 0xFFFF +#define RK_I2C_CLKDIVL_SHIFT 0 +#define RK_I2C_CLKDIVH_MASK 0xFFFF0000 +#define RK_I2C_CLKDIVH_SHIFT 16 +#define RK_I2C_CLKDIV_MUL 8 + +#define RK_I2C_MRXADDR 0x08 +#define RK_I2C_MRXADDR_SADDR_MASK 0xFFFFFF +#define RK_I2C_MRXADDR_VALID(x) (1 << (24 + x)) + +#define RK_I2C_MRXRADDR 0x0C +#define RK_I2C_MRXRADDR_SRADDR_MASK 0xFFFFFF +#define RK_I2C_MRXRADDR_VALID(x) (1 << (24 + x)) + +#define RK_I2C_MTXCNT 0x10 +#define RK_I2C_MTXCNT_MASK 0x3F + +#define RK_I2C_MRXCNT 0x14 +#define RK_I2C_MRXCNT_MASK 0x3F + +#define RK_I2C_IEN 0x18 +#define RK_I2C_IEN_BTFIEN (1 << 0) +#define RK_I2C_IEN_BRFIEN (1 << 1) +#define RK_I2C_IEN_MBTFIEN (1 << 2) +#define RK_I2C_IEN_MBRFIEN (1 << 3) +#define RK_I2C_IEN_STARTIEN (1 << 4) +#define RK_I2C_IEN_STOPIEN (1 << 5) +#define RK_I2C_IEN_NAKRCVIEN (1 << 6) +#define RK_I2C_IEN_ALL (RK_I2C_IEN_BTFIEN | \ + RK_I2C_IEN_BRFIEN | RK_I2C_IEN_MBTFIEN | RK_I2C_IEN_MBRFIEN | \ + RK_I2C_IEN_STARTIEN | RK_I2C_IEN_STOPIEN | RK_I2C_IEN_NAKRCVIEN) + +#define RK_I2C_IPD 0x1C +#define RK_I2C_IPD_BTFIPD (1 << 0) +#define RK_I2C_IPD_BRFIPD (1 << 1) +#define RK_I2C_IPD_MBTFIPD (1 << 2) +#define RK_I2C_IPD_MBRFIPD (1 << 3) +#define RK_I2C_IPD_STARTIPD (1 << 4) +#define RK_I2C_IPD_STOPIPD (1 << 5) +#define RK_I2C_IPD_NAKRCVIPD (1 << 6) +#define RK_I2C_IPD_ALL (RK_I2C_IPD_BTFIPD | \ + RK_I2C_IPD_BRFIPD | RK_I2C_IPD_MBTFIPD | RK_I2C_IPD_MBRFIPD | \ + RK_I2C_IPD_STARTIPD | RK_I2C_IPD_STOPIPD | RK_I2C_IPD_NAKRCVIPD) + +#define RK_I2C_FNCT 0x20 +#define RK_I2C_FNCT_MASK 0x3F + +#define RK_I2C_TXDATA_BASE 0x100 + +#define RK_I2C_RXDATA_BASE 0x200 + +enum rk_i2c_state { + STATE_IDLE = 0, + STATE_START, + STATE_READ, + STATE_WRITE, + STATE_STOP +}; + +struct rk_i2c_softc { + device_t dev; + struct resource *res[2]; + struct mtx mtx; + clk_t sclk; + clk_t pclk; + int busy; + void * intrhand; + uint32_t intr; + uint32_t ipd; + struct iic_msg *msg; + size_t cnt; + int transfer_done; + int nak_recv; + uint8_t mode; + uint8_t state; + + device_t iicbus; +}; + +static struct ofw_compat_data compat_data[] = { +#ifdef SOC_ROCKCHIP_RK3328 + {"rockchip,rk3328-i2c", 1}, +#endif + {NULL, 0} +}; + +static struct resource_spec rk_i2c_spec[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, + { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, + { -1, 0 } +}; + +static int rk_i2c_probe(device_t dev); +static int rk_i2c_attach(device_t dev); +static int rk_i2c_detach(device_t dev); + +#define RK_I2C_LOCK(sc) mtx_lock(&(sc)->mtx) +#define RK_I2C_UNLOCK(sc) mtx_unlock(&(sc)->mtx) +#define RK_I2C_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED) +#define RK_I2C_READ(sc, reg) bus_read_4((sc)->res[0], (reg)) +#define RK_I2C_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) + +static uint32_t +rk_i2c_get_clkdiv(struct rk_i2c_softc *sc, uint64_t speed) +{ + uint64_t pclk_freq; + uint32_t clkdiv; + int err; + + err = clk_get_freq(sc->pclk, &pclk_freq); + if (err != 0) + return (err); + + clkdiv = (pclk_freq / speed / RK_I2C_CLKDIV_MUL / 2) - 1; + clkdiv &= RK_I2C_CLKDIVL_MASK; + + clkdiv = clkdiv << RK_I2C_CLKDIVH_SHIFT | clkdiv; + + return (clkdiv); +} + +static int +rk_i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) +{ + struct rk_i2c_softc *sc; + uint32_t clkdiv; + u_int busfreq; + + sc = device_get_softc(dev); + + busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed); + + clkdiv = rk_i2c_get_clkdiv(sc, busfreq); + + RK_I2C_LOCK(sc); + + /* Set the clock divider */ + RK_I2C_WRITE(sc, RK_I2C_CLKDIV, clkdiv); + + /* Disable the module */ + RK_I2C_WRITE(sc, RK_I2C_CON, 0); + + RK_I2C_UNLOCK(sc); + + return (0); +} + +static void +rk_i2c_fill_tx(struct rk_i2c_softc *sc) +{ + uint32_t buf32; + uint8_t buf; + int i, j, len; + + if (sc->msg == NULL || sc->msg->len == sc->cnt) + return; + + len = sc->msg->len - sc->cnt; + if (len > 8) + len = 8; + + for (i = 0; i < len; i++) { + buf32 = 0; + for (j = 0; j < 4 ; j++) { + if (sc->cnt == sc->msg->len) + break; + + /* Fill the addr if needed */ + if (sc->cnt == 0) { + buf = sc->msg->slave; + } + else + buf = sc->msg->buf[sc->cnt - 1]; + + buf32 |= buf << (j * 8); + + sc->cnt++; + } + + RK_I2C_WRITE(sc, RK_I2C_TXDATA_BASE + 4 * i, buf32); + + if (sc->cnt == sc->msg->len) + break; + } +} + +static void +rk_i2c_drain_rx(struct rk_i2c_softc *sc) +{ + uint32_t buf32 = 0; + uint8_t buf8; + int len; + int i; + + if (sc->msg == NULL) { + device_printf(sc->dev, "No current iic msg\n"); + return; + } + + len = sc->msg->len - sc->cnt; + if (len > 32) + len = 32; + + for (i = 0; i < len; i++) { + if (i % 4 == 0) + buf32 = RK_I2C_READ(sc, RK_I2C_RXDATA_BASE + (i / 4) * 4); + + buf8 = (buf32 >> ((i % 4) * 8)) & 0xFF; + + sc->msg->buf[sc->cnt++] = buf8; + } +} + +static void +rk_i2c_send_start(struct rk_i2c_softc *sc) +{ + uint32_t reg; + + RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_STARTIEN); + + sc->state = STATE_START; + + reg = RK_I2C_READ(sc, RK_I2C_CON); + reg |= RK_I2C_CON_START; + reg |= RK_I2C_CON_EN; + reg &= ~RK_I2C_CON_MODE_MASK; + reg |= sc->mode << RK_I2C_CON_MODE_SHIFT; + RK_I2C_WRITE(sc, RK_I2C_CON, reg); +} + +static void +rk_i2c_send_stop(struct rk_i2c_softc *sc) +{ + uint32_t reg; + + RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_STOPIEN); + + sc->state = STATE_STOP; + + reg = RK_I2C_READ(sc, RK_I2C_CON); + reg |= RK_I2C_CON_STOP; + RK_I2C_WRITE(sc, RK_I2C_CON, reg); +} + +static void +rk_i2c_intr(void *arg) +{ + struct rk_i2c_softc *sc; + uint32_t reg; + + sc = (struct rk_i2c_softc *)arg; + + RK_I2C_LOCK(sc); + + sc->ipd = RK_I2C_READ(sc, RK_I2C_IPD); + RK_I2C_WRITE(sc, RK_I2C_IPD, sc->ipd); + + switch (sc->state) { + case STATE_START: + /* Disable start bit */ + reg = RK_I2C_READ(sc, RK_I2C_CON); + reg &= ~RK_I2C_CON_START; + RK_I2C_WRITE(sc, RK_I2C_CON, reg); + + if (sc->mode == RK_I2C_CON_MODE_RRX || + sc->mode == RK_I2C_CON_MODE_RX) { + sc->state = STATE_READ; + RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBRFIEN | + RK_I2C_IEN_NAKRCVIEN); + + reg = RK_I2C_READ(sc, RK_I2C_CON); + reg |= RK_I2C_CON_LASTACK; + RK_I2C_WRITE(sc, RK_I2C_CON, reg); + + RK_I2C_WRITE(sc, RK_I2C_MRXCNT, sc->msg->len); + } else { + sc->state = STATE_WRITE; + RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBTFIEN | + RK_I2C_IEN_NAKRCVIEN); + + sc->msg->len += 1; + rk_i2c_fill_tx(sc); + RK_I2C_WRITE(sc, RK_I2C_MTXCNT, sc->msg->len); + } + break; + case STATE_READ: + rk_i2c_drain_rx(sc); + + if (sc->cnt == sc->msg->len) + rk_i2c_send_stop(sc); + + break; + case STATE_WRITE: + if (sc->cnt == sc->msg->len) + rk_i2c_send_stop(sc); + + break; + case STATE_STOP: + /* Disable stop bit */ + reg = RK_I2C_READ(sc, RK_I2C_CON); + reg &= ~RK_I2C_CON_STOP; + RK_I2C_WRITE(sc, RK_I2C_CON, reg); + + sc->transfer_done = 1; + sc->state = STATE_IDLE; + break; + case STATE_IDLE: + break; + } + + wakeup(sc); + RK_I2C_UNLOCK(sc); +} + +static int +rk_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) +{ + struct rk_i2c_softc *sc; + uint32_t reg; + int i, j, msgskip, err = 0; + + sc = device_get_softc(dev); + + while (sc->busy) + mtx_sleep(sc, &sc->mtx, 0, "i2cbuswait", 0); + + sc->busy = 1; + + err = clk_enable(sc->pclk); + if (err != 0) { + device_printf(dev, "cannot enable pclk clock\n"); + goto out; + } + err = clk_enable(sc->sclk); + if (err != 0) { + device_printf(dev, "cannot enable i2c clock\n"); + goto out; + } + + RK_I2C_LOCK(sc); + + /* Clean stale interrupts */ + RK_I2C_WRITE(sc, RK_I2C_IPD, RK_I2C_IPD_ALL); + + for (i = 0; i < nmsgs; i += msgskip) { + if (nmsgs - i >= 2 && !(msgs[i].flags & IIC_M_RD) && + msgs[i + 1].flags & IIC_M_RD && msgs[i].len <= 4) { + sc->mode = RK_I2C_CON_MODE_RRX; + msgskip = 2; + sc->msg = &msgs[i + 1]; + + /* Write slave address */ + reg = msgs[i].slave | RK_I2C_MRXADDR_VALID(0); + RK_I2C_WRITE(sc, RK_I2C_MRXADDR, reg); + + /* Write slave register address */ + for (j = 0, reg = 0; j < msgs[i].len; j++) { + reg |= (msgs[i].buf[j] & 0xff) << (j * 8); + reg |= RK_I2C_MRXADDR_VALID(j); + } + + RK_I2C_WRITE(sc, RK_I2C_MRXRADDR, reg); + } else { + if (msgs[i].flags & IIC_M_RD) { + sc->mode = RK_I2C_CON_MODE_RX; + msgs[i].slave |= LSB; + } + else { + sc->mode = RK_I2C_CON_MODE_TX; + msgs[i].slave &= ~LSB; + } + msgskip = 1; + sc->msg = &msgs[i]; + } + + sc->transfer_done = 0; + sc->cnt = 0; + sc->state = STATE_IDLE; + rk_i2c_send_start(sc); + + while (err == 0 && sc->transfer_done != 1) { + err = msleep(sc, &sc->mtx, 0, "rk_i2c", 10 * hz); + } + } + + /* Disable the module and interrupts */ + RK_I2C_WRITE(sc, RK_I2C_CON, 0); + RK_I2C_WRITE(sc, RK_I2C_IEN, 0); + + sc->busy = 0; + + RK_I2C_UNLOCK(sc); + + err = clk_disable(sc->pclk); + if (err != 0) { + device_printf(dev, "cannot enable pclk clock\n"); + goto out; + } + err = clk_disable(sc->sclk); + if (err != 0) { + device_printf(dev, "cannot enable i2c clock\n"); + goto out; + } + +out: + return (err); +} + +static int +rk_i2c_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + device_set_desc(dev, "RockChip I2C"); + return (BUS_PROBE_DEFAULT); +} + +static int +rk_i2c_attach(device_t dev) +{ + struct rk_i2c_softc *sc; + int error; + + sc = device_get_softc(dev); + sc->dev = dev; + + mtx_init(&sc->mtx, device_get_nameunit(dev), "rk_i2c", MTX_DEF); + + if (bus_alloc_resources(dev, rk_i2c_spec, sc->res) != 0) { + device_printf(dev, "cannot allocate resources for device\n"); + error = ENXIO; + goto fail; + } + + if (bus_setup_intr(dev, sc->res[1], + INTR_TYPE_MISC | INTR_MPSAFE, NULL, rk_i2c_intr, sc, + &sc->intrhand)) { + bus_release_resources(dev, rk_i2c_spec, sc->res); + device_printf(dev, "cannot setup interrupt handler\n"); + return (ENXIO); + } + + /* Activate the module clocks. */ + error = clk_get_by_ofw_name(dev, 0, "i2c", &sc->sclk); + if (error != 0) { + device_printf(dev, "cannot get i2c clock\n"); + goto fail; + } + error = clk_get_by_ofw_name(dev, 0, "pclk", &sc->pclk); + if (error != 0) { + device_printf(dev, "cannot get pclk clock\n"); + goto fail; + } + + sc->iicbus = device_add_child(dev, "iicbus", -1); + if (sc->iicbus == NULL) { + device_printf(dev, "cannot add iicbus child device\n"); + error = ENXIO; + goto fail; + } + + bus_generic_attach(dev); + + return (0); + +fail: + if (rk_i2c_detach(dev) != 0) + device_printf(dev, "Failed to detach\n"); + return (error); +} + +static int +rk_i2c_detach(device_t dev) +{ + struct rk_i2c_softc *sc; + int error; + + sc = device_get_softc(dev); + + if ((error = bus_generic_detach(dev)) != 0) + return (error); + + if (sc->iicbus != NULL) + if ((error = device_delete_child(dev, sc->iicbus)) != 0) + return (error); + + if (sc->sclk != NULL) + clk_release(sc->sclk); + if (sc->pclk != NULL) + clk_release(sc->pclk); + + if (sc->intrhand != NULL) + bus_teardown_intr(sc->dev, sc->res[1], sc->intrhand); + + bus_release_resources(dev, rk_i2c_spec, sc->res); + + mtx_destroy(&sc->mtx); + + return (0); +} + +static phandle_t +rk_i2c_get_node(device_t bus, device_t dev) +{ + + return ofw_bus_get_node(bus); +} + +static device_method_t rk_i2c_methods[] = { + DEVMETHOD(device_probe, rk_i2c_probe), + DEVMETHOD(device_attach, rk_i2c_attach), + DEVMETHOD(device_detach, rk_i2c_detach), + + /* OFW methods */ + DEVMETHOD(ofw_bus_get_node, rk_i2c_get_node), + + DEVMETHOD(iicbus_callback, iicbus_null_callback), + DEVMETHOD(iicbus_reset, rk_i2c_reset), + DEVMETHOD(iicbus_transfer, rk_i2c_transfer), + + DEVMETHOD_END +}; + +static driver_t rk_i2c_driver = { + "rk_i2c", + rk_i2c_methods, + sizeof(struct rk_i2c_softc), +}; + +static devclass_t rk_i2c_devclass; + +EARLY_DRIVER_MODULE(rk_i2c, simplebus, rk_i2c_driver, rk_i2c_devclass, 0, 0, + BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); +EARLY_DRIVER_MODULE(ofw_iicbus, rk_i2c, ofw_iicbus_driver, ofw_iicbus_devclass, + 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); +MODULE_DEPEND(rk_i2c, iicbus, 1, 1, 1); +MODULE_DEPEND(rk_i2c, ofw_iicbus, 1, 1, 1); +MODULE_VERSION(rk_i2c, 1); Index: sys/arm64/rockchip/rk_pinctrl.c =================================================================== --- sys/arm64/rockchip/rk_pinctrl.c +++ sys/arm64/rockchip/rk_pinctrl.c @@ -438,6 +438,8 @@ /* Attach child devices */ for (node = OF_child(node); node > 0; node = OF_peer(node)) { + if (!ofw_bus_node_is_compatible(node, "rockchip,gpio-bank")) + continue; cdev = simplebus_add_device(dev, node, 0, NULL, -1, NULL); if (cdev != NULL) device_probe_and_attach(cdev); Index: sys/compat/freebsd32/freebsd32_misc.c =================================================================== --- sys/compat/freebsd32/freebsd32_misc.c +++ sys/compat/freebsd32/freebsd32_misc.c @@ -2127,11 +2127,27 @@ break; } } - CP(*in, *out, st_dev); + out->st_dev = in->st_dev; + if (out->st_dev != in->st_dev) { + switch (ino64_trunc_error) { + default: + break; + case 1: + return (EOVERFLOW); + } + } CP(*in, *out, st_mode); CP(*in, *out, st_uid); CP(*in, *out, st_gid); - CP(*in, *out, st_rdev); + out->st_rdev = in->st_rdev; + if (out->st_rdev != in->st_rdev) { + switch (ino64_trunc_error) { + default: + break; + case 1: + return (EOVERFLOW); + } + } TS_CP(*in, *out, st_atim); TS_CP(*in, *out, st_mtim); TS_CP(*in, *out, st_ctim); Index: sys/compat/linux/linux_stats.c =================================================================== --- sys/compat/linux/linux_stats.c +++ sys/compat/linux/linux_stats.c @@ -128,13 +128,32 @@ fdrop(fp, td); } +/* + * l_dev_t has the same encoding as dev_t in the latter's low 16 bits, so + * truncation of a dev_t to 16 bits gives the same result as unpacking + * using major() and minor() and repacking in the l_dev_t format. This + * detail is hidden in dev_to_ldev(). Overflow in conversions of dev_t's + * are not checked for, as for other fields. + * + * dev_to_ldev() is only used for translating st_dev. When we convert + * st_rdev for copying it out, it isn't really a dev_t, but has already + * been translated to an l_dev_t in a nontrivial way. Translating it + * again would be illogical but would have no effect since the low 16 + * bits have the same encoding. + * + * The nontrivial translation for st_rdev renumbers some devices, but not + * ones that can be mounted on, so it is consistent with the translation + * for st_dev except when the renumbering or truncation causes conflicts. + */ +#define dev_to_ldev(d) ((uint16_t)(d)) + static int newstat_copyout(struct stat *buf, void *ubuf) { struct l_newstat tbuf; bzero(&tbuf, sizeof(tbuf)); - tbuf.st_dev = minor(buf->st_dev) | (major(buf->st_dev) << 8); + tbuf.st_dev = dev_to_ldev(buf->st_dev); tbuf.st_ino = buf->st_ino; tbuf.st_mode = buf->st_mode; tbuf.st_nlink = buf->st_nlink; @@ -222,7 +241,7 @@ struct l_stat lbuf; bzero(&lbuf, sizeof(lbuf)); - lbuf.st_dev = buf->st_dev; + lbuf.st_dev = dev_to_ldev(buf->st_dev); lbuf.st_ino = buf->st_ino; lbuf.st_mode = buf->st_mode; lbuf.st_nlink = buf->st_nlink; @@ -524,7 +543,7 @@ struct l_stat64 lbuf; bzero(&lbuf, sizeof(lbuf)); - lbuf.st_dev = minor(buf->st_dev) | (major(buf->st_dev) << 8); + lbuf.st_dev = dev_to_ldev(buf->st_dev); lbuf.st_ino = buf->st_ino; lbuf.st_mode = buf->st_mode; lbuf.st_nlink = buf->st_nlink; Index: sys/conf/files =================================================================== --- sys/conf/files +++ sys/conf/files @@ -2833,6 +2833,14 @@ dev/rp/rp_isa.c optional rp isa dev/rp/rp_pci.c optional rp pci # +dev/rt2860/rt2860_fdt.c optional rt2860 fdt +dev/rt2860/rt2860.c optional rt2860 +dev/rt2860/rt2860_amrr.c optional rt2860 +dev/rt2860/rt2860_io.c optional rt2860 +dev/rt2860/rt2860_led.c optional rt2860 +dev/rt2860/rt2860_read_eeprom.c optional rt2860 +dev/rt2860/rt2860_rf.c optional rt2860 +# dev/rtwn/if_rtwn.c optional rtwn dev/rtwn/if_rtwn_beacon.c optional rtwn dev/rtwn/if_rtwn_calib.c optional rtwn Index: sys/conf/files.arm64 =================================================================== --- sys/conf/files.arm64 +++ sys/conf/files.arm64 @@ -208,6 +208,7 @@ dev/pci/pci_host_generic_fdt.c optional pci fdt dev/psci/psci.c standard dev/psci/psci_arm64.S standard +dev/psci/smccc.c standard dev/uart/uart_cpu_arm64.c optional uart dev/uart/uart_dev_mu.c optional uart uart_mu dev/uart/uart_dev_pl011.c optional uart pl011 @@ -245,6 +246,7 @@ cddl/dev/dtrace/aarch64/dtrace_subr.c optional dtrace compile-with "${DTRACE_C}" cddl/dev/fbt/aarch64/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}" +arm64/rockchip/rk_i2c.c optional rk_i2c fdt soc_rockchip_rk3328 arm64/rockchip/rk_grf.c optional fdt soc_rockchip_rk3328 arm64/rockchip/rk_pinctrl.c optional fdt soc_rockchip_rk3328 arm64/rockchip/rk_gpio.c optional fdt soc_rockchip_rk3328 @@ -255,3 +257,6 @@ arm64/rockchip/clk/rk_clk_mux.c optional fdt soc_rockchip_rk3328 arm64/rockchip/clk/rk_clk_pll.c optional fdt soc_rockchip_rk3328 arm64/rockchip/clk/rk3328_cru.c optional fdt soc_rockchip_rk3328 +arm64/rockchip/if_dwc_rk.c optional dwc_rk fdt soc_rockchip_rk3328 +dev/dwc/if_dwc.c optional dwc_rk +dev/dwc/if_dwc_if.m optional dwc_rk Index: sys/dev/aacraid/aacraid_pci.c =================================================================== --- sys/dev/aacraid/aacraid_pci.c +++ sys/dev/aacraid/aacraid_pci.c @@ -85,9 +85,6 @@ static devclass_t aacraid_devclass; -DRIVER_MODULE(aacraid, pci, aacraid_pci_driver, aacraid_devclass, 0, 0); -MODULE_DEPEND(aacraid, pci, 1, 1, 1); - struct aac_ident { u_int16_t vendor; @@ -107,6 +104,12 @@ {0, 0, 0, 0, 0, 0, 0} }; +DRIVER_MODULE(aacraid, pci, aacraid_pci_driver, aacraid_devclass, 0, 0); +MODULE_PNP_INFO("U16:vendor;U16:device", pci, aacraid, + aacraid_family_identifiers, sizeof(aacraid_family_identifiers[0]), + nitems(aacraid_family_identifiers) - 1); +MODULE_DEPEND(aacraid, pci, 1, 1, 1); + static struct aac_ident * aac_find_ident(device_t dev) { Index: sys/dev/ae/if_ae.c =================================================================== --- sys/dev/ae/if_ae.c +++ sys/dev/ae/if_ae.c @@ -177,6 +177,8 @@ static devclass_t ae_devclass; DRIVER_MODULE(ae, pci, ae_driver, ae_devclass, 0, 0); +MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, ae, ae_devs, + sizeof(ae_devs[0]), nitems(ae_devs)); DRIVER_MODULE(miibus, ae, miibus_driver, miibus_devclass, 0, 0); MODULE_DEPEND(ae, pci, 1, 1, 1); MODULE_DEPEND(ae, ether, 1, 1, 1); Index: sys/dev/age/if_age.c =================================================================== --- sys/dev/age/if_age.c +++ sys/dev/age/if_age.c @@ -183,6 +183,8 @@ static devclass_t age_devclass; DRIVER_MODULE(age, pci, age_driver, age_devclass, 0, 0); +MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, age, age_devs, + sizeof(age_devs[0]), nitems(age_devs)); DRIVER_MODULE(miibus, age, miibus_driver, miibus_devclass, 0, 0); static struct resource_spec age_res_spec_mem[] = { Index: sys/dev/ahci/ahci_pci.c =================================================================== --- sys/dev/ahci/ahci_pci.c +++ sys/dev/ahci/ahci_pci.c @@ -664,6 +664,9 @@ sizeof(struct ahci_controller) }; DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, NULL, NULL); +/* Also matches class / subclass / progid XXX need to add when we have masking support */ +MODULE_PNP_INFO("W32:vendor/device", pci, ahci, ahci_ids, + sizeof(ahci_ids[0]), nitems(ahci_ids) - 1); static device_method_t ahci_ata_methods[] = { DEVMETHOD(device_probe, ahci_ata_probe), DEVMETHOD(device_attach, ahci_pci_attach), Index: sys/dev/ale/if_ale.c =================================================================== --- sys/dev/ale/if_ale.c +++ sys/dev/ale/if_ale.c @@ -178,6 +178,8 @@ static devclass_t ale_devclass; DRIVER_MODULE(ale, pci, ale_driver, ale_devclass, NULL, NULL); +MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, ale, ale_devs, + sizeof(ale_devs[0]), nitems(ale_devs)); DRIVER_MODULE(miibus, ale, miibus_driver, miibus_devclass, NULL, NULL); static struct resource_spec ale_res_spec_mem[] = { Index: sys/dev/amr/amr_pci.c =================================================================== --- sys/dev/amr/amr_pci.c +++ sys/dev/amr/amr_pci.c @@ -116,15 +116,10 @@ sizeof(struct amr_softc) }; -static devclass_t amr_devclass; -DRIVER_MODULE(amr, pci, amr_pci_driver, amr_devclass, 0, 0); -MODULE_DEPEND(amr, pci, 1, 1, 1); -MODULE_DEPEND(amr, cam, 1, 1, 1); - static struct amr_ident { - int vendor; - int device; + uint16_t vendor; + uint16_t device; int flags; #define AMR_ID_PROBE_SIG (1<<0) /* generic i960RD, check signature */ #define AMR_ID_DO_SG64 (1<<1) @@ -144,6 +139,13 @@ {0, 0, 0} }; +static devclass_t amr_devclass; +DRIVER_MODULE(amr, pci, amr_pci_driver, amr_devclass, 0, 0); +MODULE_PNP_INFO("U16:vendor;U16:device", pci, amr, amr_device_ids, + sizeof(amr_device_ids[0]), nitems(amr_device_ids) - 1); +MODULE_DEPEND(amr, pci, 1, 1, 1); +MODULE_DEPEND(amr, cam, 1, 1, 1); + static struct amr_ident * amr_find_ident(device_t dev) { Index: sys/dev/an/if_an_pci.c =================================================================== --- sys/dev/an/if_an_pci.c +++ sys/dev/an/if_an_pci.c @@ -273,5 +273,7 @@ static devclass_t an_devclass; DRIVER_MODULE(an, pci, an_pci_driver, an_devclass, 0, 0); +MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, an, + an_devs, sizeof(an_devs[0]), nitems(an_devs) - 1); MODULE_DEPEND(an, pci, 1, 1, 1); MODULE_DEPEND(an, wlan, 1, 1, 1); Index: sys/dev/bwi/if_bwi_pci.c =================================================================== --- sys/dev/bwi/if_bwi_pci.c +++ sys/dev/bwi/if_bwi_pci.c @@ -256,6 +256,8 @@ }; static devclass_t bwi_devclass; DRIVER_MODULE(bwi, pci, bwi_driver, bwi_devclass, 0, 0); +MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, bwi, bwi_devices, + sizeof(bwi_devices[0]), nitems(bwi_devices) - 1); MODULE_DEPEND(bwi, wlan, 1, 1, 1); /* 802.11 media layer */ MODULE_DEPEND(bwi, firmware, 1, 1, 1); /* firmware support */ MODULE_DEPEND(bwi, wlan_amrr, 1, 1, 1); Index: sys/dev/bwn/if_bwn_pci.c =================================================================== --- sys/dev/bwn/if_bwn_pci.c +++ sys/dev/bwn/if_bwn_pci.c @@ -295,6 +295,10 @@ sizeof(struct bwn_pci_softc)); DRIVER_MODULE_ORDERED(bwn_pci, pci, bwn_pci_driver, bwn_pci_devclass, NULL, NULL, SI_ORDER_ANY); +MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, bwn_siba, + siba_devices, sizeof(siba_devices[0]), nitems(siba_devices) - 1); +MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, bwn_bcma, + bcma_devices, sizeof(bcma_devices[0]), nitems(bcma_devices) - 1); DRIVER_MODULE(bhndb, bwn_pci, bhndb_pci_driver, bhndb_devclass, NULL, NULL); MODULE_DEPEND(bwn_pci, bwn, 1, 1, 1); Index: sys/dev/cxgbe/t4_main.c =================================================================== --- sys/dev/cxgbe/t4_main.c +++ sys/dev/cxgbe/t4_main.c @@ -1663,7 +1663,7 @@ static int cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data) { - int rc = 0, mtu, flags, can_sleep; + int rc = 0, mtu, flags; struct vi_info *vi = ifp->if_softc; struct port_info *pi = vi->pi; struct adapter *sc = pi->adapter; @@ -1689,59 +1689,36 @@ break; case SIOCSIFFLAGS: - can_sleep = 0; -redo_sifflags: - rc = begin_synchronized_op(sc, vi, - can_sleep ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4flg"); - if (rc) { - if_printf(ifp, "%ssleepable synch operation failed: %d." - " if_flags 0x%08x, if_drv_flags 0x%08x\n", - can_sleep ? "" : "non-", rc, ifp->if_flags, - ifp->if_drv_flags); + rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4flg"); + if (rc) return (rc); - } if (ifp->if_flags & IFF_UP) { if (ifp->if_drv_flags & IFF_DRV_RUNNING) { flags = vi->if_flags; if ((ifp->if_flags ^ flags) & (IFF_PROMISC | IFF_ALLMULTI)) { - if (can_sleep == 1) { - end_synchronized_op(sc, 0); - can_sleep = 0; - goto redo_sifflags; - } rc = update_mac_settings(ifp, XGMAC_PROMISC | XGMAC_ALLMULTI); } } else { - if (can_sleep == 0) { - end_synchronized_op(sc, LOCK_HELD); - can_sleep = 1; - goto redo_sifflags; - } rc = cxgbe_init_synchronized(vi); } vi->if_flags = ifp->if_flags; } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) { - if (can_sleep == 0) { - end_synchronized_op(sc, LOCK_HELD); - can_sleep = 1; - goto redo_sifflags; - } rc = cxgbe_uninit_synchronized(vi); } - end_synchronized_op(sc, can_sleep ? 0 : LOCK_HELD); + end_synchronized_op(sc, 0); break; case SIOCADDMULTI: - case SIOCDELMULTI: /* these two are called with a mutex held :-( */ - rc = begin_synchronized_op(sc, vi, HOLD_LOCK, "t4multi"); + case SIOCDELMULTI: + rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4multi"); if (rc) return (rc); if (ifp->if_drv_flags & IFF_DRV_RUNNING) rc = update_mac_settings(ifp, XGMAC_MCADDRS); - end_synchronized_op(sc, LOCK_HELD); + end_synchronized_op(sc, 0); break; case SIOCSIFCAP: Index: sys/dev/ncr/ncr.c =================================================================== --- sys/dev/ncr/ncr.c +++ sys/dev/ncr/ncr.c @@ -3169,8 +3169,8 @@ **---------------------------------------------------------- */ typedef struct { - unsigned long device_id; - unsigned short minrevid; + uint32_t device_id; + uint16_t minrevid; char *name; unsigned char maxburst; unsigned char maxoffs; @@ -3225,7 +3225,7 @@ FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM} }; -static int ncr_chip_lookup(u_long device_id, u_char revision_id) +static int ncr_chip_lookup(uint32_t device_id, u_char revision_id) { int i, found; @@ -7108,6 +7108,8 @@ static devclass_t ncr_devclass; DRIVER_MODULE(ncr, pci, ncr_driver, ncr_devclass, 0, 0); +MODULE_PNP_INFO("W32:vendor/device;U16:#;D:#", pci, ncr, ncr_chip_table, + sizeof(ncr_chip_table[0]), nitems(ncr_chip_table)); MODULE_DEPEND(ncr, cam, 1, 1, 1); MODULE_DEPEND(ncr, pci, 1, 1, 1); Index: sys/dev/psci/psci.h =================================================================== --- sys/dev/psci/psci.h +++ sys/dev/psci/psci.h @@ -36,12 +36,23 @@ extern int psci_present; -void psci_reset(void); int psci_cpu_on(unsigned long, unsigned long, unsigned long); +void psci_reset(void); +int32_t psci_features(uint32_t); +int psci_get_version(void); + +/* Handler to let us call into the PSCI/SMCCC firmware */ +extern psci_callfn_t psci_callfn; +static inline int +psci_call(register_t a, register_t b, register_t c, register_t d) +{ + + return (psci_callfn(a, b, c, d)); +} +/* One of these handlers will be selected during the boot */ int psci_hvc_despatch(register_t, register_t, register_t, register_t); int psci_smc_despatch(register_t, register_t, register_t, register_t); -int psci_get_version(void); /* * PSCI return codes. @@ -74,6 +85,7 @@ #define PSCI_FNID_MIGRATE_INFO_UP_CPU 0xc4000007 #define PSCI_FNID_SYSTEM_OFF 0x84000008 #define PSCI_FNID_SYSTEM_RESET 0x84000009 +#define PSCI_FNID_FEATURES 0x8400000a #else #define PSCI_FNID_VERSION 0x84000000 #define PSCI_FNID_CPU_SUSPEND 0x84000001 @@ -85,6 +97,7 @@ #define PSCI_FNID_MIGRATE_INFO_UP_CPU 0x84000007 #define PSCI_FNID_SYSTEM_OFF 0x84000008 #define PSCI_FNID_SYSTEM_RESET 0x84000009 +#define PSCI_FNID_FEATURES 0x8400000a #endif #define PSCI_VER_MAJOR(v) (((v) >> 16) & 0xFF) Index: sys/dev/psci/psci.c =================================================================== --- sys/dev/psci/psci.c +++ sys/dev/psci/psci.c @@ -74,6 +74,7 @@ struct psci_softc { device_t dev; + uint32_t psci_version; uint32_t psci_fnids[PSCI_FN_MAX]; }; @@ -109,14 +110,7 @@ static int psci_find_callfn(psci_callfn_t *); static int psci_def_callfn(register_t, register_t, register_t, register_t); -static psci_callfn_t psci_callfn = psci_def_callfn; - -static inline int -psci_call(register_t a, register_t b, register_t c, register_t d) -{ - - return (psci_callfn(a, b, c, d)); -} +psci_callfn_t psci_callfn = psci_def_callfn; static void psci_init(void *dummy) @@ -413,6 +407,20 @@ return (PSCI_RETVAL_SUCCESS); } +int32_t +psci_features(uint32_t psci_func_id) +{ + + if (psci_softc == NULL) + return (PSCI_RETVAL_NOT_SUPPORTED); + + /* The feature flags were added to PSCI 1.0 */ + if (PSCI_VER_MAJOR(psci_softc->psci_version) < 1) + return (PSCI_RETVAL_NOT_SUPPORTED); + + return (psci_call(PSCI_FNID_FEATURES, psci_func_id, 0, 0)); +} + int psci_cpu_on(unsigned long cpu, unsigned long entry, unsigned long context_id) { @@ -493,6 +501,7 @@ sc->psci_fnids[PSCI_FN_MIGRATE] = psci_fnid; } + sc->psci_version = (0 << 16) | 1; if (bootverbose) device_printf(dev, "PSCI version 0.1 available\n"); @@ -523,6 +532,7 @@ if (version == PSCI_RETVAL_NOT_SUPPORTED) return (1); + sc->psci_version = version; if ((PSCI_VER_MAJOR(version) == 0 && PSCI_VER_MINOR(version) == 2) || PSCI_VER_MAJOR(version) == 1) { if (bootverbose) Index: sys/dev/psci/smccc.h =================================================================== --- sys/dev/psci/smccc.h +++ sys/dev/psci/smccc.h @@ -1,9 +1,10 @@ /*- - * Copyright (c) 2013-2014 Robert N. M. Watson - * All rights reserved. + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2018 Andrew Turner * * This software was developed by SRI International and the University of - * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) + * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 * ("CTSRD"), as part of the DARPA CRASH research programme. * * Redistribution and use in source and binary forms, with or without @@ -30,35 +31,42 @@ * $FreeBSD$ */ -#ifndef _BOOT_LOADER_H_ -#define _BOOT_LOADER_H_ +#ifndef _PSCI_SMCCC_H_ +#define _PSCI_SMCCC_H_ + +#define SMCCC_VERSION_MAJOR(ver) (((ver) >> 16) & 0x7fff) +#define SMCCC_VERSION_MINOR(ver) ((ver) & 0xffff) -/* beri_console.c */ -extern struct console altera_jtag_uart_console; +#define SMCCC_FUNC_ID(type, call_conv, range, func) \ + (((type) << 31) | \ + ((call_conv) << 30) | \ + (((range) & 0x3f) << 24) | \ + ((func) & 0xffff)) -/* beri_disk.c */ -extern struct devsw beri_cfi_disk; -extern struct devsw beri_sdcard_disk; +#define SMCCC_YIELDING_CALL 0 +#define SMCCC_FAST_CALL 1 -/* devicename.c */ -struct env_var; -int beri_arch_setcurrdev(struct env_var *, int, const void *); -char *beri_arch_fmtdev(void *); -int beri_arch_getdev(void **, const char *, const char **); +#define SMCCC_32BIT_CALL 0 +#define SMCCC_64BIT_CALL 1 -/* exec.c */ -extern struct file_format beri_elf; +/* + * Arm Architecture Calls. + * These are documented in the document ARM DEN 0070A. + */ +#define SMCCC_VERSION \ + SMCCC_FUNC_ID(SMCCC_FAST_CALL, SMCCC_64BIT_CALL, 0, 0) +#define SMCCC_ARCH_FEATURES \ + SMCCC_FUNC_ID(SMCCC_FAST_CALL, SMCCC_64BIT_CALL, 0, 1) +#define SMCCC_ARCH_WORKAROUND_1 \ + SMCCC_FUNC_ID(SMCCC_FAST_CALL, SMCCC_64BIT_CALL, 0, 0x8000) -/* main.c */ -extern int boot2_argc; -extern char **boot2_argv; -extern char **boot2_envv; -extern struct bootinfo boot2_bootinfo; +/* The return values from ARM DEN 0070A. */ +#define SMCCC_RET_SUCCESS 0 +#define SMCCC_RET_NOT_SUPPORTED -1 +#define SMCCC_RET_NOT_REQUIRED -2 -/* metadata.c */ -int md_load64(char *args, vm_offset_t *modulep, vm_offset_t *dtbp); +int32_t smccc_arch_features(uint32_t); +int smccc_arch_workaround_1(void); -/* vers.c */ -extern char bootprog_info[]; -#endif /* !_BOOT_LOADER_H_ */ +#endif /* _PSCI_SMCCC_H_ */ Index: sys/dev/psci/smccc.c =================================================================== --- sys/dev/psci/smccc.c +++ sys/dev/psci/smccc.c @@ -2,7 +2,6 @@ * SPDX-License-Identifier: BSD-2-Clause * * Copyright (c) 2018 Andrew Turner - * All rights reserved. * * This software was developed by SRI International and the University of * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 @@ -30,70 +29,65 @@ * SUCH DAMAGE. */ +#include "opt_acpi.h" #include "opt_platform.h" #include __FBSDID("$FreeBSD$"); #include +#include #include -#include - -#include #include +#include -typedef void (cpu_quirk_install)(void); -struct cpu_quirks { - cpu_quirk_install *quirk_install; - u_int midr_mask; - u_int midr_value; -}; - -static cpu_quirk_install install_psci_bp_hardening; +#define SMCCC_VERSION_1_0 0x10000 -static struct cpu_quirks cpu_quirks[] = { - { - .midr_mask = CPU_IMPL_MASK | CPU_PART_MASK, - .midr_value = CPU_ID_RAW(CPU_IMPL_ARM, CPU_PART_CORTEX_A57,0,0), - .quirk_install = install_psci_bp_hardening, - }, - { - .midr_mask = CPU_IMPL_MASK | CPU_PART_MASK, - .midr_value = CPU_ID_RAW(CPU_IMPL_ARM, CPU_PART_CORTEX_A72,0,0), - .quirk_install = install_psci_bp_hardening, - }, - { - .midr_mask = CPU_IMPL_MASK | CPU_PART_MASK, - .midr_value = CPU_ID_RAW(CPU_IMPL_ARM, CPU_PART_CORTEX_A73,0,0), - .quirk_install = install_psci_bp_hardening, - }, - { - .midr_mask = CPU_IMPL_MASK | CPU_PART_MASK, - .midr_value = CPU_ID_RAW(CPU_IMPL_ARM, CPU_PART_CORTEX_A75,0,0), - .quirk_install = install_psci_bp_hardening, - }, -}; +/* Assume 1.0 until we detect a later version */ +static uint32_t smccc_version = SMCCC_VERSION_1_0; static void -install_psci_bp_hardening(void) +smccc_init(void *dummy) { + int32_t features; + uint32_t ret; + + features = psci_features(SMCCC_VERSION); + if (features != PSCI_RETVAL_NOT_SUPPORTED) { + ret = psci_call(SMCCC_VERSION, 0, 0, 0); + /* This should always be the case as we checked it above */ + if (ret > 0) + smccc_version = ret; + } - PCPU_SET(bp_harden, psci_get_version); + if (bootverbose) { + printf("Found SMCCC version %u.%u\n", + SMCCC_VERSION_MAJOR(smccc_version), + SMCCC_VERSION_MINOR(smccc_version)); + } } +SYSINIT(smccc_start, SI_SUB_DRIVERS, SI_ORDER_ANY, smccc_init, NULL); -void -install_cpu_errata(void) +int32_t +smccc_arch_features(uint32_t smccc_func_id) { - u_int midr; - size_t i; - midr = get_midr(); + if (smccc_version == SMCCC_VERSION_1_0) + return (PSCI_RETVAL_NOT_SUPPORTED); - for (i = 0; i < nitems(cpu_quirks); i++) { - if ((midr & cpu_quirks[i].midr_mask) == - cpu_quirks[i].midr_value) { - cpu_quirks[i].quirk_install(); - } - } + return (psci_call(SMCCC_ARCH_FEATURES, smccc_func_id, 0, 0)); +} + +/* + * The SMCCC handler for Spectre variant 2: Branch target injection. + * (CVE-2017-5715) + */ +int +smccc_arch_workaround_1(void) +{ + + KASSERT(smccc_version != SMCCC_VERSION_1_0, + ("SMCCC arch workaround 1 called with an invalid SMCCC interface")); + return (psci_call(SMCCC_ARCH_WORKAROUND_1, 0, 0, 0)); } Index: sys/dev/rt2860/rt2860.c =================================================================== --- /dev/null +++ sys/dev/rt2860/rt2860.c @@ -0,0 +1,7097 @@ + +/*- + * Copyright (c) 2009-2010 Alexander Egorenkov + * Copyright (c) 2009 Damien Bergamini + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Defines and macros + */ + +#define RT2860_MAX_AGG_SIZE 3840 + +#define RT2860_TX_DATA_SEG0_SIZE \ + (sizeof(struct rt2860_txwi) + sizeof(struct ieee80211_qosframe_addr4)) + +#define RT2860_NOISE_FLOOR -95 + +#define IEEE80211_HAS_ADDR4(wh) \ + (((wh)->i_fc[1] & IEEE80211_FC1_DIR_MASK) == IEEE80211_FC1_DIR_DSTODS) + +#define RT2860_MS(_v, _f) (((_v) & _f) >> _f##_S) +#define RT2860_SM(_v, _f) (((_v) << _f##_S) & _f) + +#define RT2860_TX_WATCHDOG_TIMEOUT 5 + +#define RUN_AID2WCID(aid) ((aid) & 0xff) +#define RT2860_WCID_RESERVED 0xff +#define RT2860_WCID_MCAST 0xf7 + +/* + * Global function prototypes, used in bus depended interfaces + */ + +int rt2860_attach(device_t dev, int id); + +int rt2860_detach(device_t dev); + +int rt2860_shutdown(device_t dev); + +int rt2860_suspend(device_t dev); + +int rt2860_resume(device_t dev); + +/* + * Static function prototypes + */ + +static void rt2860_init_channels(struct rt2860_softc *sc); + +static void rt2860_init_channels_ht40(struct rt2860_softc *sc); + +static void rt2860_init_locked(void *priv); + +static void rt2860_init(void *priv); + +static int rt2860_init_bbp(struct rt2860_softc *sc); + +static void rt2860_stop_locked(void *priv); + +static void rt2860_stop(void *priv); + +static void rt2860_start(struct rt2860_softc *sc); + +static struct ieee80211vap *rt2860_vap_create(struct ieee80211com *ic, + const char name[IFNAMSIZ], int unit, enum ieee80211_opmode, int flags, + const uint8_t bssid[IEEE80211_ADDR_LEN], + const uint8_t mac[IEEE80211_ADDR_LEN]); + +static void rt2860_vap_delete(struct ieee80211vap *vap); + +static int rt2860_vap_reset(struct ieee80211vap *vap, u_long cmd); + +static int rt2860_vap_newstate(struct ieee80211vap *vap, + enum ieee80211_state nstate, int arg); + +#ifdef RT2860_HW_CRYPTO +static void rt2860_vap_key_update_begin(struct ieee80211vap *vap); + +static void rt2860_vap_key_update_end(struct ieee80211vap *vap); + +static int rt2860_vap_key_set(struct ieee80211vap *vap, + const struct ieee80211_key *k); + +static int rt2860_vap_key_delete(struct ieee80211vap *vap, + const struct ieee80211_key *k); +#endif + +static void rt2860_vap_update_beacon(struct ieee80211vap *vap, int what); + +static struct ieee80211_node *rt2860_node_alloc(struct ieee80211vap *vap, + const uint8_t mac[IEEE80211_ADDR_LEN]); + +static void rt2860_node_cleanup(struct ieee80211_node *ni); + +static int rt2860_setregdomain(struct ieee80211com *ic, + struct ieee80211_regdomain *reg, + int nchans, struct ieee80211_channel chans[]); + +static void rt2860_getradiocaps(struct ieee80211com *ic, + int maxchans, int *nchans, struct ieee80211_channel chans[]); + +static void rt2860_scan_start(struct ieee80211com *ic); + +static void rt2860_scan_end(struct ieee80211com *ic); + +static void rt2860_set_channel(struct ieee80211com *ic); + +static void rt2860_newassoc(struct ieee80211_node *ni, int isnew); + +static void rt2860_updateslot(struct ieee80211com *ic); + +static void rt2860_update_promisc(struct ieee80211com *ic); + +static int rt2860_wme_update(struct ieee80211com *ic); + +static int rt2860_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, + const struct ieee80211_bpf_params *params); + +static int rt2860_recv_action(struct ieee80211_node *ni, + const struct ieee80211_frame *wh, + const uint8_t *frm, const uint8_t *efrm); + +static int rt2860_send_action(struct ieee80211_node *ni, + int cat, int act, void *sa); + +static int rt2860_addba_response(struct ieee80211_node *ni, + struct ieee80211_tx_ampdu *tap, + int status, int baparamset, int batimeout); + +static void rt2860_addba_stop(struct ieee80211_node *ni, + struct ieee80211_tx_ampdu *tap); + +static int rt2860_ampdu_rx_start(struct ieee80211_node *ni, + struct ieee80211_rx_ampdu *rap, + int baparamset, int batimeout, int baseqctl); + +static void rt2860_ampdu_rx_stop(struct ieee80211_node *ni, + struct ieee80211_rx_ampdu *rap); + +static int rt2860_send_bar(struct ieee80211_node *ni, + struct ieee80211_tx_ampdu *tap, ieee80211_seq seqno); + +static void rt2860_amrr_update_iter_func(void *arg, struct ieee80211_node *ni); + +static void rt2860_periodic(void *arg); + +static void rt2860_tx_watchdog(void *arg); + +static int rt2860_staid_alloc(struct rt2860_softc *sc, int aid); + +static void rt2860_staid_delete(struct rt2860_softc *sc, int staid); + +static void rt2860_asic_set_bssid(struct rt2860_softc *sc, + const uint8_t *bssid); + +static void rt2860_asic_set_macaddr(struct rt2860_softc *sc, + const uint8_t *addr); + +static void rt2860_parent(struct ieee80211com *); +static int rt2860_transmit(struct ieee80211com *, struct mbuf *); + +static void rt2860_asic_enable_tsf_sync(struct rt2860_softc *sc); + +static void rt2860_asic_disable_tsf_sync(struct rt2860_softc *sc); + +static void rt2860_asic_enable_mrr(struct rt2860_softc *sc); + +static void rt2860_asic_set_txpreamble(struct rt2860_softc *sc); + +static void rt2860_asic_set_basicrates(struct rt2860_softc *sc); + +static void rt2860_asic_update_rtsthreshold(struct rt2860_softc *sc); + +static void rt2860_asic_update_txpower(struct rt2860_softc *sc); + +static void rt2860_asic_update_promisc(struct rt2860_softc *sc); + +static void rt2860_asic_updateprot(struct rt2860_softc *sc); + +static void rt2860_asic_updateslot(struct rt2860_softc *sc); + +static void rt2860_asic_wme_update(struct rt2860_softc *sc); + +static void rt2860_asic_update_beacon(struct rt2860_softc *sc, + struct ieee80211vap *vap); + +static void rt2860_asic_clear_keytables(struct rt2860_softc *sc); + +static void rt2860_asic_add_ba_session(struct rt2860_softc *sc, + uint8_t wcid, int tid); + +static void rt2860_asic_del_ba_session(struct rt2860_softc *sc, + uint8_t wcid, int tid); + +static int rt2860_beacon_alloc(struct rt2860_softc *sc, + struct ieee80211vap *vap); + +static uint8_t rt2860_rxrate(struct rt2860_rxwi *rxwi); + +static uint8_t rt2860_maxrssi_rxpath(struct rt2860_softc *sc, + const struct rt2860_rxwi *rxwi); + +static int8_t rt2860_rssi2dbm(struct rt2860_softc *sc, + uint8_t rssi, uint8_t rxpath); + +static uint8_t rt2860_rate2mcs(uint8_t rate); + +static int rt2860_tx_mgmt(struct rt2860_softc *sc, + struct mbuf *m, struct ieee80211_node *ni, int qid); + +static int rt2860_tx_data(struct rt2860_softc *sc, + struct mbuf *m, struct ieee80211_node *ni, int qid); + +/* +static int rt2860_tx_raw(struct rt2860_softc *sc, + struct mbuf *m, struct ieee80211_node *ni, + const struct ieee80211_bpf_params *params); +*/ + +static void rt2860_intr(void *arg); + +static void rt2860_tx_coherent_intr(struct rt2860_softc *sc); + +static void rt2860_rx_coherent_intr(struct rt2860_softc *sc); + +static void rt2860_txrx_coherent_intr(struct rt2860_softc *sc); + +static void rt2860_fifo_sta_full_intr(struct rt2860_softc *sc); + +static void rt2860_rx_intr(struct rt2860_softc *sc); + +static void rt2860_rx_delay_intr(struct rt2860_softc *sc); + +static void rt2860_tx_intr(struct rt2860_softc *sc, int qid); + +static void rt2860_tx_delay_intr(struct rt2860_softc *sc); + +static void rt2860_pre_tbtt_intr(struct rt2860_softc *sc); + +static void rt2860_tbtt_intr(struct rt2860_softc *sc); + +static void rt2860_mcu_cmd_intr(struct rt2860_softc *sc); + +static void rt2860_auto_wakeup_intr(struct rt2860_softc *sc); + +static void rt2860_gp_timer_intr(struct rt2860_softc *sc); + +static void rt2860_rx_done_task(void *context, int pending); + +static void rt2860_tx_done_task(void *context, int pending); + +static void rt2860_fifo_sta_full_task(void *context, int pending); + +static void rt2860_periodic_task(void *context, int pending); + +static int rt2860_rx_eof(struct rt2860_softc *sc, int limit); + +static void rt2860_tx_eof(struct rt2860_softc *sc, + struct rt2860_softc_tx_ring *ring); + +static void rt2860_update_stats(struct rt2860_softc *sc); + +static void rt2860_bbp_tuning(struct rt2860_softc *sc); + +static void rt2860_watchdog(struct rt2860_softc *sc); + +static void rt2860_drain_fifo_stats(struct rt2860_softc *sc); + +static void rt2860_update_raw_counters(struct rt2860_softc *sc); + +static void rt2860_intr_enable(struct rt2860_softc *sc, uint32_t intr_mask); + +static void rt2860_intr_disable(struct rt2860_softc *sc, uint32_t intr_mask); + +static int rt2860_txrx_enable(struct rt2860_softc *sc); + +static int rt2860_alloc_rx_ring(struct rt2860_softc *sc, + struct rt2860_softc_rx_ring *ring); + +static void rt2860_reset_rx_ring(struct rt2860_softc *sc, + struct rt2860_softc_rx_ring *ring); + +static void rt2860_free_rx_ring(struct rt2860_softc *sc, + struct rt2860_softc_rx_ring *ring); + +static int rt2860_alloc_tx_ring(struct rt2860_softc *sc, + struct rt2860_softc_tx_ring *ring, int qid); + +static void rt2860_reset_tx_ring(struct rt2860_softc *sc, + struct rt2860_softc_tx_ring *ring); + +static void rt2860_free_tx_ring(struct rt2860_softc *sc, + struct rt2860_softc_tx_ring *ring); + +static void rt2860_dma_map_addr(void *arg, bus_dma_segment_t *segs, + int nseg, int error); + +static void rt2860_sysctl_attach(struct rt2860_softc *sc); + +/* + * Static variables + */ + +static const struct +{ + uint32_t reg; + uint32_t val; +} rt2860_def_mac[] = +{ +#if 1 + { RT2860_REG_PBF_BCN_OFFSET0, 0xf8f0e8e0 }, + { RT2860_REG_PBF_BCN_OFFSET1, 0x6f77d0c8 }, + { RT2860_REG_LEGACY_BASIC_RATE, 0x0000013f }, + { RT2860_REG_HT_BASIC_RATE, 0x00008003 }, + { RT2860_REG_SYS_CTRL, 0x00000000 }, + { RT2860_REG_RX_FILTER_CFG, 0x00017f97 }, + { RT2860_REG_BKOFF_SLOT_CFG, 0x00000209 }, + { RT2860_REG_TX_SW_CFG0, 0x00000000 }, + { RT2860_REG_TX_SW_CFG1, 0x00080606 }, + { RT2860_REG_TX_LINK_CFG, 0x00001020 }, + { RT2860_REG_TX_TIMEOUT_CFG, 0x000a2090 }, + { RT2860_REG_MAX_LEN_CFG, (1 << 12) | RT2860_MAX_AGG_SIZE }, + { RT2860_REG_LED_CFG, 0x7f031e46 }, + { RT2860_REG_PBF_MAX_PCNT, 0x1f3fbf9f }, + { RT2860_REG_TX_RTY_CFG, 0x47d01f0f }, + { RT2860_REG_AUTO_RSP_CFG, 0x00000013 }, + { RT2860_REG_TX_CCK_PROT_CFG, 0x05740003 }, + { RT2860_REG_TX_OFDM_PROT_CFG, 0x05740003 }, + { RT2860_REG_TX_GF20_PROT_CFG, 0x01744004 }, + { RT2860_REG_TX_GF40_PROT_CFG, 0x03f44084 }, + { RT2860_REG_TX_MM20_PROT_CFG, 0x01744004 }, + { RT2860_REG_TX_MM40_PROT_CFG, 0x03f54084 }, + { RT2860_REG_TX_TXOP_CTRL_CFG, 0x0000583f }, + { RT2860_REG_TX_RTS_CFG, 0x00092b20 }, + { RT2860_REG_TX_EXP_ACK_TIME, 0x002400ca }, + { RT2860_REG_HCCAPSMP_TXOP_HLDR_ET, 0x00000002 }, + { RT2860_REG_XIFS_TIME_CFG, 0x33a41010 }, + { RT2860_REG_PWR_PIN_CFG, 0x00000003 }, + { RT2860_REG_SCHDMA_WMM_AIFSN_CFG, 0x00002273 }, + { RT2860_REG_SCHDMA_WMM_CWMIN_CFG, 0x00002344 }, + { RT2860_REG_SCHDMA_WMM_CWMAX_CFG, 0x000034aa }, +#else + + { RT2860_REG_PBF_BCN_OFFSET0, 0xf8f0e8e0}, /* 0x3800(e0), 0x3A00(e8), 0x3C00(f0), 0x3E00(f8), 512B for each beacon */ + { RT2860_REG_PBF_BCN_OFFSET1, 0x6f77d0c8}, /* 0x3200(c8), 0x3400(d0), 0x1DC0(77), 0x1BC0(6f), 512B for each beacon */ + { RT2860_REG_LEGACY_BASIC_RATE, 0x0000013f}, // Basic rate set bitmap + { RT2860_REG_HT_BASIC_RATE, 0x00008003}, // Basic HT rate set , 20M, MCS=3, MM. Format is the same as in TXWI. + { RT2860_REG_SYS_CTRL, 0x00000000}, // 0x1004, , default Disable RX + { RT2860_REG_RX_FILTER_CFG, 0x00017f97}, //0x1400 , RX filter control, + { RT2860_REG_BKOFF_SLOT_CFG, 0x00000209}, // default set short slot time, CC_DELAY_TIME should be 2 + { RT2860_REG_TX_SW_CFG0, 0x00000400}, // Gary,2008-05-21 0x0 for CWC test , 2008-06-19 0x400 for rf reason + { RT2860_REG_TX_SW_CFG1, 0x00000000}, // Gary,2008-06-18 + { RT2860_REG_TX_SW_CFG2, 0x00000030}, // Bruce, CwC IOT issue + { RT2860_REG_TX_LINK_CFG, 0x00001020}, // Gary,2006-08-23 + { RT2860_REG_TX_TIMEOUT_CFG, 0x000a2090}, // CCK has some problem. So increase timieout value. 2006-10-09// MArvek RT , Modify for 2860E ,2007-08-01 + { RT2860_REG_MAX_LEN_CFG, (1 << 12) | RT2860_MAX_AGG_SIZE }, // 0x3018, MAX frame length. Max PSDU = 16kbytes. + { RT2860_REG_LED_CFG, 0x7f031e46}, // Gary, 2006-08-23 + { RT2860_REG_PBF_MAX_PCNT, 0x1F3FBF9F}, //0x1F3f7f9f}, //Jan, 2006/04/20 + { RT2860_REG_TX_RTY_CFG, 0x47d01f0f}, // Jan, 2006/11/16, Set TxWI->ACK =0 in Probe Rsp Modify for 2860E ,2007-08-03 + { RT2860_REG_AUTO_RSP_CFG, 0x00000053}, // Initial Auto_Responder, because QA will turn off Auto-Responder + { RT2860_REG_TX_CCK_PROT_CFG, 0x05740003}, // Initial Auto_Responder, because QA will turn off Auto-Responder. And RTS threshold is enabled. + { RT2860_REG_TX_OFDM_PROT_CFG, 0x05740003}, // Initial Auto_Responder, because QA will turn off Auto-Responder. And RTS threshold is enabled. + { RT2860_REG_TX_GF20_PROT_CFG, 0x01744004}, // set 19:18 --> Short NAV for MIMO PS + { RT2860_REG_TX_GF40_PROT_CFG, 0x03F44084}, + { RT2860_REG_TX_MM20_PROT_CFG, 0x01744004}, + { RT2860_REG_TX_MM40_PROT_CFG, 0x03F54084}, + { RT2860_REG_TX_TXOP_CTRL_CFG, 0x0000583f}, //Extension channel backoff. + { RT2860_REG_TX_RTS_CFG, 0x00092b20}, + { RT2860_REG_TX_EXP_ACK_TIME, 0x002400ca}, // default value + { RT2860_REG_HCCAPSMP_TXOP_HLDR_ET, 0x00000002}, + { RT2860_REG_XIFS_TIME_CFG, 0x33a41010}, + { RT2860_REG_PWR_PIN_CFG, 0x00000003}, // patch for 2880-E +#if 1 /* CONFIG_AP_SUPPORT */ + { RT2860_REG_SCHDMA_WMM_AIFSN_CFG, 0x00001173}, + { RT2860_REG_SCHDMA_WMM_CWMIN_CFG, 0x00002344}, + { RT2860_REG_SCHDMA_WMM_CWMAX_CFG, 0x000034a6}, + { RT2860_REG_SCHDMA_WMM_TXOP0_CFG, 0x00100020}, + { RT2860_REG_SCHDMA_WMM_TXOP1_CFG, 0x002F0038}, + { RT2860_REG_TBTT_SYNC_CFG, 0x00012000}, +#else /* CONFIG_STA_SUPPORT */ + { RT2860_REG_SCHDMA_WMM_AIFSN_CFG, 0x00002273}, + { RT2860_REG_SCHDMA_WMM_CWMIN_CFG, 0x00002344}, + { RT2860_REG_SCHDMA_WMM_CWMAX_CFG, 0x000034aa}, +#endif // CONFIG_AP_SUPPORT // +#endif +}; + +#define RT2860_DEF_MAC_SIZE (sizeof(rt2860_def_mac) / sizeof(rt2860_def_mac[0])) + +static const struct +{ + uint8_t reg; + uint8_t val; +} rt2860_def_bbp[] = +{ +#if 1 /* orig */ + { 65, 0x2c }, + { 66, 0x38 }, + { 69, 0x12 }, + { 70, 0x0a }, + { 73, 0x10 }, + { 81, 0x37 }, + { 82, 0x62 }, + { 83, 0x6a }, + { 84, 0x99 }, + { 86, 0x00 }, + { 91, 0x04 }, + { 92, 0x00 }, + { 103, 0x00 }, + { 105, 0x05 }, + { 106, 0x35 }, +#else + { 31, 0x08}, //gary recommend for ACE + { 65, 0x2C}, // fix rssi issue + { 66, 0x38}, // Also set this default value to pAd->BbpTuning.R66CurrentValue at initial + { 68, 0x0B}, // improve Rx sensitivity. + { 69, 0x12}, + { 70, 0xa}, // BBP_R70 will change to 0x8 in ApStartUp and LinkUp for rt2860C, otherwise value is 0xa + { 73, 0x10}, + { 78, 0x0E}, + { 80, 0x08}, // requested by Gary for high power + { 81, 0x37}, + { 82, 0x62}, + { 83, 0x6A}, + { 84, 0x99}, // 0x19 is for rt2860E and after. This is for extension channel overlapping IOT. 0x99 is for rt2860D and before + { 86, 0x00}, // middle range issue, Rory @2008-01-28 + { 91, 0x04}, // middle range issue, Rory @2008-01-28 + { 92, 0x00}, // middle range issue, Rory @2008-01-28 + { 103, 0xC0}, + { 105, 0x01},/*kurtis:0x01 ori*/// 0x05 is for rt2860E to turn on FEQ control. It is safe for rt2860D and before, because Bit 7:2 are reserved in rt2860D and before. + { 106, 0x35}, // Optimizing the Short GI sampling request from Gray @2009-0409 +#endif +}; + +#define RT2860_DEF_BBP_SIZE (sizeof(rt2860_def_bbp) / sizeof(rt2860_def_bbp[0])) + +SYSCTL_NODE(_hw, OID_AUTO, rt2860, CTLFLAG_RD, 0, "RT2860 driver parameters"); + +static int rt2860_tx_stbc = 1; +SYSCTL_INT(_hw_rt2860, OID_AUTO, tx_stbc, CTLFLAG_RW, &rt2860_tx_stbc, 0, "RT2860 Tx STBC"); +TUNABLE_INT("hw.rt2860.tx_stbc", &rt2860_tx_stbc); + +#ifdef RT2860_DEBUG +static int rt2860_debug = 0; +SYSCTL_INT(_hw_rt2860, OID_AUTO, debug, CTLFLAG_RW, &rt2860_debug, 0, "RT2860 debug level"); +TUNABLE_INT("hw.rt2860.debug", &rt2860_debug); +#endif + +/* + * rt2860_attach + */ +int rt2860_attach(device_t dev, int id) +{ + struct rt2860_softc *sc; + struct ieee80211com *ic; + int error, ntries, i; + + sc = device_get_softc(dev); + ic = &sc->sc_ic; + + sc->dev = dev; + sc->pid = id; + + mtx_init(&sc->lock, device_get_nameunit(dev), + MTX_NETWORK_LOCK, MTX_DEF | MTX_RECURSE); + + sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, + &sc->mem_rid, RF_ACTIVE); + if (sc->mem == NULL) + { + printf("%s: could not allocate memory resource\n", + device_get_nameunit(dev)); + error = ENXIO; + goto fail; + } + + + sc->bst = rman_get_bustag(sc->mem); + sc->bsh = rman_get_bushandle(sc->mem); + + sc->irq_rid = 0; + sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, + &sc->irq_rid, RF_ACTIVE | RF_SHAREABLE); + if (sc->irq == NULL) + { + printf("%s: could not allocate interrupt resource\n", + device_get_nameunit(dev)); + error = ENXIO; + goto fail; + } + + sc->tx_stbc = rt2860_tx_stbc; + +#ifdef RT2860_DEBUG + sc->debug = rt2860_debug; + + SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), + SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, + "debug", CTLFLAG_RW, &sc->debug, 0, "rt2860 debug level"); +#endif + + RT2860_DPRINTF(sc, RT2860_DEBUG_ANY, + "%s: attaching\n", + device_get_nameunit(sc->dev)); + + /* wait for NIC to initialize */ + + for (ntries = 0; ntries < 100; ntries++) + { + sc->mac_rev = rt2860_io_mac_read(sc, RT2860_REG_MAC_CSR0); + if (sc->mac_rev != 0x00000000 && sc->mac_rev != 0xffffffff) + break; + + DELAY(10); + } + + if (ntries == 100) + { + printf("%s: timeout waiting for NIC to initialize\n", + device_get_nameunit(dev)); + error = EIO; + goto fail; + } + + rt2860_read_eeprom(sc); + memcpy(ic->ic_macaddr, sc->mac_addr, 6); + + printf("%s: MAC/BBP RT2860 (rev 0x%08x), RF %s\n", + device_get_nameunit(sc->dev), sc->mac_rev, + rt2860_rf_name(sc->rf_rev)); + + RT2860_SOFTC_LOCK(sc); + /* clear key tables */ + rt2860_asic_clear_keytables(sc); + RT2860_SOFTC_UNLOCK(sc); + + /* allocate Tx and Rx rings */ + + for (i = 0; i < RT2860_SOFTC_TX_RING_COUNT; i++) + { + error = rt2860_alloc_tx_ring(sc, &sc->tx_ring[i], i); + if (error != 0) + { + printf("%s: could not allocate Tx ring #%d\n", + device_get_nameunit(sc->dev), i); + goto fail; + } + } + + sc->tx_ring_mgtqid = 5; + + error = rt2860_alloc_rx_ring(sc, &sc->rx_ring); + if (error != 0) + { + printf("%s: could not allocate Rx ring\n", + device_get_nameunit(sc->dev)); + goto fail; + } + + callout_init(&sc->periodic_ch, 0); + callout_init_mtx(&sc->tx_watchdog_ch, &sc->lock, 0); + mbufq_init(&sc->sc_snd, ifqmaxlen); + + ic->ic_softc = sc; + ic->ic_name = device_get_nameunit(dev); + ic->ic_opmode = IEEE80211_M_STA; + ic->ic_phytype = IEEE80211_T_HT; + + ic->ic_caps = IEEE80211_C_MONITOR | + IEEE80211_C_IBSS | + IEEE80211_C_STA | + IEEE80211_C_AHDEMO | + IEEE80211_C_HOSTAP | + IEEE80211_C_WDS | + IEEE80211_C_MBSS | + IEEE80211_C_BGSCAN | + IEEE80211_C_TXPMGT | + IEEE80211_C_SHPREAMBLE | + IEEE80211_C_SHSLOT | + IEEE80211_C_TXFRAG | + IEEE80211_C_BURST | + IEEE80211_C_WME | + IEEE80211_C_WPA; + +#ifdef RT2860_HW_CRYPTO + ic->ic_cryptocaps |= IEEE80211_CRYPTO_WEP | + IEEE80211_CRYPTO_TKIP | + IEEE80211_CRYPTO_TKIPMIC | + IEEE80211_CRYPTO_AES_CCM; +#endif + ic->ic_htcaps = IEEE80211_HTC_HT | + IEEE80211_HTC_AMSDU | /* A-MSDU Tx */ + IEEE80211_HTC_AMPDU | /* A-MPDU Tx */ + IEEE80211_HTC_SMPS | /* MIMO power save */ + IEEE80211_HTCAP_MAXAMSDU_3839 | /* max. A-MSDU Rx length */ + IEEE80211_HTCAP_CHWIDTH40 | /* HT 40MHz channel width */ + IEEE80211_HTCAP_GREENFIELD | /* HT greenfield */ + IEEE80211_HTCAP_SHORTGI20 | /* HT 20MHz short GI */ + IEEE80211_HTCAP_SHORTGI40 | /* HT 40MHz short GI */ + IEEE80211_HTCAP_SMPS_OFF; /* MIMO power save disabled */ + + /* spatial streams */ + + if (sc->nrxpath == 2) + ic->ic_htcaps |= IEEE80211_HTCAP_RXSTBC_2STREAM; + else if (sc->nrxpath == 3) + ic->ic_htcaps |= IEEE80211_HTCAP_RXSTBC_3STREAM; + else + ic->ic_htcaps |= IEEE80211_HTCAP_RXSTBC_1STREAM; + + if (sc->ntxpath > 1) + ic->ic_htcaps |= IEEE80211_HTCAP_TXSTBC; + + /* delayed BA */ + +// if (sc->mac_rev != 0x28600100) + if (sc->mac_rev != 0x28600102) + ic->ic_htcaps |= IEEE80211_HTCAP_DELBA; + + /* init channels */ + + ic->ic_nchans = 0; + + rt2860_init_channels(sc); + + rt2860_init_channels_ht40(sc); + + ieee80211_ifattach(ic); + + ic->ic_vap_create = rt2860_vap_create; + ic->ic_vap_delete = rt2860_vap_delete; + ic->ic_parent = rt2860_parent; + ic->ic_transmit = rt2860_transmit; + + ic->ic_node_alloc = rt2860_node_alloc; + + sc->node_cleanup = ic->ic_node_cleanup; + ic->ic_node_cleanup = rt2860_node_cleanup; + + ic->ic_setregdomain = rt2860_setregdomain; + ic->ic_getradiocaps = rt2860_getradiocaps; + ic->ic_scan_start = rt2860_scan_start; + ic->ic_scan_end = rt2860_scan_end; + ic->ic_set_channel = rt2860_set_channel; + ic->ic_newassoc = rt2860_newassoc; + ic->ic_updateslot = rt2860_updateslot; + ic->ic_update_promisc = rt2860_update_promisc; + ic->ic_wme.wme_update = rt2860_wme_update; + ic->ic_raw_xmit = rt2860_raw_xmit; + + sc->recv_action = ic->ic_recv_action; + ic->ic_recv_action = rt2860_recv_action; + + sc->send_action = ic->ic_send_action; + ic->ic_send_action = rt2860_send_action; + + sc->addba_response = ic->ic_addba_response; + ic->ic_addba_response = rt2860_addba_response; + + sc->addba_stop = ic->ic_addba_stop; + ic->ic_addba_stop = rt2860_addba_stop; + + sc->ampdu_rx_start = ic->ic_ampdu_rx_start; + ic->ic_ampdu_rx_start = rt2860_ampdu_rx_start; + + sc->ampdu_rx_stop = ic->ic_ampdu_rx_stop; + ic->ic_ampdu_rx_stop = rt2860_ampdu_rx_stop; + + /* hardware requires padding between 802.11 frame header and body */ + + ic->ic_flags |= IEEE80211_F_DATAPAD | IEEE80211_F_DOTH; + + ic->ic_flags_ext |= IEEE80211_FEXT_SWBMISS; + + ieee80211_radiotap_attach(ic, + &sc->txtap.ihdr, sizeof(sc->txtap), + RT2860_SOFTC_TX_RADIOTAP_PRESENT, + &sc->rxtap.ihdr, sizeof(sc->rxtap), + RT2860_SOFTC_RX_RADIOTAP_PRESENT); + + /* init task queue */ + + TASK_INIT(&sc->rx_done_task, 0, rt2860_rx_done_task, sc); + TASK_INIT(&sc->tx_done_task, 0, rt2860_tx_done_task, sc); + TASK_INIT(&sc->fifo_sta_full_task, 0, rt2860_fifo_sta_full_task, sc); + TASK_INIT(&sc->periodic_task, 0, rt2860_periodic_task, sc); + + sc->rx_process_limit = 100; + + sc->taskqueue = taskqueue_create("rt2860_taskq", M_NOWAIT, + taskqueue_thread_enqueue, &sc->taskqueue); + + taskqueue_start_threads(&sc->taskqueue, 1, PI_NET, "%s taskq", + device_get_nameunit(sc->dev)); + + rt2860_sysctl_attach(sc); + + if (bootverbose) + ieee80211_announce(ic); + + /* set up interrupt */ + + error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, + NULL, rt2860_intr, sc, &sc->irqh); + if (error != 0) + { + printf("%s: could not set up interrupt\n", + device_get_nameunit(dev)); + goto fail; + } + + return 0; + +fail: + + /* free Tx and Rx rings */ + + for (i = 0; i < RT2860_SOFTC_TX_RING_COUNT; i++) + rt2860_free_tx_ring(sc, &sc->tx_ring[i]); + + rt2860_free_rx_ring(sc, &sc->rx_ring); + + mtx_destroy(&sc->lock); + + if (sc->mem != NULL) + bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem); + + if (sc->irq != NULL) + bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq); + + return error; +} + +/* + * rt2860_detach + */ +int rt2860_detach(device_t dev) +{ + struct rt2860_softc *sc; + struct ieee80211com *ic; + int i; + + sc = device_get_softc(dev); + ic = &sc->sc_ic; + + RT2860_DPRINTF(sc, RT2860_DEBUG_ANY, + "%s: detaching\n", + device_get_nameunit(sc->dev)); + + RT2860_SOFTC_LOCK(sc); + + sc->sc_flags &= ~RT2860_RUNNING; + + callout_stop(&sc->periodic_ch); + callout_stop(&sc->tx_watchdog_ch); + + taskqueue_drain(sc->taskqueue, &sc->rx_done_task); + taskqueue_drain(sc->taskqueue, &sc->tx_done_task); + taskqueue_drain(sc->taskqueue, &sc->fifo_sta_full_task); + taskqueue_drain(sc->taskqueue, &sc->periodic_task); + + /* free Tx and Rx rings */ + + for (i = 0; i < RT2860_SOFTC_TX_RING_COUNT; i++) + rt2860_free_tx_ring(sc, &sc->tx_ring[i]); + + rt2860_free_rx_ring(sc, &sc->rx_ring); + + RT2860_SOFTC_UNLOCK(sc); + + ieee80211_ifdetach(ic); + mbufq_drain(&sc->sc_snd); + + taskqueue_free(sc->taskqueue); + + mtx_destroy(&sc->lock); + + bus_generic_detach(dev); + + bus_teardown_intr(dev, sc->irq, sc->irqh); + + bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq); + + bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem); + + return 0; +} + +/* + * rt2860_shutdown + */ +int rt2860_shutdown(device_t dev) +{ + struct rt2860_softc *sc; + + sc = device_get_softc(dev); + + RT2860_DPRINTF(sc, RT2860_DEBUG_ANY, + "%s: shutting down\n", + device_get_nameunit(sc->dev)); + + rt2860_stop(sc); + + sc->flags &= ~RT2860_SOFTC_FLAGS_UCODE_LOADED; + + return 0; +} + +/* + * rt2860_suspend + */ +int rt2860_suspend(device_t dev) +{ + struct rt2860_softc *sc; + + sc = device_get_softc(dev); + + RT2860_DPRINTF(sc, RT2860_DEBUG_ANY, + "%s: suspending\n", + device_get_nameunit(sc->dev)); + + rt2860_stop(sc); + + sc->flags &= ~RT2860_SOFTC_FLAGS_UCODE_LOADED; + + return 0; +} + +/* + * rt2860_resume + */ +int rt2860_resume(device_t dev) +{ + struct rt2860_softc *sc; + + sc = device_get_softc(dev); + + RT2860_DPRINTF(sc, RT2860_DEBUG_ANY, + "%s: resuming\n", + device_get_nameunit(sc->dev)); + + if (sc->sc_ic.ic_nrunning > 0) + rt2860_init(sc); + + return 0; +} + +/* + * rt2860_init_channels + */ +static void rt2860_init_channels(struct rt2860_softc *sc) +{ + struct ieee80211com *ic; + struct ieee80211_channel *c; + int i, flags; + + ic = &sc->sc_ic; + + /* set supported channels for 2GHz band */ + + for (i = 1; i <= 14; i++) + { + c = &ic->ic_channels[ic->ic_nchans++]; + flags = IEEE80211_CHAN_B; + + c->ic_freq = ieee80211_ieee2mhz(i, flags); + c->ic_ieee = i; + c->ic_flags = flags; + + c = &ic->ic_channels[ic->ic_nchans++]; + flags = IEEE80211_CHAN_B | IEEE80211_CHAN_HT20; + + c->ic_freq = ieee80211_ieee2mhz(i, flags); + c->ic_ieee = i; + c->ic_flags = flags; + + c = &ic->ic_channels[ic->ic_nchans++]; + flags = IEEE80211_CHAN_G; + + c->ic_freq = ieee80211_ieee2mhz(i, flags); + c->ic_ieee = i; + c->ic_flags = flags; + + c = &ic->ic_channels[ic->ic_nchans++]; + flags = IEEE80211_CHAN_G | IEEE80211_CHAN_HT20; + + c->ic_freq = ieee80211_ieee2mhz(i, flags); + c->ic_ieee = i; + c->ic_flags = flags; + } + + /* set supported channels for 5GHz band */ + + if (sc->rf_rev == RT2860_EEPROM_RF_2850 || + sc->rf_rev == RT2860_EEPROM_RF_2750 || + sc->rf_rev == RT2860_EEPROM_RF_3052) + { + for (i = 36; i <= 64; i += 4) + { + c = &ic->ic_channels[ic->ic_nchans++]; + flags = IEEE80211_CHAN_A; + + c->ic_freq = ieee80211_ieee2mhz(i, flags); + c->ic_ieee = i; + c->ic_flags = flags; + + c = &ic->ic_channels[ic->ic_nchans++]; + flags = IEEE80211_CHAN_A | IEEE80211_CHAN_HT20; + + c->ic_freq = ieee80211_ieee2mhz(i, flags); + c->ic_ieee = i; + c->ic_flags = flags; + } + + for (i = 100; i <= 140; i += 4) + { + c = &ic->ic_channels[ic->ic_nchans++]; + flags = IEEE80211_CHAN_A; + + c->ic_freq = ieee80211_ieee2mhz(i, flags); + c->ic_ieee = i; + c->ic_flags = flags; + + c = &ic->ic_channels[ic->ic_nchans++]; + flags = IEEE80211_CHAN_A | IEEE80211_CHAN_HT20; + + c->ic_freq = ieee80211_ieee2mhz(i, flags); + c->ic_ieee = i; + c->ic_flags = flags; + } + + for (i = 149; i <= 165; i += 4) + { + c = &ic->ic_channels[ic->ic_nchans++]; + flags = IEEE80211_CHAN_A; + + c->ic_freq = ieee80211_ieee2mhz(i, flags); + c->ic_ieee = i; + c->ic_flags = flags; + + c = &ic->ic_channels[ic->ic_nchans++]; + flags = IEEE80211_CHAN_A | IEEE80211_CHAN_HT20; + + c->ic_freq = ieee80211_ieee2mhz(i, flags); + c->ic_ieee = i; + c->ic_flags = flags; + } + } +} + +/* + * rt2860_init_channels_ht40 + */ +static void rt2860_init_channels_ht40(struct rt2860_softc *sc) +{ + struct ieee80211com *ic; + struct ieee80211_channel *c, *cent, *ext; + int i, flags; + + ic = &sc->sc_ic; + + /* set supported channels for 2GHz band */ + + for (i = 1; i <= 14; i++) + { + flags = IEEE80211_CHAN_G | IEEE80211_CHAN_HT40; + + /* find the center channel */ + + cent = ieee80211_find_channel_byieee(ic, i, + flags & ~IEEE80211_CHAN_HT); + if (cent == NULL) + { + printf("%s: skip channel %d, could not find center channel\n", + device_get_nameunit(sc->dev), i); + continue; + } + + /* find the extension channel */ + + ext = ieee80211_find_channel(ic, cent->ic_freq + 20, + flags & ~IEEE80211_CHAN_HT); + if (ext == NULL) + { + printf("%s: skip channel %d, could not find extension channel\n", + device_get_nameunit(sc->dev), i); + continue; + } + + c = &ic->ic_channels[ic->ic_nchans++]; + + *c = *cent; + c->ic_extieee = ext->ic_ieee; + c->ic_flags &= ~IEEE80211_CHAN_HT; + c->ic_flags |= IEEE80211_CHAN_HT40U; + + c = &ic->ic_channels[ic->ic_nchans++]; + + *c = *ext; + c->ic_extieee = cent->ic_ieee; + c->ic_flags &= ~IEEE80211_CHAN_HT; + c->ic_flags |= IEEE80211_CHAN_HT40D; + } + + /* set supported channels for 5GHz band */ + + if (sc->rf_rev == RT2860_EEPROM_RF_2850 || + sc->rf_rev == RT2860_EEPROM_RF_2750 || + sc->rf_rev == RT2860_EEPROM_RF_3052) + { + for (i = 36; i <= 64; i += 4) + { + flags = IEEE80211_CHAN_A | IEEE80211_CHAN_HT40; + + /* find the center channel */ + + cent = ieee80211_find_channel_byieee(ic, i, + flags & ~IEEE80211_CHAN_HT); + if (cent == NULL) + { + printf("%s: skip channel %d, could not find center channel\n", + device_get_nameunit(sc->dev), i); + continue; + } + + /* find the extension channel */ + + ext = ieee80211_find_channel(ic, cent->ic_freq + 20, + flags & ~IEEE80211_CHAN_HT); + if (ext == NULL) + { + printf("%s: skip channel %d, could not find extension channel\n", + device_get_nameunit(sc->dev), i); + continue; + } + + c = &ic->ic_channels[ic->ic_nchans++]; + + *c = *cent; + c->ic_extieee = ext->ic_ieee; + c->ic_flags &= ~IEEE80211_CHAN_HT; + c->ic_flags |= IEEE80211_CHAN_HT40U; + + c = &ic->ic_channels[ic->ic_nchans++]; + + *c = *ext; + c->ic_extieee = cent->ic_ieee; + c->ic_flags &= ~IEEE80211_CHAN_HT; + c->ic_flags |= IEEE80211_CHAN_HT40D; + } + + for (i = 100; i <= 140; i += 4) + { + flags = IEEE80211_CHAN_A | IEEE80211_CHAN_HT40; + + /* find the center channel */ + + cent = ieee80211_find_channel_byieee(ic, i, + flags & ~IEEE80211_CHAN_HT); + if (cent == NULL) + { + printf("%s: skip channel %d, could not find center channel\n", + device_get_nameunit(sc->dev), i); + continue; + } + + /* find the extension channel */ + + ext = ieee80211_find_channel(ic, cent->ic_freq + 20, + flags & ~IEEE80211_CHAN_HT); + if (ext == NULL) + { + printf("%s: skip channel %d, could not find extension channel\n", + device_get_nameunit(sc->dev), i); + continue; + } + + c = &ic->ic_channels[ic->ic_nchans++]; + + *c = *cent; + c->ic_extieee = ext->ic_ieee; + c->ic_flags &= ~IEEE80211_CHAN_HT; + c->ic_flags |= IEEE80211_CHAN_HT40U; + + c = &ic->ic_channels[ic->ic_nchans++]; + + *c = *ext; + c->ic_extieee = cent->ic_ieee; + c->ic_flags &= ~IEEE80211_CHAN_HT; + c->ic_flags |= IEEE80211_CHAN_HT40D; + } + + for (i = 149; i <= 165; i += 4) + { + flags = IEEE80211_CHAN_A | IEEE80211_CHAN_HT40; + + /* find the center channel */ + + cent = ieee80211_find_channel_byieee(ic, i, + flags & ~IEEE80211_CHAN_HT); + if (cent == NULL) + { + printf("%s: skip channel %d, could not find center channel\n", + device_get_nameunit(sc->dev), i); + continue; + } + + /* find the extension channel */ + + ext = ieee80211_find_channel(ic, cent->ic_freq + 20, + flags & ~IEEE80211_CHAN_HT); + if (ext == NULL) + { + printf("%s: skip channel %d, could not find extension channel\n", + device_get_nameunit(sc->dev), i); + continue; + } + + c = &ic->ic_channels[ic->ic_nchans++]; + + *c = *cent; + c->ic_extieee = ext->ic_ieee; + c->ic_flags &= ~IEEE80211_CHAN_HT; + c->ic_flags |= IEEE80211_CHAN_HT40U; + + c = &ic->ic_channels[ic->ic_nchans++]; + + *c = *ext; + c->ic_extieee = cent->ic_ieee; + c->ic_flags &= ~IEEE80211_CHAN_HT; + c->ic_flags |= IEEE80211_CHAN_HT40D; + } + } +} + +/* + * rt2860_init_locked + */ +static void rt2860_init_locked(void *priv) +{ + struct rt2860_softc *sc; + struct ieee80211com *ic; + struct ieee80211vap *vap; + int error, i, ntries; + uint32_t tmp, stacnt[6]; + const struct firmware *fp; + + sc = priv; + ic = &sc->sc_ic; + vap = TAILQ_FIRST(&ic->ic_vaps); + + RT2860_DPRINTF(sc, RT2860_DEBUG_ANY, + "%s: initializing\n", + device_get_nameunit(sc->dev)); + + RT2860_SOFTC_ASSERT_LOCKED(sc); + + if (sc->mac_rev != 0x28720200) + { + if (!(sc->flags & RT2860_SOFTC_FLAGS_UCODE_LOADED)) + { + RT2860_DPRINTF(sc, RT2860_DEBUG_ANY, + "%s: loading 8051 microcode\n", + device_get_nameunit(sc->dev)); + + fp = firmware_get("rt2860fw"); + if (fp == NULL) { + device_printf(sc->dev, + "unable to receive rt2860fw firmware image\n"); + goto fail; + } + + error = rt2860_io_mcu_load_ucode(sc, fp->data, fp->datasize); + if (error != 0) + { + printf("%s: could not load 8051 microcode\n", + device_get_nameunit(sc->dev)); + goto fail; + } + + RT2860_DPRINTF(sc, RT2860_DEBUG_ANY, + "%s: 8051 microcode was successfully loaded\n", + device_get_nameunit(sc->dev)); + + sc->flags |= RT2860_SOFTC_FLAGS_UCODE_LOADED; + } + } + else + { + sc->flags |= RT2860_SOFTC_FLAGS_UCODE_LOADED; + + /* Blink every TX */ +#define LED_CFG_LED_POLARITY (1<<30) +#define LED_CFG_Y_LED_MODE_ONTX (1<<28) +#define LED_CFG_G_LED_MODE_ONTX (1<<26) +#define LED_CFG_R_LED_MODE_ONTX (1<<24) +#define LED_CFG_SLOW_BLK_TIME (0x03<<16) /* sec */ +#define LED_CFG_LED_OFF_TIME (0x1e<<8) /* msec */ +#define LED_CFG_LED_ON_TIME (0x46) /* msec */ + rt2860_io_mac_write(sc, RT2860_REG_LED_CFG, + LED_CFG_LED_POLARITY | + LED_CFG_Y_LED_MODE_ONTX | + LED_CFG_G_LED_MODE_ONTX | + LED_CFG_R_LED_MODE_ONTX | + LED_CFG_SLOW_BLK_TIME | + LED_CFG_LED_OFF_TIME | + LED_CFG_LED_ON_TIME); + } + + rt2860_io_mac_write(sc, RT2860_REG_PWR_PIN_CFG, 0x2); + + /* disable DMA engine */ + + tmp = rt2860_io_mac_read(sc, RT2860_REG_SCHDMA_WPDMA_GLO_CFG); + + tmp &= 0xff0; + tmp |= RT2860_REG_TX_WB_DDONE; + + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_WPDMA_GLO_CFG, tmp); + + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_WPDMA_RST_IDX, 0xffffffff); + + /* PBF hardware reset */ + + rt2860_io_mac_write(sc, RT2860_REG_PBF_SYS_CTRL, 0xe1f); + rt2860_io_mac_write(sc, RT2860_REG_PBF_SYS_CTRL, 0xe00); + + /* wait while DMA engine is busy */ + + for (ntries = 0; ntries < 100; ntries++) + { + tmp = rt2860_io_mac_read(sc, RT2860_REG_SCHDMA_WPDMA_GLO_CFG); + if (!(tmp & (RT2860_REG_TX_DMA_BUSY | RT2860_REG_RX_DMA_BUSY))) + break; + + DELAY(1000); + } + + if (ntries == 100) + { + printf("%s: timeout waiting for DMA engine\n", + device_get_nameunit(sc->dev)); + goto fail; + } + + tmp &= 0xff0; + tmp |= RT2860_REG_TX_WB_DDONE; + + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_WPDMA_GLO_CFG, tmp); + + /* reset Rx and Tx rings */ + + tmp = RT2860_REG_RST_IDX_RX | + RT2860_REG_RST_IDX_TX_MGMT | + RT2860_REG_RST_IDX_TX_HCCA | + RT2860_REG_RST_IDX_TX_AC3 | + RT2860_REG_RST_IDX_TX_AC2 | + RT2860_REG_RST_IDX_TX_AC1 | + RT2860_REG_RST_IDX_TX_AC0; + + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_WPDMA_RST_IDX, tmp); + + /* PBF hardware reset */ + + rt2860_io_mac_write(sc, RT2860_REG_PBF_SYS_CTRL, 0xe1f); + rt2860_io_mac_write(sc, RT2860_REG_PBF_SYS_CTRL, 0xe00); + + rt2860_io_mac_write(sc, RT2860_REG_PWR_PIN_CFG, 0x3); + + rt2860_io_mac_write(sc, RT2860_REG_SYS_CTRL, + RT2860_REG_MAC_SRST | RT2860_REG_BBP_HRST); + rt2860_io_mac_write(sc, RT2860_REG_SYS_CTRL, 0); + + /* init Tx power per rate */ + + for (i = 0; i < RT2860_SOFTC_TXPOW_RATE_COUNT; i++) + { + if (sc->txpow_rate_20mhz[i] == 0xffffffff) + continue; + + rt2860_io_mac_write(sc, RT2860_REG_TX_PWR_CFG(i), + sc->txpow_rate_20mhz[i]); + } + + for (i = 0; i < RT2860_DEF_MAC_SIZE; i++) + rt2860_io_mac_write(sc, rt2860_def_mac[i].reg, + rt2860_def_mac[i].val); + + /* wait while MAC is busy */ + + for (ntries = 0; ntries < 100; ntries++) + { + if (!(rt2860_io_mac_read(sc, RT2860_REG_STATUS_CFG) & + (RT2860_REG_STATUS_TX_BUSY | RT2860_REG_STATUS_RX_BUSY))) + break; + + DELAY(1000); + } + + if (ntries == 100) + { + printf("%s: timeout waiting for MAC\n", + device_get_nameunit(sc->dev)); + goto fail; + } + + /* clear Host to MCU mailbox */ + + rt2860_io_mac_write(sc, RT2860_REG_H2M_MAILBOX_BBP_AGENT, 0); + rt2860_io_mac_write(sc, RT2860_REG_H2M_MAILBOX, 0); + + rt2860_io_mcu_cmd(sc, RT2860_IO_MCU_CMD_BOOT, + RT2860_REG_H2M_TOKEN_NO_INTR, 0); + + DELAY(1000); + + error = rt2860_init_bbp(sc); + if (error != 0) + goto fail; + + /* set up maximum buffer sizes */ + + tmp = (1 << 12) | RT2860_MAX_AGG_SIZE; + + rt2860_io_mac_write(sc, RT2860_REG_MAX_LEN_CFG, tmp); + + if (sc->mac_rev == 0x28720200) + { + /* set max. PSDU length from 16K to 32K bytes */ + + tmp = rt2860_io_mac_read(sc, RT2860_REG_MAX_LEN_CFG); + + tmp &= ~(3 << 12); + tmp |= (2 << 12); + + rt2860_io_mac_write(sc, RT2860_REG_MAX_LEN_CFG, tmp); + } + + if (sc->mac_rev >= 0x28720200 && sc->mac_rev < 0x30700200) + { + tmp = rt2860_io_mac_read(sc, RT2860_REG_MAX_LEN_CFG); + + tmp &= 0xfff; + tmp |= 0x2000; + + rt2860_io_mac_write(sc, RT2860_REG_MAX_LEN_CFG, tmp); + } + + /* set mac address */ + + rt2860_asic_set_macaddr(sc, vap ? vap->iv_myaddr : ic->ic_macaddr); + + /* clear statistic registers */ + + rt2860_io_mac_read_multi(sc, RT2860_REG_RX_STA_CNT0, + stacnt, sizeof(stacnt)); + + /* set RTS threshold */ + + rt2860_asic_update_rtsthreshold(sc); + + /* set Tx power */ + + rt2860_asic_update_txpower(sc); + + /* set up protection mode */ + + sc->tx_ampdu_sessions = 0; + + rt2860_asic_updateprot(sc); + + /* clear beacon frame space (entries = 8, entry size = 512) */ + + rt2860_io_mac_set_region_4(sc, RT2860_REG_BEACON_BASE(0), 0, 1024); + + taskqueue_unblock(sc->taskqueue); + + /* init Tx rings (4 EDCAs + HCCA + MGMT) */ + + for (i = 0; i < RT2860_SOFTC_TX_RING_COUNT; i++) + rt2860_reset_tx_ring(sc, &sc->tx_ring[i]); + + for (i = 0; i < RT2860_SOFTC_TX_RING_COUNT; i++) + { + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_TX_BASE_PTR(i), + sc->tx_ring[i].desc_phys_addr); + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_TX_MAX_CNT(i), + RT2860_SOFTC_TX_RING_DESC_COUNT); + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_TX_CTX_IDX(i), 0); + } + + /* init Rx ring */ + + rt2860_reset_rx_ring(sc, &sc->rx_ring); + + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_RX_BASE_PTR, + sc->rx_ring.desc_phys_addr); + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_RX_MAX_CNT, + RT2860_SOFTC_RX_RING_DATA_COUNT); + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_RX_CALC_IDX, + RT2860_SOFTC_RX_RING_DATA_COUNT - 1); + + /* wait while DMA engine is busy */ + + for (ntries = 0; ntries < 100; ntries++) + { + tmp = rt2860_io_mac_read(sc, RT2860_REG_SCHDMA_WPDMA_GLO_CFG); + if (!(tmp & (RT2860_REG_TX_DMA_BUSY | RT2860_REG_RX_DMA_BUSY))) + break; + + DELAY(1000); + } + + if (ntries == 100) + { + printf("%s: timeout waiting for DMA engine\n", + device_get_nameunit(sc->dev)); + goto fail; + } + + tmp &= 0xff0; + tmp |= RT2860_REG_TX_WB_DDONE; + + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_WPDMA_GLO_CFG, tmp); + + /* disable interrupts mitigation */ + + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_DELAY_INT_CFG, 0); + + /* select Main antenna for 1T1R devices */ + if (sc->rf_rev == RT2860_EEPROM_RF_2020 || + sc->rf_rev == RT2860_EEPROM_RF_3020 || + sc->rf_rev == RT2860_EEPROM_RF_3320) + rt3090_set_rx_antenna(sc, 0); + + /* send LEDs operating mode to microcontroller */ + rt2860_io_mcu_cmd(sc, RT2860_IO_MCU_CMD_LED1, + RT2860_REG_H2M_TOKEN_NO_INTR, sc->led_off[0]); + rt2860_io_mcu_cmd(sc, RT2860_IO_MCU_CMD_LED2, + RT2860_REG_H2M_TOKEN_NO_INTR, sc->led_off[1]); + rt2860_io_mcu_cmd(sc, RT2860_IO_MCU_CMD_LED3, + RT2860_REG_H2M_TOKEN_NO_INTR, sc->led_off[2]); + + /* turn radio LED on */ + + rt2860_led_cmd(sc, RT2860_LED_CMD_RADIO_ON); + + /* write vendor-specific BBP values (from EEPROM) */ + + for (i = 0; i < RT2860_SOFTC_BBP_EEPROM_COUNT; i++) + { + if (sc->bbp_eeprom[i].reg == 0x00 || + sc->bbp_eeprom[i].reg == 0xff) + continue; + + rt2860_io_bbp_write(sc, sc->bbp_eeprom[i].reg, + sc->bbp_eeprom[i].val); + } + + if ((sc->mac_rev & 0xffff0000) >= 0x30710000) + rt3090_rf_init(sc); + + if (sc->mac_rev != 0x28720200) { + /* 0x28720200 don`t have RT2860_REG_SCHDMA_GPIO_CTRL_CFG */ + tmp = rt2860_io_mac_read(sc, RT2860_REG_SCHDMA_GPIO_CTRL_CFG); + if (tmp & (1 << 2)) { + rt2860_io_mcu_cmd(sc, RT2860_IO_MCU_CMD_SLEEP, + RT2860_REG_H2M_TOKEN_RADIOOFF, 0x02ff); + rt2860_io_mcu_cmd_check(sc, RT2860_REG_H2M_TOKEN_RADIOOFF); + + rt2860_io_mcu_cmd(sc, RT2860_IO_MCU_CMD_WAKEUP, + RT2860_REG_H2M_TOKEN_WAKEUP, 0); + rt2860_io_mcu_cmd_check(sc, RT2860_REG_H2M_TOKEN_WAKEUP); + } + } + + if ((sc->mac_rev & 0xffff0000) >= 0x30710000) + rt3090_rf_wakeup(sc); + + /* disable non-existing Rx chains */ + + tmp = rt2860_io_bbp_read(sc, 3); + + tmp &= ~((1 << 4) | (1 << 3)); + + if (sc->nrxpath == 3) + tmp |= (1 << 4); + else if (sc->nrxpath == 2) + tmp |= (1 << 3); + + rt2860_io_bbp_write(sc, 3, tmp); + + /* disable non-existing Tx chains */ + + tmp = rt2860_io_bbp_read(sc, 1); + + tmp &= ~((1 << 4) | (1 << 3)); + + if (sc->ntxpath == 2) + tmp |= (1 << 4); + + rt2860_io_bbp_write(sc, 1, tmp); + + if ((sc->mac_rev & 0xffff0000) >= 0x30710000) + rt3090_rf_setup(sc); + +// if (sc->rf_rev == RT2860_EEPROM_RF_3022 || + if (sc->rf_rev == RT2860_EEPROM_RF_3020) + { + /* calibrate RF */ + tmp = rt2860_io_rf_read(sc, 30); + tmp |= 0x80; + rt2860_io_rf_write(sc, 30, tmp); + DELAY(1000); + tmp &= 0x7F; + rt2860_io_rf_write(sc, 30, tmp); + + /* Initialize RF register to default value */ + rt2860_io_rf_load_defaults(sc); + } + + /* set current channel */ + rt2860_rf_set_chan(sc, ic->ic_curchan); + + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_WMM_TXOP0_CFG, 0); + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_WMM_TXOP1_CFG, + (48 << 16) | 96); + + if ((sc->mac_rev & 0xffff) != 0x0101) + rt2860_io_mac_write(sc, RT2860_REG_TX_TXOP_CTRL_CFG, 0x583f); + + /* clear pending interrupts */ + + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_INT_STATUS, 0xffffffff); + + /* enable interrupts */ + + tmp = RT2860_REG_INT_TX_COHERENT | + RT2860_REG_INT_RX_COHERENT | + RT2860_REG_INT_GP_TIMER | + RT2860_REG_INT_AUTO_WAKEUP | + RT2860_REG_INT_FIFO_STA_FULL | + RT2860_REG_INT_PRE_TBTT | + RT2860_REG_INT_TBTT | + RT2860_REG_INT_TXRX_COHERENT | + RT2860_REG_INT_MCU_CMD | + RT2860_REG_INT_TX_MGMT_DONE | + RT2860_REG_INT_TX_HCCA_DONE | + RT2860_REG_INT_TX_AC3_DONE | + RT2860_REG_INT_TX_AC2_DONE | + RT2860_REG_INT_TX_AC1_DONE | + RT2860_REG_INT_TX_AC0_DONE | + RT2860_REG_INT_RX_DONE; + + sc->intr_enable_mask = tmp; + + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_INT_MASK, tmp); + + if (rt2860_txrx_enable(sc) != 0) + goto fail; + + /* clear garbage interrupts */ + + tmp = rt2860_io_mac_read(sc, 0x1300); + + sc->sc_flags |= RT2860_RUNNING; + + sc->periodic_round = 0; + + callout_reset(&sc->periodic_ch, hz / 10, rt2860_periodic, sc); + + return; + +fail: + + rt2860_stop_locked(sc); +} + +/* + * rt2860_init + */ +static void rt2860_init(void *priv) +{ + struct rt2860_softc *sc; + + sc = priv; + + RT2860_SOFTC_LOCK(sc); + + rt2860_init_locked(sc); + + RT2860_SOFTC_UNLOCK(sc); +} + +/* + * rt2860_init_bbp + */ +static int rt2860_init_bbp(struct rt2860_softc *sc) +{ + int ntries, i; + uint8_t tmp; + + for (ntries = 0; ntries < 20; ntries++) + { + tmp = rt2860_io_bbp_read(sc, 0); + if (tmp != 0x00 && tmp != 0xff) + break; + } + + if (tmp == 0x00 || tmp == 0xff) + { + printf("%s: timeout waiting for BBP to wakeup\n", + device_get_nameunit(sc->dev)); + return ETIMEDOUT; + } + + for (i = 0; i < RT2860_DEF_BBP_SIZE; i++) + rt2860_io_bbp_write(sc, rt2860_def_bbp[i].reg, + rt2860_def_bbp[i].val); + + if ((sc->mac_rev & 0xffff) != 0x0101) + rt2860_io_bbp_write(sc, 84, 0x19); + +// if (sc->mac_rev == 0x28600100) + if (sc->mac_rev == 0x28600102) + { + rt2860_io_bbp_write(sc, 69, 0x16); + rt2860_io_bbp_write(sc, 73, 0x12); + } + + return 0; +} + +/* + * rt2860_stop_locked + */ +static void rt2860_stop_locked(void *priv) +{ + struct rt2860_softc *sc; + struct ieee80211com *ic; + uint32_t tmp; + + sc = priv; + ic = &sc->sc_ic; + + RT2860_DPRINTF(sc, RT2860_DEBUG_ANY, + "%s: stopping\n", + device_get_nameunit(sc->dev)); + + RT2860_SOFTC_ASSERT_LOCKED(sc); + + sc->tx_timer = 0; + + if (sc->sc_flags & RT2860_RUNNING) + rt2860_led_cmd(sc, RT2860_LED_CMD_RADIO_OFF); + + sc->sc_flags &= ~RT2860_RUNNING; + + callout_stop(&sc->periodic_ch); + callout_stop(&sc->tx_watchdog_ch); + + RT2860_SOFTC_UNLOCK(sc); + + taskqueue_block(sc->taskqueue); + + taskqueue_drain(sc->taskqueue, &sc->rx_done_task); + taskqueue_drain(sc->taskqueue, &sc->tx_done_task); + taskqueue_drain(sc->taskqueue, &sc->fifo_sta_full_task); + taskqueue_drain(sc->taskqueue, &sc->periodic_task); + + RT2860_SOFTC_LOCK(sc); + + /* clear key tables */ + + rt2860_asic_clear_keytables(sc); + + /* disable interrupts */ + + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_INT_MASK, 0); + + /* disable Tx/Rx */ + + tmp = rt2860_io_mac_read(sc, RT2860_REG_SYS_CTRL); + + tmp &= ~(RT2860_REG_RX_ENABLE | RT2860_REG_TX_ENABLE); + + rt2860_io_mac_write(sc, RT2860_REG_SYS_CTRL, tmp); + + /* reset adapter */ + + rt2860_io_mac_write(sc, RT2860_REG_SYS_CTRL, + RT2860_REG_MAC_SRST | RT2860_REG_BBP_HRST); + rt2860_io_mac_write(sc, RT2860_REG_SYS_CTRL, 0); +} + +/* + * rt2860_stop + */ +static void rt2860_stop(void *priv) +{ + struct rt2860_softc *sc; + + sc = priv; + + RT2860_SOFTC_LOCK(sc); + + rt2860_stop_locked(sc); + + RT2860_SOFTC_UNLOCK(sc); +} + +/* + * rt2860_start + */ +static void rt2860_start(struct rt2860_softc *sc) +{ + struct ieee80211_frame *wh; + struct ieee80211_node *ni; + struct ieee80211_key *k; + struct mbuf *m; + int qid; + + if (!(sc->sc_flags & RT2860_RUNNING)) + return; + + RT2860_SOFTC_LOCK(sc); + + for (;;) + { + m = mbufq_dequeue(&sc->sc_snd); + if (m == NULL) + break; + + ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; + + KASSERT(ni != NULL, ("%s:%d: fail", __func__, __LINE__)); + wh = mtod(m, struct ieee80211_frame *); + if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { + k = ieee80211_crypto_encap(ni, m); + if (k == NULL) { + ieee80211_free_node(ni); + m_freem(m); + counter_u64_add(sc->sc_ic.ic_oerrors, 1); + continue; + } + } + wh = NULL; /* Catch any invalid use */ + + m->m_pkthdr.rcvif = NULL; + + qid = M_WME_GETAC(m); + + RT2860_SOFTC_TX_RING_LOCK(&sc->tx_ring[qid]); + + if (sc->tx_ring[qid].data_queued >= RT2860_SOFTC_TX_RING_DATA_COUNT) + { + RT2860_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]); + + RT2860_DPRINTF(sc, RT2860_DEBUG_TX, + "%s: if_start: Tx ring with qid=%d is full\n", + device_get_nameunit(sc->dev), qid); + + m_freem(m); + ieee80211_free_node(ni); + + counter_u64_add(sc->sc_ic.ic_oerrors, 1); + + sc->tx_data_queue_full[qid]++; + + break; + } + + if (rt2860_tx_data(sc, m, ni, qid) != 0) + { + RT2860_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]); + + ieee80211_free_node(ni); + + counter_u64_add(sc->sc_ic.ic_oerrors, 1); + + break; + } + + RT2860_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]); + + rt2860_drain_fifo_stats(sc); + + sc->tx_timer = RT2860_TX_WATCHDOG_TIMEOUT; + + callout_reset(&sc->tx_watchdog_ch, hz, rt2860_tx_watchdog, sc); + } + RT2860_SOFTC_UNLOCK(sc); + +} + +/* + * rt2860_vap_create + */ +static struct ieee80211vap *rt2860_vap_create(struct ieee80211com *ic, + const char name[IFNAMSIZ], int unit, enum ieee80211_opmode opmode, + int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], + const uint8_t mac[IEEE80211_ADDR_LEN]) +{ + struct rt2860_softc *sc; + struct rt2860_softc_vap *rvap; + struct ieee80211vap *vap; + + sc = ic->ic_softc; + + RT2860_DPRINTF(sc, RT2860_DEBUG_STATE, + "%s: VAP create: opmode=%s\n", + device_get_nameunit(sc->dev), + ieee80211_opmode_name[opmode]); + + switch (opmode) + { + case IEEE80211_M_IBSS: + case IEEE80211_M_STA: + case IEEE80211_M_AHDEMO: + case IEEE80211_M_HOSTAP: + case IEEE80211_M_MBSS: + if ((sc->napvaps + sc->nadhocvaps + sc->nstavaps) != 0) + { + device_printf(sc->dev, "only 1 VAP supported\n"); + return NULL; + } + + if (opmode == IEEE80211_M_STA) + flags |= IEEE80211_CLONE_NOBEACONS; + break; + + case IEEE80211_M_WDS: + if (sc->napvaps == 0) + { + device_printf(sc->dev, "WDS only supported in AP mode\n"); + return NULL; + } + break; + + case IEEE80211_M_MONITOR: + break; + + default: + device_printf(sc->dev, "unknown opmode %d\n", opmode); + return NULL; + } + + rvap = (struct rt2860_softc_vap *) malloc(sizeof(struct rt2860_softc_vap), + M_80211_VAP, M_NOWAIT | M_ZERO); + if (rvap == NULL) + return NULL; + + vap = &rvap->vap; + + ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); + + rvap->newstate = vap->iv_newstate; + vap->iv_newstate = rt2860_vap_newstate; + + vap->iv_reset = rt2860_vap_reset; +#ifdef RT2860_HW_CRYPTO + vap->iv_key_update_begin = rt2860_vap_key_update_begin; + vap->iv_key_update_end = rt2860_vap_key_update_end; + vap->iv_key_set = rt2860_vap_key_set; + vap->iv_key_delete = rt2860_vap_key_delete; +#endif + vap->iv_update_beacon = rt2860_vap_update_beacon; + + rt2860_amrr_init(&rvap->amrr, vap, + sc->ntxpath, + RT2860_AMRR_MIN_SUCCESS_THRESHOLD, + RT2860_AMRR_MAX_SUCCESS_THRESHOLD, + 500); + + vap->iv_max_aid = RT2860_SOFTC_STAID_COUNT; + + /* overwrite default Rx A-MPDU factor */ + + vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_32K; + vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_NA; + vap->iv_ampdu_limit = vap->iv_ampdu_rxmax; + + ieee80211_vap_attach(vap, ieee80211_media_change, ieee80211_media_status, + mac); + + switch (vap->iv_opmode) + { + case IEEE80211_M_HOSTAP: + case IEEE80211_M_MBSS: + case IEEE80211_M_AHDEMO: + sc->napvaps++; + break; + + case IEEE80211_M_IBSS: + sc->nadhocvaps++; + break; + + case IEEE80211_M_STA: + sc->nstavaps++; + break; + + case IEEE80211_M_WDS: + sc->nwdsvaps++; + break; + + default: + break; + } + + sc->nvaps++; + + if (sc->napvaps > 0) + ic->ic_opmode = IEEE80211_M_HOSTAP; + else if (sc->nadhocvaps > 0) + ic->ic_opmode = IEEE80211_M_IBSS; + else if (sc->nstavaps > 0) + ic->ic_opmode = IEEE80211_M_STA; + else + ic->ic_opmode = opmode; + + return vap; +} + +/* + * rt2860_vap_delete + */ +static void rt2860_vap_delete(struct ieee80211vap *vap) +{ + struct rt2860_softc *sc; + struct ieee80211com *ic; + struct rt2860_softc_vap *rvap; + enum ieee80211_opmode opmode; + + ic = vap->iv_ic; + sc = ic->ic_softc; + rvap = (struct rt2860_softc_vap *) vap; + opmode = vap->iv_opmode; + + RT2860_DPRINTF(sc, RT2860_DEBUG_STATE, + "%s: VAP delete: opmode=%s\n", + device_get_nameunit(sc->dev), ieee80211_opmode_name[opmode]); + + rt2860_amrr_cleanup(&rvap->amrr); + + ieee80211_vap_detach(vap); + + if (rvap->beacon_mbuf != NULL) + { + m_free(rvap->beacon_mbuf); + rvap->beacon_mbuf = NULL; + } + + switch (opmode) + { + case IEEE80211_M_HOSTAP: + case IEEE80211_M_MBSS: + case IEEE80211_M_AHDEMO: + sc->napvaps--; + break; + + case IEEE80211_M_IBSS: + sc->nadhocvaps--; + break; + + case IEEE80211_M_STA: + sc->nstavaps--; + break; + + case IEEE80211_M_WDS: + sc->nwdsvaps--; + break; + + default: + break; + } + + sc->nvaps--; + + if (sc->napvaps > 0) + ic->ic_opmode = IEEE80211_M_HOSTAP; + else if (sc->nadhocvaps > 0) + ic->ic_opmode = IEEE80211_M_IBSS; + else if (sc->nstavaps > 0) + ic->ic_opmode = IEEE80211_M_STA; + + free(rvap, M_80211_VAP); +} + +/* + * rt2860_reset_vap + */ +static int rt2860_vap_reset(struct ieee80211vap *vap, u_long cmd) +{ + struct rt2860_softc *sc; + struct ieee80211com *ic; + struct rt2860_softc_vap *rvap; + int error; + + ic = vap->iv_ic; + sc = ic->ic_softc; + rvap = (struct rt2860_softc_vap *) vap; + + RT2860_DPRINTF(sc, RT2860_DEBUG_STATE, + "%s: VAP reset: cmd=%lu\n", + device_get_nameunit(sc->dev), cmd); + + error = 0; + + RT2860_SOFTC_LOCK(sc); + + switch (cmd) + { + case IEEE80211_IOC_RTSTHRESHOLD: + case IEEE80211_IOC_AMSDU: + rt2860_asic_update_rtsthreshold(sc); + break; + + case IEEE80211_IOC_PROTMODE: + case IEEE80211_IOC_HTPROTMODE: + rt2860_asic_updateprot(sc); + break; + + case IEEE80211_IOC_TXPOWER: + rt2860_asic_update_txpower(sc); + break; + + case IEEE80211_IOC_BURST: + rt2860_asic_updateslot(sc); + break; + + case IEEE80211_IOC_SHORTGI: + case IEEE80211_IOC_AMPDU_DENSITY: + case IEEE80211_IOC_SMPS: + break; + + default: + error = ENETRESET; + break; + } + + RT2860_SOFTC_UNLOCK(sc); + + return error; +} + +/* + * rt2860_vap_newstate + */ +static int rt2860_vap_newstate(struct ieee80211vap *vap, + enum ieee80211_state nstate, int arg) +{ + struct rt2860_softc *sc; + struct ieee80211com *ic; + struct rt2860_softc_vap *rvap; + struct ieee80211_node *ni; + enum ieee80211_state ostate; + int error; + + ic = vap->iv_ic; + sc = ic->ic_softc; + rvap = (struct rt2860_softc_vap *) vap; + + ostate = vap->iv_state; + + RT2860_DPRINTF(sc, RT2860_DEBUG_STATE, + "%s: VAP newstate: %s -> %s\n", + device_get_nameunit(sc->dev), + ieee80211_state_name[ostate], ieee80211_state_name[nstate]); + + error = rvap->newstate(vap, nstate, arg); + if (error != 0) + return error; + + IEEE80211_UNLOCK(ic); + + RT2860_SOFTC_LOCK(sc); + + /* turn link LED off */ + + if (nstate != IEEE80211_S_RUN) + rt2860_led_cmd(sc, RT2860_LED_CMD_RADIO_OFF); + + switch (nstate) + { + case IEEE80211_S_INIT: + rt2860_asic_disable_tsf_sync(sc); + break; + + case IEEE80211_S_RUN: + ni = vap->iv_bss; + + rt2860_rf_set_chan(sc, ni->ni_chan); + + if (vap->iv_opmode != IEEE80211_M_MONITOR) + { + rt2860_asic_enable_mrr(sc); + rt2860_asic_set_txpreamble(sc); + rt2860_asic_set_basicrates(sc); + rt2860_asic_update_txpower(sc); + rt2860_asic_set_bssid(sc, ni->ni_bssid); + } + + if (vap->iv_opmode == IEEE80211_M_HOSTAP || + vap->iv_opmode == IEEE80211_M_IBSS || + vap->iv_opmode == IEEE80211_M_MBSS) + { + error = rt2860_beacon_alloc(sc, vap); + if (error != 0) + break; + + rt2860_asic_update_beacon(sc, vap); + } + + if (vap->iv_opmode != IEEE80211_M_MONITOR) + rt2860_asic_enable_tsf_sync(sc); + + /* turn link LED on */ + + if (vap->iv_opmode != IEEE80211_M_MONITOR) + { + rt2860_led_cmd(sc, RT2860_LED_CMD_RADIO_ON | + (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan) ? + RT2860_LED_CMD_LINK_2GHZ : RT2860_LED_CMD_LINK_5GHZ)); + } + break; + + case IEEE80211_S_SLEEP: + break; + + default: + break; + } + + RT2860_SOFTC_UNLOCK(sc); + + IEEE80211_LOCK(ic); + + return error; +} + +#ifdef RT2860_HW_CRYPTO +/* + * rt2860_vap_key_update_begin + */ +static void rt2860_vap_key_update_begin(struct ieee80211vap *vap) +{ + struct rt2860_softc *sc; + struct ieee80211com *ic; + + ic = vap->iv_ic; + sc = ic->ic_softc; + + RT2860_DPRINTF(sc, RT2860_DEBUG_KEY, + "%s: VAP key update begin\n", + device_get_nameunit(sc->dev)); + + taskqueue_block(sc->taskqueue); + +// IF_LOCK(&ifp->if_snd); +} + +/* + * rt2860_vap_key_update_end + */ +static void rt2860_vap_key_update_end(struct ieee80211vap *vap) +{ + struct rt2860_softc *sc; + struct ieee80211com *ic; + + ic = vap->iv_ic; + sc = ic->ic_softc; + + RT2860_DPRINTF(sc, RT2860_DEBUG_KEY, + "%s: VAP key update end\n", + device_get_nameunit(sc->dev)); + +// IF_UNLOCK(&ifp->if_snd); + + taskqueue_unblock(sc->taskqueue); +} + +/* + * rt2860_vap_key_set + */ +static int rt2860_vap_key_set(struct ieee80211vap *vap, + const struct ieee80211_key *k) +{ + struct rt2860_softc *sc; + struct ieee80211com *ic; + struct ieee80211_node *ni; + struct rt2860_softc_node *rni; + uint16_t key_base, keymode_base; + uint8_t mode, vapid, wcid, iv[8]; + uint32_t tmp; + + switch (k->wk_cipher->ic_cipher) + { + case IEEE80211_CIPHER_WEP: + if(k->wk_keylen < 8) + mode = RT2860_REG_CIPHER_MODE_WEP40; + else + mode = RT2860_REG_CIPHER_MODE_WEP104; + break; + + case IEEE80211_CIPHER_TKIP: + mode = RT2860_REG_CIPHER_MODE_TKIP; + break; + + case IEEE80211_CIPHER_AES_CCM: + mode = RT2860_REG_CIPHER_MODE_AES_CCMP; + break; + + default: + printf("Wrong key CIPHER (%d)\n", k->wk_cipher->ic_cipher); + return 0; + } + + ic = vap->iv_ic; + sc = ic->ic_softc; + + RT2860_DPRINTF(sc, RT2860_DEBUG_KEY, + "%s: VAP key set: keyix=%d, keylen=%d, macaddr=%s, mode=%d, group=%d\n", + device_get_nameunit(sc->dev), k->wk_keyix, k->wk_keylen, ether_sprintf(k->wk_macaddr), + mode, (k->wk_flags & IEEE80211_KEY_GROUP) ? 1 : 0); + + if (!(k->wk_flags & IEEE80211_KEY_GROUP)) + { + /* install pairwise key */ + + if (vap->iv_opmode == IEEE80211_M_HOSTAP) + ni = ieee80211_find_vap_node(&ic->ic_sta, vap, ic->ic_macaddr); + else + ni = vap->iv_bss; + + rni = (struct rt2860_softc_node *) ni; + + vapid = 0; + wcid = (ni != NULL) ? rni->staid : 0; + key_base = RT2860_REG_PKEY(wcid); + + if (ni != NULL) + ieee80211_free_node(ni); + + if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_WEP) + { + memset(iv, 0, 8); + + iv[3] = (k->wk_keyix << 6); + } + else + { + if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP) + { + iv[0] = (k->wk_keytsc >> 8); + iv[1] = ((iv[0] | 0x20) & 0x7f); + iv[2] = k->wk_keytsc; + } + else + { + /* AES CCMP */ + iv[0] = k->wk_keytsc; + iv[1] = k->wk_keytsc >> 8; + iv[2] = 0; + } + + iv[3] = ((k->wk_keyix << 6) | IEEE80211_WEP_EXTIV); + iv[4] = (k->wk_keytsc >> 16); + iv[5] = (k->wk_keytsc >> 24); + iv[6] = (k->wk_keytsc >> 32); + iv[7] = (k->wk_keytsc >> 40); + + RT2860_DPRINTF(sc, RT2860_DEBUG_KEY, + "%s: VAP key set: iv=%02x %02x %02x %02x %02x %02x %02x %02x\n", + device_get_nameunit(sc->dev), + iv[0], iv[1], iv[2], iv[3], iv[4], iv[5], iv[6], iv[7]); + } + + rt2860_io_mac_write_multi(sc, RT2860_REG_IVEIV(wcid), iv, 8); + + if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP) + { + rt2860_io_mac_write_multi(sc, key_base, k->wk_key, 16); + + if (vap->iv_opmode != IEEE80211_M_HOSTAP) + { + rt2860_io_mac_write_multi(sc, key_base + 16, &k->wk_key[16], 8); + rt2860_io_mac_write_multi(sc, key_base + 24, &k->wk_key[24], 8); + } + else + { + rt2860_io_mac_write_multi(sc, key_base + 16, &k->wk_key[24], 8); + rt2860_io_mac_write_multi(sc, key_base + 24, &k->wk_key[16], 8); + } + } + else + { + rt2860_io_mac_write_multi(sc, key_base, k->wk_key, k->wk_keylen); + } + tmp = ((vapid & RT2860_REG_VAP_MASK) << RT2860_REG_VAP_SHIFT) | + (mode << RT2860_REG_CIPHER_MODE_SHIFT) | RT2860_REG_PKEY_ENABLE; + + rt2860_io_mac_write(sc, RT2860_REG_WCID_ATTR(wcid), tmp); + } + + if ((k->wk_flags & IEEE80211_KEY_GROUP) || + (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_WEP)) + { + /* install group key */ + + vapid = 0; + wcid = RT2860_WCID_MCAST; + key_base = RT2860_REG_SKEY(vapid, k->wk_keyix); + keymode_base = RT2860_REG_SKEY_MODE(vapid); + + if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP) + { + rt2860_io_mac_write_multi(sc, key_base, k->wk_key, 16); + + if (vap->iv_opmode != IEEE80211_M_HOSTAP) + { + rt2860_io_mac_write_multi(sc, key_base + 16, &k->wk_key[16], 8); + rt2860_io_mac_write_multi(sc, key_base + 24, &k->wk_key[24], 8); + } + else + { + rt2860_io_mac_write_multi(sc, key_base + 16, &k->wk_key[24], 8); + rt2860_io_mac_write_multi(sc, key_base + 24, &k->wk_key[16], 8); + } + } + else + { + rt2860_io_mac_write_multi(sc, key_base, k->wk_key, k->wk_keylen); + } + + tmp = rt2860_io_mac_read(sc, keymode_base); + + tmp &= ~(0xf << (k->wk_keyix * 4 + 16 * (vapid % 2))); + tmp |= (mode << (k->wk_keyix * 4 + 16 * (vapid % 2))); + + rt2860_io_mac_write(sc, keymode_base, tmp); + + if (vap->iv_opmode == IEEE80211_M_HOSTAP) + { + if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_WEP) + { + memset(iv, 0, 8); + + iv[3] = (k->wk_keyix << 6); + } + else + { + if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP) + { + iv[0] = (k->wk_keytsc >> 8); + iv[1] = ((iv[0] | 0x20) & 0x7f); + iv[2] = k->wk_keytsc; + } + else + { + /* AES CCMP */ + + iv[0] = k->wk_keytsc; + iv[1] = k->wk_keytsc >> 8; + iv[2] = 0; + } + + iv[3] = ((k->wk_keyix << 6) | IEEE80211_WEP_EXTIV); + iv[4] = (k->wk_keytsc >> 16); + iv[5] = (k->wk_keytsc >> 24); + iv[6] = (k->wk_keytsc >> 32); + iv[7] = (k->wk_keytsc >> 40); + + RT2860_DPRINTF(sc, RT2860_DEBUG_KEY, + "%s: VAP key set: iv=%02x %02x %02x %02x %02x %02x %02x %02x\n", + device_get_nameunit(sc->dev), + iv[0], iv[1], iv[2], iv[3], iv[4], iv[5], iv[6], iv[7]); + } + + rt2860_io_mac_write_multi(sc, RT2860_REG_IVEIV(wcid), iv, 8); + + tmp = ((vapid & RT2860_REG_VAP_MASK) << RT2860_REG_VAP_SHIFT) | + (mode << RT2860_REG_CIPHER_MODE_SHIFT); + + rt2860_io_mac_write(sc, RT2860_REG_WCID_ATTR(wcid), tmp); + } + } + + return 1; +} + +/* + * rt2860_vap_key_delete + */ +static int rt2860_vap_key_delete(struct ieee80211vap *vap, + const struct ieee80211_key *k) +{ + struct rt2860_softc *sc; + struct ieee80211com *ic; + uint8_t vapid, wcid; + uint32_t tmp; + + ic = vap->iv_ic; + sc = ic->ic_softc; + + RT2860_DPRINTF(sc, RT2860_DEBUG_KEY, + "%s: VAP key delete: keyix=%d, keylen=%d, macaddr=%s, group=%d\n", + device_get_nameunit(sc->dev), k->wk_keyix, k->wk_keylen, ether_sprintf(k->wk_macaddr), + (k->wk_flags & IEEE80211_KEY_GROUP) ? 1 : 0); + + if (k->wk_flags & IEEE80211_KEY_GROUP) + { + /* remove group key */ + + vapid = 0; + wcid = RT2860_WCID_MCAST; + + tmp = rt2860_io_mac_read(sc, RT2860_REG_SKEY_MODE(vapid)); + + tmp &= ~(0xf << (k->wk_keyix * 4 + 16 * (vapid % 2))); + tmp |= (RT2860_REG_CIPHER_MODE_NONE << (k->wk_keyix * 4 + 16 * (vapid % 2))); + + rt2860_io_mac_write(sc, RT2860_REG_SKEY_MODE(vapid), tmp); + + if (vap->iv_opmode == IEEE80211_M_HOSTAP) + { + tmp = ((vapid & RT2860_REG_VAP_MASK) << RT2860_REG_VAP_SHIFT) | + (RT2860_REG_CIPHER_MODE_NONE << RT2860_REG_CIPHER_MODE_SHIFT) | RT2860_REG_PKEY_ENABLE; + + rt2860_io_mac_write(sc, RT2860_REG_WCID_ATTR(wcid), tmp); + } + } + + return 1; +} +#endif + +/* + * rt2860_vap_update_beacon + */ +static void rt2860_vap_update_beacon(struct ieee80211vap *vap, int what) +{ + struct rt2860_softc *sc; + struct ieee80211com *ic; + struct rt2860_softc_vap *rvap; + struct mbuf *m; + struct ieee80211_beacon_offsets *bo; + int error; + + ic = vap->iv_ic; + sc = ic->ic_softc; + rvap = (struct rt2860_softc_vap *) vap; + m = rvap->beacon_mbuf; + bo = &rvap->beacon_offsets; + + RT2860_DPRINTF(sc, RT2860_DEBUG_BEACON, + "%s: VAP update beacon: what=%d\n", + device_get_nameunit(sc->dev), what); + + setbit(bo->bo_flags, what); + + if (m == NULL) + { + error = rt2860_beacon_alloc(sc, vap); + if (error != 0) + return; + + m = rvap->beacon_mbuf; + } + + ieee80211_beacon_update(vap->iv_bss, m, 0); + + rt2860_asic_update_beacon(sc, vap); +} + +/* + * rt2860_node_alloc + */ +static struct ieee80211_node *rt2860_node_alloc(struct ieee80211vap *vap, + const uint8_t mac[IEEE80211_ADDR_LEN]) +{ + return malloc(sizeof(struct rt2860_softc_node), + M_80211_NODE, M_NOWAIT | M_ZERO); +} + +/* + * rt2860_node_cleanup + */ +static void rt2860_node_cleanup(struct ieee80211_node *ni) +{ + struct rt2860_softc *sc; + struct ieee80211com *ic; + struct rt2860_softc_node *rni; + uint8_t vapid, wcid; + uint32_t tmp; + + ic = ni->ni_ic; + sc = ic->ic_softc; + rni = (struct rt2860_softc_node *) ni; + + RT2860_DPRINTF(sc, RT2860_DEBUG_NODE, + "%s: node cleanup: macaddr=%s, associd=0x%04x, staid=0x%02x\n", + device_get_nameunit(sc->dev), ether_sprintf(ni->ni_macaddr), + ni->ni_associd, rni->staid); + + if (rni->staid != 0) + { + vapid = 0; + wcid = rni->staid; + + tmp = ((vapid & RT2860_REG_VAP_MASK) << RT2860_REG_VAP_SHIFT) | + (RT2860_REG_CIPHER_MODE_NONE << RT2860_REG_CIPHER_MODE_SHIFT) | RT2860_REG_PKEY_ENABLE; + + rt2860_io_mac_write(sc, RT2860_REG_WCID_ATTR(wcid), tmp); + + rt2860_io_mac_write(sc, RT2860_REG_WCID(wcid), 0x00000000); + rt2860_io_mac_write(sc, RT2860_REG_WCID(wcid) + 4, 0x00000000); + + rt2860_staid_delete(sc, rni->staid); + + rni->staid = 0; + } + + sc->node_cleanup(ni); +} + +/* + * rt2860_setregdomain + */ +static int rt2860_setregdomain(struct ieee80211com *ic, + struct ieee80211_regdomain *reg, + int nchans, struct ieee80211_channel chans[]) +{ + struct rt2860_softc *sc; + + sc = ic->ic_softc; + + RT2860_DPRINTF(sc, RT2860_DEBUG_STATE, + "%s: set regulatory domain: country=%d, country code string=%c%c, location=%c\n", + device_get_nameunit(sc->dev), + reg->country, reg->isocc[0], reg->isocc[1], reg->location); + + return 0; +} + +/* + * rt2860_getradiocaps + */ +static void rt2860_getradiocaps(struct ieee80211com *ic, + int maxchans, int *nchans, struct ieee80211_channel chans[]) +{ + *nchans = (ic->ic_nchans >= maxchans) ? maxchans : ic->ic_nchans; + + memcpy(chans, ic->ic_channels, (*nchans) * sizeof(struct ieee80211_channel)); +} + +/* + * rt2860_scan_start + */ +static void rt2860_scan_start(struct ieee80211com *ic) +{ + struct rt2860_softc *sc; + + sc = ic->ic_softc; + + RT2860_SOFTC_LOCK(sc); + + rt2860_asic_disable_tsf_sync(sc); + + RT2860_SOFTC_UNLOCK(sc); +} + +/* + * rt2860_scan_end + */ +static void rt2860_scan_end(struct ieee80211com *ic) +{ + struct rt2860_softc *sc; + + sc = ic->ic_softc; + + RT2860_SOFTC_LOCK(sc); + + rt2860_asic_enable_tsf_sync(sc); + + RT2860_SOFTC_UNLOCK(sc); +} + +/* + * rt2860_set_channel + */ +static void rt2860_set_channel(struct ieee80211com *ic) +{ + struct rt2860_softc *sc; + + sc = ic->ic_softc; + + RT2860_DPRINTF(sc, RT2860_DEBUG_CHAN, + "%s: set channel: channel=%u, HT%s%s\n", + device_get_nameunit(sc->dev), + ieee80211_chan2ieee(ic, ic->ic_curchan), + !IEEE80211_IS_CHAN_HT(ic->ic_curchan) ? " disabled" : + IEEE80211_IS_CHAN_HT20(ic->ic_curchan) ? "20": + IEEE80211_IS_CHAN_HT40U(ic->ic_curchan) ? "40U" : "40D", + (ic->ic_flags & IEEE80211_F_SCAN) ? ", scanning" : ""); + + RT2860_SOFTC_LOCK(sc); + + rt2860_rf_set_chan(sc, ic->ic_curchan); + + RT2860_SOFTC_UNLOCK(sc); +} + +/* + * rt2860_newassoc + */ +static void rt2860_newassoc(struct ieee80211_node *ni, int isnew) +{ + struct rt2860_softc *sc; + struct ieee80211com *ic; + struct ieee80211vap *vap; + struct rt2860_softc_vap *rvap; + struct rt2860_softc_node *rni; + uint16_t aid; + uint8_t wcid; + uint32_t tmp; + + vap = ni->ni_vap; + ic = vap->iv_ic; + sc = ic->ic_softc; + rvap = (struct rt2860_softc_vap *) vap; + rni = (struct rt2860_softc_node *) ni; + + if (isnew) + { + aid = IEEE80211_AID(ni->ni_associd); + rni->staid = rt2860_staid_alloc(sc, aid); + wcid = rni->staid; + + tmp = (ni->ni_macaddr[3] << 24) | + (ni->ni_macaddr[2] << 16) | + (ni->ni_macaddr[1] << 8) | + ni->ni_macaddr[0]; + + rt2860_io_mac_write(sc, RT2860_REG_WCID(wcid), tmp); + + tmp = (ni->ni_macaddr[5] << 8) | + ni->ni_macaddr[4]; + + rt2860_io_mac_write(sc, RT2860_REG_WCID(wcid) + 4, tmp); + + rt2860_amrr_node_init(&rvap->amrr, &sc->amrr_node[wcid], ni); + + RT2860_DPRINTF(sc, RT2860_DEBUG_RATE, + "%s: initial%s node Tx rate: associd=0x%04x, rate=0x%02x, max rate=0x%02x\n", + device_get_nameunit(sc->dev), + (ni->ni_flags & IEEE80211_NODE_HT) ? " HT" : "", + ni->ni_associd, ni->ni_txrate, + (ni->ni_flags & IEEE80211_NODE_HT) ? + (ni->ni_htrates.rs_rates[ni->ni_htrates.rs_nrates - 1] | IEEE80211_RATE_MCS) : + (ni->ni_rates.rs_rates[ni->ni_rates.rs_nrates - 1] & IEEE80211_RATE_VAL)); + + rt2860_asic_updateprot(sc); + rt2860_asic_updateslot(sc); + rt2860_asic_set_txpreamble(sc); + } + + RT2860_DPRINTF(sc, RT2860_DEBUG_NODE, + "%s: new association: isnew=%d, macaddr=%s, associd=0x%04x, staid=0x%02x, QoS %s, ERP %s, HT %s\n", + device_get_nameunit(sc->dev), isnew, ether_sprintf(ni->ni_macaddr), + ni->ni_associd, rni->staid, + (ni->ni_flags & IEEE80211_NODE_QOS) ? "enabled" : "disabled", + (ni->ni_flags & IEEE80211_NODE_ERP) ? "enabled" : "disabled", + (ni->ni_flags & IEEE80211_NODE_HT) ? "enabled" : "disabled"); +} + +/* + * rt2860_updateslot + */ +static void rt2860_updateslot(struct ieee80211com *ic) +{ + struct rt2860_softc *sc; + + sc = ic->ic_softc; + + rt2860_asic_updateslot(sc); +} + +/* + * rt2860_update_promisc + */ +static void rt2860_update_promisc(struct ieee80211com *ic) +{ + struct rt2860_softc *sc; + + sc = ic->ic_softc; + + RT2860_SOFTC_LOCK(sc); + rt2860_asic_update_promisc(sc); + RT2860_SOFTC_UNLOCK(sc); +} + +/* + * rt2860_wme_update + */ +static int rt2860_wme_update(struct ieee80211com *ic) +{ + struct rt2860_softc *sc; + + sc = ic->ic_softc; + + rt2860_asic_wme_update(sc); + + return 0; +} + +/* + * rt2860_raw_xmit + */ +static int rt2860_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, + const struct ieee80211_bpf_params *params) +{ + struct rt2860_softc *sc; + struct ieee80211com *ic; + + ic = ni->ni_ic; + sc = ic->ic_softc; + + if (!(sc->sc_flags & RT2860_RUNNING)) + { + m_freem(m); + ieee80211_free_node(ni); + + return ENETDOWN; + } + + RT2860_SOFTC_TX_RING_LOCK(&sc->tx_ring[sc->tx_ring_mgtqid]); + + if (sc->tx_ring[sc->tx_ring_mgtqid].data_queued >= RT2860_SOFTC_TX_RING_DATA_COUNT) + { + RT2860_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[sc->tx_ring_mgtqid]); + + RT2860_DPRINTF(sc, RT2860_DEBUG_TX, + "%s: raw xmit: Tx ring with qid=%d is full\n", + device_get_nameunit(sc->dev), sc->tx_ring_mgtqid); + + m_freem(m); + ieee80211_free_node(ni); + + sc->tx_data_queue_full[sc->tx_ring_mgtqid]++; + + return ENOBUFS; + } + + if (rt2860_tx_mgmt(sc, m, ni, sc->tx_ring_mgtqid) != 0) + { + RT2860_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[sc->tx_ring_mgtqid]); + + counter_u64_add(sc->sc_ic.ic_oerrors, 1); + + ieee80211_free_node(ni); + + return EIO; + } + + RT2860_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[sc->tx_ring_mgtqid]); + + sc->tx_timer = RT2860_TX_WATCHDOG_TIMEOUT; + + return 0; +} + +/* + * rt2860_recv_action + */ + +#define LE_READ_2(p) \ + ((uint16_t) \ + ((((const uint8_t *)(p))[0] ) | \ + (((const uint8_t *)(p))[1] << 8))) + +static int rt2860_recv_action(struct ieee80211_node *ni, + const struct ieee80211_frame *wh, + const uint8_t *frm, const uint8_t *efrm) +{ + struct rt2860_softc *sc; + struct ieee80211com *ic; + struct rt2860_softc_node *rni; + const struct ieee80211_action *ia; + uint16_t baparamset; + uint8_t wcid; + int tid; + + ic = ni->ni_ic; + sc = ic->ic_softc; + rni = (struct rt2860_softc_node *) ni; + + ia = (const struct ieee80211_action *) frm; + + if (ia->ia_category == IEEE80211_ACTION_CAT_BA) + { + switch (ia->ia_action) + { + /* IEEE80211_ACTION_BA_DELBA */ + case IEEE80211_ACTION_BA_DELBA: + baparamset = LE_READ_2(frm + 2); + tid = RT2860_MS(baparamset, IEEE80211_BAPS_TID); + wcid = rni->staid; + + RT2860_DPRINTF(sc, RT2860_DEBUG_BA, + "%s: received DELBA request: associd=0x%04x, staid=0x%02x, tid=%d\n", + device_get_nameunit(sc->dev), ni->ni_associd, rni->staid, tid); + + if (rni->staid != 0) { + RT2860_SOFTC_LOCK(sc); + + rt2860_asic_del_ba_session(sc, wcid, tid); + RT2860_SOFTC_UNLOCK(sc); + + } + break; + } + } + + return sc->recv_action(ni, wh, frm, efrm); +} + +/* + * rt2860_send_action + */ +static int rt2860_send_action(struct ieee80211_node *ni, + int cat, int act, void *sa) +{ + struct rt2860_softc *sc; + struct ieee80211com *ic; + struct rt2860_softc_node *rni; + uint16_t *args, status, baparamset; + uint8_t wcid; + int tid, bufsize; + + ic = ni->ni_ic; + sc = ic->ic_softc; + rni = (struct rt2860_softc_node *) ni; + + wcid = rni->staid; + args = sa; + + if (cat == IEEE80211_ACTION_CAT_BA) + { + switch (act) + { + /* IEEE80211_ACTION_BA_ADDBA_RESPONSE */ + case IEEE80211_ACTION_BA_ADDBA_RESPONSE: + status = args[1]; + baparamset = args[2]; + tid = RT2860_MS(baparamset, IEEE80211_BAPS_TID); + bufsize = RT2860_MS(baparamset, IEEE80211_BAPS_BUFSIZ); + + RT2860_DPRINTF(sc, RT2860_DEBUG_BA, + "%s: sending ADDBA response: associd=0x%04x, staid=0x%02x, status=%d, tid=%d, bufsize=%d\n", + device_get_nameunit(sc->dev), ni->ni_associd, rni->staid, status, tid, bufsize); + + if (status == IEEE80211_STATUS_SUCCESS) { + RT2860_SOFTC_LOCK(sc); + + rt2860_asic_add_ba_session(sc, wcid, tid); + RT2860_SOFTC_UNLOCK(sc); + + } + break; + + /* IEEE80211_ACTION_BA_DELBA */ + case IEEE80211_ACTION_BA_DELBA: + baparamset = RT2860_SM(args[0], IEEE80211_DELBAPS_TID) | args[1]; + tid = RT2860_MS(baparamset, IEEE80211_DELBAPS_TID); + + RT2860_DPRINTF(sc, RT2860_DEBUG_BA, + "%s: sending DELBA request: associd=0x%04x, staid=0x%02x, tid=%d\n", + device_get_nameunit(sc->dev), ni->ni_associd, rni->staid, tid); + + if (RT2860_MS(baparamset, IEEE80211_DELBAPS_INIT) != IEEE80211_DELBAPS_INIT) { + RT2860_SOFTC_LOCK(sc); + + rt2860_asic_del_ba_session(sc, wcid, tid); + RT2860_SOFTC_UNLOCK(sc); + + } + break; + } + } + + return sc->send_action(ni, cat, act, sa); +} + +/* + * rt2860_addba_response + */ +static int rt2860_addba_response(struct ieee80211_node *ni, + struct ieee80211_tx_ampdu *tap, + int status, int baparamset, int batimeout) +{ + struct rt2860_softc *sc; + struct ieee80211com *ic; + struct rt2860_softc_node *rni; + ieee80211_seq seqno; + int ret, tid, old_bufsize, new_bufsize; + + ic = ni->ni_ic; + sc = ic->ic_softc; + rni = (struct rt2860_softc_node *) ni; + + tid = RT2860_MS(baparamset, IEEE80211_BAPS_TID); + old_bufsize = RT2860_MS(baparamset, IEEE80211_BAPS_BUFSIZ); + new_bufsize = old_bufsize; + + if (status == IEEE80211_STATUS_SUCCESS) + { + if (sc->mac_rev >= 0x28830300) + { + if (sc->mac_rev >= 0x30700200) + new_bufsize = 13; + else + new_bufsize = 31; + } + else if (sc->mac_rev >= 0x28720200) + { + new_bufsize = 13; + } + else + { + new_bufsize = 7; + } + + if (old_bufsize > new_bufsize) + { + baparamset &= ~IEEE80211_BAPS_BUFSIZ; + baparamset = RT2860_SM(new_bufsize, IEEE80211_BAPS_BUFSIZ); + } + + if (!(tap->txa_flags & IEEE80211_AGGR_RUNNING)) + { + sc->tx_ampdu_sessions++; + + if (sc->tx_ampdu_sessions == 1) { + RT2860_SOFTC_LOCK(sc); + + rt2860_asic_updateprot(sc); + RT2860_SOFTC_UNLOCK(sc); + + } + } + } + + RT2860_DPRINTF(sc, RT2860_DEBUG_BA, + "%s: received ADDBA response: associd=0x%04x, staid=0x%02x, status=%d, tid=%d, " + "old bufsize=%d, new bufsize=%d\n", + device_get_nameunit(sc->dev), ni->ni_associd, rni->staid, status, tid, + old_bufsize, new_bufsize); + + ret = sc->addba_response(ni, tap, status, baparamset, batimeout); + + if (status == IEEE80211_STATUS_SUCCESS) + { + seqno = ni->ni_txseqs[tid]; + + rt2860_send_bar(ni, tap, seqno); + } + + return ret; +} + +/* + * rt2860_addba_stop + */ +static void rt2860_addba_stop(struct ieee80211_node *ni, + struct ieee80211_tx_ampdu *tap) +{ + struct rt2860_softc *sc; + struct ieee80211com *ic; + struct rt2860_softc_node *rni; + int tid; + + ic = ni->ni_ic; + sc = ic->ic_softc; + rni = (struct rt2860_softc_node *) ni; + +// tid = WME_AC_TO_TID(tap->txa_ac); + tid = WME_AC_TO_TID(tap->txa_tid); + + RT2860_DPRINTF(sc, RT2860_DEBUG_BA, + "%s: stopping A-MPDU Tx: associd=0x%04x, staid=0x%02x, tid=%d\n", + device_get_nameunit(sc->dev), ni->ni_associd, rni->staid, tid); + + if (tap->txa_flags & IEEE80211_AGGR_RUNNING) + { + if (sc->tx_ampdu_sessions > 0) + { + sc->tx_ampdu_sessions--; + + if (sc->tx_ampdu_sessions == 0) { + RT2860_SOFTC_LOCK(sc); + + rt2860_asic_updateprot(sc); + RT2860_SOFTC_UNLOCK(sc); + + } + } + else + { + printf("%s: number of A-MPDU Tx sessions cannot be negative\n", + device_get_nameunit(sc->dev)); + } + } + + sc->addba_stop(ni, tap); +} + +/* + * rt2860_ampdu_rx_start + */ +static int rt2860_ampdu_rx_start(struct ieee80211_node *ni, + struct ieee80211_rx_ampdu *rap, + int baparamset, int batimeout, int baseqctl) +{ + struct rt2860_softc *sc; + struct ieee80211com *ic; + struct rt2860_softc_node *rni; + int tid; + + ic = ni->ni_ic; + sc = ic->ic_softc; + rni = (struct rt2860_softc_node *) ni; + + tid = RT2860_MS(baparamset, IEEE80211_BAPS_TID); + + RT2860_DPRINTF(sc, RT2860_DEBUG_BA, + "%s: starting A-MPDU Rx: associd=0x%04x, staid=0x%02x, tid=%d\n", + device_get_nameunit(sc->dev), ni->ni_associd, rni->staid, tid); + + if (!(rap->rxa_flags & IEEE80211_AGGR_RUNNING)) + sc->rx_ampdu_sessions++; + + return sc->ampdu_rx_start(ni, rap, baparamset, batimeout, baseqctl); +} + +/* + * rt2860_ampdu_rx_stop + */ +static void rt2860_ampdu_rx_stop(struct ieee80211_node *ni, + struct ieee80211_rx_ampdu *rap) +{ + struct rt2860_softc *sc; + struct ieee80211com *ic; + struct rt2860_softc_node *rni; + + ic = ni->ni_ic; + sc = ic->ic_softc; + rni = (struct rt2860_softc_node *) ni; + + RT2860_DPRINTF(sc, RT2860_DEBUG_BA, + "%s: stopping A-MPDU Rx: associd=0x%04x, staid=0x%02x\n", + device_get_nameunit(sc->dev), ni->ni_associd, rni->staid); + + if (rap->rxa_flags & IEEE80211_AGGR_RUNNING) + { + if (sc->rx_ampdu_sessions > 0) + sc->rx_ampdu_sessions--; + else + printf("%s: number of A-MPDU Rx sessions cannot be negative\n", + device_get_nameunit(sc->dev)); + } + + sc->ampdu_rx_stop(ni, rap); +} + +/* + * rt2860_send_bar + */ +static int rt2860_send_bar(struct ieee80211_node *ni, + struct ieee80211_tx_ampdu *tap, ieee80211_seq seqno) +{ + struct rt2860_softc *sc; + struct ieee80211com *ic; + struct ieee80211vap *vap; + struct ieee80211_frame_bar *bar; + struct rt2860_softc_node *rni; + struct mbuf *m; + uint16_t barctl, barseqctl; + uint8_t *frm; + int ret, tid; + + ic = ni->ni_ic; + sc = ic->ic_softc; + vap = ni->ni_vap; + rni = (struct rt2860_softc_node *) ni; + + if (!(tap->txa_flags & IEEE80211_AGGR_RUNNING)) + return EINVAL; + + m = ieee80211_getmgtframe(&frm, ic->ic_headroom, sizeof(struct ieee80211_frame_bar)); + if (m == NULL) + return ENOMEM; + + bar = mtod(m, struct ieee80211_frame_bar *); + + bar->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR; + bar->i_fc[1] = 0; + + IEEE80211_ADDR_COPY(bar->i_ra, ni->ni_macaddr); + IEEE80211_ADDR_COPY(bar->i_ta, vap->iv_myaddr); + +// tid = WME_AC_TO_TID(tap->txa_ac); + tid = WME_AC_TO_TID(tap->txa_tid); + + barctl = (tap->txa_flags & IEEE80211_AGGR_IMMEDIATE ? 0 : IEEE80211_BAR_NOACK) | + IEEE80211_BAR_COMP | + RT2860_SM(tid, IEEE80211_BAR_TID); + barseqctl = RT2860_SM(seqno, IEEE80211_BAR_SEQ_START); + + bar->i_ctl = htole16(barctl); + bar->i_seq = htole16(barseqctl); + + m->m_pkthdr.len = m->m_len = sizeof(struct ieee80211_frame_bar); + + tap->txa_start = seqno; + + ieee80211_ref_node(ni); + + RT2860_DPRINTF(sc, RT2860_DEBUG_BA, + "%s: sending BAR: associd=0x%04x, staid=0x%02x, tid=%d, seqno=%d\n", + device_get_nameunit(sc->dev), ni->ni_associd, rni->staid, tid, seqno); + + ret = ic->ic_raw_xmit(ni, m, NULL); + if (ret != 0) + ieee80211_free_node(ni); + + return ret; +} + +/* + * rt2860_amrr_update_iter_func + */ +static void rt2860_amrr_update_iter_func(void *arg, struct ieee80211_node *ni) +{ + struct rt2860_softc *sc; + struct ieee80211com *ic; + struct ieee80211vap *vap; + struct rt2860_softc_vap *rvap; + struct rt2860_softc_node *rni; + uint8_t wcid; + + vap = arg; + ic = vap->iv_ic; + sc = ic->ic_softc; + rvap = (struct rt2860_softc_vap *) vap; + rni = (struct rt2860_softc_node *) ni; + + /* only associated stations */ + + if ((ni->ni_vap == vap) && (rni->staid != 0)) + { + wcid = rni->staid; + + RT2860_DPRINTF(sc, RT2860_DEBUG_RATE, + "%s: AMRR node: staid=0x%02x, txcnt=%d, success=%d, retrycnt=%d\n", + device_get_nameunit(sc->dev), + rni->staid, sc->amrr_node[wcid].txcnt, sc->amrr_node[wcid].success, sc->amrr_node[wcid].retrycnt); + + rt2860_amrr_choose(ni, &sc->amrr_node[wcid]); + + RT2860_DPRINTF(sc, RT2860_DEBUG_RATE, + "%s:%s node Tx rate: associd=0x%04x, staid=0x%02x, rate=0x%02x, max rate=0x%02x\n", + device_get_nameunit(sc->dev), + (ni->ni_flags & IEEE80211_NODE_HT) ? " HT" : "", + ni->ni_associd, rni->staid, ni->ni_txrate, + (ni->ni_flags & IEEE80211_NODE_HT) ? + (ni->ni_htrates.rs_rates[ni->ni_htrates.rs_nrates - 1] | IEEE80211_RATE_MCS) : + (ni->ni_rates.rs_rates[ni->ni_rates.rs_nrates - 1] & IEEE80211_RATE_VAL)); + } +} + +/* + * rt2860_periodic + */ +static void rt2860_periodic(void *arg) +{ + struct rt2860_softc *sc; + + sc = arg; + + RT2860_DPRINTF(sc, RT2860_DEBUG_PERIODIC, + "%s: periodic\n", + device_get_nameunit(sc->dev)); + + taskqueue_enqueue(sc->taskqueue, &sc->periodic_task); +} + +/* + * rt2860_tx_watchdog + */ +static void rt2860_tx_watchdog(void *arg) +{ + struct rt2860_softc *sc; + + sc = arg; + + if (sc->tx_timer == 0) + return; + + if (--sc->tx_timer == 0) + { + printf("%s: Tx watchdog timeout: resetting\n", + device_get_nameunit(sc->dev)); + + rt2860_stop_locked(sc); + rt2860_init_locked(sc); + + counter_u64_add(sc->sc_ic.ic_oerrors, 1); + + sc->tx_watchdog_timeouts++; + } + + callout_reset(&sc->tx_watchdog_ch, hz, rt2860_tx_watchdog, sc); +} + +/* + * rt2860_staid_alloc + */ +static int rt2860_staid_alloc(struct rt2860_softc *sc, int aid) +{ + int staid; + + if ((aid > 0 && aid < RT2860_SOFTC_STAID_COUNT) && isclr(sc->staid_mask, aid)) + { + staid = aid; + } + else + { + for (staid = 1; staid < RT2860_SOFTC_STAID_COUNT; staid++) + { + if (isclr(sc->staid_mask, staid)) + break; + } + } + + setbit(sc->staid_mask, staid); + + return staid; +} + +/* + * rt2860_staid_delete + */ +static void rt2860_staid_delete(struct rt2860_softc *sc, int staid) +{ + clrbit(sc->staid_mask, staid); +} + +/* + * rt2860_asic_set_bssid + */ +static void rt2860_asic_set_bssid(struct rt2860_softc *sc, + const uint8_t *bssid) +{ + uint32_t tmp; + + RT2860_DPRINTF(sc, RT2860_DEBUG_STATE, + "%s: set bssid: bssid=%s\n", + device_get_nameunit(sc->dev), + ether_sprintf(bssid)); + + tmp = bssid[0] | (bssid[1]) << 8 | (bssid[2] << 16) | (bssid[3] << 24); + + rt2860_io_mac_write(sc, RT2860_REG_BSSID_DW0, tmp); + + tmp = bssid[4] | (bssid[5] << 8); + + rt2860_io_mac_write(sc, RT2860_REG_BSSID_DW1, tmp); +} + +/* + * rt2860_asic_set_macaddr + */ +static void rt2860_asic_set_macaddr(struct rt2860_softc *sc, + const uint8_t *addr) +{ + uint32_t tmp; + + tmp = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24); + + rt2860_io_mac_write(sc, RT2860_REG_ADDR_DW0, tmp); + + tmp = addr[4] | (addr[5] << 8) | (0xff << 16); + + rt2860_io_mac_write(sc, RT2860_REG_ADDR_DW1, tmp); +} + +/* + * rt2860_asic_enable_tsf_sync + */ +static void rt2860_asic_enable_tsf_sync(struct rt2860_softc *sc) +{ + struct ieee80211com *ic; + struct ieee80211vap *vap; + uint32_t tmp; + + ic = &sc->sc_ic; + vap = TAILQ_FIRST(&ic->ic_vaps); + + RT2860_DPRINTF(sc, RT2860_DEBUG_BEACON, + "%s: enabling TSF\n", + device_get_nameunit(sc->dev)); + + tmp = rt2860_io_mac_read(sc, RT2860_REG_BCN_TIME_CFG); + + tmp &= ~0x1fffff; + tmp |= vap->iv_bss->ni_intval * 16; + tmp |= (RT2860_REG_TSF_TIMER_ENABLE | RT2860_REG_TBTT_TIMER_ENABLE); + + if (vap->iv_opmode == IEEE80211_M_STA) + { + tmp |= (RT2860_REG_TSF_SYNC_MODE_STA << RT2860_REG_TSF_SYNC_MODE_SHIFT); + } + else if (vap->iv_opmode == IEEE80211_M_IBSS) + { + tmp |= RT2860_REG_BCN_TX_ENABLE; + tmp |= (RT2860_REG_TSF_SYNC_MODE_IBSS << RT2860_REG_TSF_SYNC_MODE_SHIFT); + } + else if (vap->iv_opmode == IEEE80211_M_HOSTAP) + { + tmp |= RT2860_REG_BCN_TX_ENABLE; + tmp |= (RT2860_REG_TSF_SYNC_MODE_HOSTAP << RT2860_REG_TSF_SYNC_MODE_SHIFT); + } + + rt2860_io_mac_write(sc, RT2860_REG_BCN_TIME_CFG, tmp); +} + +/* + * rt2860_asic_disable_tsf_sync + */ +static void rt2860_asic_disable_tsf_sync(struct rt2860_softc *sc) +{ + uint32_t tmp; + + RT2860_DPRINTF(sc, RT2860_DEBUG_BEACON, + "%s: disabling TSF\n", + device_get_nameunit(sc->dev)); + + tmp = rt2860_io_mac_read(sc, RT2860_REG_BCN_TIME_CFG); + + tmp &= ~(RT2860_REG_BCN_TX_ENABLE | + RT2860_REG_TSF_TIMER_ENABLE | + RT2860_REG_TBTT_TIMER_ENABLE); + + tmp &= ~(RT2860_REG_TSF_SYNC_MODE_MASK << RT2860_REG_TSF_SYNC_MODE_SHIFT); + tmp |= (RT2860_REG_TSF_SYNC_MODE_DISABLE << RT2860_REG_TSF_SYNC_MODE_SHIFT); + + rt2860_io_mac_write(sc, RT2860_REG_BCN_TIME_CFG, tmp); +} + +/* + * rt2860_asic_enable_mrr + */ +static void rt2860_asic_enable_mrr(struct rt2860_softc *sc) +{ +#define CCK(mcs) (mcs) +#define OFDM(mcs) ((1 << 3) | (mcs)) +#define HT(mcs) (mcs) + + rt2860_io_mac_write(sc, RT2860_REG_TX_LG_FBK_CFG0, + (OFDM(6) << 28) | /* 54 -> 48 */ + (OFDM(5) << 24) | /* 48 -> 36 */ + (OFDM(4) << 20) | /* 36 -> 24 */ + (OFDM(3) << 16) | /* 24 -> 18 */ + (OFDM(2) << 12) | /* 18 -> 12 */ + (OFDM(1) << 8) | /* 12 -> 9 */ + (OFDM(0) << 4) | /* 9 -> 6 */ + OFDM(0)); /* 6 -> 6 */ + + rt2860_io_mac_write(sc, RT2860_REG_TX_LG_FBK_CFG1, + (CCK(2) << 12) | /* 11 -> 5.5 */ + (CCK(1) << 8) | /* 5.5 -> 2 */ + (CCK(0) << 4) | /* 2 -> 1 */ + CCK(0)); /* 1 -> 1 */ + + rt2860_io_mac_write(sc, RT2860_REG_TX_HT_FBK_CFG0, + (HT(6) << 28) | + (HT(5) << 24) | + (HT(4) << 20) | + (HT(3) << 16) | + (HT(2) << 12) | + (HT(1) << 8) | + (HT(0) << 4) | + HT(0)); + + rt2860_io_mac_write(sc, RT2860_REG_TX_HT_FBK_CFG1, + (HT(14) << 28) | + (HT(13) << 24) | + (HT(12) << 20) | + (HT(11) << 16) | + (HT(10) << 12) | + (HT(9) << 8) | + (HT(8) << 4) | + HT(7)); + +#undef HT +#undef OFDM +#undef CCK +} + +/* + * rt2860_asic_set_txpreamble + */ +static void rt2860_asic_set_txpreamble(struct rt2860_softc *sc) +{ + struct ieee80211com *ic; + uint32_t tmp; + + ic = &sc->sc_ic; + + RT2860_DPRINTF(sc, RT2860_DEBUG_STATE, + "%s: %s short Tx preamble\n", + device_get_nameunit(sc->dev), + (ic->ic_flags & IEEE80211_F_SHPREAMBLE) ? "enabling" : "disabling"); + + tmp = rt2860_io_mac_read(sc, RT2860_REG_AUTO_RSP_CFG); + + tmp &= ~RT2860_REG_CCK_SHORT_ENABLE; + + if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) + tmp |= RT2860_REG_CCK_SHORT_ENABLE; + + rt2860_io_mac_write(sc, RT2860_REG_AUTO_RSP_CFG, tmp); +} + +/* + * rt2860_asic_set_basicrates + */ +static void rt2860_asic_set_basicrates(struct rt2860_softc *sc) +{ + struct ieee80211com *ic; + + ic = &sc->sc_ic; + + if (ic->ic_curmode == IEEE80211_MODE_11B) + rt2860_io_mac_write(sc, RT2860_REG_LEGACY_BASIC_RATE, 0xf); + else if (ic->ic_curmode == IEEE80211_MODE_11A) + rt2860_io_mac_write(sc, RT2860_REG_LEGACY_BASIC_RATE, 0x150); + else + rt2860_io_mac_write(sc, RT2860_REG_LEGACY_BASIC_RATE, 0x15f); +} + +/* + * rt2860_asic_update_rtsthreshold + */ +static void rt2860_asic_update_rtsthreshold(struct rt2860_softc *sc) +{ + struct ieee80211com *ic; + struct ieee80211vap *vap; + uint32_t tmp; + uint16_t threshold; + + ic = &sc->sc_ic; + vap = TAILQ_FIRST(&ic->ic_vaps); + + if (vap == NULL) + threshold = IEEE80211_RTS_MAX; + else if (vap->iv_flags_ht & IEEE80211_FHT_AMSDU_TX) + threshold = 0x1000; + else + threshold = vap->iv_rtsthreshold; + + RT2860_DPRINTF(sc, RT2860_DEBUG_PROT, + "%s: updating RTS threshold: %d\n", + device_get_nameunit(sc->dev), threshold); + + tmp = rt2860_io_mac_read(sc, RT2860_REG_TX_RTS_CFG); + + tmp &= ~(RT2860_REG_TX_RTS_THRESHOLD_MASK << RT2860_REG_TX_RTS_THRESHOLD_SHIFT); + + tmp |= ((threshold & RT2860_REG_TX_RTS_THRESHOLD_MASK) << + RT2860_REG_TX_RTS_THRESHOLD_SHIFT); + + rt2860_io_mac_write(sc, RT2860_REG_TX_RTS_CFG, tmp); +} + +/* + * rt2860_asic_update_txpower + */ +static void rt2860_asic_update_txpower(struct rt2860_softc *sc) +{ + struct ieee80211com *ic; + uint32_t *txpow_rate; + int8_t delta; + uint8_t val; + uint32_t tmp; + int i; + + ic = &sc->sc_ic; + + RT2860_DPRINTF(sc, RT2860_DEBUG_STATE, + "%s: updating Tx power: %d\n", + device_get_nameunit(sc->dev), ic->ic_txpowlimit); + + if (!IEEE80211_IS_CHAN_HT40(ic->ic_curchan)) + { + txpow_rate = sc->txpow_rate_20mhz; + } + else + { + if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) + txpow_rate = sc->txpow_rate_40mhz_2ghz; + else + txpow_rate = sc->txpow_rate_40mhz_5ghz; + } + + delta = 0; + + val = rt2860_io_bbp_read(sc, 1); + val &= 0xfc; + + if (ic->ic_txpowlimit > 90) + { + /* do nothing */ + } + else if (ic->ic_txpowlimit > 60) + { + delta -= 1; + } + else if (ic->ic_txpowlimit > 30) + { + delta -= 3; + } + else if (ic->ic_txpowlimit > 15) + { + val |= 0x1; + } + else if (ic->ic_txpowlimit > 9) + { + val |= 0x1; + delta -= 3; + } + else + { + val |= 0x2; + } + + rt2860_io_bbp_write(sc, 1, val); + + for (i = 0; i < RT2860_SOFTC_TXPOW_RATE_COUNT; i++) + { + if (txpow_rate[i] == 0xffffffff) + continue; + + tmp = rt2860_read_eeprom_txpow_rate_add_delta(txpow_rate[i], delta); + + rt2860_io_mac_write(sc, RT2860_REG_TX_PWR_CFG(i), tmp); + } +} + +/* + * rt2860_asic_update_promisc + */ +static void rt2860_asic_update_promisc(struct rt2860_softc *sc) +{ + struct ieee80211com *ic; + uint32_t tmp; + + ic = &sc->sc_ic; + + printf("%s: %s promiscuous mode\n", + device_get_nameunit(sc->dev), + (ic->ic_promisc == 1) ? "entering" : "leaving"); + + tmp = rt2860_io_mac_read(sc, RT2860_REG_RX_FILTER_CFG); + + tmp &= ~RT2860_REG_RX_FILTER_DROP_UC_NOME; + + if (ic->ic_promisc == 0) + tmp |= RT2860_REG_RX_FILTER_DROP_UC_NOME; + + rt2860_io_mac_write(sc, RT2860_REG_RX_FILTER_CFG, tmp); +} + +/* + * rt2860_asic_updateprot + */ +static void rt2860_asic_updateprot(struct rt2860_softc *sc) +{ + struct ieee80211com *ic; + struct ieee80211vap *vap; + uint32_t cck_prot, ofdm_prot, mm20_prot, mm40_prot, gf20_prot, gf40_prot; + uint8_t htopmode; + enum ieee80211_protmode htprotmode; + + ic = &sc->sc_ic; + vap = TAILQ_FIRST(&ic->ic_vaps); + + /* CCK frame protection */ + + cck_prot = RT2860_REG_RTSTH_ENABLE | RT2860_REG_PROT_NAV_SHORT | + RT2860_REG_TXOP_ALLOW_ALL | RT2860_REG_PROT_CTRL_NONE; + + /* set up protection frame phy mode and rate (MCS code) */ + + if (ic->ic_curmode == IEEE80211_MODE_11A) + cck_prot |= (RT2860_REG_PROT_PHYMODE_OFDM << RT2860_REG_PROT_PHYMODE_SHIFT) | + (0 << RT2860_REG_PROT_MCS_SHIFT); + else + cck_prot |= ((RT2860_REG_PROT_PHYMODE_CCK << RT2860_REG_PROT_PHYMODE_SHIFT) | + (3 << RT2860_REG_PROT_MCS_SHIFT)); + + rt2860_io_mac_write(sc, RT2860_REG_TX_CCK_PROT_CFG, cck_prot); + + /* OFDM frame protection */ + + ofdm_prot = RT2860_REG_RTSTH_ENABLE | RT2860_REG_PROT_NAV_SHORT | + RT2860_REG_TXOP_ALLOW_ALL; + + if (ic->ic_flags & IEEE80211_F_USEPROT) + { + RT2860_DPRINTF(sc, RT2860_DEBUG_PROT, + "%s: updating protection mode: b/g protection mode=%s\n", + device_get_nameunit(sc->dev), + (ic->ic_protmode == IEEE80211_PROT_RTSCTS) ? "RTS/CTS" : + ((ic->ic_protmode == IEEE80211_PROT_CTSONLY) ? "CTS-to-self" : "none")); + + if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) + ofdm_prot |= RT2860_REG_PROT_CTRL_RTS_CTS; + else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) + ofdm_prot |= RT2860_REG_PROT_CTRL_CTS; + else + ofdm_prot |= RT2860_REG_PROT_CTRL_NONE; + } + else + { + RT2860_DPRINTF(sc, RT2860_DEBUG_PROT, + "%s: updating protection mode: b/g protection mode=%s\n", + device_get_nameunit(sc->dev), "none"); + + ofdm_prot |= RT2860_REG_PROT_CTRL_NONE; + } + + rt2860_io_mac_write(sc, RT2860_REG_TX_OFDM_PROT_CFG, ofdm_prot); + + /* HT frame protection */ + + if ((vap != NULL) && (vap->iv_opmode == IEEE80211_M_STA) && (vap->iv_state == IEEE80211_S_RUN)) + htopmode = vap->iv_bss->ni_htopmode; + else + htopmode = ic->ic_curhtprotmode; + + htprotmode = ic->ic_htprotmode; + + /* force HT mixed mode and RTS/CTS protection if A-MPDU Tx aggregation is enabled */ + + if (sc->tx_ampdu_sessions > 0) + { + RT2860_DPRINTF(sc, RT2860_DEBUG_PROT, + "%s: updating protection mode: forcing HT mixed mode and RTS/CTS protection\n", + device_get_nameunit(sc->dev)); + + htopmode = IEEE80211_HTINFO_OPMODE_MIXED; + htprotmode = IEEE80211_PROT_RTSCTS; + } + + RT2860_DPRINTF(sc, RT2860_DEBUG_PROT, + "%s: updating protection mode: HT operation mode=0x%02x, protection mode=%s\n", + device_get_nameunit(sc->dev), + htopmode & IEEE80211_HTINFO_OPMODE, + (htprotmode == IEEE80211_PROT_RTSCTS) ? "RTS/CTS" : + ((htprotmode == IEEE80211_PROT_CTSONLY) ? "CTS-to-self" : "none")); + + switch (htopmode & IEEE80211_HTINFO_OPMODE) + { + /* IEEE80211_HTINFO_OPMODE_HT20PR */ + case IEEE80211_HTINFO_OPMODE_HT20PR: + mm20_prot = RT2860_REG_PROT_NAV_SHORT | RT2860_REG_PROT_CTRL_NONE | + RT2860_REG_TXOP_ALLOW_CCK | RT2860_REG_TXOP_ALLOW_OFDM | + RT2860_REG_TXOP_ALLOW_MM20 | RT2860_REG_TXOP_ALLOW_GF20 | + (RT2860_REG_PROT_PHYMODE_OFDM << RT2860_REG_PROT_PHYMODE_SHIFT) | + (4 << RT2860_REG_PROT_MCS_SHIFT); + + gf20_prot = mm20_prot; + + mm40_prot = RT2860_REG_PROT_NAV_SHORT | RT2860_REG_TXOP_ALLOW_ALL | + (RT2860_REG_PROT_PHYMODE_OFDM << RT2860_REG_PROT_PHYMODE_SHIFT) | + (0x84 << RT2860_REG_PROT_MCS_SHIFT); + + if (htprotmode == IEEE80211_PROT_RTSCTS) + mm40_prot |= RT2860_REG_PROT_CTRL_RTS_CTS; + else if (htprotmode == IEEE80211_PROT_CTSONLY) + mm40_prot |= RT2860_REG_PROT_CTRL_CTS; + else + mm40_prot |= RT2860_REG_PROT_CTRL_NONE; + + gf40_prot = mm40_prot; + break; + + /* IEEE80211_HTINFO_OPMODE_MIXED */ + case IEEE80211_HTINFO_OPMODE_MIXED: + mm20_prot = RT2860_REG_PROT_NAV_SHORT | + RT2860_REG_TXOP_ALLOW_CCK | RT2860_REG_TXOP_ALLOW_OFDM | + RT2860_REG_TXOP_ALLOW_MM20 | RT2860_REG_TXOP_ALLOW_GF20; + + if (ic->ic_flags & IEEE80211_F_USEPROT) + mm20_prot |= (RT2860_REG_PROT_PHYMODE_CCK << RT2860_REG_PROT_PHYMODE_SHIFT) | + (3 << RT2860_REG_PROT_MCS_SHIFT); + else + mm20_prot |= (RT2860_REG_PROT_PHYMODE_OFDM << RT2860_REG_PROT_PHYMODE_SHIFT) | + (4 << RT2860_REG_PROT_MCS_SHIFT); + + if (htprotmode == IEEE80211_PROT_RTSCTS) + mm20_prot |= RT2860_REG_PROT_CTRL_RTS_CTS; + else if (htprotmode == IEEE80211_PROT_CTSONLY) + mm20_prot |= RT2860_REG_PROT_CTRL_CTS; + else + mm20_prot |= RT2860_REG_PROT_CTRL_NONE; + + gf20_prot = mm20_prot; + + mm40_prot = RT2860_REG_PROT_NAV_SHORT | RT2860_REG_TXOP_ALLOW_ALL; + + if (ic->ic_flags & IEEE80211_F_USEPROT) + mm40_prot |= (RT2860_REG_PROT_PHYMODE_CCK << RT2860_REG_PROT_PHYMODE_SHIFT) | + (3 << RT2860_REG_PROT_MCS_SHIFT); + else + mm40_prot |= (RT2860_REG_PROT_PHYMODE_OFDM << RT2860_REG_PROT_PHYMODE_SHIFT) | + (0x84 << RT2860_REG_PROT_MCS_SHIFT); + + if (htprotmode == IEEE80211_PROT_RTSCTS) + mm40_prot |= RT2860_REG_PROT_CTRL_RTS_CTS; + else if (htprotmode == IEEE80211_PROT_CTSONLY) + mm40_prot |= RT2860_REG_PROT_CTRL_CTS; + else + mm40_prot |= RT2860_REG_PROT_CTRL_NONE; + + gf40_prot = mm40_prot; + break; + + /* + * IEEE80211_HTINFO_OPMODE_PURE + * IEEE80211_HTINFO_OPMODE_PROTOPT + */ + case IEEE80211_HTINFO_OPMODE_PURE: + case IEEE80211_HTINFO_OPMODE_PROTOPT: + default: + mm20_prot = RT2860_REG_PROT_NAV_SHORT | RT2860_REG_PROT_CTRL_NONE | + RT2860_REG_TXOP_ALLOW_CCK | RT2860_REG_TXOP_ALLOW_OFDM | + RT2860_REG_TXOP_ALLOW_MM20 | RT2860_REG_TXOP_ALLOW_GF20 | + (RT2860_REG_PROT_PHYMODE_OFDM << RT2860_REG_PROT_PHYMODE_SHIFT) | + (4 << RT2860_REG_PROT_MCS_SHIFT); + + gf20_prot = mm20_prot; + + mm40_prot = RT2860_REG_PROT_NAV_SHORT | RT2860_REG_PROT_CTRL_NONE | + RT2860_REG_TXOP_ALLOW_ALL | + (RT2860_REG_PROT_PHYMODE_OFDM << RT2860_REG_PROT_PHYMODE_SHIFT) | + (0x84 << RT2860_REG_PROT_MCS_SHIFT); + + gf40_prot = mm40_prot; + break; + } + + rt2860_io_mac_write(sc, RT2860_REG_TX_MM20_PROT_CFG, mm20_prot); + rt2860_io_mac_write(sc, RT2860_REG_TX_MM40_PROT_CFG, mm40_prot); + rt2860_io_mac_write(sc, RT2860_REG_TX_GF20_PROT_CFG, gf20_prot); + rt2860_io_mac_write(sc, RT2860_REG_TX_GF40_PROT_CFG, gf40_prot); +} + +/* + * rt2860_asic_updateslot + */ +static void rt2860_asic_updateslot(struct rt2860_softc *sc) +{ + struct ieee80211com *ic; + struct ieee80211vap *vap; + uint32_t tmp; + + ic = &sc->sc_ic; + vap = TAILQ_FIRST(&ic->ic_vaps); + + RT2860_DPRINTF(sc, RT2860_DEBUG_STATE, + "%s: %s short slot time\n", + device_get_nameunit(sc->dev), + ((ic->ic_flags & IEEE80211_F_SHSLOT) || + ((vap != NULL) && (vap->iv_flags & IEEE80211_F_BURST))) ? "enabling" : "disabling"); + + tmp = rt2860_io_mac_read(sc, RT2860_REG_BKOFF_SLOT_CFG); + + tmp &= ~0xff; + + if ((ic->ic_flags & IEEE80211_F_SHSLOT) || + ((vap != NULL) && (vap->iv_flags & IEEE80211_F_BURST))) + tmp |= IEEE80211_DUR_SHSLOT; + else + tmp |= IEEE80211_DUR_SLOT; + + rt2860_io_mac_write(sc, RT2860_REG_BKOFF_SLOT_CFG, tmp); +} + +/* + * rt2860_asic_wme_update + */ +static void rt2860_asic_wme_update(struct rt2860_softc *sc) +{ + struct ieee80211com *ic; + struct ieee80211_wme_state *wme; + const struct wmeParams *wmep; + int i; + + ic = &sc->sc_ic; + wme = &ic->ic_wme; + wmep = wme->wme_chanParams.cap_wmeParams; + + RT2860_DPRINTF(sc, RT2860_DEBUG_WME, + "%s: wme update: WME_AC_VO=%d/%d/%d/%d, WME_AC_VI=%d/%d/%d/%d, " + "WME_AC_BK=%d/%d/%d/%d, WME_AC_BE=%d/%d/%d/%d\n", + device_get_nameunit(sc->dev), + wmep[WME_AC_VO].wmep_aifsn, + wmep[WME_AC_VO].wmep_logcwmin, wmep[WME_AC_VO].wmep_logcwmax, + wmep[WME_AC_VO].wmep_txopLimit, + wmep[WME_AC_VI].wmep_aifsn, + wmep[WME_AC_VI].wmep_logcwmin, wmep[WME_AC_VI].wmep_logcwmax, + wmep[WME_AC_VI].wmep_txopLimit, + wmep[WME_AC_BK].wmep_aifsn, + wmep[WME_AC_BK].wmep_logcwmin, wmep[WME_AC_BK].wmep_logcwmax, + wmep[WME_AC_BK].wmep_txopLimit, + wmep[WME_AC_BE].wmep_aifsn, + wmep[WME_AC_BE].wmep_logcwmin, wmep[WME_AC_BE].wmep_logcwmax, + wmep[WME_AC_BE].wmep_txopLimit); + + for (i = 0; i < WME_NUM_AC; i++) + rt2860_io_mac_write(sc, RT2860_REG_TX_EDCA_AC_CFG(i), + (wmep[i].wmep_logcwmax << 16) | (wmep[i].wmep_logcwmin << 12) | + (wmep[i].wmep_aifsn << 8) | wmep[i].wmep_txopLimit); + + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_WMM_AIFSN_CFG, + (wmep[WME_AC_VO].wmep_aifsn << 12) | (wmep[WME_AC_VI].wmep_aifsn << 8) | + (wmep[WME_AC_BK].wmep_aifsn << 4) | wmep[WME_AC_BE].wmep_aifsn); + + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_WMM_CWMIN_CFG, + (wmep[WME_AC_VO].wmep_logcwmin << 12) | (wmep[WME_AC_VI].wmep_logcwmin << 8) | + (wmep[WME_AC_BK].wmep_logcwmin << 4) | wmep[WME_AC_BE].wmep_logcwmin); + + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_WMM_CWMAX_CFG, + (wmep[WME_AC_VO].wmep_logcwmax << 12) | (wmep[WME_AC_VI].wmep_logcwmax << 8) | + (wmep[WME_AC_BK].wmep_logcwmax << 4) | wmep[WME_AC_BE].wmep_logcwmax); + + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_WMM_TXOP0_CFG, + (wmep[WME_AC_BK].wmep_txopLimit << 16) | wmep[WME_AC_BE].wmep_txopLimit); + + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_WMM_TXOP1_CFG, + (wmep[WME_AC_VO].wmep_txopLimit << 16) | wmep[WME_AC_VI].wmep_txopLimit); +} + +/* + * rt2860_asic_update_beacon + */ +static void rt2860_asic_update_beacon(struct rt2860_softc *sc, + struct ieee80211vap *vap) +{ + struct rt2860_softc_vap *rvap; + struct mbuf *m; + struct rt2860_txwi *txwi; + uint32_t tmp; + + rvap = (struct rt2860_softc_vap *) vap; + + m = rvap->beacon_mbuf; + txwi = &rvap->beacon_txwi; + + /* disable temporarily TSF sync */ + + tmp = rt2860_io_mac_read(sc, RT2860_REG_BCN_TIME_CFG); + + tmp &= ~(RT2860_REG_BCN_TX_ENABLE | + RT2860_REG_TSF_TIMER_ENABLE | + RT2860_REG_TBTT_TIMER_ENABLE); + + rt2860_io_mac_write(sc, RT2860_REG_BCN_TIME_CFG, tmp); + + /* write Tx wireless info and beacon frame to on-chip memory */ + + rt2860_io_mac_write_multi(sc, RT2860_REG_BEACON_BASE(0), + txwi, sizeof(struct rt2860_txwi)); + + rt2860_io_mac_write_multi(sc, RT2860_REG_BEACON_BASE(0) + sizeof(struct rt2860_txwi), + mtod(m, uint8_t *), m->m_pkthdr.len); + + /* enable again TSF sync */ + + tmp = rt2860_io_mac_read(sc, RT2860_REG_BCN_TIME_CFG); + + tmp |= (RT2860_REG_BCN_TX_ENABLE | + RT2860_REG_TSF_TIMER_ENABLE | + RT2860_REG_TBTT_TIMER_ENABLE); + + rt2860_io_mac_write(sc, RT2860_REG_BCN_TIME_CFG, tmp); +} + +/* + * rt2860_asic_clear_keytables + */ +static void rt2860_asic_clear_keytables(struct rt2860_softc *sc) +{ + int i; + + /* clear Rx WCID search table (entries = 256, entry size = 8) */ + + for (i = 0; i < 256; i++) + { + rt2860_io_mac_write(sc, RT2860_REG_WCID(i), 0xffffffff); + rt2860_io_mac_write(sc, RT2860_REG_WCID(i) + 4, 0x0000ffff); + } + + /* clear WCID attribute table (entries = 256, entry size = 4) */ + + rt2860_io_mac_set_region_4(sc, RT2860_REG_WCID_ATTR(0), RT2860_REG_PKEY_ENABLE, 256); + + /* clear IV/EIV table (entries = 256, entry size = 8) */ + + rt2860_io_mac_set_region_4(sc, RT2860_REG_IVEIV(0), 0, 2 * 256); + + /* clear pairwise key table (entries = 64, entry size = 32) */ + + rt2860_io_mac_set_region_4(sc, RT2860_REG_PKEY(0), 0, 8 * 64); + + /* clear shared key table (entries = 32, entry size = 32) */ + + rt2860_io_mac_set_region_4(sc, RT2860_REG_SKEY(0, 0), 0, 8 * 32); + + /* clear shared key mode (entries = 32, entry size = 2) */ + + rt2860_io_mac_set_region_4(sc, RT2860_REG_SKEY_MODE(0), 0, 16); +} + +/* + * rt2860_asic_add_ba_session + */ +static void rt2860_asic_add_ba_session(struct rt2860_softc *sc, + uint8_t wcid, int tid) +{ + uint32_t tmp; + + RT2860_DPRINTF(sc, RT2860_DEBUG_BA, + "%s: adding BA session: wcid=0x%02x, tid=%d\n", + device_get_nameunit(sc->dev), wcid, tid); + + tmp = rt2860_io_mac_read(sc, RT2860_REG_WCID(wcid) + 4); + + tmp |= (0x10000 << tid); + + rt2860_io_mac_write(sc, RT2860_REG_WCID(wcid) + 4, tmp); +} + +/* + * rt2860_asic_del_ba_session + */ +static void rt2860_asic_del_ba_session(struct rt2860_softc *sc, + uint8_t wcid, int tid) +{ + uint32_t tmp; + + RT2860_DPRINTF(sc, RT2860_DEBUG_BA, + "%s: deleting BA session: wcid=0x%02x, tid=%d\n", + device_get_nameunit(sc->dev), wcid, tid); + + tmp = rt2860_io_mac_read(sc, RT2860_REG_WCID(wcid) + 4); + + tmp &= ~(0x10000 << tid); + + rt2860_io_mac_write(sc, RT2860_REG_WCID(wcid) + 4, tmp); +} + +/* + * rt2860_beacon_alloc + */ +static int rt2860_beacon_alloc(struct rt2860_softc *sc, + struct ieee80211vap *vap) +{ + struct ieee80211com *ic; + struct rt2860_softc_vap *rvap; + struct mbuf *m; + struct rt2860_txwi txwi; + uint8_t rate, mcs; + + ic = vap->iv_ic; + rvap = (struct rt2860_softc_vap *) vap; + + m = ieee80211_beacon_alloc(vap->iv_bss); + if (m == NULL) + return ENOMEM; + + rate = IEEE80211_IS_CHAN_5GHZ(vap->iv_bss->ni_chan) ? 12 : 2; + mcs = rt2860_rate2mcs(rate); + + RT2860_DPRINTF(sc, RT2860_DEBUG_BEACON, + "%s: beacon allocate: mcs=0x%02x\n", + device_get_nameunit(sc->dev), mcs); + + memset(&txwi, 0, sizeof(struct rt2860_txwi)); + + txwi.wcid = RT2860_WCID_RESERVED; + txwi.pid_mpdu_len = ((htole16(m->m_pkthdr.len) & RT2860_TXWI_MPDU_LEN_MASK) << + RT2860_TXWI_MPDU_LEN_SHIFT); + txwi.txop = (RT2860_TXWI_TXOP_HT << RT2860_TXWI_TXOP_SHIFT); + txwi.mpdu_density_flags |= + (RT2860_TXWI_FLAGS_TS << RT2860_TXWI_FLAGS_SHIFT); + txwi.bawin_size_xflags |= + (RT2860_TXWI_XFLAGS_NSEQ << RT2860_TXWI_XFLAGS_SHIFT); + + if (rate == 2) + { + txwi.phymode_ifs_stbc_shortgi = + (RT2860_TXWI_PHYMODE_CCK << RT2860_TXWI_PHYMODE_SHIFT); + + if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) + mcs |= RT2860_TXWI_MCS_SHOTPRE; + } + else + { + txwi.phymode_ifs_stbc_shortgi = + (RT2860_TXWI_PHYMODE_OFDM << RT2860_TXWI_PHYMODE_SHIFT); + } + + txwi.bw_mcs = (RT2860_TXWI_BW_20 << RT2860_TXWI_BW_SHIFT) | + ((mcs & RT2860_TXWI_MCS_MASK) << RT2860_TXWI_MCS_SHIFT); + + if (rvap->beacon_mbuf != NULL) + { + m_free(rvap->beacon_mbuf); + rvap->beacon_mbuf = NULL; + } + + rvap->beacon_mbuf = m; + rvap->beacon_txwi = txwi; + + return 0; +} + +/* + * rt2860_rxrate + */ +static uint8_t rt2860_rxrate(struct rt2860_rxwi *rxwi) +{ + uint8_t mcs, phymode; + uint8_t rate; + + mcs = (rxwi->bw_mcs >> RT2860_RXWI_MCS_SHIFT) & RT2860_RXWI_MCS_MASK; + phymode = (rxwi->phymode_stbc_shortgi >> RT2860_RXWI_PHYMODE_SHIFT) & + RT2860_RXWI_PHYMODE_MASK; + + rate = 2; + + switch (phymode) { + case RT2860_RXWI_PHYMODE_CCK: + switch (mcs & ~RT2860_RXWI_MCS_SHOTPRE) + { + case 0: rate = 2; break; /* 1 Mbps */ + case 1: rate = 4; break; /* 2 MBps */ + case 2: rate = 11; break; /* 5.5 Mbps */ + case 3: rate = 22; break; /* 11 Mbps */ + } + break; + + case RT2860_RXWI_PHYMODE_OFDM: + switch (mcs) + { + case 0: rate = 12; break; /* 6 Mbps */ + case 1: rate = 18; break; /* 9 Mbps */ + case 2: rate = 24; break; /* 12 Mbps */ + case 3: rate = 36; break; /* 18 Mbps */ + case 4: rate = 48; break; /* 24 Mbps */ + case 5: rate = 72; break; /* 36 Mbps */ + case 6: rate = 96; break; /* 48 Mbps */ + case 7: rate = 108; break; /* 54 Mbps */ + } + break; + + case RT2860_RXWI_PHYMODE_HT_MIXED: + case RT2860_RXWI_PHYMODE_HT_GF: + break; + } + + return rate; +} + +/* + * rt2860_maxrssi_rxpath + */ +static uint8_t rt2860_maxrssi_rxpath(struct rt2860_softc *sc, + const struct rt2860_rxwi *rxwi) +{ + uint8_t rxpath; + + rxpath = 0; + + if (sc->nrxpath > 1) + if (rxwi->rssi[1] > rxwi->rssi[rxpath]) + rxpath = 1; + + if (sc->nrxpath > 2) + if (rxwi->rssi[2] > rxwi->rssi[rxpath]) + rxpath = 2; + + return rxpath; +} + +/* + * rt2860_rssi2dbm + */ +static int8_t rt2860_rssi2dbm(struct rt2860_softc *sc, + uint8_t rssi, uint8_t rxpath) +{ + struct ieee80211com *ic; + struct ieee80211_channel *c; + int chan; + int8_t rssi_off, lna_gain; + + if (rssi == 0) + return -99; + + ic = &sc->sc_ic; + c = ic->ic_curchan; + chan = ieee80211_chan2ieee(ic, c); + + if (IEEE80211_IS_CHAN_5GHZ(c)) + { + rssi_off = sc->rssi_off_5ghz[rxpath]; + + if (chan <= 64) + lna_gain = sc->lna_gain[1]; + else if (chan <= 128) + lna_gain = sc->lna_gain[2]; + else + lna_gain = sc->lna_gain[3]; + } + else + { + rssi_off = sc->rssi_off_2ghz[rxpath] - sc->lna_gain[0]; + lna_gain = sc->lna_gain[0]; + } + + return (-12 - rssi_off - lna_gain - rssi); +} + +/* + * rt2860_rate2mcs + */ +static uint8_t rt2860_rate2mcs(uint8_t rate) +{ + switch (rate) + { + /* CCK rates */ + case 2: return 0; + case 4: return 1; + case 11: return 2; + case 22: return 3; + + /* OFDM rates */ + case 12: return 0; + case 18: return 1; + case 24: return 2; + case 36: return 3; + case 48: return 4; + case 72: return 5; + case 96: return 6; + case 108: return 7; + } + + return 0; +} + +/* + * rt2860_tx_mgmt + */ +static int rt2860_tx_mgmt(struct rt2860_softc *sc, + struct mbuf *m, struct ieee80211_node *ni, int qid) +{ + struct ieee80211com *ic; + struct ieee80211vap *vap; + const struct ieee80211_txparam *tp; + struct rt2860_softc_node *rni; + struct rt2860_softc_tx_ring *ring; + struct rt2860_softc_tx_data *data; + struct rt2860_txdesc *desc; + struct rt2860_txwi *txwi; + struct ieee80211_frame *wh; + struct rt2860_softc_tx_radiotap_header *tap; + bus_dma_segment_t dma_seg[RT2860_SOFTC_MAX_SCATTER]; + struct mbuf *m_d; + u_int hdrsize, hdrspace; + uint8_t rate, mcs, pid, qsel; + uint16_t len, dmalen, mpdu_len, dur; + int error, mimops, ndmasegs, ndescs, i, j; + + KASSERT(qid >= 0 && qid < RT2860_SOFTC_TX_RING_COUNT, + ("%s: Tx MGMT: invalid qid=%d\n", + device_get_nameunit(sc->dev), qid)); + + RT2860_SOFTC_TX_RING_ASSERT_LOCKED(&sc->tx_ring[qid]); + + ic = &sc->sc_ic; + vap = ni->ni_vap; + rni = (struct rt2860_softc_node *) ni; + tp = ni->ni_txparms; + + ring = &sc->tx_ring[qid]; + desc = &ring->desc[ring->desc_cur]; + data = &ring->data[ring->data_cur]; + txwi = (struct rt2860_txwi *) (ring->seg0 + ring->data_cur * RT2860_TX_DATA_SEG0_SIZE); + + wh = mtod(m, struct ieee80211_frame *); + + rate = tp->mgmtrate & IEEE80211_RATE_VAL; +/* XXX */ + if (!rate) + return EFBIG; + + /* fill Tx wireless info */ + + if (ni->ni_flags & IEEE80211_NODE_HT) + mcs = rate; + else + mcs = rt2860_rate2mcs(rate); + + /* calculate MPDU length without padding */ + + hdrsize = ieee80211_anyhdrsize(wh); + hdrspace = ieee80211_anyhdrspace(ic, wh); + mpdu_len = m->m_pkthdr.len - hdrspace + hdrsize; + + memset(txwi, 0, sizeof(struct rt2860_txwi)); + + /* management frames do not need encryption */ + + txwi->wcid = RT2860_WCID_RESERVED; + + /* MIMO power save */ + + if ((ni->ni_flags & IEEE80211_NODE_HT) && (ni->ni_flags & IEEE80211_NODE_MIMO_PS)) + { + if (mcs > 7) + { + if (ni->ni_flags & IEEE80211_NODE_MIMO_RTS) + { + /* dynamic MIMO power save */ + + txwi->mpdu_density_flags |= + (RT2860_TXWI_FLAGS_MIMOPS << RT2860_TXWI_FLAGS_SHIFT); + } + else + { + /* static MIMO power save */ + + mcs = 7; + } + } + + mimops = 1; + } + else + { + mimops = 0; + } + + pid = (mcs < 0xf) ? (mcs + 1) : mcs; + + txwi->pid_mpdu_len = ((htole16(pid) & RT2860_TXWI_PID_MASK) << + RT2860_TXWI_PID_SHIFT) | ((htole16(mpdu_len) & RT2860_TXWI_MPDU_LEN_MASK) << + RT2860_TXWI_MPDU_LEN_SHIFT); + + if (ni->ni_flags & IEEE80211_NODE_HT) + { + txwi->phymode_ifs_stbc_shortgi |= + (RT2860_TXWI_PHYMODE_HT_MIXED << RT2860_TXWI_PHYMODE_SHIFT); + } + else + { + if (ieee80211_rate2phytype(ic->ic_rt, rate) != IEEE80211_T_OFDM) + { + txwi->phymode_ifs_stbc_shortgi |= + (RT2860_TXWI_PHYMODE_CCK << RT2860_TXWI_PHYMODE_SHIFT); + + if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) + mcs |= RT2860_TXWI_MCS_SHOTPRE; + } + else + { + txwi->phymode_ifs_stbc_shortgi |= + (RT2860_TXWI_PHYMODE_OFDM << RT2860_TXWI_PHYMODE_SHIFT); + } + } + + txwi->bw_mcs = (RT2860_TXWI_BW_20 << RT2860_TXWI_BW_SHIFT) | + ((mcs & RT2860_TXWI_MCS_MASK) << RT2860_TXWI_MCS_SHIFT); + + txwi->txop = (RT2860_TXWI_TXOP_BACKOFF << RT2860_TXWI_TXOP_SHIFT); + + /* skip ACKs for multicast frames */ + + if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) + { + txwi->bawin_size_xflags |= + (RT2860_TXWI_XFLAGS_ACK << RT2860_TXWI_XFLAGS_SHIFT); + + if (ni->ni_flags & IEEE80211_NODE_HT) + { + /* preamble + plcp + signal extension + SIFS */ + + dur = 16 + 4 + 6 + 10; + } + else + { + dur = ieee80211_ack_duration(ic->ic_rt, rate, + ic->ic_flags & IEEE80211_F_SHPREAMBLE); + } + + *(uint16_t *) wh->i_dur = htole16(dur); + } + + /* ask MAC to insert timestamp into probe responses */ + + if ((wh->i_fc[0] & (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == + (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) + txwi->mpdu_density_flags |= + (RT2860_TXWI_FLAGS_TS << RT2860_TXWI_FLAGS_SHIFT); + + if (ieee80211_radiotap_active_vap(vap)) + { + tap = &sc->txtap; + + tap->flags = IEEE80211_RADIOTAP_F_DATAPAD; + tap->chan_flags = htole32(ic->ic_curchan->ic_flags); + tap->chan_freq = htole16(ic->ic_curchan->ic_freq); + tap->chan_ieee = ic->ic_curchan->ic_ieee; + tap->chan_maxpow = 0; + + if (ni->ni_flags & IEEE80211_NODE_HT) + tap->rate = mcs | IEEE80211_RATE_MCS; + else + tap->rate = rate; + + if (mcs & RT2860_TXWI_MCS_SHOTPRE) + tap->flags |= IEEE80211_RADIOTAP_F_SHORTPRE; + + if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) + tap->flags |= IEEE80211_RADIOTAP_F_WEP; + + if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) + { + wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; + + ieee80211_radiotap_tx(vap, m); + + wh->i_fc[1] |= IEEE80211_FC1_PROTECTED; + } + else + { + ieee80211_radiotap_tx(vap, m); + } + } + + /* copy and trim 802.11 header */ + + m_copydata(m, 0, hdrsize, (caddr_t) (txwi + 1)); + m_adj(m, hdrspace); + + error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag, data->dma_map, m, + dma_seg, &ndmasegs, BUS_DMA_NOWAIT); + if (error != 0) + { + /* too many fragments, linearize */ + + RT2860_DPRINTF(sc, RT2860_DEBUG_TX, + "%s: could not load mbuf DMA map, trying to linearize mbuf: ndmasegs=%d, len=%d, error=%d\n", + device_get_nameunit(sc->dev), ndmasegs, m->m_pkthdr.len, error); + + m_d = m_collapse(m, M_NOWAIT, 16); + if (m_d == NULL) { + m_freem(m); + m = NULL; + return (ENOMEM); + } + m = m_d; + + sc->tx_defrag_packets++; + + error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag, data->dma_map, m, + dma_seg, &ndmasegs, BUS_DMA_NOWAIT); + if (error != 0) + { + printf("%s: could not load mbuf DMA map: ndmasegs=%d, len=%d, error=%d\n", + device_get_nameunit(sc->dev), ndmasegs, m->m_pkthdr.len, error); + m_freem(m); + return error; + } + } + + if (m->m_pkthdr.len == 0) + ndmasegs = 0; + + /* determine how many Tx descs are required */ + + ndescs = 1 + ndmasegs / 2; + if ((ring->desc_queued + ndescs) > (RT2860_SOFTC_TX_RING_DESC_COUNT - 2)) + { + RT2860_DPRINTF(sc, RT2860_DEBUG_TX, + "%s: there are not enough Tx descs\n", + device_get_nameunit(sc->dev)); + + sc->no_tx_desc_avail++; + + bus_dmamap_unload(ring->data_dma_tag, data->dma_map); + m_freem(m); + return EFBIG; + } + + data->m = m; + data->ni = ni; + + /* set up Tx descs */ + + /* first segment is Tx wireless info and 802.11 header */ + + len = sizeof(struct rt2860_txwi) + hdrsize; + + /* align end on a 4-bytes boundary */ + + dmalen = (len + 3) & ~ 3; + + memset((caddr_t) txwi + len, 0, dmalen - len); + + qsel = RT2860_TXDESC_QSEL_EDCA; + + desc->sdp0 = htole32(ring->seg0_phys_addr + ring->data_cur * RT2860_TX_DATA_SEG0_SIZE); + desc->sdl0 = htole16(dmalen); + desc->qsel_flags = (qsel << RT2860_TXDESC_QSEL_SHIFT); + + /* set up payload segments */ + + for (i = ndmasegs, j = 0; i >= 2; i -= 2) + { + desc->sdp1 = htole32(dma_seg[j].ds_addr); + desc->sdl1 = htole16(dma_seg[j].ds_len); + + ring->desc_queued++; + ring->desc_cur = (ring->desc_cur + 1) % RT2860_SOFTC_TX_RING_DESC_COUNT; + + j++; + + desc = &ring->desc[ring->desc_cur]; + + desc->sdp0 = htole32(dma_seg[j].ds_addr); + desc->sdl0 = htole16(dma_seg[j].ds_len); + desc->qsel_flags = (qsel << RT2860_TXDESC_QSEL_SHIFT); + + j++; + } + + /* finalize last payload segment */ + + if (i > 0) + { + desc->sdp1 = htole32(dma_seg[j].ds_addr); + desc->sdl1 = htole16(dma_seg[j].ds_len | RT2860_TXDESC_SDL1_LASTSEG); + } + else + { + desc->sdl0 |= htole16(RT2860_TXDESC_SDL0_LASTSEG); + desc->sdl1 = 0; + } + + RT2860_DPRINTF(sc, RT2860_DEBUG_TX, + "%s: sending MGMT frame: qid=%d, hdrsize=%d, hdrspace=%d, len=%d, " + "mcs=%d, mimops=%d, DMA len=%d, ndmasegs=%d, DMA ds_len=%d/%d/%d/%d/%d\n", + device_get_nameunit(sc->dev), + qid, hdrsize, hdrspace, m->m_pkthdr.len + hdrsize, + mcs, mimops, dmalen, ndmasegs, + (int) dma_seg[0].ds_len, (int) dma_seg[1].ds_len, (int) dma_seg[2].ds_len, (int) dma_seg[3].ds_len, (int) dma_seg[4].ds_len); + + bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map, + BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(ring->data_dma_tag, data->dma_map, + BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, + BUS_DMASYNC_PREWRITE); + + ring->desc_queued++; + ring->desc_cur = (ring->desc_cur + 1) % RT2860_SOFTC_TX_RING_DESC_COUNT; + + ring->data_queued++; + ring->data_cur = (ring->data_cur + 1) % RT2860_SOFTC_TX_RING_DATA_COUNT; + + /* kick Tx */ + + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_TX_CTX_IDX(qid), ring->desc_cur); + + return 0; +} + +/* + * rt2860_tx_data + */ +static int rt2860_tx_data(struct rt2860_softc *sc, + struct mbuf *m, struct ieee80211_node *ni, int qid) +{ + struct ieee80211com *ic; + struct ieee80211vap *vap; + const struct ieee80211_txparam *tp; + struct rt2860_softc_node *rni; + struct rt2860_softc_tx_ring *ring; + struct rt2860_softc_tx_data *data; + struct rt2860_txdesc *desc; + struct rt2860_txwi *txwi; + struct ieee80211_frame *wh; + struct ieee80211_tx_ampdu *tx_ampdu; + ieee80211_seq seqno; + struct rt2860_softc_tx_radiotap_header *tap; + bus_dma_segment_t dma_seg[RT2860_SOFTC_MAX_SCATTER]; + u_int hdrsize, hdrspace; + uint8_t type, rate, bw, stbc, shortgi, mcs, pid, wcid, mpdu_density, bawin_size, qsel; + uint16_t qos, len, dmalen, mpdu_len, dur; + int error, hasqos, ac, tid, ampdu, mimops, ndmasegs, ndescs, i, j; + + KASSERT(qid >= 0 && qid < RT2860_SOFTC_TX_RING_COUNT, + ("%s: Tx data: invalid qid=%d\n", + device_get_nameunit(sc->dev), qid)); + + RT2860_SOFTC_TX_RING_ASSERT_LOCKED(&sc->tx_ring[qid]); + + ic = &sc->sc_ic; + vap = ni->ni_vap; + rni = (struct rt2860_softc_node *) ni; + tp = ni->ni_txparms; + + ring = &sc->tx_ring[qid]; + desc = &ring->desc[ring->desc_cur]; + data = &ring->data[ring->data_cur]; + txwi = (struct rt2860_txwi *) (ring->seg0 + ring->data_cur * RT2860_TX_DATA_SEG0_SIZE); + + wh = mtod(m, struct ieee80211_frame *); + + type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; + + hasqos = IEEE80211_QOS_HAS_SEQ(wh); + if (hasqos) + { + if (IEEE80211_HAS_ADDR4(wh)) + qos = le16toh(*(const uint16_t *) + (((struct ieee80211_qosframe_addr4 *) wh)->i_qos)); + else + qos = le16toh(*(const uint16_t *) + (((struct ieee80211_qosframe *) wh)->i_qos)); + } + else + { + qos = 0; + } + + if (IEEE80211_IS_MULTICAST(wh->i_addr1)) + rate = tp->mcastrate; + else if (m->m_flags & M_EAPOL) + rate = tp->mgmtrate; + else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) + rate = tp->ucastrate; + else + rate = ni->ni_txrate; + + rate &= IEEE80211_RATE_VAL; +/* XXX */ + if (!rate) + return EFBIG; + + /* fill Tx wireless info */ + + if (ni->ni_flags & IEEE80211_NODE_HT) + mcs = rate; + else + mcs = rt2860_rate2mcs(rate); + + if (type == IEEE80211_FC0_TYPE_DATA) + wcid = !IEEE80211_IS_MULTICAST(wh->i_addr1) ? rni->staid : RT2860_WCID_MCAST; + else + wcid = RT2860_WCID_RESERVED; + + /* calculate MPDU length without padding */ + + hdrsize = ieee80211_anyhdrsize(wh); + hdrspace = ieee80211_anyhdrspace(ic, wh); + mpdu_len = m->m_pkthdr.len - hdrspace + hdrsize; + + memset(txwi, 0, sizeof(struct rt2860_txwi)); + + txwi->wcid = wcid; + + /* MIMO power save */ + + if ((ni->ni_flags & IEEE80211_NODE_HT) && (ni->ni_flags & IEEE80211_NODE_MIMO_PS)) + { + if (mcs > 7) + { + if (ni->ni_flags & IEEE80211_NODE_MIMO_RTS) + { + /* dynamic MIMO power save */ + + txwi->mpdu_density_flags |= + (RT2860_TXWI_FLAGS_MIMOPS << RT2860_TXWI_FLAGS_SHIFT); + } + else + { + /* static MIMO power save */ + + mcs = 7; + } + } + + mimops = 1; + } + else + { + mimops = 0; + } + + pid = (mcs < 0xf) ? (mcs + 1) : mcs; + + txwi->pid_mpdu_len = ((htole16(pid) & RT2860_TXWI_PID_MASK) << + RT2860_TXWI_PID_SHIFT) | ((htole16(mpdu_len) & RT2860_TXWI_MPDU_LEN_MASK) << + RT2860_TXWI_MPDU_LEN_SHIFT); + + stbc = sc->tx_stbc && (mcs <= 7) && (vap->iv_htcaps & IEEE80211_HTCAP_TXSTBC) && + (ni->ni_flags & IEEE80211_NODE_HT) && (ni->ni_htcap & IEEE80211_HTCAP_RXSTBC); + + shortgi = ((vap->iv_flags_ht & IEEE80211_FHT_SHORTGI20) && (ni->ni_flags & IEEE80211_NODE_SGI20) && (ni->ni_chw == 20)) || + ((vap->iv_flags_ht & IEEE80211_FHT_SHORTGI40) && (ni->ni_flags & IEEE80211_NODE_SGI40) && (ni->ni_chw == 40)); + + txwi->phymode_ifs_stbc_shortgi |= + ((stbc & RT2860_TXWI_STBC_MASK) << RT2860_TXWI_STBC_SHIFT) | + ((shortgi & RT2860_TXWI_SHORTGI_MASK) << RT2860_TXWI_SHORTGI_SHIFT); + + if (ni->ni_flags & IEEE80211_NODE_HT) + { + txwi->phymode_ifs_stbc_shortgi |= + (RT2860_TXWI_PHYMODE_HT_MIXED << RT2860_TXWI_PHYMODE_SHIFT); + } + else + { + if (ieee80211_rate2phytype(ic->ic_rt, rate) != IEEE80211_T_OFDM) + { + txwi->phymode_ifs_stbc_shortgi |= + (RT2860_TXWI_PHYMODE_CCK << RT2860_TXWI_PHYMODE_SHIFT); + + if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) + mcs |= RT2860_TXWI_MCS_SHOTPRE; + } + else + { + txwi->phymode_ifs_stbc_shortgi |= + (RT2860_TXWI_PHYMODE_OFDM << RT2860_TXWI_PHYMODE_SHIFT); + } + } + + if ((ni->ni_flags & IEEE80211_NODE_HT) && (ni->ni_chw == 40)) + bw = RT2860_TXWI_BW_40; + else + bw = RT2860_TXWI_BW_20; + + txwi->bw_mcs = ((bw & RT2860_TXWI_BW_MASK) << RT2860_TXWI_BW_SHIFT) | + ((mcs & RT2860_TXWI_MCS_MASK) << RT2860_TXWI_MCS_SHIFT); + + txwi->txop = (RT2860_TXWI_TXOP_HT << RT2860_TXWI_TXOP_SHIFT); + + if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && + (!hasqos || (qos & IEEE80211_QOS_ACKPOLICY) != IEEE80211_QOS_ACKPOLICY_NOACK)) + { + txwi->bawin_size_xflags |= + (RT2860_TXWI_XFLAGS_ACK << RT2860_TXWI_XFLAGS_SHIFT); + + if (ni->ni_flags & IEEE80211_NODE_HT) + { + /* preamble + plcp + signal extension + SIFS */ + + dur = 16 + 4 + 6 + 10; + } + else + { + dur = ieee80211_ack_duration(ic->ic_rt, rate, + ic->ic_flags & IEEE80211_F_SHPREAMBLE); + } + + *(uint16_t *) wh->i_dur = htole16(dur); + } + + /* check for A-MPDU */ + + if (m->m_flags & M_AMPDU_MPDU) + { + ac = M_WME_GETAC(m); + tid = WME_AC_TO_TID(ac); + tx_ampdu = &ni->ni_tx_ampdu[ac]; + + mpdu_density = RT2860_MS(ni->ni_htparam, IEEE80211_HTCAP_MPDUDENSITY); + bawin_size = tx_ampdu->txa_wnd; + + txwi->mpdu_density_flags |= + ((mpdu_density & RT2860_TXWI_MPDU_DENSITY_MASK) << RT2860_TXWI_MPDU_DENSITY_SHIFT) | + (RT2860_TXWI_FLAGS_AMPDU << RT2860_TXWI_FLAGS_SHIFT); + + txwi->bawin_size_xflags |= + ((bawin_size & RT2860_TXWI_BAWIN_SIZE_MASK) << RT2860_TXWI_BAWIN_SIZE_SHIFT); + + seqno = ni->ni_txseqs[tid]++; + + *(uint16_t *) &wh->i_seq[0] = htole16(seqno << IEEE80211_SEQ_SEQ_SHIFT); + + ampdu = 1; + } + else + { + mpdu_density = 0; + bawin_size = 0; + ampdu = 0; + } + + /* ask MAC to insert timestamp into probe responses */ + + if ((wh->i_fc[0] & (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == + (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) + txwi->mpdu_density_flags |= + (RT2860_TXWI_FLAGS_TS << RT2860_TXWI_FLAGS_SHIFT); + + if (ieee80211_radiotap_active_vap(vap)) + { + tap = &sc->txtap; + + tap->flags = IEEE80211_RADIOTAP_F_DATAPAD; + tap->chan_flags = htole32(ic->ic_curchan->ic_flags); + tap->chan_freq = htole16(ic->ic_curchan->ic_freq); + tap->chan_ieee = ic->ic_curchan->ic_ieee; + tap->chan_maxpow = 0; + + if (ni->ni_flags & IEEE80211_NODE_HT) + tap->rate = mcs | IEEE80211_RATE_MCS; + else + tap->rate = rate; + + if (mcs & RT2860_TXWI_MCS_SHOTPRE) + tap->flags |= IEEE80211_RADIOTAP_F_SHORTPRE; + + if (shortgi) + tap->flags |= IEEE80211_RADIOTAP_F_SHORTGI; + + if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) + tap->flags |= IEEE80211_RADIOTAP_F_WEP; + + /* XXX use temporarily radiotap CFP flag as A-MPDU flag */ + + if (ampdu) + tap->flags |= IEEE80211_RADIOTAP_F_CFP; + + if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) + { + wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; + + ieee80211_radiotap_tx(vap, m); + + wh->i_fc[1] |= IEEE80211_FC1_PROTECTED; + } + else + { + ieee80211_radiotap_tx(vap, m); + } + } + + /* copy and trim 802.11 header */ + + m_copydata(m, 0, hdrsize, (caddr_t) (txwi + 1)); + m_adj(m, hdrspace); + + error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag, data->dma_map, m, + dma_seg, &ndmasegs, BUS_DMA_NOWAIT); + if (error != 0) + { + /* too many fragments, linearize */ + + RT2860_DPRINTF(sc, RT2860_DEBUG_TX, + "%s: could not load mbuf DMA map, trying to linearize mbuf: ndmasegs=%d, len=%d, error=%d\n", + device_get_nameunit(sc->dev), ndmasegs, m->m_pkthdr.len, error); + + m = m_defrag(m, M_NOWAIT); + if (m == NULL) + return ENOMEM; + + sc->tx_defrag_packets++; + + error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag, data->dma_map, m, + dma_seg, &ndmasegs, BUS_DMA_NOWAIT); + if (error != 0) + { + printf("%s: could not load mbuf DMA map: ndmasegs=%d, len=%d, error=%d\n", + device_get_nameunit(sc->dev), ndmasegs, m->m_pkthdr.len, error); + m_freem(m); + return error; + } + } + + if (m->m_pkthdr.len == 0) + ndmasegs = 0; + + /* determine how many Tx descs are required */ + + ndescs = 1 + ndmasegs / 2; + if ((ring->desc_queued + ndescs) > (RT2860_SOFTC_TX_RING_DESC_COUNT - 2)) + { + RT2860_DPRINTF(sc, RT2860_DEBUG_TX, + "%s: there are not enough Tx descs\n", + device_get_nameunit(sc->dev)); + + sc->no_tx_desc_avail++; + + bus_dmamap_unload(ring->data_dma_tag, data->dma_map); + m_freem(m); + return EFBIG; + } + + data->m = m; + data->ni = ni; + + /* set up Tx descs */ + + /* first segment is Tx wireless info and 802.11 header */ + + len = sizeof(struct rt2860_txwi) + hdrsize; + + /* align end on a 4-bytes boundary */ + + dmalen = (len + 3) & ~ 3; + + memset((caddr_t) txwi + len, 0, dmalen - len); + + qsel = RT2860_TXDESC_QSEL_EDCA; + + desc->sdp0 = htole32(ring->seg0_phys_addr + ring->data_cur * RT2860_TX_DATA_SEG0_SIZE); + desc->sdl0 = htole16(dmalen); + desc->qsel_flags = (qsel << RT2860_TXDESC_QSEL_SHIFT); + + /* set up payload segments */ + + for (i = ndmasegs, j = 0; i >= 2; i -= 2) + { + desc->sdp1 = htole32(dma_seg[j].ds_addr); + desc->sdl1 = htole16(dma_seg[j].ds_len); + + ring->desc_queued++; + ring->desc_cur = (ring->desc_cur + 1) % RT2860_SOFTC_TX_RING_DESC_COUNT; + + j++; + + desc = &ring->desc[ring->desc_cur]; + + desc->sdp0 = htole32(dma_seg[j].ds_addr); + desc->sdl0 = htole16(dma_seg[j].ds_len); + desc->qsel_flags = (qsel << RT2860_TXDESC_QSEL_SHIFT); + + j++; + } + + /* finalize last payload segment */ + + if (i > 0) + { + desc->sdp1 = htole32(dma_seg[j].ds_addr); + desc->sdl1 = htole16(dma_seg[j].ds_len | RT2860_TXDESC_SDL1_LASTSEG); + } + else + { + desc->sdl0 |= htole16(RT2860_TXDESC_SDL0_LASTSEG); + desc->sdl1 = 0; + } + + RT2860_DPRINTF(sc, RT2860_DEBUG_TX, + "%s: sending data: qid=%d, hdrsize=%d, hdrspace=%d, len=%d, " + "bw=%d, stbc=%d, shortgi=%d, mcs=%d, wcid=0x%02x, " + "ampdu=%d (density=%d, winsize=%d), mimops=%d, DMA len=%d, ndmasegs=%d, DMA ds_len=%d/%d/%d/%d/%d\n", + device_get_nameunit(sc->dev), + qid, hdrsize, hdrspace, m->m_pkthdr.len + hdrsize, + bw, stbc, shortgi, mcs, wcid, ampdu, mpdu_density, bawin_size, mimops, dmalen, ndmasegs, + (int) dma_seg[0].ds_len, (int) dma_seg[1].ds_len, (int) dma_seg[2].ds_len, (int) dma_seg[3].ds_len, (int) dma_seg[4].ds_len); + + bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map, + BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(ring->data_dma_tag, data->dma_map, + BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, + BUS_DMASYNC_PREWRITE); + + ring->desc_queued++; + ring->desc_cur = (ring->desc_cur + 1) % RT2860_SOFTC_TX_RING_DESC_COUNT; + + ring->data_queued++; + ring->data_cur = (ring->data_cur + 1) % RT2860_SOFTC_TX_RING_DATA_COUNT; + + /* kick Tx */ + + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_TX_CTX_IDX(qid), ring->desc_cur); + + return 0; +} + +/* + * rt2860_tx_raw +static int rt2860_tx_raw(struct rt2860_softc *sc, + struct mbuf *m, struct ieee80211_node *ni, + const struct ieee80211_bpf_params *params) +{ + RT2860_DPRINTF(sc, RT2860_DEBUG_TX, + "%s: Tx raw\n", + device_get_nameunit(sc->dev)); + + return 0; +} + */ + +/* + * rt2860_intr + */ +static void rt2860_intr(void *arg) +{ + struct rt2860_softc *sc; + uint32_t status; + + sc = arg; + + /* acknowledge interrupts */ + + status = rt2860_io_mac_read(sc, RT2860_REG_SCHDMA_INT_STATUS); + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_INT_STATUS, status); + + RT2860_DPRINTF(sc, RT2860_DEBUG_INTR, + "%s: interrupt: status = 0x%08x\n", + device_get_nameunit(sc->dev), status); + + if (status == 0xffffffff || /* device likely went away */ + status == 0) /* not for us */ + return; + + sc->interrupts++; + + if (!(sc->sc_flags & RT2860_RUNNING)) + return; + + if (status & RT2860_REG_INT_TX_COHERENT) + rt2860_tx_coherent_intr(sc); + + if (status & RT2860_REG_INT_RX_COHERENT) + rt2860_rx_coherent_intr(sc); + + if (status & RT2860_REG_INT_TXRX_COHERENT) + rt2860_txrx_coherent_intr(sc); + + if (status & RT2860_REG_INT_FIFO_STA_FULL) + rt2860_fifo_sta_full_intr(sc); + + if (status & RT2860_REG_INT_TX_MGMT_DONE) + rt2860_tx_intr(sc, 5); + + if (status & RT2860_REG_INT_RX_DONE) + rt2860_rx_intr(sc); + + if (status & RT2860_REG_INT_RX_DELAY_DONE) + rt2860_rx_delay_intr(sc); + + if (status & RT2860_REG_INT_TX_HCCA_DONE) + rt2860_tx_intr(sc, 4); + + if (status & RT2860_REG_INT_TX_AC3_DONE) + rt2860_tx_intr(sc, 3); + + if (status & RT2860_REG_INT_TX_AC2_DONE) + rt2860_tx_intr(sc, 2); + + if (status & RT2860_REG_INT_TX_AC1_DONE) + rt2860_tx_intr(sc, 1); + + if (status & RT2860_REG_INT_TX_AC0_DONE) + rt2860_tx_intr(sc, 0); + + if (status & RT2860_REG_INT_TX_DELAY_DONE) + rt2860_tx_delay_intr(sc); + + if (status & RT2860_REG_INT_PRE_TBTT) + rt2860_pre_tbtt_intr(sc); + + if (status & RT2860_REG_INT_TBTT) + rt2860_tbtt_intr(sc); + + if (status & RT2860_REG_INT_MCU_CMD) + rt2860_mcu_cmd_intr(sc); + + if (status & RT2860_REG_INT_AUTO_WAKEUP) + rt2860_auto_wakeup_intr(sc); + + if (status & RT2860_REG_INT_GP_TIMER) + rt2860_gp_timer_intr(sc); + +} + +/* + * rt2860_tx_coherent_intr + */ +static void rt2860_tx_coherent_intr(struct rt2860_softc *sc) +{ + uint32_t tmp; + int i; + + RT2860_DPRINTF(sc, RT2860_DEBUG_INTR, + "%s: Tx coherent interrupt\n", + device_get_nameunit(sc->dev)); + + sc->tx_coherent_interrupts++; + + /* restart DMA engine */ + + tmp = rt2860_io_mac_read(sc, RT2860_REG_SCHDMA_WPDMA_GLO_CFG); + + tmp &= ~(RT2860_REG_TX_WB_DDONE | + RT2860_REG_RX_DMA_ENABLE | + RT2860_REG_TX_DMA_ENABLE); + + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_WPDMA_GLO_CFG, tmp); + + /* init Tx rings (4 EDCAs + HCCA + MGMT) */ + + for (i = 0; i < RT2860_SOFTC_TX_RING_COUNT; i++) + rt2860_reset_tx_ring(sc, &sc->tx_ring[i]); + + for (i = 0; i < RT2860_SOFTC_TX_RING_COUNT; i++) + { + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_TX_BASE_PTR(i), + sc->tx_ring[i].desc_phys_addr); + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_TX_MAX_CNT(i), + RT2860_SOFTC_TX_RING_DESC_COUNT); + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_TX_CTX_IDX(i), 0); + } + + /* init Rx ring */ + + rt2860_reset_rx_ring(sc, &sc->rx_ring); + + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_RX_BASE_PTR, + sc->rx_ring.desc_phys_addr); + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_RX_MAX_CNT, + RT2860_SOFTC_RX_RING_DATA_COUNT); + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_RX_CALC_IDX, + RT2860_SOFTC_RX_RING_DATA_COUNT - 1); + + rt2860_txrx_enable(sc); +} + +/* + * rt2860_rx_coherent_intr + */ +static void rt2860_rx_coherent_intr(struct rt2860_softc *sc) +{ + uint32_t tmp; + int i; + + RT2860_DPRINTF(sc, RT2860_DEBUG_INTR, + "%s: Rx coherent interrupt\n", + device_get_nameunit(sc->dev)); + + sc->rx_coherent_interrupts++; + + /* restart DMA engine */ + + tmp = rt2860_io_mac_read(sc, RT2860_REG_SCHDMA_WPDMA_GLO_CFG); + + tmp &= ~(RT2860_REG_TX_WB_DDONE | + RT2860_REG_RX_DMA_ENABLE | + RT2860_REG_TX_DMA_ENABLE); + + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_WPDMA_GLO_CFG, tmp); + + /* init Tx rings (4 EDCAs + HCCA + MGMT) */ + + for (i = 0; i < RT2860_SOFTC_TX_RING_COUNT; i++) + rt2860_reset_tx_ring(sc, &sc->tx_ring[i]); + + for (i = 0; i < RT2860_SOFTC_TX_RING_COUNT; i++) + { + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_TX_BASE_PTR(i), + sc->tx_ring[i].desc_phys_addr); + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_TX_MAX_CNT(i), + RT2860_SOFTC_TX_RING_DESC_COUNT); + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_TX_CTX_IDX(i), 0); + } + + /* init Rx ring */ + + rt2860_reset_rx_ring(sc, &sc->rx_ring); + + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_RX_BASE_PTR, + sc->rx_ring.desc_phys_addr); + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_RX_MAX_CNT, + RT2860_SOFTC_RX_RING_DATA_COUNT); + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_RX_CALC_IDX, + RT2860_SOFTC_RX_RING_DATA_COUNT - 1); + + rt2860_txrx_enable(sc); +} + +/* + * rt2860_txrx_coherent_intr + */ +static void rt2860_txrx_coherent_intr(struct rt2860_softc *sc) +{ + uint32_t tmp; + int i; + + RT2860_DPRINTF(sc, RT2860_DEBUG_INTR, + "%s: Tx/Rx coherent interrupt\n", + device_get_nameunit(sc->dev)); + + sc->txrx_coherent_interrupts++; + + /* restart DMA engine */ + + tmp = rt2860_io_mac_read(sc, RT2860_REG_SCHDMA_WPDMA_GLO_CFG); + + tmp &= ~(RT2860_REG_TX_WB_DDONE | + RT2860_REG_RX_DMA_ENABLE | + RT2860_REG_TX_DMA_ENABLE); + + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_WPDMA_GLO_CFG, tmp); + + /* init Tx rings (4 EDCAs + HCCA + MGMT) */ + + for (i = 0; i < RT2860_SOFTC_TX_RING_COUNT; i++) + rt2860_reset_tx_ring(sc, &sc->tx_ring[i]); + + for (i = 0; i < RT2860_SOFTC_TX_RING_COUNT; i++) + { + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_TX_BASE_PTR(i), + sc->tx_ring[i].desc_phys_addr); + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_TX_MAX_CNT(i), + RT2860_SOFTC_TX_RING_DESC_COUNT); + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_TX_CTX_IDX(i), 0); + } + + /* init Rx ring */ + + rt2860_reset_rx_ring(sc, &sc->rx_ring); + + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_RX_BASE_PTR, + sc->rx_ring.desc_phys_addr); + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_RX_MAX_CNT, + RT2860_SOFTC_RX_RING_DATA_COUNT); + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_RX_CALC_IDX, + RT2860_SOFTC_RX_RING_DATA_COUNT - 1); + + rt2860_txrx_enable(sc); +} + +/* + * rt2860_fifo_sta_full_intr + */ +static void rt2860_fifo_sta_full_intr(struct rt2860_softc *sc) +{ + RT2860_DPRINTF(sc, RT2860_DEBUG_INTR, + "%s: FIFO statistic full interrupt\n", + device_get_nameunit(sc->dev)); + + sc->fifo_sta_full_interrupts++; + + RT2860_SOFTC_LOCK(sc); + + if (!(sc->intr_disable_mask & RT2860_REG_INT_FIFO_STA_FULL)) + { + rt2860_intr_disable(sc, RT2860_REG_INT_FIFO_STA_FULL); + + taskqueue_enqueue(sc->taskqueue, &sc->fifo_sta_full_task); + } + + sc->intr_pending_mask |= RT2860_REG_INT_FIFO_STA_FULL; + + RT2860_SOFTC_UNLOCK(sc); +} + +/* + * rt2860_rx_intr + */ +static void rt2860_rx_intr(struct rt2860_softc *sc) +{ + RT2860_DPRINTF(sc, RT2860_DEBUG_INTR, + "%s: Rx interrupt\n", + device_get_nameunit(sc->dev)); + + sc->rx_interrupts++; + + RT2860_SOFTC_LOCK(sc); + + if (!(sc->intr_disable_mask & RT2860_REG_INT_RX_DONE)) + { + rt2860_intr_disable(sc, RT2860_REG_INT_RX_DONE); + + taskqueue_enqueue(sc->taskqueue, &sc->rx_done_task); + } + + sc->intr_pending_mask |= RT2860_REG_INT_RX_DONE; + + RT2860_SOFTC_UNLOCK(sc); +} + +/* + * rt2860_rx_delay_intr + */ +static void rt2860_rx_delay_intr(struct rt2860_softc *sc) +{ + RT2860_DPRINTF(sc, RT2860_DEBUG_INTR, + "%s: Rx delay interrupt\n", + device_get_nameunit(sc->dev)); + + sc->rx_delay_interrupts++; +} + +/* + * rt2860_tx_intr + */ +static void rt2860_tx_intr(struct rt2860_softc *sc, int qid) +{ + KASSERT(qid >= 0 && qid < RT2860_SOFTC_TX_RING_COUNT, + ("%s: Tx interrupt: invalid qid=%d\n", + device_get_nameunit(sc->dev), qid)); + + RT2860_DPRINTF(sc, RT2860_DEBUG_INTR, + "%s: Tx interrupt: qid=%d\n", + device_get_nameunit(sc->dev), qid); + + sc->tx_interrupts[qid]++; + + RT2860_SOFTC_LOCK(sc); + + if (!(sc->intr_disable_mask & (RT2860_REG_INT_TX_AC0_DONE << qid))) + { + rt2860_intr_disable(sc, (RT2860_REG_INT_TX_AC0_DONE << qid)); + + taskqueue_enqueue(sc->taskqueue, &sc->tx_done_task); + } + + sc->intr_pending_mask |= (RT2860_REG_INT_TX_AC0_DONE << qid); + + RT2860_SOFTC_UNLOCK(sc); +} + +/* + * rt2860_tx_delay_intr + */ +static void rt2860_tx_delay_intr(struct rt2860_softc *sc) +{ + RT2860_DPRINTF(sc, RT2860_DEBUG_INTR, + "%s: Tx delay interrupt\n", + device_get_nameunit(sc->dev)); + + sc->tx_delay_interrupts++; +} + +/* + * rt2860_pre_tbtt_intr + */ +static void rt2860_pre_tbtt_intr(struct rt2860_softc *sc) +{ + RT2860_DPRINTF(sc, RT2860_DEBUG_INTR, + "%s: Pre-TBTT interrupt\n", + device_get_nameunit(sc->dev)); + + sc->pre_tbtt_interrupts++; +} + +/* + * rt2860_tbtt_intr + */ +static void rt2860_tbtt_intr(struct rt2860_softc *sc) +{ + RT2860_DPRINTF(sc, RT2860_DEBUG_INTR, + "%s: TBTT interrupt\n", + device_get_nameunit(sc->dev)); + + sc->tbtt_interrupts++; +} + +/* + * rt2860_mcu_cmd_intr + */ +static void rt2860_mcu_cmd_intr(struct rt2860_softc *sc) +{ + RT2860_DPRINTF(sc, RT2860_DEBUG_INTR, + "%s: MCU command interrupt\n", + device_get_nameunit(sc->dev)); + + sc->mcu_cmd_interrupts++; +} + +/* + * rt2860_auto_wakeup_intr + */ +static void rt2860_auto_wakeup_intr(struct rt2860_softc *sc) +{ + RT2860_DPRINTF(sc, RT2860_DEBUG_INTR, + "%s: auto wakeup interrupt\n", + device_get_nameunit(sc->dev)); + + sc->auto_wakeup_interrupts++; +} + +/* + * rt2860_gp_timer_intr + */ +static void rt2860_gp_timer_intr(struct rt2860_softc *sc) +{ + RT2860_DPRINTF(sc, RT2860_DEBUG_INTR, + "%s: GP timer interrupt\n", + device_get_nameunit(sc->dev)); + + sc->gp_timer_interrupts++; +} + +/* + * rt2860_rx_done_task + */ +static void rt2860_rx_done_task(void *context, int pending) +{ + struct rt2860_softc *sc; + int again; + + sc = context; + + RT2860_DPRINTF(sc, RT2860_DEBUG_RX, + "%s: Rx done task\n", + device_get_nameunit(sc->dev)); + + if (!(sc->sc_flags & RT2860_RUNNING)) + return; + + sc->intr_pending_mask &= ~RT2860_REG_INT_RX_DONE; + + again = rt2860_rx_eof(sc, sc->rx_process_limit); + + RT2860_SOFTC_LOCK(sc); + + if ((sc->intr_pending_mask & RT2860_REG_INT_RX_DONE) || again) + { + RT2860_DPRINTF(sc, RT2860_DEBUG_RX, + "%s: Rx done task: scheduling again\n", + device_get_nameunit(sc->dev)); + + taskqueue_enqueue(sc->taskqueue, &sc->rx_done_task); + } + else + { + rt2860_intr_enable(sc, RT2860_REG_INT_RX_DONE); + } + + RT2860_SOFTC_UNLOCK(sc); +} + +/* + * rt2860_tx_done_task + */ +static void rt2860_tx_done_task(void *context, int pending) +{ + struct rt2860_softc *sc; + uint32_t intr_mask; + int i; + + sc = context; + + RT2860_DPRINTF(sc, RT2860_DEBUG_TX, + "%s: Tx done task\n", + device_get_nameunit(sc->dev)); + + if (!(sc->sc_flags & RT2860_RUNNING)) + return; + + for (i = RT2860_SOFTC_TX_RING_COUNT - 1; i >= 0; i--) + { + if (sc->intr_pending_mask & (RT2860_REG_INT_TX_AC0_DONE << i)) + { + sc->intr_pending_mask &= ~(RT2860_REG_INT_TX_AC0_DONE << i); + + rt2860_tx_eof(sc, &sc->tx_ring[i]); + } + } + + sc->tx_timer = 0; + + intr_mask = (RT2860_REG_INT_TX_MGMT_DONE | + RT2860_REG_INT_TX_HCCA_DONE | + RT2860_REG_INT_TX_AC3_DONE | + RT2860_REG_INT_TX_AC2_DONE | + RT2860_REG_INT_TX_AC1_DONE | + RT2860_REG_INT_TX_AC0_DONE); + + RT2860_SOFTC_LOCK(sc); + + rt2860_intr_enable(sc, ~sc->intr_pending_mask & + (sc->intr_disable_mask & intr_mask)); + + if (sc->intr_pending_mask & intr_mask) + { + RT2860_DPRINTF(sc, RT2860_DEBUG_TX, + "%s: Tx done task: scheduling again\n", + device_get_nameunit(sc->dev)); + + taskqueue_enqueue(sc->taskqueue, &sc->tx_done_task); + } + + RT2860_SOFTC_UNLOCK(sc); + +// if (!IFQ_IS_EMPTY(&ifp->if_snd)) + rt2860_start(sc); +} + +/* + * rt2860_fifo_sta_full_task + */ +static void rt2860_fifo_sta_full_task(void *context, int pending) +{ + struct rt2860_softc *sc; + + sc = context; + + RT2860_DPRINTF(sc, RT2860_DEBUG_STATS, + "%s: FIFO statistic full task\n", + device_get_nameunit(sc->dev)); + + if (!(sc->sc_flags & RT2860_RUNNING)) + return; + + sc->intr_pending_mask &= ~RT2860_REG_INT_FIFO_STA_FULL; + + rt2860_drain_fifo_stats(sc); + + RT2860_SOFTC_LOCK(sc); + + if (sc->intr_pending_mask & RT2860_REG_INT_FIFO_STA_FULL) + { + RT2860_DPRINTF(sc, RT2860_DEBUG_STATS, + "%s: FIFO statistic full task: scheduling again\n", + device_get_nameunit(sc->dev)); + + taskqueue_enqueue(sc->taskqueue, &sc->fifo_sta_full_task); + } + else + { + rt2860_intr_enable(sc, RT2860_REG_INT_FIFO_STA_FULL); + } + + RT2860_SOFTC_UNLOCK(sc); + +// if (!IFQ_IS_EMPTY(&ifp->if_snd)) + rt2860_start(sc); +} + +/* + * rt2860_periodic_task + */ +static void rt2860_periodic_task(void *context, int pending) +{ + struct rt2860_softc *sc; + struct ieee80211com *ic; + struct ieee80211vap *vap; + + sc = context; + ic = &sc->sc_ic; + vap = TAILQ_FIRST(&ic->ic_vaps); + + RT2860_DPRINTF(sc, RT2860_DEBUG_PERIODIC, + "%s: periodic task: round=%lu\n", + device_get_nameunit(sc->dev), sc->periodic_round); + + if (!(sc->sc_flags & RT2860_RUNNING)) + return; + + RT2860_SOFTC_LOCK(sc); + + sc->periodic_round++; + + rt2860_update_stats(sc); + + if ((sc->periodic_round % 10) == 0) + { + rt2860_bbp_tuning(sc); + + rt2860_update_raw_counters(sc); + + rt2860_watchdog(sc); + + if (vap != NULL && vap->iv_opmode != IEEE80211_M_MONITOR && vap->iv_state == IEEE80211_S_RUN) + { + if (vap->iv_opmode == IEEE80211_M_STA) + rt2860_amrr_update_iter_func(vap, vap->iv_bss); + else + ieee80211_iterate_nodes(&ic->ic_sta, rt2860_amrr_update_iter_func, vap); + } + } + + RT2860_SOFTC_UNLOCK(sc); + + callout_reset(&sc->periodic_ch, hz / 10, rt2860_periodic, sc); +} + +/* + * rt2860_rx_eof + */ +static int rt2860_rx_eof(struct rt2860_softc *sc, int limit) +{ + struct ieee80211com *ic; + struct ieee80211_frame *wh; + struct ieee80211_node *ni; + struct rt2860_softc_node *rni; + struct rt2860_softc_rx_radiotap_header *tap; + struct rt2860_softc_rx_ring *ring; + struct rt2860_rxdesc *desc; + struct rt2860_softc_rx_data *data; + struct rt2860_rxwi *rxwi; + struct mbuf *m, *mnew; + bus_dma_segment_t segs[1]; + bus_dmamap_t dma_map; + uint32_t index, desc_flags; + uint8_t rssi, ant, phymode, bw, shortgi, stbc, mcs, tid, frag; +#ifdef RT2860_HW_CRYPTO + uint8_t cipher_err, keyidx; +#endif + uint16_t seq; + int8_t rssi_dbm; + int error, nsegs, len, ampdu, amsdu, rssi_dbm_rel, nframes, i; + + ic = &sc->sc_ic; + ring = &sc->rx_ring; + + nframes = 0; + + while (limit != 0) + { + index = rt2860_io_mac_read(sc, RT2860_REG_SCHDMA_RX_DRX_IDX); + if (ring->cur == index) + break; + + desc = &ring->desc[ring->cur]; + data = &ring->data[ring->cur]; + + bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); +#ifdef XXX_TESTED_AND_WORKED + if (!(desc->sdl0 & htole16(RT2860_RXDESC_SDL0_DDONE))) + break; +#endif + + nframes++; + + mnew = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); + if (mnew == NULL) + { + sc->rx_mbuf_alloc_errors++; + counter_u64_add(ic->ic_ierrors, 1); + goto skip; + } + + mnew->m_len = mnew->m_pkthdr.len = MJUMPAGESIZE; + + error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag, ring->spare_dma_map, + mnew, segs, &nsegs, BUS_DMA_NOWAIT); + if (error != 0) + { + RT2860_DPRINTF(sc, RT2860_DEBUG_RX, + "%s: could not load Rx mbuf DMA map: error=%d, nsegs=%d\n", + device_get_nameunit(sc->dev), error, nsegs); + + m_freem(mnew); + + sc->rx_mbuf_dmamap_errors++; + counter_u64_add(ic->ic_ierrors, 1); + + goto skip; + } + + KASSERT(nsegs == 1, ("%s: too many DMA segments", + device_get_nameunit(sc->dev))); + + bus_dmamap_sync(ring->data_dma_tag, data->dma_map, + BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(ring->data_dma_tag, data->dma_map); + + dma_map = data->dma_map; + data->dma_map = ring->spare_dma_map; + ring->spare_dma_map = dma_map; + + bus_dmamap_sync(ring->data_dma_tag, data->dma_map, + BUS_DMASYNC_PREREAD); + + m = data->m; + + data->m = mnew; + desc->sdp0 = htole32(segs[0].ds_addr); + + desc_flags = le32toh(desc->flags); + + RT2860_DPRINTF(sc, RT2860_DEBUG_RX, + "%s: Rx frame: rxdesc flags=0x%08x\n", + device_get_nameunit(sc->dev), desc_flags); + + /* get Rx wireless info */ + + rxwi = mtod(m, struct rt2860_rxwi *); + len = (le16toh(rxwi->tid_size) >> RT2860_RXWI_SIZE_SHIFT) & + RT2860_RXWI_SIZE_MASK; + + /* check for L2 padding between IEEE 802.11 frame header and body */ + + if (desc_flags & RT2860_RXDESC_FLAGS_L2PAD) + { + RT2860_DPRINTF(sc, RT2860_DEBUG_RX, + "%s: L2 padding: len=%d\n", + device_get_nameunit(sc->dev), len); + + len += 2; + } + +// m->m_pkthdr.rcvif = ifp; + m->m_data = (caddr_t) (rxwi + 1); + m->m_pkthdr.len = m->m_len = len; + + /* check for crc errors */ + + if (desc_flags & RT2860_RXDESC_FLAGS_CRC_ERR) + { + RT2860_DPRINTF(sc, RT2860_DEBUG_RX, + "%s: rxdesc: crc error\n", + device_get_nameunit(sc->dev)); + + counter_u64_add(ic->ic_ierrors, 1); + + if (ic->ic_promisc == 0) + { + m_freem(m); + goto skip; + } + } + + wh = (struct ieee80211_frame *) (rxwi + 1); + + /* check for cipher errors */ +#ifdef RT2860_HW_CRYPTO + if (desc_flags & RT2860_RXDESC_FLAGS_DECRYPTED) + { + cipher_err = ((desc_flags >> RT2860_RXDESC_FLAGS_CIPHER_ERR_SHIFT) & + RT2860_RXDESC_FLAGS_CIPHER_ERR_MASK); + if (cipher_err == RT2860_RXDESC_FLAGS_CIPHER_ERR_NONE) + { + if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) + wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; + + m->m_flags |= M_WEP; + + sc->rx_cipher_no_errors++; + } + else + { + RT2860_DPRINTF(sc, RT2860_DEBUG_RX_CRYPT, + "%s: rxdesc: cipher error=0x%02x keyidx=%d\n", + device_get_nameunit(sc->dev), cipher_err, + (rxwi->udf_bssidx_keyidx >> RT2860_RXWI_KEYIDX_SHIFT) & + RT2860_RXWI_KEYIDX_MASK); + + if (cipher_err == RT2860_RXDESC_FLAGS_CIPHER_ERR_ICV) + sc->rx_cipher_icv_errors++; + else if (cipher_err == RT2860_RXDESC_FLAGS_CIPHER_ERR_MIC) + sc->rx_cipher_mic_errors++; + else if (cipher_err == RT2860_RXDESC_FLAGS_CIPHER_ERR_INVALID_KEY) + sc->rx_cipher_invalid_key_errors++; + + if ((cipher_err == RT2860_RXDESC_FLAGS_CIPHER_ERR_MIC) && + (desc_flags & RT2860_RXDESC_FLAGS_MYBSS)) + { + ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh); + if (ni != NULL) + { + keyidx = (rxwi->udf_bssidx_keyidx >> RT2860_RXWI_KEYIDX_SHIFT) & + RT2860_RXWI_KEYIDX_MASK; + + ieee80211_notify_michael_failure(ni->ni_vap, wh, keyidx); + + ieee80211_free_node(ni); + } + } + + counter_u64_add(ic->ic_ierrors, 1); + + if (ic->ic_promisc == 0) + { + m_free(m); + goto skip; + } + } + } + else + { + if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) + { + RT2860_DPRINTF(sc, RT2860_DEBUG_RX, + "%s: rxdesc: not decrypted but protected flag set\n", + device_get_nameunit(sc->dev)); + + counter_u64_add(ic->ic_ierrors, 1); + + if (ic->ic_promisc == 0) + { + m_free(m); + goto skip; + } + } + } +#endif + /* check for A-MPDU */ + + if (desc_flags & RT2860_RXDESC_FLAGS_BA) + { + m->m_flags |= M_AMPDU; + + sc->rx_ampdu++; + + if (wh->i_fc[1] & IEEE80211_FC1_RETRY) + sc->rx_ampdu_retries++; + + ampdu = 1; + } + else + { + ampdu = 0; + } + + /* check for A-MSDU */ + + if (desc_flags & RT2860_RXDESC_FLAGS_AMSDU) + { + sc->rx_amsdu++; + + amsdu = 1; + } + else + { + amsdu = 0; + } + + ant = rt2860_maxrssi_rxpath(sc, rxwi); + rssi = rxwi->rssi[ant]; + rssi_dbm = rt2860_rssi2dbm(sc, rssi, ant); + phymode = ((rxwi->phymode_stbc_shortgi >> RT2860_RXWI_PHYMODE_SHIFT) & + RT2860_RXWI_PHYMODE_MASK); + bw = ((rxwi->bw_mcs >> RT2860_RXWI_BW_SHIFT) & RT2860_RXWI_BW_MASK); + shortgi = ((rxwi->phymode_stbc_shortgi >> RT2860_RXWI_SHORTGI_SHIFT) & + RT2860_RXWI_SHORTGI_MASK); + stbc = ((rxwi->phymode_stbc_shortgi >> RT2860_RXWI_STBC_SHIFT) & + RT2860_RXWI_STBC_MASK); + mcs = ((rxwi->bw_mcs >> RT2860_RXWI_MCS_SHIFT) & RT2860_RXWI_MCS_MASK); + tid = ((rxwi->tid_size >> RT2860_RXWI_TID_SHIFT) & RT2860_RXWI_TID_MASK); + seq = ((rxwi->seq_frag >> RT2860_RXWI_SEQ_SHIFT) & RT2860_RXWI_SEQ_MASK); + frag = ((rxwi->seq_frag >> RT2860_RXWI_FRAG_SHIFT) & RT2860_RXWI_FRAG_MASK); + + if (ieee80211_radiotap_active(ic)) + { + tap = &sc->rxtap; + + tap->flags = (desc_flags & RT2860_RXDESC_FLAGS_L2PAD) ? IEEE80211_RADIOTAP_F_DATAPAD : 0; + tap->dbm_antsignal = rssi_dbm; + tap->dbm_antnoise = RT2860_NOISE_FLOOR; + tap->antenna = ant; + tap->antsignal = rssi; + tap->chan_flags = htole32(ic->ic_curchan->ic_flags); + tap->chan_freq = htole16(ic->ic_curchan->ic_freq); + tap->chan_ieee = ic->ic_curchan->ic_ieee; + tap->chan_maxpow = 0; + + if (phymode == RT2860_TXWI_PHYMODE_HT_MIXED || phymode == RT2860_TXWI_PHYMODE_HT_GF) + tap->rate = mcs | IEEE80211_RATE_MCS; + else + tap->rate = rt2860_rxrate(rxwi); + + if (desc_flags & RT2860_RXDESC_FLAGS_CRC_ERR) + tap->flags |= IEEE80211_RADIOTAP_F_BADFCS; + + if (desc_flags & RT2860_RXDESC_FLAGS_FRAG) + tap->flags |= IEEE80211_RADIOTAP_F_FRAG; + + if (rxwi->bw_mcs & RT2860_RXWI_MCS_SHOTPRE) + tap->flags |= IEEE80211_RADIOTAP_F_SHORTPRE; + + if ((desc_flags & RT2860_RXDESC_FLAGS_DECRYPTED) || + (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)) + tap->flags |= IEEE80211_RADIOTAP_F_WEP; + + if (shortgi) + tap->flags |= IEEE80211_RADIOTAP_F_SHORTGI; + + /* XXX use temporarily radiotap CFP flag as A-MPDU flag */ + + if (ampdu) + tap->flags |= IEEE80211_RADIOTAP_F_CFP; + } + + /* + * net80211 assumes that RSSI data are in the range [-127..127] and + * in .5 dBm units relative to the current noise floor + */ + + rssi_dbm_rel = (rssi_dbm - RT2860_NOISE_FLOOR) * 2; + if (rssi_dbm_rel > 127) + rssi_dbm_rel = 127; + + RT2860_DPRINTF(sc, RT2860_DEBUG_RX, + "%s: received frame: len=%d, phymode=%d, bw=%d, shortgi=%d, stbc=0x%02x, mcs=%d, " + "ant=%d, rssi=%d/%d/%d, snr=%d/%d, wcid=0x%02x, ampdu=%d, amsdu=%d, tid=%d, seq=%d, frag=%d, " + "retry=%d, rssi_dbm=%d, rssi_dbm_rel=%d\n", + device_get_nameunit(sc->dev), + len, phymode, bw, shortgi, stbc, mcs, + ant, rxwi->rssi[0], rxwi->rssi[1], rxwi->rssi[2], + rxwi->snr[0], rxwi->snr[1], + rxwi->wcid, ampdu, amsdu, tid, seq, frag, (wh->i_fc[1] & IEEE80211_FC1_RETRY) ? 1 : 0, + rssi_dbm, rssi_dbm_rel); + + ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *) wh); + if (ni != NULL) + { + rni = (struct rt2860_softc_node *) ni; + + for (i = 0; i < RT2860_SOFTC_RSSI_COUNT; i++) + { + rni->last_rssi[i] = rxwi->rssi[i]; + rni->last_rssi_dbm[i] = rt2860_rssi2dbm(sc, rxwi->rssi[i], i); + } + + ieee80211_input(ni, m, rssi_dbm_rel, RT2860_NOISE_FLOOR); + ieee80211_free_node(ni); + } + else + { + ieee80211_input_all(ic, m, rssi_dbm_rel, RT2860_NOISE_FLOOR); + } + +skip: + + desc->sdl0 &= ~htole16(RT2860_RXDESC_SDL0_DDONE); + + bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + ring->cur = (ring->cur + 1) % RT2860_SOFTC_RX_RING_DATA_COUNT; + + limit--; + } + + if (ring->cur == 0) + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_RX_CALC_IDX, + RT2860_SOFTC_RX_RING_DATA_COUNT - 1); + else + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_RX_CALC_IDX, + ring->cur - 1); + + RT2860_DPRINTF(sc, RT2860_DEBUG_RX, + "%s: Rx eof: nframes=%d\n", + device_get_nameunit(sc->dev), nframes); + + sc->rx_packets += nframes; + + return (limit == 0); +} + +/* + * rt2860_tx_eof + */ +static void rt2860_tx_eof(struct rt2860_softc *sc, + struct rt2860_softc_tx_ring *ring) +{ + struct rt2860_txdesc *desc; + struct rt2860_softc_tx_data *data; + uint32_t index; + int ndescs, nframes; + + ndescs = 0; + nframes = 0; + + for (;;) + { + index = rt2860_io_mac_read(sc, RT2860_REG_SCHDMA_TX_DTX_IDX(ring->qid)); + if (ring->desc_next == index) + break; + + ndescs++; + + rt2860_drain_fifo_stats(sc); + + desc = &ring->desc[ring->desc_next]; + + bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + + if (desc->sdl0 & htole16(RT2860_TXDESC_SDL0_LASTSEG) || + desc->sdl1 & htole16(RT2860_TXDESC_SDL1_LASTSEG)) + { + nframes++; + + data = &ring->data[ring->data_next]; + + if (data->m->m_flags & M_TXCB) + ieee80211_process_callback(data->ni, data->m, 0); + + bus_dmamap_sync(ring->data_dma_tag, data->dma_map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(ring->data_dma_tag, data->dma_map); + +// m_freem(data->m); + +// ieee80211_free_node(data->ni); + ieee80211_tx_complete(data->ni, data->m, 0); + + data->m = NULL; + data->ni = NULL; + +// ifp->if_opackets++; + + RT2860_SOFTC_TX_RING_LOCK(ring); + + ring->data_queued--; + ring->data_next = (ring->data_next + 1) % RT2860_SOFTC_TX_RING_DATA_COUNT; + + RT2860_SOFTC_TX_RING_UNLOCK(ring); + } + + desc->sdl0 &= ~htole16(RT2860_TXDESC_SDL0_DDONE); + + bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + RT2860_SOFTC_TX_RING_LOCK(ring); + + ring->desc_queued--; + ring->desc_next = (ring->desc_next + 1) % RT2860_SOFTC_TX_RING_DESC_COUNT; + + RT2860_SOFTC_TX_RING_UNLOCK(ring); + } + + RT2860_DPRINTF(sc, RT2860_DEBUG_TX, + "%s: Tx eof: qid=%d, ndescs=%d, nframes=%d\n", + device_get_nameunit(sc->dev), ring->qid, ndescs, nframes); +} + +/* + * rt2860_update_stats + */ +static void rt2860_update_stats(struct rt2860_softc *sc) +{ + struct ieee80211com *ic; + uint32_t stacnt[3]; + int beacons, noretryok, retryok, failed, underflows, zerolen; + + ic = &sc->sc_ic; + + RT2860_DPRINTF(sc, RT2860_DEBUG_STATS, + "%s: update statistic\n", + device_get_nameunit(sc->dev)); + + rt2860_drain_fifo_stats(sc); + + /* read and clear Tx statistic registers */ + + rt2860_io_mac_read_multi(sc, RT2860_REG_TX_STA_CNT0, + stacnt, sizeof(stacnt)); + + stacnt[0] = le32toh(stacnt[0]); + stacnt[1] = le32toh(stacnt[1]); + stacnt[2] = le32toh(stacnt[2]); + + beacons = stacnt[0] >> 16; + noretryok = stacnt[1] & 0xffff; + retryok = stacnt[1] >> 16; + failed = stacnt[0] & 0xffff; + underflows = stacnt[2] >> 16; + zerolen = stacnt[2] & 0xffff; + + RT2860_DPRINTF(sc, RT2860_DEBUG_STATS, + "%s: update statistic: beacons=%d, noretryok=%d, retryok=%d, failed=%d, underflows=%d, zerolen=%d\n", + device_get_nameunit(sc->dev), + beacons, noretryok, retryok, failed, underflows, zerolen); + + counter_u64_add(sc->sc_ic.ic_oerrors, failed); + + sc->tx_beacons += beacons; + sc->tx_noretryok += noretryok; + sc->tx_retryok += retryok; + sc->tx_failed += failed; + sc->tx_underflows += underflows; + sc->tx_zerolen += zerolen; +} + +/* + * rt2860_bbp_tuning + */ +static void rt2860_bbp_tuning(struct rt2860_softc *sc) +{ + struct ieee80211com *ic; + struct ieee80211vap *vap; + struct ieee80211_node *ni; + int chan, group; + int8_t rssi, old, new; + + /* RT2860C does not support BBP tuning */ + +// if (sc->mac_rev == 0x28600100) + if (sc->mac_rev == 0x28600102) + return; + + ic = &sc->sc_ic; + vap = TAILQ_FIRST(&ic->ic_vaps); + + if ((ic->ic_flags & IEEE80211_F_SCAN) || vap == NULL || + vap->iv_opmode != IEEE80211_M_STA || vap->iv_state != IEEE80211_S_RUN) + return; + + ni = vap->iv_bss; + + chan = ieee80211_chan2ieee(ic, ni->ni_chan); + + if (chan <= 14) + group = 0; + else if (chan <= 64) + group = 1; + else if (chan <= 128) + group = 2; + else + group = 3; + + rssi = ieee80211_getrssi(vap); + + if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) + { + new = 0x2e + sc->lna_gain[group]; + } + else + { + if (!IEEE80211_IS_CHAN_HT40(ni->ni_chan)) + new = 0x32 + sc->lna_gain[group] * 5 / 3; + else + new = 0x3a + sc->lna_gain[group] * 5 / 3; + } + + /* Tune if absolute average RSSI is greater than -80 */ + + if (rssi > 30) + new += 0x10; + + old = rt2860_io_bbp_read(sc, 66); + + if (old != new) + rt2860_io_bbp_write(sc, 66, new); +} + +/* + * rt2860_watchdog + */ +static void rt2860_watchdog(struct rt2860_softc *sc) +{ + uint32_t tmp; + int ntries; + + tmp = rt2860_io_mac_read(sc, RT2860_REG_PBF_TXRXQ_PCNT); + + RT2860_DPRINTF(sc, RT2860_DEBUG_WATCHDOG, + "%s: watchdog: TXRXQ_PCNT=0x%08x\n", + device_get_nameunit(sc->dev), tmp); + + if (((tmp >> RT2860_REG_TX0Q_PCNT_SHIFT) & RT2860_REG_TX0Q_PCNT_MASK) != 0) + { + sc->tx_queue_not_empty[0]++; + + rt2860_io_mac_write(sc, RT2860_REG_PBF_CFG, 0xf40012); + + for (ntries = 0; ntries < 10; ntries++) + { + tmp = rt2860_io_mac_read(sc, RT2860_REG_PBF_TXRXQ_PCNT); + if (((tmp >> RT2860_REG_TX0Q_PCNT_SHIFT) & RT2860_REG_TX0Q_PCNT_MASK) == 0) + break; + + DELAY(1); + } + + rt2860_io_mac_write(sc, RT2860_REG_PBF_CFG, 0xf40006); + } + + if (((tmp >> RT2860_REG_TX1Q_PCNT_SHIFT) & RT2860_REG_TX1Q_PCNT_MASK) != 0) + { + sc->tx_queue_not_empty[1]++; + + rt2860_io_mac_write(sc, RT2860_REG_PBF_CFG, 0xf4000a); + + for (ntries = 0; ntries < 10; ntries++) + { + tmp = rt2860_io_mac_read(sc, RT2860_REG_PBF_TXRXQ_PCNT); + if (((tmp >> RT2860_REG_TX1Q_PCNT_SHIFT) & RT2860_REG_TX1Q_PCNT_MASK) == 0) + break; + + DELAY(1); + } + + rt2860_io_mac_write(sc, RT2860_REG_PBF_CFG, 0xf40006); + } +} + +/* + * rt2860_drain_fifo_stats + */ +static void rt2860_drain_fifo_stats(struct rt2860_softc *sc) +{ + uint32_t stats; + uint8_t wcid, mcs, pid; + int ok, agg, retrycnt; + + /* drain Tx status FIFO (maxsize = 16) */ + + while ((stats = rt2860_io_mac_read(sc, RT2860_REG_TX_STA_FIFO)) & + RT2860_REG_TX_STA_FIFO_VALID) + { + wcid = (stats >> RT2860_REG_TX_STA_FIFO_WCID_SHIFT) & + RT2860_REG_TX_STA_FIFO_WCID_MASK; + + /* if no ACK was requested, no feedback is available */ + + if (!(stats & RT2860_REG_TX_STA_FIFO_ACK_REQ) || wcid == RT2860_WCID_RESERVED) + continue; + + /* update AMRR statistic */ + + ok = (stats & RT2860_REG_TX_STA_FIFO_TX_OK) ? 1 : 0; + agg = (stats & RT2860_REG_TX_STA_FIFO_AGG) ? 1 : 0; + mcs = (stats >> RT2860_REG_TX_STA_FIFO_MCS_SHIFT) & + RT2860_REG_TX_STA_FIFO_MCS_MASK; + pid = (stats >> RT2860_REG_TX_STA_FIFO_PID_SHIFT) & + RT2860_REG_TX_STA_FIFO_PID_MASK; + retrycnt = (mcs < 0xf) ? (pid - mcs - 1) : 0; + + RT2860_DPRINTF(sc, RT2860_DEBUG_STATS, + "%s: FIFO statistic: wcid=0x%02x, ok=%d, agg=%d, mcs=0x%02x, pid=0x%02x, retrycnt=%d\n", + device_get_nameunit(sc->dev), + wcid, ok, agg, mcs, pid, retrycnt); + + rt2860_amrr_tx_complete(&sc->amrr_node[wcid], ok, retrycnt); + + if (!ok) + counter_u64_add(sc->sc_ic.ic_oerrors, 1); + } +} + +/* + * rt2860_update_raw_counters + */ +static void rt2860_update_raw_counters(struct rt2860_softc *sc) +{ + uint32_t tmp; + + tmp = rt2860_io_mac_read(sc, RT2860_REG_TX_AGG_CNT); + + sc->tx_nonagg += tmp & 0xffff; + sc->tx_agg += tmp >> 16; + + tmp = rt2860_io_mac_read(sc, RT2860_REG_TX_AGG_CNT0); + + sc->tx_ampdu += (tmp & 0xffff) / 1 + (tmp >> 16) / 2; + + tmp = rt2860_io_mac_read(sc, RT2860_REG_TX_AGG_CNT1); + + sc->tx_ampdu += (tmp & 0xffff) / 3 + (tmp >> 16) / 4; + + tmp = rt2860_io_mac_read(sc, RT2860_REG_TX_AGG_CNT2); + + sc->tx_ampdu += (tmp & 0xffff) / 5 + (tmp >> 16) / 6; + + tmp = rt2860_io_mac_read(sc, RT2860_REG_TX_AGG_CNT3); + + sc->tx_ampdu += (tmp & 0xffff) / 7 + (tmp >> 16) / 8; + + tmp = rt2860_io_mac_read(sc, RT2860_REG_TX_AGG_CNT4); + + sc->tx_ampdu += (tmp & 0xffff) / 9 + (tmp >> 16) / 10; + + tmp = rt2860_io_mac_read(sc, RT2860_REG_TX_AGG_CNT5); + + sc->tx_ampdu += (tmp & 0xffff) / 11 + (tmp >> 16) / 12; + + tmp = rt2860_io_mac_read(sc, RT2860_REG_TX_AGG_CNT6); + + sc->tx_ampdu += (tmp & 0xffff) / 13 + (tmp >> 16) / 14; + + tmp = rt2860_io_mac_read(sc, RT2860_REG_TX_AGG_CNT7); + + sc->tx_ampdu += (tmp & 0xffff) / 15 + (tmp >> 16) / 16; + + tmp = rt2860_io_mac_read(sc, RT2860_REG_RX_STA_CNT0); + + sc->rx_crc_errors += tmp & 0xffff; + sc->rx_phy_errors += tmp >> 16; + + tmp = rt2860_io_mac_read(sc, RT2860_REG_RX_STA_CNT1); + + sc->rx_false_ccas += tmp & 0xffff; + sc->rx_plcp_errors += tmp >> 16; + + tmp = rt2860_io_mac_read(sc, RT2860_REG_RX_STA_CNT2); + + sc->rx_dup_packets += tmp & 0xffff; + sc->rx_fifo_overflows += tmp >> 16; + + tmp = rt2860_io_mac_read(sc, RT2860_REG_TXRX_MPDU_DEN_CNT); + + sc->tx_mpdu_zero_density += tmp & 0xffff; + sc->rx_mpdu_zero_density += tmp >> 16; +} + +/* + * rt2860_intr_enable + */ +static void rt2860_intr_enable(struct rt2860_softc *sc, uint32_t intr_mask) +{ + uint32_t tmp; + + sc->intr_disable_mask &= ~intr_mask; + + tmp = sc->intr_enable_mask & ~sc->intr_disable_mask; + + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_INT_MASK, tmp); +} + +/* + * rt2860_intr_disable + */ +static void rt2860_intr_disable(struct rt2860_softc *sc, uint32_t intr_mask) +{ + uint32_t tmp; + + sc->intr_disable_mask |= intr_mask; + + tmp = sc->intr_enable_mask & ~sc->intr_disable_mask; + + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_INT_MASK, tmp); +} + +/* + * rt2860_txrx_enable + */ +static int rt2860_txrx_enable(struct rt2860_softc *sc) +{ + struct ieee80211com *ic; + uint32_t tmp; + int ntries; + + ic = &sc->sc_ic; + + /* enable Tx/Rx DMA engine */ + + rt2860_io_mac_write(sc, RT2860_REG_SYS_CTRL, RT2860_REG_TX_ENABLE); + + for (ntries = 0; ntries < 200; ntries++) + { + tmp = rt2860_io_mac_read(sc, RT2860_REG_SCHDMA_WPDMA_GLO_CFG); + if (!(tmp & (RT2860_REG_TX_DMA_BUSY | RT2860_REG_RX_DMA_BUSY))) + break; + + DELAY(1000); + } + + if (ntries == 200) + { + printf("%s: timeout waiting for DMA engine\n", + device_get_nameunit(sc->dev)); + return -1; + } + + DELAY(50); + + tmp |= RT2860_REG_TX_WB_DDONE | + RT2860_REG_RX_DMA_ENABLE | + RT2860_REG_TX_DMA_ENABLE | + (RT2860_REG_WPDMA_BT_SIZE64 << RT2860_REG_WPDMA_BT_SIZE_SHIFT); + + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_WPDMA_GLO_CFG, tmp); + + /* set Rx filter */ + + tmp = RT2860_REG_RX_FILTER_DROP_CRC_ERR | + RT2860_REG_RX_FILTER_DROP_PHY_ERR; + + if (ic->ic_opmode != IEEE80211_M_MONITOR) + { + tmp |= RT2860_REG_RX_FILTER_DROP_DUPL | + RT2860_REG_RX_FILTER_DROP_CTS | + RT2860_REG_RX_FILTER_DROP_BA | + RT2860_REG_RX_FILTER_DROP_ACK | + RT2860_REG_RX_FILTER_DROP_VER_ERR | + RT2860_REG_RX_FILTER_DROP_CTRL_RSV | + RT2860_REG_RX_FILTER_DROP_CFACK | + RT2860_REG_RX_FILTER_DROP_CFEND; + + if (ic->ic_opmode == IEEE80211_M_STA) + tmp |= RT2860_REG_RX_FILTER_DROP_RTS | + RT2860_REG_RX_FILTER_DROP_PSPOLL; + + if (ic->ic_promisc == 0) + tmp |= RT2860_REG_RX_FILTER_DROP_UC_NOME; + } + + rt2860_io_mac_write(sc, RT2860_REG_RX_FILTER_CFG, tmp); + + rt2860_io_mac_write(sc, RT2860_REG_SYS_CTRL, + RT2860_REG_RX_ENABLE | RT2860_REG_TX_ENABLE); + + return 0; +} + +/* + * rt2860_alloc_rx_ring + */ +static int rt2860_alloc_rx_ring(struct rt2860_softc *sc, + struct rt2860_softc_rx_ring *ring) +{ + struct rt2860_rxdesc *desc; + struct rt2860_softc_rx_data *data; + bus_dma_segment_t segs[1]; + int i, nsegs, error; + + error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0, + BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, + RT2860_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt2860_rxdesc), 1, + RT2860_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt2860_rxdesc), + 0, NULL, NULL, &ring->desc_dma_tag); + if (error != 0) + { + printf("%s: could not create Rx desc DMA tag\n", + device_get_nameunit(sc->dev)); + goto fail; + } + + error = bus_dmamem_alloc(ring->desc_dma_tag, (void **) &ring->desc, + BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_dma_map); + if (error != 0) + { + printf("%s: could not allocate Rx desc DMA memory\n", + device_get_nameunit(sc->dev)); + goto fail; + } + + error = bus_dmamap_load(ring->desc_dma_tag, ring->desc_dma_map, + ring->desc, + RT2860_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt2860_rxdesc), + rt2860_dma_map_addr, &ring->desc_phys_addr, 0); + if (error != 0) + { + printf("%s: could not load Rx desc DMA map\n", + device_get_nameunit(sc->dev)); + goto fail; + } + + error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0, + BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, + MJUMPAGESIZE, 1, MJUMPAGESIZE, 0, NULL, NULL, + &ring->data_dma_tag); + if (error != 0) + { + printf("%s: could not create Rx data DMA tag\n", + device_get_nameunit(sc->dev)); + goto fail; + } + + for (i = 0; i < RT2860_SOFTC_RX_RING_DATA_COUNT; i++) + { + desc = &ring->desc[i]; + data = &ring->data[i]; + + error = bus_dmamap_create(ring->data_dma_tag, 0, &data->dma_map); + if (error != 0) + { + printf("%s: could not create Rx data DMA map\n", + device_get_nameunit(sc->dev)); + goto fail; + } + + data->m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); + if (data->m == NULL) + { + printf("%s: could not allocate Rx mbuf\n", + device_get_nameunit(sc->dev)); + error = ENOMEM; + goto fail; + } + + data->m->m_len = data->m->m_pkthdr.len = MJUMPAGESIZE; + + error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag, data->dma_map, + data->m, segs, &nsegs, BUS_DMA_NOWAIT); + if (error != 0) + { + printf("%s: could not load Rx mbuf DMA map\n", + device_get_nameunit(sc->dev)); + goto fail; + } + + KASSERT(nsegs == 1, ("%s: too many DMA segments", + device_get_nameunit(sc->dev))); + + desc->sdp0 = htole32(segs[0].ds_addr); + desc->sdl0 = htole16(MJUMPAGESIZE); + } + + error = bus_dmamap_create(ring->data_dma_tag, 0, &ring->spare_dma_map); + if (error != 0) + { + printf("%s: could not create Rx spare DMA map\n", + device_get_nameunit(sc->dev)); + goto fail; + } + + bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + return 0; + +fail: + + rt2860_free_rx_ring(sc, ring); + + return error; +} + +/* + * rt2860_reset_rx_ring + */ +static void rt2860_reset_rx_ring(struct rt2860_softc *sc, + struct rt2860_softc_rx_ring *ring) +{ + struct rt2860_rxdesc *desc; + int i; + + for (i = 0; i < RT2860_SOFTC_RX_RING_DATA_COUNT; i++) { + desc = &ring->desc[i]; + + desc->sdl0 &= ~htole16(RT2860_RXDESC_SDL0_DDONE); + } + + bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + ring->cur = 0; +} + +/* + * rt2860_free_rx_ring + */ +static void rt2860_free_rx_ring(struct rt2860_softc *sc, + struct rt2860_softc_rx_ring *ring) +{ + struct rt2860_softc_rx_data *data; + int i; + + if (ring->desc != NULL) { + bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(ring->desc_dma_tag, ring->desc_dma_map); + bus_dmamem_free(ring->desc_dma_tag, ring->desc, + ring->desc_dma_map); + } + + if (ring->desc_dma_tag != NULL) + bus_dma_tag_destroy(ring->desc_dma_tag); + + for (i = 0; i < RT2860_SOFTC_RX_RING_DATA_COUNT; i++) { + data = &ring->data[i]; + + if (data->m != NULL) { + bus_dmamap_sync(ring->data_dma_tag, data->dma_map, + BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(ring->data_dma_tag, data->dma_map); + m_freem(data->m); + } + + if (data->dma_map != NULL) + bus_dmamap_destroy(ring->data_dma_tag, data->dma_map); + } + + if (ring->spare_dma_map != NULL) + bus_dmamap_destroy(ring->data_dma_tag, ring->spare_dma_map); + + if (ring->data_dma_tag != NULL) + bus_dma_tag_destroy(ring->data_dma_tag); +} + +/* + * rt2860_alloc_tx_ring + */ +static int rt2860_alloc_tx_ring(struct rt2860_softc *sc, + struct rt2860_softc_tx_ring *ring, int qid) +{ + struct rt2860_softc_tx_data *data; + int error, i, size; + + size = RT2860_SOFTC_TX_RING_DESC_COUNT * sizeof(struct rt2860_txdesc); + mtx_init(&ring->lock, device_get_nameunit(sc->dev), NULL, MTX_DEF); + + error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0, + BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, + size, 1, size, 0, NULL, NULL, &ring->desc_dma_tag); + if (error != 0) { + device_printf(sc->dev, "could not create Tx desc DMA tag\n"); + goto fail; + } + + error = bus_dmamem_alloc(ring->desc_dma_tag, (void **) &ring->desc, + BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_dma_map); + if (error != 0) { + device_printf(sc->dev, + "could not allocate Tx desc DMA memory\n"); + goto fail; + } + + error = bus_dmamap_load(ring->desc_dma_tag, ring->desc_dma_map, + ring->desc, size, rt2860_dma_map_addr, &ring->desc_phys_addr, 0); + if (error != 0) { + device_printf(sc->dev, "could not load Tx desc DMA map\n"); + goto fail; + } + + ring->desc_queued = 0; + ring->desc_cur = 0; + ring->desc_next = 0; + + size = RT2860_SOFTC_TX_RING_DATA_COUNT * RT2860_TX_DATA_SEG0_SIZE; + error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0, + BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, + size, 1, size, 0, NULL, NULL, &ring->seg0_dma_tag); + if (error != 0) { + device_printf(sc->dev, "could not create Tx seg0 DMA tag\n"); + goto fail; + } + + error = bus_dmamem_alloc(ring->seg0_dma_tag, (void **) &ring->seg0, + BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->seg0_dma_map); + if (error != 0) { + device_printf(sc->dev, "could not allocate Tx seg0 DMA memory\n"); + goto fail; + } + + error = bus_dmamap_load(ring->seg0_dma_tag, ring->seg0_dma_map, + ring->seg0, size, rt2860_dma_map_addr, &ring->seg0_phys_addr, 0); + if (error != 0) { + device_printf(sc->dev, "could not load Tx seg0 DMA map\n"); + goto fail; + } + + + error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0, + BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, + MJUMPAGESIZE, RT2860_SOFTC_MAX_SCATTER, MJUMPAGESIZE, 0, + NULL, NULL, &ring->data_dma_tag); + if (error != 0) { + device_printf(sc->dev, "could not create Tx data DMA tag\n"); + goto fail; + } + + for (i = 0; i < RT2860_SOFTC_TX_RING_DATA_COUNT; i++){ + data = &ring->data[i]; + + error = bus_dmamap_create(ring->data_dma_tag, 0, + &data->dma_map); + if (error != 0) { + device_printf(sc->dev, "could not create Tx data DMA map\n"); + goto fail; + } + } + + ring->data_queued = 0; + ring->data_cur = 0; + ring->data_next = 0; + + ring->qid = qid; + + return 0; + +fail: + + rt2860_free_tx_ring(sc, ring); + + return error; +} + +/* + * rt2860_reset_tx_ring + */ +static void rt2860_reset_tx_ring(struct rt2860_softc *sc, + struct rt2860_softc_tx_ring *ring) +{ + struct rt2860_softc_tx_data *data; + struct rt2860_txdesc *desc; + int i; + + for (i = 0; i < RT2860_SOFTC_TX_RING_DESC_COUNT; i++) + { + desc = &ring->desc[i]; + + desc->sdl0 = 0; + desc->sdl1 = 0; + } + + ring->desc_queued = 0; + ring->desc_cur = 0; + ring->desc_next = 0; + + bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, + BUS_DMASYNC_PREWRITE); + + bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map, + BUS_DMASYNC_PREWRITE); + + for (i = 0; i < RT2860_SOFTC_TX_RING_DATA_COUNT; i++) + { + data = &ring->data[i]; + + if (data->m != NULL) + { + bus_dmamap_sync(ring->data_dma_tag, data->dma_map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(ring->data_dma_tag, data->dma_map); + m_freem(data->m); + data->m = NULL; + } + + if (data->ni != NULL) + { + ieee80211_free_node(data->ni); + data->ni = NULL; + } + } + + ring->data_queued = 0; + ring->data_cur = 0; + ring->data_next = 0; +} + +/* + * rt2860_free_tx_ring + */ +static void rt2860_free_tx_ring(struct rt2860_softc *sc, + struct rt2860_softc_tx_ring *ring) +{ + struct rt2860_softc_tx_data *data; + int i; + + if (ring->desc != NULL) + { + bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(ring->desc_dma_tag, ring->desc_dma_map); + bus_dmamem_free(ring->desc_dma_tag, ring->desc, + ring->desc_dma_map); + } + + if (ring->desc_dma_tag != NULL) + bus_dma_tag_destroy(ring->desc_dma_tag); + + if (ring->seg0 != NULL) + { + bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(ring->seg0_dma_tag, ring->seg0_dma_map); + bus_dmamem_free(ring->seg0_dma_tag, ring->seg0, + ring->seg0_dma_map); + } + + if (ring->seg0_dma_tag != NULL) + bus_dma_tag_destroy(ring->seg0_dma_tag); + + for (i = 0; i < RT2860_SOFTC_TX_RING_DATA_COUNT; i++) + { + data = &ring->data[i]; + + if (data->m != NULL) + { + bus_dmamap_sync(ring->data_dma_tag, data->dma_map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(ring->data_dma_tag, data->dma_map); + m_freem(data->m); + } + + if (data->ni != NULL) + ieee80211_free_node(data->ni); + + if (data->dma_map != NULL) + bus_dmamap_destroy(ring->data_dma_tag, data->dma_map); + } + + if (ring->data_dma_tag != NULL) + bus_dma_tag_destroy(ring->data_dma_tag); + + mtx_destroy(&ring->lock); +} + +/* + * rt2860_dma_map_addr + */ +static void rt2860_dma_map_addr(void *arg, bus_dma_segment_t *segs, + int nseg, int error) +{ + if (error != 0) + return; + + KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); + + *(bus_addr_t *) arg = segs[0].ds_addr; +} + +/* + * rt2860_sysctl_attach + */ +static void rt2860_sysctl_attach(struct rt2860_softc *sc) +{ + struct sysctl_ctx_list *ctx; + struct sysctl_oid *tree; + struct sysctl_oid *stats; + + ctx = device_get_sysctl_ctx(sc->dev); + tree = device_get_sysctl_tree(sc->dev); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, + "tx_stbc", CTLFLAG_RW, &sc->tx_stbc, 0, + "Tx STBC"); + + /* statistic counters */ + + stats = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, + "stats", CTLFLAG_RD, 0, "statistic"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "interrupts", CTLFLAG_RD, &sc->interrupts, 0, + "all interrupts"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_coherent_interrupts", CTLFLAG_RD, &sc->tx_coherent_interrupts, 0, + "Tx coherent interrupts"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "rx_coherent_interrupts", CTLFLAG_RD, &sc->rx_coherent_interrupts, 0, + "Rx coherent interrupts"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "txrx_coherent_interrupts", CTLFLAG_RD, &sc->txrx_coherent_interrupts, 0, + "Tx/Rx coherent interrupts"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "fifo_sta_full_interrupts", CTLFLAG_RD, &sc->fifo_sta_full_interrupts, 0, + "FIFO statistic full interrupts"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "rx_interrupts", CTLFLAG_RD, &sc->rx_interrupts, 0, + "Rx interrupts"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "rx_delay_interrupts", CTLFLAG_RD, &sc->rx_delay_interrupts, 0, + "Rx delay interrupts"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_mgmt_interrupts", CTLFLAG_RD, &sc->tx_interrupts[5], 0, + "Tx MGMT interrupts"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_hcca_interrupts", CTLFLAG_RD, &sc->tx_interrupts[4], 0, + "Tx HCCA interrupts"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_ac3_interrupts", CTLFLAG_RD, &sc->tx_interrupts[3], 0, + "Tx AC3 interrupts"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_ac2_interrupts", CTLFLAG_RD, &sc->tx_interrupts[2], 0, + "Tx AC2 interrupts"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_ac1_interrupts", CTLFLAG_RD, &sc->tx_interrupts[1], 0, + "Tx AC1 interrupts"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_ac0_interrupts", CTLFLAG_RD, &sc->tx_interrupts[0], 0, + "Tx AC0 interrupts"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_delay_interrupts", CTLFLAG_RD, &sc->tx_delay_interrupts, 0, + "Tx delay interrupts"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "pre_tbtt_interrupts", CTLFLAG_RD, &sc->pre_tbtt_interrupts, 0, + "Pre-TBTT interrupts"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tbtt_interrupts", CTLFLAG_RD, &sc->tbtt_interrupts, 0, + "TBTT interrupts"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "mcu_cmd_interrupts", CTLFLAG_RD, &sc->mcu_cmd_interrupts, 0, + "MCU command interrupts"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "auto_wakeup_interrupts", CTLFLAG_RD, &sc->auto_wakeup_interrupts, 0, + "auto wakeup interrupts"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "gp_timer_interrupts", CTLFLAG_RD, &sc->gp_timer_interrupts, 0, + "GP timer interrupts"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_mgmt_desc_queued", CTLFLAG_RD, &sc->tx_ring[5].desc_queued, 0, + "Tx MGMT descriptors queued"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_mgmt_data_queued", CTLFLAG_RD, &sc->tx_ring[5].data_queued, 0, + "Tx MGMT data queued"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_hcca_desc_queued", CTLFLAG_RD, &sc->tx_ring[4].desc_queued, 0, + "Tx HCCA descriptors queued"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_hcca_data_queued", CTLFLAG_RD, &sc->tx_ring[4].data_queued, 0, + "Tx HCCA data queued"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_ac3_desc_queued", CTLFLAG_RD, &sc->tx_ring[3].desc_queued, 0, + "Tx AC3 descriptors queued"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_ac3_data_queued", CTLFLAG_RD, &sc->tx_ring[3].data_queued, 0, + "Tx AC3 data queued"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_ac2_desc_queued", CTLFLAG_RD, &sc->tx_ring[2].desc_queued, 0, + "Tx AC2 descriptors queued"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_ac2_data_queued", CTLFLAG_RD, &sc->tx_ring[2].data_queued, 0, + "Tx AC2 data queued"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_ac1_desc_queued", CTLFLAG_RD, &sc->tx_ring[1].desc_queued, 0, + "Tx AC1 descriptors queued"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_ac1_data_queued", CTLFLAG_RD, &sc->tx_ring[1].data_queued, 0, + "Tx AC1 data queued"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_ac0_desc_queued", CTLFLAG_RD, &sc->tx_ring[0].desc_queued, 0, + "Tx AC0 descriptors queued"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_ac0_data_queued", CTLFLAG_RD, &sc->tx_ring[0].data_queued, 0, + "Tx AC0 data queued"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_mgmt_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[5], 0, + "Tx MGMT data queue full"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_hcca_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[4], 0, + "Tx HCCA data queue full"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_ac3_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[3], 0, + "Tx AC3 data queue full"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_ac2_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[2], 0, + "Tx AC2 data queue full"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_ac1_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[1], 0, + "Tx AC1 data queue full"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_ac0_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[0], 0, + "Tx AC0 data queue full"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_watchdog_timeouts", CTLFLAG_RD, &sc->tx_watchdog_timeouts, 0, + "Tx watchdog timeouts"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_defrag_packets", CTLFLAG_RD, &sc->tx_defrag_packets, 0, + "Tx defragmented packets"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "no_tx_desc_avail", CTLFLAG_RD, &sc->no_tx_desc_avail, 0, + "no Tx descriptors available"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "rx_mbuf_alloc_errors", CTLFLAG_RD, &sc->rx_mbuf_alloc_errors, 0, + "Rx mbuf allocation errors"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "rx_mbuf_dmamap_errors", CTLFLAG_RD, &sc->rx_mbuf_dmamap_errors, 0, + "Rx mbuf DMA mapping errors"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_queue_0_not_empty", CTLFLAG_RD, &sc->tx_queue_not_empty[0], 0, + "Tx queue 0 not empty"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_queue_1_not_empty", CTLFLAG_RD, &sc->tx_queue_not_empty[1], 0, + "Tx queue 1 not empty"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_beacons", CTLFLAG_RD, &sc->tx_beacons, 0, + "Tx beacons"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_noretryok", CTLFLAG_RD, &sc->tx_noretryok, 0, + "Tx successfull without retries"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_retryok", CTLFLAG_RD, &sc->tx_retryok, 0, + "Tx successfull with retries"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_failed", CTLFLAG_RD, &sc->tx_failed, 0, + "Tx failed"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_underflows", CTLFLAG_RD, &sc->tx_underflows, 0, + "Tx underflows"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_zerolen", CTLFLAG_RD, &sc->tx_zerolen, 0, + "Tx zero length"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_nonagg", CTLFLAG_RD, &sc->tx_nonagg, 0, + "Tx non-aggregated"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_agg", CTLFLAG_RD, &sc->tx_agg, 0, + "Tx aggregated"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_ampdu", CTLFLAG_RD, &sc->tx_ampdu, 0, + "Tx A-MPDU"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_mpdu_zero_density", CTLFLAG_RD, &sc->tx_mpdu_zero_density, 0, + "Tx MPDU with zero density"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "tx_ampdu_sessions", CTLFLAG_RD, &sc->tx_ampdu_sessions, 0, + "Tx A-MPDU sessions"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "rx_packets", CTLFLAG_RD, &sc->rx_packets, 0, + "Rx packets"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "rx_ampdu", CTLFLAG_RD, &sc->rx_ampdu, 0, + "Rx A-MPDU"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "rx_ampdu_retries", CTLFLAG_RD, &sc->rx_ampdu_retries, 0, + "Rx A-MPDU retries"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "rx_mpdu_zero_density", CTLFLAG_RD, &sc->rx_mpdu_zero_density, 0, + "Rx MPDU with zero density"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "rx_ampdu_sessions", CTLFLAG_RD, &sc->rx_ampdu_sessions, 0, + "Rx A-MPDU sessions"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "rx_amsdu", CTLFLAG_RD, &sc->rx_amsdu, 0, + "Rx A-MSDU"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "rx_crc_errors", CTLFLAG_RD, &sc->rx_crc_errors, 0, + "Rx CRC errors"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "rx_phy_errors", CTLFLAG_RD, &sc->rx_phy_errors, 0, + "Rx PHY errors"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "rx_false_ccas", CTLFLAG_RD, &sc->rx_false_ccas, 0, + "Rx false CCAs"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "rx_plcp_errors", CTLFLAG_RD, &sc->rx_plcp_errors, 0, + "Rx PLCP errors"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "rx_dup_packets", CTLFLAG_RD, &sc->rx_dup_packets, 0, + "Rx duplicate packets"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "rx_fifo_overflows", CTLFLAG_RD, &sc->rx_fifo_overflows, 0, + "Rx FIFO overflows"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "rx_cipher_no_errors", CTLFLAG_RD, &sc->rx_cipher_no_errors, 0, + "Rx cipher no errors"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "rx_cipher_icv_errors", CTLFLAG_RD, &sc->rx_cipher_icv_errors, 0, + "Rx cipher ICV errors"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "rx_cipher_mic_errors", CTLFLAG_RD, &sc->rx_cipher_mic_errors, 0, + "Rx cipher MIC errors"); + + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, + "rx_cipher_invalid_key_errors", CTLFLAG_RD, &sc->rx_cipher_invalid_key_errors, 0, + "Rx cipher invalid key errors"); +} + + +static void +rt2860_parent(struct ieee80211com *ic) +{ + struct rt2860_softc *sc = ic->ic_softc; + int startall = 0; + + RT2860_SOFTC_LOCK(sc); + if (ic->ic_nrunning> 0) { + if (!(sc->sc_flags & RT2860_RUNNING)) { + rt2860_init_locked(sc); + startall = 1; + } else + rt2860_update_promisc(ic); + } else if (sc->sc_flags & RT2860_RUNNING) + rt2860_stop_locked(sc); + RT2860_SOFTC_UNLOCK(sc); + if (startall) + ieee80211_start_all(ic); +} + +static int +rt2860_transmit(struct ieee80211com *ic, struct mbuf *m) +{ + struct rt2860_softc *sc = ic->ic_softc; + int error; + + RT2860_SOFTC_LOCK(sc); + if ((sc->sc_flags & RT2860_RUNNING) == 0) { + RT2860_SOFTC_UNLOCK(sc); + return (ENXIO); + } + error = mbufq_enqueue(&sc->sc_snd, m); + if (error) { + RT2860_SOFTC_UNLOCK(sc); + return (error); + } + rt2860_start(sc); + RT2860_SOFTC_UNLOCK(sc); + + return (0); +} + Index: sys/dev/rt2860/rt2860_amrr.h =================================================================== --- /dev/null +++ sys/dev/rt2860/rt2860_amrr.h @@ -0,0 +1,80 @@ + +/*- + * Copyright (c) 2009-2010 Alexander Egorenkov + * Copyright (c) 2009 Damien Bergamini + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RT2860_AMRR_H_ +#define _RT2860_AMRR_H_ + +#define RT2860_AMRR_MIN_SUCCESS_THRESHOLD 1 +#define RT2860_AMRR_MAX_SUCCESS_THRESHOLD 15 + +struct rt2860_amrr +{ + int ntxpath; + + unsigned int min_success_threshold; + unsigned int max_success_threshold; + + int interval; +}; + +struct rt2860_amrr_node +{ + struct rt2860_amrr *amrr; + + int rate_index; + + int ticks; + + unsigned int txcnt; + unsigned int success; + unsigned int success_threshold; + unsigned int recovery; + unsigned int retrycnt; +}; + +void rt2860_amrr_init(struct rt2860_amrr *amrr, struct ieee80211vap *vap, + int ntxpath, int min_success_threshold, int max_success_threshold, int msecs); + +void rt2860_amrr_cleanup(struct rt2860_amrr *amrr); + +void rt2860_amrr_node_init(struct rt2860_amrr *amrr, + struct rt2860_amrr_node *amrr_node, struct ieee80211_node *ni); + +int rt2860_amrr_choose(struct ieee80211_node *ni, + struct rt2860_amrr_node *amrr_node); + +static __inline void rt2860_amrr_tx_complete(struct rt2860_amrr_node *amrr_node, + int ok, int retries) +{ + amrr_node->txcnt++; + + if (ok) + amrr_node->success++; + + amrr_node->retrycnt += retries; +} + +static __inline void rt2860_amrr_tx_update(struct rt2860_amrr_node *amrr_node, + int txcnt, int success, int retrycnt) +{ + amrr_node->txcnt = txcnt; + amrr_node->success = success; + amrr_node->retrycnt = retrycnt; +} + +#endif /* #ifndef _RT2860_AMRR_H_ */ Index: sys/dev/rt2860/rt2860_amrr.c =================================================================== --- /dev/null +++ sys/dev/rt2860/rt2860_amrr.c @@ -0,0 +1,224 @@ + +/*- + * Copyright (c) 2009-2010 Alexander Egorenkov + * Copyright (c) 2009 Damien Bergamini + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + + +#include + +#include + +/* + * Defines and macros + */ + +#define RT2860_AMRR_IS_SUCCESS(amrr_node) ((amrr_node)->retrycnt < (amrr_node)->txcnt / 10) + +#define RT2860_AMRR_IS_FAILURE(amrr_node) ((amrr_node)->retrycnt > (amrr_node)->txcnt / 3) + +#define RT2860_AMRR_IS_ENOUGH(amrr_node) ((amrr_node)->txcnt > 10) + +/* + * Static function prototypes + */ + +static int rt2860_amrr_update(struct rt2860_amrr *amrr, + struct rt2860_amrr_node *amrr_node, struct ieee80211_node *ni); + +/* + * rt2860_amrr_init + */ +void rt2860_amrr_init(struct rt2860_amrr *amrr, struct ieee80211vap *vap, + int ntxpath, int min_success_threshold, int max_success_threshold, int msecs) +{ + int t; + + amrr->ntxpath = ntxpath; + + amrr->min_success_threshold = min_success_threshold; + amrr->max_success_threshold = max_success_threshold; + + if (msecs < 100) + msecs = 100; + + t = msecs_to_ticks(msecs); + + amrr->interval = (t < 1) ? 1 : t; +} + +/* + * rt2860_amrr_cleanup + */ +void rt2860_amrr_cleanup(struct rt2860_amrr *amrr) +{ +} + +/* + * rt2860_amrr_node_init + */ +void rt2860_amrr_node_init(struct rt2860_amrr *amrr, + struct rt2860_amrr_node *amrr_node, struct ieee80211_node *ni) +{ + const struct ieee80211_rateset *rs; + + amrr_node->amrr = amrr; + amrr_node->success = 0; + amrr_node->recovery = 0; + amrr_node->txcnt = 0; + amrr_node->retrycnt = 0; + amrr_node->success_threshold = amrr->min_success_threshold; + + if (ni->ni_flags & IEEE80211_NODE_HT) + { + rs = (const struct ieee80211_rateset *) &ni->ni_htrates; + + for (amrr_node->rate_index = rs->rs_nrates - 1; + amrr_node->rate_index > 0 && (rs->rs_rates[amrr_node->rate_index] & IEEE80211_RATE_VAL) > 4; + amrr_node->rate_index--) ; + + ni->ni_txrate = rs->rs_rates[amrr_node->rate_index] | IEEE80211_RATE_MCS; + } + else + { + rs = &ni->ni_rates; + + for (amrr_node->rate_index = rs->rs_nrates - 1; + amrr_node->rate_index > 0 && (rs->rs_rates[amrr_node->rate_index] & IEEE80211_RATE_VAL) > 72; + amrr_node->rate_index--) ; + + ni->ni_txrate = rs->rs_rates[amrr_node->rate_index] & IEEE80211_RATE_VAL; + } + + amrr_node->ticks = ticks; +} + +/* + * rt2860_amrr_choose + */ +int rt2860_amrr_choose(struct ieee80211_node *ni, + struct rt2860_amrr_node *amrr_node) +{ + struct rt2860_amrr *amrr; + int rate_index; + + amrr = amrr_node->amrr; + + if (RT2860_AMRR_IS_ENOUGH(amrr_node) && + (ticks - amrr_node->ticks) > amrr->interval) + { + rate_index = rt2860_amrr_update(amrr, amrr_node, ni); + if (rate_index != amrr_node->rate_index) + { + if (ni->ni_flags & IEEE80211_NODE_HT) + ni->ni_txrate = ni->ni_htrates.rs_rates[rate_index] | IEEE80211_RATE_MCS; + else + ni->ni_txrate = ni->ni_rates.rs_rates[rate_index] & IEEE80211_RATE_VAL; + + amrr_node->rate_index = rate_index; + } + + amrr_node->ticks = ticks; + } + else + { + rate_index = amrr_node->rate_index; + } + + return rate_index; +} + +/* + * rt2860_amrr_update + */ +static int rt2860_amrr_update(struct rt2860_amrr *amrr, + struct rt2860_amrr_node *amrr_node, struct ieee80211_node *ni) +{ + const struct ieee80211_rateset *rs; + int rate_index; + + KASSERT(RT2860_AMRR_IS_ENOUGH(amrr_node), + ("not enough Tx count: txcnt=%d", + amrr_node->txcnt)); + + if (ni->ni_flags & IEEE80211_NODE_HT) + rs = (const struct ieee80211_rateset *) &ni->ni_htrates; + else + rs = &ni->ni_rates; + + rate_index = amrr_node->rate_index; + + if (RT2860_AMRR_IS_SUCCESS(amrr_node)) + { + amrr_node->success++; + if ((amrr_node->success >= amrr_node->success_threshold) && + (rate_index + 1 < rs->rs_nrates) && + (!(ni->ni_flags & IEEE80211_NODE_HT) || (rs->rs_rates[rate_index + 1] & IEEE80211_RATE_VAL) < (amrr->ntxpath * 8))) + { + amrr_node->recovery = 1; + amrr_node->success = 0; + + rate_index++; + } + else + { + amrr_node->recovery = 0; + } + } + else if (RT2860_AMRR_IS_FAILURE(amrr_node)) + { + amrr_node->success = 0; + + if (rate_index > 0) + { + if (amrr_node->recovery) + { + amrr_node->success_threshold *= 2; + if (amrr_node->success_threshold > amrr->max_success_threshold) + amrr_node->success_threshold = amrr->max_success_threshold; + } + else + { + amrr_node->success_threshold = amrr->min_success_threshold; + } + + rate_index--; + } + + amrr_node->recovery = 0; + } + + amrr_node->txcnt = 0; + amrr_node->retrycnt = 0; + + return rate_index; +} Index: sys/dev/rt2860/rt2860_debug.h =================================================================== --- /dev/null +++ sys/dev/rt2860/rt2860_debug.h @@ -0,0 +1,55 @@ + +/*- + * Copyright (c) 2009-2010 Alexander Egorenkov + * Copyright (c) 2009 Damien Bergamini + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RT2860_DEBUG_H_ +#define _RT2860_DEBUG_H_ + +#ifdef RT2860_DEBUG + +enum +{ + RT2860_DEBUG_EEPROM = 0x00000001, + RT2860_DEBUG_RX = 0x00000002, + RT2860_DEBUG_TX = 0x00000004, + RT2860_DEBUG_INTR = 0x00000008, + RT2860_DEBUG_STATE = 0x00000010, + RT2860_DEBUG_CHAN = 0x00000020, + RT2860_DEBUG_NODE = 0x00000040, + RT2860_DEBUG_KEY = 0x00000080, + RT2860_DEBUG_PROT = 0x00000100, + RT2860_DEBUG_WME = 0x00000200, + RT2860_DEBUG_BEACON = 0x00000400, + RT2860_DEBUG_BA = 0x00000800, + RT2860_DEBUG_STATS = 0x00001000, + RT2860_DEBUG_RATE = 0x00002000, + RT2860_DEBUG_PERIODIC = 0x00004000, + RT2860_DEBUG_WATCHDOG = 0x00008000, + RT2860_DEBUG_RX_CRYPT = 0x00010000, + RT2860_DEBUG_TX_CRYPT = 0x00020000, + RT2860_DEBUG_ANY = 0xffffffff +}; + +#define RT2860_DPRINTF(sc, m, fmt, ...) do { if ((sc)->debug & (m)) printf(fmt, __VA_ARGS__); } while (0) + +#else + +#define RT2860_DPRINTF(sc, m, fmt, ...) + +#endif /* #ifdef RT2860_DEBUG */ + +#endif /* #ifndef _RT2860_DEBUG_H_ */ Index: sys/dev/rt2860/rt2860_eeprom.h =================================================================== --- /dev/null +++ sys/dev/rt2860/rt2860_eeprom.h @@ -0,0 +1,91 @@ + +/*- + * Copyright (c) 2009-2010 Alexander Egorenkov + * Copyright (c) 2009 Damien Bergamini + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RT2860_EEPROM_H_ +#define _RT2860_EEPROM_H_ + +#define RT2860_EEPROM_VERSION 0x0002 +#define RT2860_EEPROM_ADDRESS01 0x0004 +#define RT2860_EEPROM_ADDRESS23 0x0006 +#define RT2860_EEPROM_ADDRESS45 0x0008 +#define RT2860_EEPROM_POWERSAVE_LEVEL 0x0022 +#define RT2860_EEPROM_ANTENNA 0x0034 +#define RT2860_EEPROM_NIC_CONFIG 0x0036 +#define RT2860_EEPROM_COUNTRY 0x0038 +#define RT2860_EEPROM_RF_FREQ_OFF 0x003a +#define RT2860_EEPROM_LED1_OFF 0x003c +#define RT2860_EEPROM_LED2_OFF 0x003e +#define RT2860_EEPROM_LED3_OFF 0x0040 +#define RT2860_EEPROM_LNA_GAIN 0x0044 +#define RT2860_EEPROM_RSSI_OFF_2GHZ_BASE 0x0046 +#define RT2860_EEPROM_RSSI2_OFF_2GHZ_BASE 0x0048 +#define RT2860_EEPROM_RSSI_OFF_5GHZ_BASE 0x004a +#define RT2860_EEPROM_RSSI2_OFF_5GHZ_BASE 0x004c +#define RT2860_EEPROM_TXPOW_RATE_DELTA 0x0050 +#define RT2860_EEPROM_TXPOW1_2GHZ_BASE 0x0052 +#define RT2860_EEPROM_TXPOW2_2GHZ_BASE 0x0060 +#define RT2860_EEPROM_TSSI_2GHZ_BASE 0x006e +#define RT2860_EEPROM_TXPOW1_5GHZ_BASE 0x0078 +#define RT2860_EEPROM_TXPOW2_5GHZ_BASE 0x00a6 +#define RT2860_EEPROM_TSSI_5GHZ_BASE 0x00d4 +#define RT2860_EEPROM_TXPOW_RATE_BASE 0x00de +#define RT2860_EEPROM_BBP_BASE 0x00f0 +#define RT3071_EEPROM_RF_BASE 0x0082 + +#define RT2860_EEPROM_RF_2820 1 /* 2.4GHz 2T3R */ +#define RT2860_EEPROM_RF_2850 2 /* 2.4/5GHz 2T3R */ +#define RT2860_EEPROM_RF_2720 3 /* 2.4GHz 1T2R */ +#define RT2860_EEPROM_RF_2750 4 /* 2.4G/5GHz 1T2R */ +#define RT2860_EEPROM_RF_3020 5 /* 2.4G 1T1R */ +#define RT2860_EEPROM_RF_2020 6 /* 2.4G B/G */ +#define RT2860_EEPROM_RF_3021 7 /* 2.4G 1T2R */ +#define RT2860_EEPROM_RF_3022 8 /* 2.4G 2T2R */ +#define RT2860_EEPROM_RF_3052 9 /* 2.4G/5G 2T2R */ +#define RT2860_EEPROM_RF_2853 10 /* 2.4G.5G 3T3R */ +#define RT2860_EEPROM_RF_3320 11 /* 2.4G 1T1R with PA (RT3350/RT3370/RT3390) */ +#define RT2860_EEPROM_RF_3322 12 /* 2.4G 2T2R with PA (RT3352/RT3371/RT3372/RT3391/RT3392) */ +#define RT2860_EEPROM_RF_3053 13 /* 2.4G/5G 3T3R (RT3883/RT3563/RT3573/RT3593/RT3662) */ +#define RT2860_EEPROM_RF_3853 13 /* 2.4G/5G 3T3R (RT3883/RT3563/RT3573/RT3593/RT3662) */ + +/* + * RT2860_EEPROM_NIC_CONFIG flags + */ +#define RT2860_EEPROM_EXT_LNA_5GHZ (1 << 3) +#define RT2860_EEPROM_EXT_LNA_2GHZ (1 << 2) +#define RT2860_EEPROM_TX_AGC_CNTL (1 << 1) +#define RT2860_EEPROM_HW_RADIO_CNTL (1 << 0) + +#define RT2860_EEPROM_LED_POLARITY (1 << 7) +#define RT2860_EEPROM_LED_MODE_MASK 0x7f + +#define RT2860_EEPROM_LED_CNTL_DEFAULT 0x01 +#define RT2860_EEPROM_LED1_OFF_DEFAULT 0x5555 +#define RT2860_EEPROM_LED2_OFF_DEFAULT 0x2221 +#define RT2860_EEPROM_LED3_OFF_DEFAULT 0xa9f8 + +#define RT2860_EEPROM_RSSI_OFF_MIN -10 +#define RT2860_EEPROM_RSSI_OFF_MAX 10 + +#define RT2860_EEPROM_TXPOW_2GHZ_MIN 0 +#define RT2860_EEPROM_TXPOW_2GHZ_MAX 31 +#define RT2860_EEPROM_TXPOW_2GHZ_DEFAULT 5 +#define RT2860_EEPROM_TXPOW_5GHZ_MIN -7 +#define RT2860_EEPROM_TXPOW_5GHZ_MAX 15 +#define RT2860_EEPROM_TXPOW_5GHZ_DEFAULT 5 + +#endif /* #ifndef _RT2860_EEPROM_H_ */ Index: sys/dev/rt2860/rt2860_fdt.c =================================================================== --- /dev/null +++ sys/dev/rt2860/rt2860_fdt.c @@ -0,0 +1,114 @@ + +/*- + * Copyright (c) 2018 Hiroki Mori + * Copyright (c) 2009-2010 Alexander Egorenkov + * Copyright (c) 2009 Damien Bergamini + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +static const struct ofw_compat_data rt_compat_data[] = { + { "ralink,rt3050-wmac", RT_CHIPID_RT3050 }, + { "ralink,rt3052-wmac", RT_CHIPID_RT3052 }, + { NULL, 0 } +}; + +/* + * Static function prototypes + */ + +static int rt2860_fdt_probe(device_t dev); + +static int rt2860_fdt_attach(device_t dev); + +int rt2860_attach(device_t dev, int id); + +int rt2860_detach(device_t dev); + +int rt2860_shutdown(device_t dev); + +int rt2860_suspend(device_t dev); + +int rt2860_resume(device_t dev); + +/* + * rt2860_fdt_probe + */ +static int rt2860_fdt_probe(device_t dev) +{ + const struct ofw_compat_data * cd; + + + cd = ofw_bus_search_compatible(dev, rt_compat_data); + if (cd->ocd_data == 0) + return (ENXIO); + + device_set_desc(dev, "Ralink RT2860 802.11n MAC/BPP"); + return 0; +} + +/* + * rt2860_fdt_attach + */ +static int rt2860_fdt_attach(device_t dev) +{ + struct rt2860_softc *sc; + const struct ofw_compat_data * cd; + + sc = device_get_softc(dev); + sc->mem_rid = 0; + + cd = ofw_bus_search_compatible(dev, rt_compat_data); + + return (rt2860_attach(dev, cd->ocd_data)); +} + +static device_method_t rt2860_fdt_dev_methods[] = +{ + DEVMETHOD(device_probe, rt2860_fdt_probe), + DEVMETHOD(device_attach, rt2860_fdt_attach), + DEVMETHOD(device_detach, rt2860_detach), + DEVMETHOD(device_shutdown, rt2860_shutdown), + DEVMETHOD(device_suspend, rt2860_suspend), + DEVMETHOD(device_resume, rt2860_resume), + { 0, 0 } +}; + +static driver_t rt2860_fdt_driver = +{ + "rt2860", + rt2860_fdt_dev_methods, + sizeof(struct rt2860_softc) +}; + +static devclass_t rt2860_fdt_dev_class; + +DRIVER_MODULE(rt2860, simplebus, rt2860_fdt_driver, rt2860_fdt_dev_class, 0, 0); +MODULE_DEPEND(rt2860, wlan, 1, 1, 1); + Index: sys/dev/rt2860/rt2860_io.h =================================================================== --- /dev/null +++ sys/dev/rt2860/rt2860_io.h @@ -0,0 +1,73 @@ + +/*- + * Copyright (c) 2009-2010 Alexander Egorenkov + * Copyright (c) 2009 Damien Bergamini + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RT2860_IO_H_ +#define _RT2860_IO_H_ + +#include + +#define RT2860_IO_MCU_CMD_SLEEP 0x30 +#define RT2860_IO_MCU_CMD_WAKEUP 0x31 +#define RT2860_IO_MCU_CMD_RADIOOFF 0x35 +#define RT2860_IO_MCU_CMD_LEDS 0x50 +#define RT2860_IO_MCU_CMD_LED_BRIGHTNESS 0x51 +#define RT2860_IO_MCU_CMD_LED1 0x52 +#define RT2860_IO_MCU_CMD_LED2 0x53 +#define RT2860_IO_MCU_CMD_LED3 0x54 +#define RT2860_IO_MCU_CMD_BOOT 0x72 +#define RT2860_IO_MCU_CMD_BBP 0x80 +#define RT2860_IO_MCU_CMD_POWERSAVE_LEVEL 0x83 + +void rt2860_io_rf_load_defaults(struct rt2860_softc *sc); +uint32_t rt2860_io_mac_read(struct rt2860_softc *sc, uint16_t reg); + +void rt2860_io_mac_read_multi(struct rt2860_softc *sc, + uint16_t reg, void *buf, size_t len); + +void rt2860_io_mac_write(struct rt2860_softc *sc, + uint16_t reg, uint32_t val); + +void rt2860_io_mac_write_multi(struct rt2860_softc *sc, + uint16_t reg, const void *buf, size_t len); + +void rt2860_io_mac_set_region_4(struct rt2860_softc *sc, + uint16_t reg, uint32_t val, size_t len); + +uint16_t rt2860_io_eeprom_read(struct rt2860_softc *sc, uint16_t addr); + +void rt2860_io_eeprom_read_multi(struct rt2860_softc *sc, + uint16_t addr, void *buf, size_t len); + +uint8_t rt2860_io_bbp_read(struct rt2860_softc *sc, uint8_t reg); + +void rt2860_io_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val); + +void rt2860_io_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val); + +int32_t rt2860_io_rf_read(struct rt2860_softc *sc, uint8_t reg); + +void rt2860_io_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, + uint8_t token, uint16_t arg); + +int rt2860_io_mcu_cmd_check(struct rt2860_softc *sc, uint8_t cid); + +int rt2860_io_mcu_load_ucode(struct rt2860_softc *sc, + const uint8_t *ucode, size_t len); + + +#endif /* #ifndef _RT2860_IO_H_ */ Index: sys/dev/rt2860/rt2860_io.c =================================================================== --- /dev/null +++ sys/dev/rt2860/rt2860_io.c @@ -0,0 +1,931 @@ + +/*- + * Copyright (c) 2009-2010 Alexander Egorenkov + * Copyright (c) 2009 Damien Bergamini + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include +#include + +/* + * Defines and macros + */ + +/* + * RT2860_IO_EEPROM_RAISE_CLK + */ +#define RT2860_IO_EEPROM_RAISE_CLK(sc, val) \ +do \ +{ \ + (val) |= RT2860_REG_EESK; \ + \ + rt2860_io_mac_write((sc), RT2860_REG_EEPROM_CSR, (val)); \ + \ + DELAY(1); \ +} while (0) + +/* + * RT2860_IO_EEPROM_LOWER_CLK + */ +#define RT2860_IO_EEPROM_LOWER_CLK(sc, val) \ +do \ +{ \ + (val) &= ~RT2860_REG_EESK; \ + \ + rt2860_io_mac_write((sc), RT2860_REG_EEPROM_CSR, (val)); \ + \ + DELAY(1); \ +} while (0) + +#define RT2860_IO_BYTE_CRC16(byte, crc) \ + ((uint16_t) (((crc) << 8) ^ rt2860_io_ccitt16[(((crc) >> 8) ^ (byte)) & 255])) + +/* + * Static function prototypes + */ + +static void rt2860_io_eeprom_shiftout_bits(struct rt2860_softc *sc, + uint16_t val, uint16_t count); + +static uint16_t rt2860_io_eeprom_shiftin_bits(struct rt2860_softc *sc); + +static uint8_t rt2860_io_byte_rev(uint8_t byte); + +/* Default EEPROM value for RT3050 */ +static const uint8_t rt3050_eeprom[] = { + 0x50, 0x30, 0x01, 0x01, 0x00, 0x0c, 0x43, 0x30, 0x52, 0x88, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x0c, + 0x43, 0x30, 0x52, 0x77, 0x00, 0x0c, 0x43, 0x30, 0x52, 0x66, 0x11, 0x05, 0x20, 0x00, + 0xff, 0xff, 0x2f, 0x01, 0x55, 0x77, 0xa8, 0xaa, 0x8c, 0x88, 0xff, 0xff, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0x0d, 0x0d, + 0x0d, 0x0d, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x10, 0x10, + 0x11, 0x11, 0x11, 0x12, 0x12, 0x12, 0x13, 0x13, 0x13, 0x14, 0x14, 0x14, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x66, 0x66, + 0xcc, 0xaa, 0x88, 0x66, 0xcc, 0xaa, 0x88, 0x66, 0xcc, 0xaa, 0x88, 0x66, 0xcc, 0xaa, + 0x88, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF + }; + +/* Default EEPROM value for RT3052 */ +static const uint8_t rt3052_eeprom[] = { + 0x50, 0x30, 0x01, 0x01, 0x00, 0x0c, 0x43, 0x30, 0x52, 0x88, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x0c, + 0x43, 0x30, 0x52, 0x77, 0x00, 0x0c, 0x43, 0x30, 0x52, 0x66, 0x11, 0x05, 0x20, 0x00, + 0xff, 0xff, 0x2f, 0x01, 0x55, 0x77, 0xa8, 0xaa, 0x8c, 0x88, 0xff, 0xff, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0x0d, 0x0d, + 0x0d, 0x0d, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x10, 0x10, + 0x11, 0x11, 0x11, 0x12, 0x12, 0x12, 0x13, 0x13, 0x13, 0x14, 0x14, 0x14, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x66, 0x66, + 0xcc, 0xaa, 0x88, 0x66, 0xcc, 0xaa, 0x88, 0x66, 0xcc, 0xaa, 0x88, 0x66, 0xcc, 0xaa, + 0x88, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF + }; + +#if 0 +/* #ifdef RT305X_SOC */ +static const uint16_t rt3052_eeprom[] = +{ + 0x3052, 0x0101, 0x0c00, 0x3043, 0x8852, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0x0c00, 0x3043, 0x7752, 0x0c00, + 0x3043, 0x6652, 0x0822, 0x0024, 0xffff, 0x012f, 0x7755, 0xaaa8, + 0x888c, 0xffff, 0x000c, 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, + 0xffff, 0x0d0d, 0x0d0d, 0x0c0c, 0x0c0c, 0x0c0c, 0x0c0c, 0x0c0c, + 0x1010, 0x1111, 0x1211, 0x1212, 0x1313, 0x1413, 0x1414, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x6666, + 0xaacc, 0x6688, 0xaacc, 0x6688, 0xaacc, 0x6688, 0xaacc, 0x6688, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, +}; +#endif + +uint8_t rt3052_rf_default[] = { + 0x50, /* 0 */ + 0x01, + 0xF7, + 0x75, + 0x40, + 0x03, + 0x42, + 0x50, + 0x39, + 0x0F, + 0x60, /* 10 */ + 0x21, + 0x75, + 0x75, + 0x90, + 0x58, + 0xB3, + 0x92, + 0x2C, + 0x02, + 0xBA, /* 20 */ + 0xDB, + 0x00, + 0x31, + 0x08, + 0x01, + 0x25, /* Core Power: 0x25=1.25V */ + 0x23, /* RF: 1.35V */ + 0x13, /* ADC: must consist with R27 */ + 0x83, + 0x00, /* 30 */ + 0x00, +}; +/* #endif */ + + +/* + * Static variables + */ + +static const uint16_t rt2860_io_ccitt16[] = +{ + 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, + 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, + 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, + 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, + 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485, + 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, + 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4, + 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, + 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823, + 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, + 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12, + 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, + 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41, + 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49, + 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70, + 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, + 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f, + 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, + 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, + 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256, + 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, + 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, + 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c, + 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, + 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, + 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3, + 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, + 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92, + 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, + 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1, + 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, + 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0 +}; + +/* + * rt2860_io_mac_read + */ +uint32_t rt2860_io_mac_read(struct rt2860_softc *sc, uint16_t reg) +{ + + return bus_space_read_4(sc->bst, sc->bsh, reg); +} + +/* + * rt2860_io_mac_read_multi + */ +void rt2860_io_mac_read_multi(struct rt2860_softc *sc, + uint16_t reg, void *buf, size_t len) +{ + + bus_space_read_region_1(sc->bst, sc->bsh, reg, buf, len); +} + +/* + * rt2860_io_mac_write + */ +void rt2860_io_mac_write(struct rt2860_softc *sc, + uint16_t reg, uint32_t val) +{ + + bus_space_write_4(sc->bst, sc->bsh, reg, val); +} + +/* + * rt2860_io_mac_write_multi + */ +void rt2860_io_mac_write_multi(struct rt2860_softc *sc, + uint16_t reg, const void *buf, size_t len) +{ + int i; + const uint8_t *p; + + p = buf; + for (i = 0; i < len; i ++) + bus_space_write_1(sc->bst, sc->bsh, reg + i, *(p+i)); + +#ifdef notyet + bus_space_write_region_1(sc->bst, sc->bsh, reg, buf, len); +#endif +} + +/* + * rt2860_io_mac_set_region_4 + */ +void rt2860_io_mac_set_region_4(struct rt2860_softc *sc, + uint16_t reg, uint32_t val, size_t len) +{ + int i; + + for (i = 0; i < len; i += sizeof(uint32_t)) + rt2860_io_mac_write(sc, reg + i, val); +} + +/* Read 16-bit from eFUSE ROM (>=RT3071 only.) */ +static uint16_t +rt3090_efuse_read_2(struct rt2860_softc *sc, uint16_t addr) +{ + uint32_t tmp; + uint16_t reg; + int ntries; + + addr *= 2; + /*- + * Read one 16-byte block into registers EFUSE_DATA[0-3]: + * DATA0: F E D C + * DATA1: B A 9 8 + * DATA2: 7 6 5 4 + * DATA3: 3 2 1 0 + */ + tmp = rt2860_io_mac_read(sc, RT3070_EFUSE_CTRL); + tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); + tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; + rt2860_io_mac_write(sc, RT3070_EFUSE_CTRL, tmp); + for (ntries = 0; ntries < 500; ntries++) { + tmp = rt2860_io_mac_read(sc, RT3070_EFUSE_CTRL); + if (!(tmp & RT3070_EFSROM_KICK)) + break; + DELAY(2); + } + if (ntries == 500) + return 0xffff; + + if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) + return 0xffff; /* address not found */ + + /* determine to which 32-bit register our 16-bit word belongs */ + reg = RT3070_EFUSE_DATA3 - (addr & 0xc); + tmp = rt2860_io_mac_read(sc, reg); + + return (addr & 2) ? tmp >> 16 : tmp & 0xffff; +} + + +/* + * rt2860_io_eeprom_read + */ +uint16_t rt2860_io_eeprom_read(struct rt2860_softc *sc, uint16_t addr) +{ + uint32_t tmp; + uint16_t val; + + addr = (addr >> 1); + + if (sc->mac_rev == 0x28720200) { + if (sc->pid == RT_CHIPID_RT3050) + return (rt3050_eeprom[addr*2] + + rt3050_eeprom[addr*2+1] * 0x100); + else /* RT_CHIPID_RT3052 */ + return (rt3052_eeprom[addr*2] + + rt3052_eeprom[addr*2+1] * 0x100); + } else if ((sc->mac_rev & 0xffff0000) >= 0x30710000) { + tmp = rt2860_io_mac_read(sc, RT3070_EFUSE_CTRL); + if (tmp & RT3070_SEL_EFUSE) + return (rt3090_efuse_read_2(sc, addr)); + } + + tmp = rt2860_io_mac_read(sc, RT2860_REG_EEPROM_CSR); + + tmp &= ~(RT2860_REG_EEDI | RT2860_REG_EEDO | RT2860_REG_EESK); + tmp |= RT2860_REG_EECS; + + rt2860_io_mac_write(sc, RT2860_REG_EEPROM_CSR, tmp); + + if (((sc->mac_rev & 0xffff0000) != 0x30710000) && + ((sc->mac_rev & 0xffff0000) != 0x30900000) && + ((sc->mac_rev & 0xffff0000) != 0x35720000) && + ((sc->mac_rev & 0xffff0000) != 0x33900000)) + { + RT2860_IO_EEPROM_RAISE_CLK(sc, tmp); + RT2860_IO_EEPROM_LOWER_CLK(sc, tmp); + } + + rt2860_io_eeprom_shiftout_bits(sc, RT2860_REG_EEOP_READ, 3); + rt2860_io_eeprom_shiftout_bits(sc, addr, sc->eeprom_addr_num); + + val = rt2860_io_eeprom_shiftin_bits(sc); + + tmp = rt2860_io_mac_read(sc, RT2860_REG_EEPROM_CSR); + + tmp &= ~(RT2860_REG_EECS | RT2860_REG_EEDI); + + rt2860_io_mac_write(sc, RT2860_REG_EEPROM_CSR, tmp); + + RT2860_IO_EEPROM_RAISE_CLK(sc, tmp); + RT2860_IO_EEPROM_LOWER_CLK(sc, tmp); + + return val; +} + +/* + * rt2860_io_eeprom_read_multi + */ +void rt2860_io_eeprom_read_multi(struct rt2860_softc *sc, + uint16_t addr, void *buf, size_t len) +{ + uint16_t *ptr; + int i; + + len += len % sizeof(uint16_t); + ptr = buf; + + i = 0; + + do + { + *ptr++ = rt2860_io_eeprom_read(sc, addr + i); + + i += sizeof(uint16_t); + len -= sizeof(uint16_t); + } while (len > 0); +} + +/* + * rt2860_io_bbp_read + */ +uint8_t rt2860_io_bbp_read(struct rt2860_softc *sc, uint8_t reg) +{ + int ntries; + uint32_t tmp; + + if (sc->mac_rev == 0x28720200) + { + for (ntries = 0; ntries < 100; ntries ++) { + if ( !(rt2860_io_mac_read(sc, RT2860_REG_BBP_CSR_CFG) & + RT2860_REG_BBP_CSR_BUSY) ) + break; + DELAY(1); + } + if (ntries == 100) { + printf("%s:%s: BBP busy after 100 probes\n", + device_get_nameunit(sc->dev), __func__); + return (0); + } + rt2860_io_mac_write(sc, RT2860_REG_BBP_CSR_CFG, + RT2860_REG_BBP_CSR_READ | + RT2860_REG_BBP_CSR_KICK | RT2860_REG_BBP_RW_MODE_PARALLEL | + (reg & RT2860_REG_BBP_REG_MASK) << RT2860_REG_BBP_REG_SHIFT); + for (ntries = 0; ntries < 100; ntries ++) { + if ( !(rt2860_io_mac_read(sc, RT2860_REG_BBP_CSR_CFG) & + RT2860_REG_BBP_CSR_BUSY) ) + break; + DELAY(1); + } + if (ntries == 100) { + printf("%s:%s: BBP busy after 100 probes\n", + device_get_nameunit(sc->dev), __func__); + return (0); + } + else { + return + ((rt2860_io_mac_read(sc, RT2860_REG_BBP_CSR_CFG) >> + RT2860_REG_BBP_VAL_SHIFT) & + RT2860_REG_BBP_VAL_MASK); + } + return (0); + } + + for (ntries = 0; ntries < 100; ntries++) + { + if (!(rt2860_io_mac_read(sc, RT2860_REG_H2M_MAILBOX_BBP_AGENT) & + RT2860_REG_BBP_CSR_BUSY)) + break; + + DELAY(1); + } + + if (ntries == 100) + { + printf("%s: could not read from BBP through MCU: reg=0x%02x\n", + device_get_nameunit(sc->dev), reg); + return 0; + } + + tmp = RT2860_REG_BBP_RW_MODE_PARALLEL | + RT2860_REG_BBP_CSR_BUSY | + RT2860_REG_BBP_CSR_READ | + ((reg & RT2860_REG_BBP_REG_MASK) << RT2860_REG_BBP_REG_SHIFT); + + rt2860_io_mac_write(sc, RT2860_REG_H2M_MAILBOX_BBP_AGENT, tmp); + + rt2860_io_mcu_cmd(sc, RT2860_IO_MCU_CMD_BBP, + RT2860_REG_H2M_TOKEN_NO_INTR, 0); + + DELAY(1000); + + for (ntries = 0; ntries < 100; ntries++) + { + tmp = rt2860_io_mac_read(sc, RT2860_REG_H2M_MAILBOX_BBP_AGENT); + if (!(tmp & RT2860_REG_BBP_CSR_BUSY)) + return ((tmp >> RT2860_REG_BBP_VAL_SHIFT) & + RT2860_REG_BBP_VAL_MASK); + + DELAY(1); + } + + printf("%s: could not read from BBP through MCU: reg=0x%02x\n", + device_get_nameunit(sc->dev), reg); + + return 0; +} + +/* + * rt2860_io_bbp_write + */ +void rt2860_io_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) +{ + int ntries; + uint32_t tmp; + + if (sc->mac_rev == 0x28720200) + { + for (ntries = 0; ntries < 100; ntries ++) { + if ( !(rt2860_io_mac_read(sc, RT2860_REG_BBP_CSR_CFG) & + RT2860_REG_BBP_CSR_BUSY) ) + break; + DELAY(1); + } + if (ntries == 100) { + printf("%s:%s: BBP busy after 100 probes\n", + device_get_nameunit(sc->dev), __func__); + return; + } + rt2860_io_mac_write(sc, RT2860_REG_BBP_CSR_CFG, + RT2860_REG_BBP_CSR_KICK | RT2860_REG_BBP_RW_MODE_PARALLEL | + (reg & RT2860_REG_BBP_REG_MASK) << RT2860_REG_BBP_REG_SHIFT | + (val & RT2860_REG_BBP_VAL_MASK) << RT2860_REG_BBP_VAL_SHIFT ); + rt2860_io_bbp_read(sc, reg); + return; + } + + for (ntries = 0; ntries < 100; ntries++) + { + if (!(rt2860_io_mac_read(sc, RT2860_REG_H2M_MAILBOX_BBP_AGENT) & + RT2860_REG_BBP_CSR_BUSY)) + break; + + DELAY(1); + } + + if (ntries == 100) + { + printf("%s: could not write to BBP through MCU: reg=0x%02x\n", + device_get_nameunit(sc->dev), reg); + return; + } + + tmp = RT2860_REG_BBP_RW_MODE_PARALLEL | + RT2860_REG_BBP_CSR_BUSY | + ((reg & RT2860_REG_BBP_REG_MASK) << RT2860_REG_BBP_REG_SHIFT) | + ((val & RT2860_REG_BBP_VAL_MASK) << RT2860_REG_BBP_VAL_SHIFT); + + rt2860_io_mac_write(sc, RT2860_REG_H2M_MAILBOX_BBP_AGENT, tmp); + + rt2860_io_mcu_cmd(sc, RT2860_IO_MCU_CMD_BBP, + RT2860_REG_H2M_TOKEN_NO_INTR, 0); + + DELAY(1000); +} + +/* + * rt2860_io_rf_write + */ +void rt2860_io_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val) +{ + int ntries; + if (sc->mac_rev == 0x28720200) + { + for (ntries = 0; ntries < 100; ntries ++) { + if ( !(rt2860_io_mac_read(sc, RT2872_REG_RF_CSR_CFG) & + RT2872_REG_RF_CSR_BUSY) ) + break; + DELAY(1); + } + if (ntries == 100) { + printf("%s:%s: RF busy after 100 probes\n", + device_get_nameunit(sc->dev), __func__); + return; + } + rt2860_io_mac_write(sc, RT2872_REG_RF_CSR_CFG, + RT2872_REG_RF_CSR_KICK | RT2872_REG_RF_CSR_WRITE | + (reg & RT2872_REG_RF_ID_MASK) << RT2872_REG_RF_ID_SHIFT | + (val & RT2872_REG_RF_VAL_MASK) << RT2872_REG_RF_VAL_SHIFT ); + rt2860_io_rf_read(sc, reg); + return; + } + + + for (ntries = 0; ntries < 100; ntries++) + if (!(rt2860_io_mac_read(sc, RT2860_REG_RF_CSR_CFG0) & + RT2860_REG_RF_BUSY)) + break; + + if (ntries == 100) + { + printf("%s: could not write to RF: reg=0x%02x\n", + device_get_nameunit(sc->dev), reg); + return; + } + + rt2860_io_mac_write(sc, RT2860_REG_RF_CSR_CFG0, val); +} + +/* + * rt2860_io_rf_read + */ +int32_t rt2860_io_rf_read(struct rt2860_softc *sc, uint8_t reg) +{ + int ntries; + if (sc->mac_rev == 0x28720200) + { + for (ntries = 0; ntries < 100; ntries ++) { + if ( !(rt2860_io_mac_read(sc, RT2872_REG_RF_CSR_CFG) & + RT2872_REG_RF_CSR_BUSY) ) + break; + DELAY(1); + } + if (ntries == 100) { + printf("%s:%s: RF busy after 100 probes\n", + device_get_nameunit(sc->dev), __func__); + return (-1); + } + rt2860_io_mac_write(sc, RT2872_REG_RF_CSR_CFG, + RT2872_REG_RF_CSR_KICK | + (reg & RT2872_REG_RF_ID_MASK) << RT2872_REG_RF_ID_SHIFT ); + + for (ntries = 0; ntries < 100; ntries ++) { + if ( !(rt2860_io_mac_read(sc, RT2872_REG_RF_CSR_CFG) & + RT2872_REG_RF_CSR_BUSY) ) + break; + DELAY(1); + } + if (ntries == 100) { + printf("%s:%s: RF busy after 100 probes\n", + device_get_nameunit(sc->dev), __func__); + } + + return (rt2860_io_mac_read(sc, RT2872_REG_RF_CSR_CFG) & RT2872_REG_RF_VAL_MASK); + } + return (-1); +} + +/* + * rt2860_io_rf_load_defaults + */ +void rt2860_io_rf_load_defaults(struct rt2860_softc *sc) +{ + int i; + + if (sc->mac_rev == 0x28720200) { + for (i = 0; i < 32; i ++) + rt2860_io_rf_write(sc, i, rt3052_rf_default[i]); + } +} + +/* + * rt2860_io_mcu_cmd + */ +void rt2860_io_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, + uint8_t token, uint16_t arg) +{ + uint32_t tmp; + int ntries; + + if (sc->mac_rev == 0x28720200) + return; + + for (ntries = 0; ntries < 100; ntries++) + { + if (!(rt2860_io_mac_read(sc, RT2860_REG_H2M_MAILBOX) & + RT2860_REG_H2M_BUSY)) + break; + + DELAY(2); + } + + if (ntries == 100) + { + printf("%s: could not read H2M: cmd=0x%02x\n", + device_get_nameunit(sc->dev), cmd); + return; + } + + tmp = RT2860_REG_H2M_BUSY | (token << 16) | arg; + + rt2860_io_mac_write(sc, RT2860_REG_H2M_MAILBOX, tmp); + rt2860_io_mac_write(sc, RT2860_REG_H2M_HOST_CMD, cmd); +} + +/* + * rt2860_io_mcu_cmd_check + */ +int rt2860_io_mcu_cmd_check(struct rt2860_softc *sc, uint8_t cid) +{ + uint32_t tmp, mask, status; + int result, ntries; + + result = -1; + + for (ntries = 0; ntries < 200; ntries++) + { + tmp = rt2860_io_mac_read(sc, RT2860_REG_H2M_MAILBOX_CID); + + if (((cid >> RT2860_REG_H2M_CID0_SHIFT) & RT2860_REG_H2M_CID_MASK) == cid) + { + mask = (RT2860_REG_H2M_CID_MASK << RT2860_REG_H2M_CID0_SHIFT); + break; + } + else if (((tmp >> RT2860_REG_H2M_CID1_SHIFT) & RT2860_REG_H2M_CID_MASK) == cid) + { + mask = (RT2860_REG_H2M_CID_MASK << RT2860_REG_H2M_CID1_SHIFT); + break; + } + else if (((tmp >> RT2860_REG_H2M_CID2_SHIFT) & RT2860_REG_H2M_CID_MASK) == cid) + { + mask = (RT2860_REG_H2M_CID_MASK << RT2860_REG_H2M_CID2_SHIFT); + break; + } + else if (((tmp >> RT2860_REG_H2M_CID3_SHIFT) & RT2860_REG_H2M_CID_MASK) == cid) + { + mask = (RT2860_REG_H2M_CID_MASK << RT2860_REG_H2M_CID3_SHIFT); + break; + } + + DELAY(100); + } + + status = rt2860_io_mac_read(sc, RT2860_REG_H2M_MAILBOX_STATUS); + + if (ntries < 200) + { + status &= mask; + + if ((status == 0x1) || + (status == 0x100) || + (status == 0x10000) || + (status == 0x1000000)) + result = 0; + } + + rt2860_io_mac_write(sc, RT2860_REG_H2M_MAILBOX_STATUS, 0xffffffff); + rt2860_io_mac_write(sc, RT2860_REG_H2M_MAILBOX_CID, 0xffffffff); + + return result; +} + +/* + * rt2860_io_mcu_load_ucode + */ +int rt2860_io_mcu_load_ucode(struct rt2860_softc *sc, + const uint8_t *ucode, size_t len) +{ + int i, ntries; + uint16_t crc; + + for (i = 0, crc = 0xffff; i < len - 2; i++) + crc = RT2860_IO_BYTE_CRC16(rt2860_io_byte_rev(ucode[i]), crc); + + if (ucode[len - 2] != rt2860_io_byte_rev(crc >> 8) || + ucode[len - 1] != rt2860_io_byte_rev(crc)) + { + printf("%s: wrong microcode crc\n", + device_get_nameunit(sc->dev)); + return EINVAL; + } + + rt2860_io_mac_write(sc, RT2860_REG_PBF_SYS_CTRL, RT2860_REG_HST_PM_SEL); + + for(i = 0; i < len; i += 4) + { + rt2860_io_mac_write(sc, RT2860_REG_MCU_UCODE_BASE + i, + (ucode[i+3] << 24) | (ucode[i+2] << 16) | + (ucode[i+1] << 8) | ucode[i]); + } + + if (sc->mac_rev != 0x28720200) + rt2860_io_mac_write_multi(sc, RT2860_REG_MCU_UCODE_BASE, + ucode, len); + + rt2860_io_mac_write(sc, RT2860_REG_PBF_SYS_CTRL, 0); + + if (sc->mac_rev != 0x28720200) + rt2860_io_mac_write(sc, RT2860_REG_PBF_SYS_CTRL, + RT2860_REG_MCU_RESET); + + DELAY(10000); + + /* initialize BBP R/W access agent */ + + rt2860_io_mac_write(sc, RT2860_REG_H2M_MAILBOX_BBP_AGENT, 0); + rt2860_io_mac_write(sc, RT2860_REG_H2M_MAILBOX, 0); + + if (sc->mac_rev != 0x28720200) { + + for (ntries = 0; ntries < 1000; ntries++) + { + if (rt2860_io_mac_read(sc, RT2860_REG_PBF_SYS_CTRL) & + RT2860_REG_MCU_READY) + break; + + DELAY(1000); + } + + if (ntries == 1000) + { + printf("%s: timeout waiting for MCU to initialize\n", + device_get_nameunit(sc->dev)); + return ETIMEDOUT; + } + } + + return 0; +} + +/* + * rt2860_io_eeprom_shiftout_bits + */ +static void rt2860_io_eeprom_shiftout_bits(struct rt2860_softc *sc, + uint16_t val, uint16_t count) +{ + uint32_t mask, tmp; + + mask = (1 << (count - 1)); + + tmp = rt2860_io_mac_read(sc, RT2860_REG_EEPROM_CSR); + + tmp &= ~(RT2860_REG_EEDO | RT2860_REG_EEDI); + + do + { + tmp &= ~RT2860_REG_EEDI; + + if(val & mask) + tmp |= RT2860_REG_EEDI; + + rt2860_io_mac_write(sc, RT2860_REG_EEPROM_CSR, tmp); + + RT2860_IO_EEPROM_RAISE_CLK(sc, tmp); + RT2860_IO_EEPROM_LOWER_CLK(sc, tmp); + + mask = (mask >> 1); + } while (mask); + + tmp &= ~RT2860_REG_EEDI; + + rt2860_io_mac_write(sc, RT2860_REG_EEPROM_CSR, tmp); +} + +/* + * rt2860_io_eeprom_shiftin_bits + */ +static uint16_t rt2860_io_eeprom_shiftin_bits(struct rt2860_softc *sc) +{ + uint32_t tmp; + uint16_t val; + int i; + + val = 0; + + tmp = rt2860_io_mac_read(sc, RT2860_REG_EEPROM_CSR); + + tmp &= ~(RT2860_REG_EEDO | RT2860_REG_EEDI); + + for(i = 0; i < 16; i++) + { + val = (val << 1); + + RT2860_IO_EEPROM_RAISE_CLK(sc, tmp); + + tmp = rt2860_io_mac_read(sc, RT2860_REG_EEPROM_CSR); + + RT2860_IO_EEPROM_LOWER_CLK(sc, tmp); + + tmp &= ~RT2860_REG_EEDI; + if(tmp & RT2860_REG_EEDO) + val |= 1; + } + + return val; +} + +/* + * rt2860_io_byte_rev + */ +static uint8_t rt2860_io_byte_rev(uint8_t byte) +{ + int i; + uint8_t tmp; + + for(i = 0, tmp = 0; ; i++) + { + if(byte & 0x80) + tmp |= 0x80; + + if(i == 7) + break; + + byte <<= 1; + tmp >>= 1; + } + + return tmp; +} Index: sys/dev/rt2860/rt2860_led.h =================================================================== --- /dev/null +++ sys/dev/rt2860/rt2860_led.h @@ -0,0 +1,33 @@ + +/*- + * Copyright (c) 2009-2010 Alexander Egorenkov + * Copyright (c) 2009 Damien Bergamini + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RT2860_LED_H_ +#define _RT2860_LED_H_ + +#include + +#define RT2860_LED_CMD_RADIO_OFF 0 +#define RT2860_LED_CMD_RADIO_ON (1 << 5) +#define RT2860_LED_CMD_LINK_2GHZ (1 << 6) +#define RT2860_LED_CMD_LINK_5GHZ (1 << 7) + +void rt2860_led_brightness(struct rt2860_softc *sc, uint8_t brightness); + +void rt2860_led_cmd(struct rt2860_softc *sc, uint8_t cmd); + +#endif /* #ifndef _RT2860_LED_H_ */ Index: sys/dev/rt2860/rt2860_led.c =================================================================== --- /dev/null +++ sys/dev/rt2860/rt2860_led.c @@ -0,0 +1,51 @@ + +/*- + * Copyright (c) 2009-2010 Alexander Egorenkov + * Copyright (c) 2009 Damien Bergamini + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include +#include +#include +#include + +/* + * rt2860_led_brightness + */ +void rt2860_led_brightness(struct rt2860_softc *sc, uint8_t brightness) +{ + uint8_t polarity; + uint16_t tmp; + + polarity = (sc->led_cntl & RT2860_EEPROM_LED_POLARITY) ? 1 : 0; + + tmp = (polarity << 8) | brightness; + + rt2860_io_mcu_cmd(sc, RT2860_IO_MCU_CMD_LED_BRIGHTNESS, + RT2860_REG_H2M_TOKEN_NO_INTR, tmp); +} + +/* + * rt2860_led_cmd + */ +void rt2860_led_cmd(struct rt2860_softc *sc, uint8_t cmd) +{ + uint16_t tmp; + + tmp = (cmd << 8) | (sc->led_cntl & RT2860_EEPROM_LED_MODE_MASK); + + rt2860_io_mcu_cmd(sc, RT2860_IO_MCU_CMD_LEDS, + RT2860_REG_H2M_TOKEN_NO_INTR, tmp); +} Index: sys/dev/rt2860/rt2860_pci.c =================================================================== --- /dev/null +++ sys/dev/rt2860/rt2860_pci.c @@ -0,0 +1,163 @@ + +/*- + * Copyright (c) 2009-2010 Alexander Egorenkov + * Copyright (c) 2009 Damien Bergamini + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* + * Defines and macros + */ + +#define PCI_VENDOR_RALINK 0x1814 +#define PCI_PRODUCT_RALINK_RT2860_PCI 0x0601 +#define PCI_PRODUCT_RALINK_RT2860_PCIe 0x0681 +#define PCI_PRODUCT_RALINK_RT2760_PCI 0x0701 +#define PCI_PRODUCT_RALINK_RT2790_PCIe 0x0781 +#define PCI_PRODUCT_RALINK_RT3090_PCIe 0x3090 + +/* + * Data structures and types + */ + +struct rt2860_pci_ident +{ + uint16_t vendor; + uint16_t device; + const char *name; +}; + +/* + * Static function prototypes + */ + +static int rt2860_pci_probe(device_t dev); + +static int rt2860_pci_attach(device_t dev); + +/* + * Bus independed methods + */ + +int rt2860_attach(device_t dev, int id); + +int rt2860_detach(device_t dev); + +int rt2860_shutdown(device_t dev); + +int rt2860_suspend(device_t dev); + +int rt2860_resume(device_t dev); + + +/* + * Static variables + */ + +static const struct rt2860_pci_ident rt2860_pci_ids[] = +{ + { PCI_VENDOR_RALINK, PCI_PRODUCT_RALINK_RT2860_PCI, "Ralink RT2860 PCI" }, + { PCI_VENDOR_RALINK, PCI_PRODUCT_RALINK_RT2860_PCIe, "Ralink RT2860 PCIe" }, + { PCI_VENDOR_RALINK, PCI_PRODUCT_RALINK_RT2760_PCI, "Ralink RT2760 PCI" }, + { PCI_VENDOR_RALINK, PCI_PRODUCT_RALINK_RT2790_PCIe, "Ralink RT2790 PCIe" }, + { PCI_VENDOR_RALINK, PCI_PRODUCT_RALINK_RT2790_PCIe, "Ralink RT2790 PCIe" }, + { PCI_VENDOR_RALINK, PCI_PRODUCT_RALINK_RT3090_PCIe, "Ralink RT3090 PCIe" }, + { 0, 0, NULL } +}; + + +/* + * rt2860_pci_probe + */ +static int rt2860_pci_probe(device_t dev) +{ + const struct rt2860_pci_ident *ident; + + for (ident = rt2860_pci_ids; ident->name != NULL; ident++) + { + if (pci_get_vendor(dev) == ident->vendor && + pci_get_device(dev) == ident->device) + { + device_set_desc(dev, ident->name); + return 0; + } + } + + return ENXIO; +} + +/* + * rt2860_pci_attach + */ +static int rt2860_pci_attach(device_t dev) +{ + struct rt2860_softc *sc; + + sc = device_get_softc(dev); + + if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) + { + printf("%s: chip is in D%d power mode, setting to D0\n", + device_get_nameunit(dev), pci_get_powerstate(dev)); + pci_set_powerstate(dev, PCI_POWERSTATE_D0); + } + + /* enable bus-mastering */ + pci_enable_busmaster(dev); + sc->mem_rid = PCIR_BAR(0); + + return (rt2860_attach(dev, pci_get_device(dev))); +} + +static device_method_t rt2860_pci_dev_methods[] = +{ + /* PCI only */ + DEVMETHOD(device_probe, rt2860_pci_probe), + DEVMETHOD(device_attach, rt2860_pci_attach), + + /* Any bus */ + DEVMETHOD(device_detach, rt2860_detach), + DEVMETHOD(device_shutdown, rt2860_shutdown), + DEVMETHOD(device_suspend, rt2860_suspend), + DEVMETHOD(device_resume, rt2860_resume), + { 0, 0 } +}; + +static driver_t rt2860_pci_driver = +{ + "rt2860", + rt2860_pci_dev_methods, + sizeof(struct rt2860_softc) +}; + +static devclass_t rt2860_pci_dev_class; + +DRIVER_MODULE(rt2860, pci, rt2860_pci_driver, rt2860_pci_dev_class, 0, 0); +MODULE_DEPEND(rt2860, pci, 1, 1, 1); +MODULE_DEPEND(rt2860, wlan, 1, 1, 1); + Index: sys/dev/rt2860/rt2860_read_eeprom.h =================================================================== --- /dev/null +++ sys/dev/rt2860/rt2860_read_eeprom.h @@ -0,0 +1,29 @@ + +/*- + * Copyright (c) 2009-2010 Alexander Egorenkov + * Copyright (c) 2009 Damien Bergamini + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RT2860_READ_EEPROM_H_ +#define _RT2860_READ_EEPROM_H_ + +#include + +void rt2860_read_eeprom(struct rt2860_softc *sc); + +uint32_t rt2860_read_eeprom_txpow_rate_add_delta(uint32_t txpow_rate, + int8_t delta); + +#endif /* #ifndef _RT2860_READ_EEPROM_H_ */ Index: sys/dev/rt2860/rt2860_read_eeprom.c =================================================================== --- /dev/null +++ sys/dev/rt2860/rt2860_read_eeprom.c @@ -0,0 +1,510 @@ + +/*- + * Copyright (c) 2009-2010 Alexander Egorenkov + * Copyright (c) 2009 Damien Bergamini + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include +#include +#include +#include +#include + +/* + * rt2860_read_eeprom + */ +void rt2860_read_eeprom(struct rt2860_softc *sc) +{ + uint32_t tmp; + uint16_t val; + int i; + + /* read EEPROM address number */ + + tmp = rt2860_io_mac_read(sc, RT2860_REG_EEPROM_CSR); + + if((tmp & 0x30) == 0) + sc->eeprom_addr_num = 6; + else if((tmp & 0x30) == 0x10) + sc->eeprom_addr_num = 8; + else + sc->eeprom_addr_num = 8; + + /* read EEPROM version */ + + sc->eeprom_rev = rt2860_io_eeprom_read(sc, RT2860_EEPROM_VERSION); + + RT2860_DPRINTF(sc, RT2860_DEBUG_EEPROM, + "%s: EEPROM rev=0x%04x\n", + device_get_nameunit(sc->dev), sc->eeprom_rev); + + /* read MAC address */ + + val = rt2860_io_eeprom_read(sc, RT2860_EEPROM_ADDRESS01); + + sc->mac_addr[0] = (val & 0xff); + sc->mac_addr[1] = (val >> 8); + + val = rt2860_io_eeprom_read(sc, RT2860_EEPROM_ADDRESS23); + + sc->mac_addr[2] = (val & 0xff); + sc->mac_addr[3] = (val >> 8); + + val = rt2860_io_eeprom_read(sc, RT2860_EEPROM_ADDRESS45); + + sc->mac_addr[4] = (val & 0xff); + sc->mac_addr[5] = (val >> 8); + + RT2860_DPRINTF(sc, RT2860_DEBUG_EEPROM, + "%s: EEPROM mac address=%s\n", + device_get_nameunit(sc->dev), ether_sprintf(sc->mac_addr)); + + /* read RF information */ + + val = rt2860_io_eeprom_read(sc, RT2860_EEPROM_ANTENNA); + if (val == 0xffff) + { + printf("%s: invalid EEPROM antenna info\n", + device_get_nameunit(sc->dev)); + + sc->rf_rev = RT2860_EEPROM_RF_2820; + sc->ntxpath = 1; + sc->nrxpath = 2; + } + else + { + sc->rf_rev = (val >> 8) & 0xf; + sc->ntxpath = (val >> 4) & 0xf; + sc->nrxpath = (val & 0xf); + } + + if ((sc->mac_rev != 0x28830300) && (sc->nrxpath > 2)) + { + /* only 2 Rx streams for RT2860 series */ + + sc->nrxpath = 2; + } + + RT2860_DPRINTF(sc, RT2860_DEBUG_EEPROM, + "%s: EEPROM RF rev=0x%04x, paths=%dT%dR\n", + device_get_nameunit(sc->dev), sc->rf_rev, sc->ntxpath, sc->nrxpath); + + val = rt2860_io_eeprom_read(sc, RT2860_EEPROM_NIC_CONFIG); + if ((val & 0xff00) != 0xff00) + sc->patch_dac = (val >> 15) & 1; + + sc->hw_radio_cntl = ((val & RT2860_EEPROM_HW_RADIO_CNTL) ? 1 : 0); + sc->tx_agc_cntl = ((val & RT2860_EEPROM_TX_AGC_CNTL) ? 1 : 0); + sc->ext_lna_2ghz = ((val & RT2860_EEPROM_EXT_LNA_2GHZ) ? 1 : 0); + sc->ext_lna_5ghz = ((val & RT2860_EEPROM_EXT_LNA_5GHZ) ? 1 : 0); + + RT2860_DPRINTF(sc, RT2860_DEBUG_EEPROM, + "%s: EEPROM NIC config: HW radio cntl=%d, Tx AGC cntl=%d, ext LNA gains=%d/%d\n", + device_get_nameunit(sc->dev), + sc->hw_radio_cntl, sc->tx_agc_cntl, sc->ext_lna_2ghz, sc->ext_lna_5ghz); + + /* read country code */ + + val = rt2860_io_eeprom_read(sc, RT2860_EEPROM_COUNTRY); + + sc->country_2ghz = (val >> 8) & 0xff; + sc->country_5ghz = (val & 0xff); + + RT2860_DPRINTF(sc, RT2860_DEBUG_EEPROM, + "%s: EEPROM country code=%d/%d\n", + device_get_nameunit(sc->dev), sc->country_2ghz, sc->country_5ghz); + + /* read RF frequency offset */ + + val = rt2860_io_eeprom_read(sc, RT2860_EEPROM_RF_FREQ_OFF); + + if ((val & 0xff) != 0xff) + { + sc->rf_freq_off = (val & 0xff); + } + else + { + printf("%s: invalid EEPROM RF freq offset\n", + device_get_nameunit(sc->dev)); + + sc->rf_freq_off = 0; + } + + RT2860_DPRINTF(sc, RT2860_DEBUG_EEPROM, + "%s: EEPROM freq offset=0x%02x\n", + device_get_nameunit(sc->dev), sc->rf_freq_off); + + /* read LEDs operating mode */ + + if (((val >> 8) & 0xff) != 0xff) + { + sc->led_cntl = ((val >> 8) & 0xff); + sc->led_off[0] = rt2860_io_eeprom_read(sc, RT2860_EEPROM_LED1_OFF); + sc->led_off[1] = rt2860_io_eeprom_read(sc, RT2860_EEPROM_LED2_OFF); + sc->led_off[2] = rt2860_io_eeprom_read(sc, RT2860_EEPROM_LED3_OFF); + } + else + { + printf("%s: invalid EEPROM LED settings\n", + device_get_nameunit(sc->dev)); + + sc->led_cntl = RT2860_EEPROM_LED_CNTL_DEFAULT; + sc->led_off[0] = RT2860_EEPROM_LED1_OFF_DEFAULT; + sc->led_off[1] = RT2860_EEPROM_LED2_OFF_DEFAULT; + sc->led_off[2] = RT2860_EEPROM_LED3_OFF_DEFAULT; + } + + RT2860_DPRINTF(sc, RT2860_DEBUG_EEPROM, + "%s: EEPROM LED cntl=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", + device_get_nameunit(sc->dev), sc->led_cntl, + sc->led_off[0], sc->led_off[1], sc->led_off[2]); + + /* read RSSI offsets and LNA gains */ + + val = rt2860_io_eeprom_read(sc, RT2860_EEPROM_LNA_GAIN); + if ((sc->mac_rev & 0xffff0000) >= 0x30710000) + sc->lna_gain[0] = RT3090_DEF_LNA; + else /* channel group 0 */ + sc->lna_gain[0] = val & 0xff; + + sc->lna_gain[1] = (val >> 8) & 0xff; + + val = rt2860_io_eeprom_read(sc, RT2860_EEPROM_RSSI_OFF_2GHZ_BASE); + + sc->rssi_off_2ghz[0] = (val & 0xff); + sc->rssi_off_2ghz[1] = (val >> 8) & 0xff; + + val = rt2860_io_eeprom_read(sc, RT2860_EEPROM_RSSI_OFF_2GHZ_BASE + 2); + + if ((sc->mac_rev & 0xffff0000) >= 0x30710000) { + /* + * On RT3090 chips (limited to 2 Rx chains), this ROM + * field contains the Tx mixer gain for the 2GHz band. + */ + if ((val & 0xff) != 0xff) + sc->txmixgain_2ghz = val & 0x7; + } else + sc->rssi_off_2ghz[2] = val & 0xff; /* Ant C */ + sc->lna_gain[2] = (val >> 8) & 0xff; + + val = rt2860_io_eeprom_read(sc, RT2860_EEPROM_RSSI_OFF_5GHZ_BASE); + + sc->rssi_off_5ghz[0] = (val & 0xff); + sc->rssi_off_5ghz[1] = (val >> 8) & 0xff; + + val = rt2860_io_eeprom_read(sc, RT2860_EEPROM_RSSI_OFF_5GHZ_BASE + 2); + + sc->rssi_off_5ghz[2] = (val & 0xff); + sc->lna_gain[3] = (val >> 8) & 0xff; + + for (i = 2; i < RT2860_SOFTC_LNA_GAIN_COUNT; i++) + { + if (sc->lna_gain[i] == 0x00 || sc->lna_gain[i] == (int8_t) 0xff) + { + printf("%s: invalid EEPROM LNA gain #%d: 0x%02x\n", + device_get_nameunit(sc->dev), i, sc->lna_gain[i]); + + sc->lna_gain[i] = sc->lna_gain[1]; + } + } + + RT2860_DPRINTF(sc, RT2860_DEBUG_EEPROM, + "%s: EEPROM LNA gains=0x%02x/0x%02x/0x%02x/0x%02x\n", + device_get_nameunit(sc->dev), + sc->lna_gain[0], sc->lna_gain[1], sc->lna_gain[2], sc->lna_gain[3]); + + for (i = 0; i < RT2860_SOFTC_RSSI_OFF_COUNT; i++) + { + if (sc->rssi_off_2ghz[i] < RT2860_EEPROM_RSSI_OFF_MIN || + sc->rssi_off_2ghz[i] > RT2860_EEPROM_RSSI_OFF_MAX) + { + printf("%s: invalid EEPROM RSSI offset #%d (2GHz): 0x%02x\n", + device_get_nameunit(sc->dev), i, sc->rssi_off_2ghz[i]); + + sc->rssi_off_2ghz[i] = 0; + } + + if (sc->rssi_off_5ghz[i] < RT2860_EEPROM_RSSI_OFF_MIN || + sc->rssi_off_5ghz[i] > RT2860_EEPROM_RSSI_OFF_MAX) + { + printf("%s: invalid EEPROM RSSI offset #%d (5GHz): 0x%02x\n", + device_get_nameunit(sc->dev), i, sc->rssi_off_5ghz[i]); + + sc->rssi_off_5ghz[i] = 0; + } + } + + RT2860_DPRINTF(sc, RT2860_DEBUG_EEPROM, + "%s: EEPROM RSSI offsets 2GHz=%d/%d/%d\n", + device_get_nameunit(sc->dev), + sc->rssi_off_2ghz[0], sc->rssi_off_2ghz[1], sc->rssi_off_2ghz[2]); + + RT2860_DPRINTF(sc, RT2860_DEBUG_EEPROM, + "%s: EEPROM RSSI offsets 5GHz=%d/%d/%d\n", + device_get_nameunit(sc->dev), + sc->rssi_off_5ghz[0], sc->rssi_off_5ghz[1], sc->rssi_off_5ghz[2]); + + /* read Tx power settings for 2GHz channels */ + + for (i = 0; i < 14; i += 2) + { + val = rt2860_io_eeprom_read(sc, RT2860_EEPROM_TXPOW1_2GHZ_BASE + i / 2); + + sc->txpow1[i + 0] = (int8_t) (val & 0xff); + sc->txpow1[i + 1] = (int8_t) (val >> 8); + + val = rt2860_io_eeprom_read(sc, RT2860_EEPROM_TXPOW2_2GHZ_BASE + i / 2); + + sc->txpow2[i + 0] = (int8_t) (val & 0xff); + sc->txpow2[i + 1] = (int8_t) (val >> 8); + } + + /* read Tx power settings for 5GHz channels */ + + for (; i < RT2860_SOFTC_TXPOW_COUNT; i += 2) + { + val = rt2860_io_eeprom_read(sc, RT2860_EEPROM_TXPOW1_5GHZ_BASE + i / 2); + + sc->txpow1[i + 0] = (int8_t) (val & 0xff); + sc->txpow1[i + 1] = (int8_t) (val >> 8); + + val = rt2860_io_eeprom_read(sc, RT2860_EEPROM_TXPOW2_5GHZ_BASE + i / 2); + + sc->txpow2[i + 0] = (int8_t) (val & 0xff); + sc->txpow2[i + 1] = (int8_t) (val >> 8); + } + + /* fix broken Tx power settings */ + + for (i = 0; i < 14; i++) + { + if (sc->txpow1[i] < RT2860_EEPROM_TXPOW_2GHZ_MIN || + sc->txpow1[i] > RT2860_EEPROM_TXPOW_2GHZ_MAX) + { + printf("%s: invalid EEPROM Tx power1 #%d (2GHz): 0x%02x\n", + device_get_nameunit(sc->dev), i, sc->txpow1[i]); + + sc->txpow1[i] = RT2860_EEPROM_TXPOW_2GHZ_DEFAULT; + } + + if (sc->txpow2[i] < RT2860_EEPROM_TXPOW_2GHZ_MIN || + sc->txpow2[i] > RT2860_EEPROM_TXPOW_2GHZ_MAX) + { + printf("%s: invalid EEPROM Tx power2 #%d (2GHz): 0x%02x\n", + device_get_nameunit(sc->dev), i, sc->txpow2[i]); + + sc->txpow2[i] = RT2860_EEPROM_TXPOW_2GHZ_DEFAULT; + } + } + + for (; i < RT2860_SOFTC_TXPOW_COUNT; i++) + { + if (sc->txpow1[i] < RT2860_EEPROM_TXPOW_5GHZ_MIN || + sc->txpow1[i] > RT2860_EEPROM_TXPOW_5GHZ_MAX) + { + printf("%s: invalid EEPROM Tx power1 #%d (5GHz): 0x%02x\n", + device_get_nameunit(sc->dev), i, sc->txpow1[i]); + + sc->txpow1[i] = RT2860_EEPROM_TXPOW_5GHZ_DEFAULT; + } + + if (sc->txpow2[i] < RT2860_EEPROM_TXPOW_5GHZ_MIN || + sc->txpow2[i] > RT2860_EEPROM_TXPOW_5GHZ_MAX) + { + printf("%s: invalid EEPROM Tx power2 #%d (5GHz): 0x%02x\n", + device_get_nameunit(sc->dev), i, sc->txpow2[i]); + + sc->txpow2[i] = RT2860_EEPROM_TXPOW_5GHZ_DEFAULT; + } + } + + /* read Tx power per rate deltas */ + + val = rt2860_io_eeprom_read(sc, RT2860_EEPROM_TXPOW_RATE_DELTA); + + sc->txpow_rate_delta_2ghz = 0; + sc->txpow_rate_delta_5ghz = 0; + + if ((val & 0xff) != 0xff) + { + if (val & 0x80) + sc->txpow_rate_delta_2ghz = (val & 0xf); + + if (!(val & 0x40)) + sc->txpow_rate_delta_2ghz = -sc->txpow_rate_delta_2ghz; + } + + val >>= 8; + + if ((val & 0xff) != 0xff) + { + if (val & 0x80) + sc->txpow_rate_delta_5ghz = (val & 0xf); + + if (!(val & 0x40)) + sc->txpow_rate_delta_5ghz = -sc->txpow_rate_delta_5ghz; + } + + RT2860_DPRINTF(sc, RT2860_DEBUG_EEPROM, + "%s: EEPROM Tx power per rate deltas=%d(2MHz), %d(5MHz)\n", + device_get_nameunit(sc->dev), + sc->txpow_rate_delta_2ghz, sc->txpow_rate_delta_5ghz); + + /* read Tx power per rate */ + + for (i = 0; i < RT2860_SOFTC_TXPOW_RATE_COUNT; i++) + { + rt2860_io_eeprom_read_multi(sc, RT2860_EEPROM_TXPOW_RATE_BASE + i * sizeof(uint32_t), + &tmp, sizeof(uint32_t)); + + sc->txpow_rate_20mhz[i] = tmp; + sc->txpow_rate_40mhz_2ghz[i] = + rt2860_read_eeprom_txpow_rate_add_delta(tmp, sc->txpow_rate_delta_2ghz); + sc->txpow_rate_40mhz_5ghz[i] = + rt2860_read_eeprom_txpow_rate_add_delta(tmp, sc->txpow_rate_delta_5ghz); + + RT2860_DPRINTF(sc, RT2860_DEBUG_EEPROM, + "%s: EEPROM Tx power per rate #%d=0x%08x(20MHz), 0x%08x(40MHz/2GHz), 0x%08x(40MHz/5GHz)\n", + device_get_nameunit(sc->dev), i, + sc->txpow_rate_20mhz[i], sc->txpow_rate_40mhz_2ghz[i], sc->txpow_rate_40mhz_5ghz[i]); + } + + if (sc->tx_agc_cntl) + sc->tx_agc_cntl_2ghz = sc->tx_agc_cntl_5ghz = 1; + + /* read factory-calibrated samples for temperature compensation */ + + val = rt2860_io_eeprom_read(sc, RT2860_EEPROM_TSSI_2GHZ_BASE); + + sc->tssi_2ghz[0] = (val & 0xff); /* [-4] */ + sc->tssi_2ghz[1] = (val >> 8); /* [-3] */ + + val = rt2860_io_eeprom_read(sc, RT2860_EEPROM_TSSI_2GHZ_BASE + 2); + + sc->tssi_2ghz[2] = (val & 0xff); /* [-2] */ + sc->tssi_2ghz[3] = (val >> 8); /* [-1] */ + + val = rt2860_io_eeprom_read(sc, RT2860_EEPROM_TSSI_2GHZ_BASE + 2 * 2); + + sc->tssi_2ghz[4] = (val & 0xff); /* [0] */ + sc->tssi_2ghz[5] = (val >> 8); /* [+1] */ + + val = rt2860_io_eeprom_read(sc, RT2860_EEPROM_TSSI_2GHZ_BASE + 3 * 2); + + sc->tssi_2ghz[6] = (val & 0xff); /* [+2] */ + sc->tssi_2ghz[7] = (val >> 8); /* [+3] */ + + val = rt2860_io_eeprom_read(sc, RT2860_EEPROM_TSSI_2GHZ_BASE + 4 * 2); + + sc->tssi_2ghz[8] = (val & 0xff); /* [+4] */ + sc->tssi_step_2ghz = (val >> 8); + + if (sc->tssi_2ghz[4] == 0xff) + sc->tx_agc_cntl_2ghz = 0; + + RT2860_DPRINTF(sc, RT2860_DEBUG_EEPROM, + "%s: EEPROM TSSI 2GHz: 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, " + "0x%02x, 0x%02x, step=%d\n", + device_get_nameunit(sc->dev), + sc->tssi_2ghz[0], sc->tssi_2ghz[1], sc->tssi_2ghz[2], + sc->tssi_2ghz[3], sc->tssi_2ghz[4], sc->tssi_2ghz[5], + sc->tssi_2ghz[6], sc->tssi_2ghz[7], sc->tssi_2ghz[8], + sc->tssi_step_2ghz); + + val = rt2860_io_eeprom_read(sc, RT2860_EEPROM_TSSI_5GHZ_BASE); + + sc->tssi_5ghz[0] = (val & 0xff); /* [-4] */ + sc->tssi_5ghz[1] = (val >> 8); /* [-3] */ + + val = rt2860_io_eeprom_read(sc, RT2860_EEPROM_TSSI_5GHZ_BASE + 2); + + sc->tssi_5ghz[2] = (val & 0xff); /* [-2] */ + sc->tssi_5ghz[3] = (val >> 8); /* [-1] */ + + val = rt2860_io_eeprom_read(sc, RT2860_EEPROM_TSSI_5GHZ_BASE + 2 * 2); + + sc->tssi_5ghz[4] = (val & 0xff); /* [0] */ + sc->tssi_5ghz[5] = (val >> 8); /* [+1] */ + + val = rt2860_io_eeprom_read(sc, RT2860_EEPROM_TSSI_5GHZ_BASE + 3 * 2); + + sc->tssi_5ghz[6] = (val & 0xff); /* [+2] */ + sc->tssi_5ghz[7] = (val >> 8); /* [+3] */ + + val = rt2860_io_eeprom_read(sc, RT2860_EEPROM_TSSI_5GHZ_BASE + 4 * 2); + + sc->tssi_5ghz[8] = (val & 0xff); /* [+4] */ + sc->tssi_step_5ghz = (val >> 8); + + if (sc->tssi_5ghz[4] == 0xff) + sc->tx_agc_cntl_5ghz = 0; + + RT2860_DPRINTF(sc, RT2860_DEBUG_EEPROM, + "%s: EEPROM TSSI 5GHz: 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, " + "0x%02x, 0x%02x, step=%d\n", + device_get_nameunit(sc->dev), + sc->tssi_5ghz[0], sc->tssi_5ghz[1], sc->tssi_5ghz[2], + sc->tssi_5ghz[3], sc->tssi_5ghz[4], sc->tssi_5ghz[5], + sc->tssi_5ghz[6], sc->tssi_5ghz[7], sc->tssi_5ghz[8], + sc->tssi_step_5ghz); + + /* read default BBP settings */ + + rt2860_io_eeprom_read_multi(sc, RT2860_EEPROM_BBP_BASE, + sc->bbp_eeprom, RT2860_SOFTC_BBP_EEPROM_COUNT * 2); + + if ((sc->mac_rev & 0xffff0000) >= 0x30710000) { + /* read vendor RF settings */ + rt2860_io_eeprom_read_multi(sc, RT3071_EEPROM_RF_BASE, sc->rf, 10 * 2); + } + + /* read powersave level */ + val = rt2860_io_eeprom_read(sc, RT2860_EEPROM_POWERSAVE_LEVEL); + + sc->powersave_level = val & 0xff; + + if ((sc->powersave_level & 0xff) == 0xff) + printf("%s: invalid EEPROM powersave level\n", + device_get_nameunit(sc->dev)); + + RT2860_DPRINTF(sc, RT2860_DEBUG_EEPROM, + "%s: EEPROM powersave level=0x%02x\n", + device_get_nameunit(sc->dev), sc->powersave_level); +} + +/* + * rt2860_read_eeprom_txpow_rate_add_delta + */ +uint32_t rt2860_read_eeprom_txpow_rate_add_delta(uint32_t txpow_rate, + int8_t delta) +{ + int8_t b4; + int i; + + for (i = 0; i < 8; i++) + { + b4 = txpow_rate & 0xf; + b4 += delta; + + if (b4 < 0) + b4 = 0; + else if (b4 > 0xf) + b4 = 0xf; + + txpow_rate = (txpow_rate >> 4) | (b4 << 28); + } + + return txpow_rate; +} Index: sys/dev/rt2860/rt2860_reg.h =================================================================== --- /dev/null +++ sys/dev/rt2860/rt2860_reg.h @@ -0,0 +1,560 @@ + +/*- + * Copyright (c) 2009-2010 Alexander Egorenkov + * Copyright (c) 2009 Damien Bergamini + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RT2860_REG_H_ +#define _RT2860_REG_H_ + +#define RT2860_REG_PCI_CFG 0x0000 +#define RT2860_REG_EEPROM_CSR 0x0004 +#define RT2860_REG_PCI_MCU_CSR 0x0008 +#define RT2860_REG_PCI_SYS_CSR 0x000c +#define RT2860_REG_PCIE_JTAG 0x0010 + +#define RT2860_REG_SCHDMA_INT_STATUS 0x0200 +#define RT2860_REG_SCHDMA_INT_MASK 0x0204 +#define RT2860_REG_SCHDMA_WPDMA_GLO_CFG 0x0208 +#define RT2860_REG_SCHDMA_WPDMA_RST_IDX 0x020c +#define RT2860_REG_SCHDMA_DELAY_INT_CFG 0x0210 +#define RT2860_REG_SCHDMA_WMM_AIFSN_CFG 0x0214 +#define RT2860_REG_SCHDMA_WMM_CWMIN_CFG 0x0218 +#define RT2860_REG_SCHDMA_WMM_CWMAX_CFG 0x021c +#define RT2860_REG_SCHDMA_WMM_TXOP0_CFG 0x0220 +#define RT2860_REG_SCHDMA_WMM_TXOP1_CFG 0x0224 +#define RT2860_REG_SCHDMA_GPIO_CTRL_CFG 0x0228 +#define RT2860_REG_SCHDMA_RX_BASE_PTR 0x0290 +#define RT2860_REG_SCHDMA_RX_MAX_CNT 0x0294 +#define RT2860_REG_SCHDMA_RX_CALC_IDX 0x0298 +#define RT2860_REG_SCHDMA_RX_DRX_IDX 0x029c +#define RT2860_REG_SCHDMA_TX_BASE_PTR(qid) (0x0230 + (qid) * 16) +#define RT2860_REG_SCHDMA_TX_MAX_CNT(qid) (0x0234 + (qid) * 16) +#define RT2860_REG_SCHDMA_TX_CTX_IDX(qid) (0x0238 + (qid) * 16) +#define RT2860_REG_SCHDMA_TX_DTX_IDX(qid) (0x023c + (qid) * 16) +#define RT2860_REG_SCHDMA_US_CYC_CNT 0x02a4 + +#define RT2860_REG_PBF_SYS_CTRL 0x0400 +#define RT2860_REG_PBF_HOST_CMD 0x0404 +#define RT2860_REG_PBF_CFG 0x0408 +#define RT2860_REG_PBF_MAX_PCNT 0x040c +#define RT2860_REG_PBF_BUF_CTRL 0x0410 +#define RT2860_REG_PBF_MCU_INT_STA 0x0414 +#define RT2860_REG_PBF_MCU_INT_ENA 0x0418 +#define RT2860_REG_PBF_TX0Q_IO 0x041c +#define RT2860_REG_PBF_TX1Q_IO 0x0420 +#define RT2860_REG_PBF_TX2Q_IO 0x0424 +#define RT2860_REG_PBF_RX0Q_IO 0x0428 +#define RT2860_REG_PBF_BCN_OFFSET0 0x042c +#define RT2860_REG_PBF_BCN_OFFSET1 0x0430 +#define RT2860_REG_PBF_TXRXQ_STA 0x0434 +#define RT2860_REG_PBF_TXRXQ_PCNT 0x0438 +#define RT2860_REG_PBF_DBG 0x043c +#define RT2860_REG_PBF_CAP_CTRL 0x0440 + +#define RT2872_REG_RF_CSR_CFG 0x500 +#define RT2872_REG_RF_SETTING 0x504 +#define RT2872_REG_RF_TEST_CONTROL 0x508 + +#define RT2860_REG_MAC_CSR0 0x1000 +#define RT2860_REG_SYS_CTRL 0x1004 +#define RT2860_REG_ADDR_DW0 0x1008 +#define RT2860_REG_ADDR_DW1 0x100c +#define RT2860_REG_BSSID_DW0 0x1010 +#define RT2860_REG_BSSID_DW1 0x1014 +#define RT2860_REG_MAX_LEN_CFG 0x1018 +#define RT2860_REG_BBP_CSR_CFG 0x101c +#define RT2860_REG_RF_CSR_CFG0 0x1020 +#define RT2860_REG_LED_CFG 0x102c +#define RT2860_REG_AMPDU_MAX_LEN_20M1S 0x1030 +#define RT2860_REG_AMPDU_MAX_LEN_20M2S 0x1034 +#define RT2860_REG_AMPDU_MAX_LEN_40M1S 0x1038 +#define RT2860_REG_AMPDU_MAX_LEN_40M2S 0x103c +#define RT2860_REG_AMPDU_BA_WINSIZE 0x1040 + +#define RT2860_REG_XIFS_TIME_CFG 0x1100 +#define RT2860_REG_BKOFF_SLOT_CFG 0x1104 +#define RT2860_REG_NAV_TIME_CFG 0x1108 +#define RT2860_REG_CH_TIME_CFG 0x110c +#define RT2860_REG_PBF_LIFE_TIMER 0x1110 +#define RT2860_REG_BCN_TIME_CFG 0x1114 +#define RT2860_REG_TBTT_SYNC_CFG 0x1118 +#define RT2860_REG_TSF_TIMER_DW0 0x111c +#define RT2860_REG_TSF_TIMER_DW1 0x1120 +#define RT2860_REG_TBTT_TIMER 0x1124 +#define RT2860_REG_INT_TIMER 0x1128 +#define RT2860_REG_INT_TIMER_EN 0x112c +#define RT2860_REG_CH_IDLE_STA 0x1130 + +#define RT2860_REG_STATUS_CFG 0x1200 +#define RT2860_REG_PWR_PIN_CFG 0x1204 +#define RT2860_REG_AUTO_WAKEUP_CFG 0x1208 + +#define RT2860_REG_TX_EDCA_AC_CFG(aci) (0x1300 + (aci) * 4) +#define RT2860_REG_TX_EDCA_TID_AC_MAP 0x1310 +#define RT2860_REG_TX_PWR_CFG(ridx) (0x1314 + (ridx) * 4) +#define RT2860_REG_TX_PIN_CFG 0x1328 +#define RT2860_REG_TX_BAND_CFG 0x132c +#define RT2860_REG_TX_SW_CFG0 0x1330 +#define RT2860_REG_TX_SW_CFG1 0x1334 +#define RT2860_REG_TX_SW_CFG2 0x1338 +#define RT2860_REG_TX_TXOP_THRES_CFG 0x133c +#define RT2860_REG_TX_TXOP_CTRL_CFG 0x1340 +#define RT2860_REG_TX_RTS_CFG 0x1344 +#define RT2860_REG_TX_TIMEOUT_CFG 0x1348 +#define RT2860_REG_TX_RTY_CFG 0x134c +#define RT2860_REG_TX_LINK_CFG 0x1350 +#define RT2860_REG_TX_HT_FBK_CFG0 0x1354 +#define RT2860_REG_TX_HT_FBK_CFG1 0x1358 +#define RT2860_REG_TX_LG_FBK_CFG0 0x135c +#define RT2860_REG_TX_LG_FBK_CFG1 0x1360 +#define RT2860_REG_TX_CCK_PROT_CFG 0x1364 +#define RT2860_REG_TX_OFDM_PROT_CFG 0x1368 +#define RT2860_REG_TX_MM20_PROT_CFG 0x136c +#define RT2860_REG_TX_MM40_PROT_CFG 0x1370 +#define RT2860_REG_TX_GF20_PROT_CFG 0x1374 +#define RT2860_REG_TX_GF40_PROT_CFG 0x1378 +#define RT2860_REG_TX_EXP_CTS_TIME 0x137c +#define RT2860_REG_TX_EXP_ACK_TIME 0x1380 + +#define RT2860_REG_RX_FILTER_CFG 0x1400 +#define RT2860_REG_AUTO_RSP_CFG 0x1404 +#define RT2860_REG_LEGACY_BASIC_RATE 0x1408 +#define RT2860_REG_HT_BASIC_RATE 0x140c +#define RT2860_REG_HT_CTRL_CFG 0x1410 +#define RT2860_REG_SIFS_COST_CFG 0x1414 +#define RT2860_REG_RX_PARSER_CFG 0x1418 + +#define RT2860_REG_TX_SEC_CNT0 0x1500 +#define RT2860_REG_RX_SEC_CNT0 0x1504 +#define RT2860_REG_CCMP_FC_MUTE 0x1508 + +#define RT2860_REG_HCCAPSMP_TXOP_HLDR_ADDR0 0x1600 +#define RT2860_REG_HCCAPSMP_TXOP_HLDR_ADDR1 0x1604 +#define RT2860_REG_HCCAPSMP_TXOP_HLDR_ET 0x1608 +#define RT2860_REG_HCCAPSMP_QOS_CFPOLL_RA_DW0 0x160c +#define RT2860_REG_HCCAPSMP_QOS_CFPOLL_A1_DW1 0x1610 +#define RT2860_REG_HCCAPSMP_QOS_CFPOLL_QC 0x1614 + +#define RT2860_REG_RX_STA_CNT0 0x1700 +#define RT2860_REG_RX_STA_CNT1 0x1704 +#define RT2860_REG_RX_STA_CNT2 0x1708 +#define RT2860_REG_TX_STA_CNT0 0x170c +#define RT2860_REG_TX_STA_CNT1 0x1710 +#define RT2860_REG_TX_STA_CNT2 0x1714 +#define RT2860_REG_TX_STA_FIFO 0x1718 +#define RT2860_REG_TX_AGG_CNT 0x171c +#define RT2860_REG_TX_AGG_CNT0 0x1720 +#define RT2860_REG_TX_AGG_CNT1 0x1724 +#define RT2860_REG_TX_AGG_CNT2 0x1728 +#define RT2860_REG_TX_AGG_CNT3 0x172c +#define RT2860_REG_TX_AGG_CNT4 0x1730 +#define RT2860_REG_TX_AGG_CNT5 0x1734 +#define RT2860_REG_TX_AGG_CNT6 0x1738 +#define RT2860_REG_TX_AGG_CNT7 0x173c +#define RT2860_REG_TXRX_MPDU_DEN_CNT 0x1740 + +#define RT2860_REG_WCID(wcid) (0x1800 + (wcid) * 8) +#define RT2860_REG_PKEY(wcid) (0x4000 + (wcid) * 32) +#define RT2860_REG_IVEIV(wcid) (0x6000 + (wcid) * 8) +#define RT2860_REG_WCID_ATTR(wcid) (0x6800 + (wcid) * 4) +#define RT2860_REG_SKEY(vap, kidx) (0x6c00 + ((vap) * 4 + (kidx)) * 32) +#define RT2860_REG_SKEY_MODE(vap) (0x7000 + ((vap) / 2) * 4) +#define RT2860_REG_SKEY_MODE_0_7 0x7000 + +#define RT2860_REG_MCU_UCODE_BASE 0x2000 + +#define RT2860_REG_H2M_HOST_CMD 0x0404 +#define RT2860_REG_H2M_MAILBOX 0x7010 +#define RT2860_REG_H2M_MAILBOX_CID 0x7014 +#define RT2860_REG_H2M_MAILBOX_STATUS 0x701c +#define RT2860_REG_H2M_MAILBOX_BBP_AGENT 0x7028 + +#define RT2860_REG_BEACON_BASE(vap) (0x7800 + (vap) * 512) + +/* RT3070 registers */ +#define RT3070_RF_CSR_CFG 0x0500 +#define RT3070_EFUSE_CTRL 0x0580 +#define RT3070_EFUSE_DATA0 0x0590 +#define RT3070_EFUSE_DATA1 0x0594 +#define RT3070_EFUSE_DATA2 0x0598 +#define RT3070_EFUSE_DATA3 0x059c +#define RT3090_OSC_CTRL 0x05a4 +#define RT3070_LDO_CFG0 0x05d4 +#define RT3070_GPIO_SWITCH 0x05dc + +#define RT3090_AUX_CTRL 0x010c +#define RT3070_OPT_14 0x0114 + +/* possible flags for register RF_CSR_CFG */ +#define RT3070_RF_KICK (1 << 17) +#define RT3070_RF_WRITE (1 << 16) + +/* possible flags for register EFUSE_CTRL */ +#define RT3070_SEL_EFUSE (1 << 31) +#define RT3070_EFSROM_KICK (1 << 30) +#define RT3070_EFSROM_AIN_MASK 0x03ff0000 +#define RT3070_EFSROM_AIN_SHIFT 16 +#define RT3070_EFSROM_MODE_MASK 0x000000c0 +#define RT3070_EFUSE_AOUT_MASK 0x0000003f + +/* possible flags for RT3020 RF register 1 */ +#define RT3070_RF_BLOCK (1 << 0) +#define RT3070_RX0_PD (1 << 2) +#define RT3070_TX0_PD (1 << 3) +#define RT3070_RX1_PD (1 << 4) +#define RT3070_TX1_PD (1 << 5) +#define RT3070_RX2_PD (1 << 6) +#define RT3070_TX2_PD (1 << 7) + +/* possible flags for RT3020 RF register 1 */ +#define RT3070_RF_BLOCK (1 << 0) +#define RT3070_RX0_PD (1 << 2) +#define RT3070_TX0_PD (1 << 3) +#define RT3070_RX1_PD (1 << 4) +#define RT3070_TX1_PD (1 << 5) +#define RT3070_RX2_PD (1 << 6) +#define RT3070_TX2_PD (1 << 7) + +/* possible flags for RT3020 RF register 7 */ +#define RT3070_TUNE (1 << 0) + +/* possible flags for RT3020 RF register 15 */ +#define RT3070_TX_LO2 (1 << 3) + +/* possible flags for RT3020 RF register 17 */ +#define RT3070_TX_LO1 (1 << 3) + +/* possible flags for RT3020 RF register 20 */ +#define RT3070_RX_LO1 (1 << 3) + +/* possible flags for RT3020 RF register 21 */ +#define RT3070_RX_LO2 (1 << 3) +#define RT3070_RX_CTB (1 << 7) + +/* possible flags for RT3020 RF register 22 */ +#define RT3070_BB_LOOPBACK (1 << 0) + +/* possible flags for RT3053 RF register 1 */ +#define RT3593_VCO (1 << 0) + +/* possible flags for RT3053 RF register 2 */ +#define RT3593_RESCAL (1 << 7) + +/* possible flags for RT3053 RF register 3 */ +#define RT3593_VCOCAL (1 << 7) + +/* possible flags for RT3053 RF register 6 */ +#define RT3593_VCO_IC (1 << 6) + +/* possible flags for RT3053 RF register 20 */ +#define RT3593_LDO_PLL_VC_MASK 0x0e +#define RT3593_LDO_RF_VC_MASK 0xe0 + +/* possible flags for RT3053 RF register 22 */ +#define RT3593_CP_IC_MASK 0xe0 +#define RT3593_CP_IC_SHIFT 5 + +/* possible flags for RT3053 RF register 46 */ +#define RT3593_RX_CTB (1 << 5) + +#define RT3090_DEF_LNA 10 + + +#define RT2860_REG_RF_R1 0 +#define RT2860_REG_RF_R2 1 +#define RT2860_REG_RF_R3 2 +#define RT2860_REG_RF_R4 3 + +/* + * RT2860_REG_EEPROM_CSR flags + */ +#define RT2860_REG_EERL (1 << 7) +#define RT2860_REG_EEDO (1 << 3) +#define RT2860_REG_EEDI (1 << 2) +#define RT2860_REG_EECS (1 << 1) +#define RT2860_REG_EESK (1 << 0) +#define RT2860_REG_EEOP_READ 0x6 + +/* + * RT2860_REG_SCHDMA_INT_STATUS + * RT2860_REG_SCHDMA_INT_MASK flags + */ +#define RT2860_REG_INT_TX_COHERENT (1 << 17) +#define RT2860_REG_INT_RX_COHERENT (1 << 16) +#define RT2860_REG_INT_GP_TIMER (1 << 15) +#define RT2860_REG_INT_AUTO_WAKEUP (1 << 14) +#define RT2860_REG_INT_FIFO_STA_FULL (1 << 13) +#define RT2860_REG_INT_PRE_TBTT (1 << 12) +#define RT2860_REG_INT_TBTT (1 << 11) +#define RT2860_REG_INT_TXRX_COHERENT (1 << 10) +#define RT2860_REG_INT_MCU_CMD (1 << 9) +#define RT2860_REG_INT_TX_MGMT_DONE (1 << 8) +#define RT2860_REG_INT_TX_HCCA_DONE (1 << 7) +#define RT2860_REG_INT_TX_AC3_DONE (1 << 6) +#define RT2860_REG_INT_TX_AC2_DONE (1 << 5) +#define RT2860_REG_INT_TX_AC1_DONE (1 << 4) +#define RT2860_REG_INT_TX_AC0_DONE (1 << 3) +#define RT2860_REG_INT_RX_DONE (1 << 2) +#define RT2860_REG_INT_TX_DELAY_DONE (1 << 1) +#define RT2860_REG_INT_RX_DELAY_DONE (1 << 0) + +/* + * RT2860_REG_SCHDMA_WPDMA_GLO_CFG flags + */ +#define RT2860_REG_TX_WB_DDONE (1 << 6) +#define RT2860_REG_RX_DMA_BUSY (1 << 3) +#define RT2860_REG_RX_DMA_ENABLE (1 << 2) +#define RT2860_REG_TX_DMA_BUSY (1 << 1) +#define RT2860_REG_TX_DMA_ENABLE (1 << 0) +#define RT2860_REG_WPDMA_BT_SIZE_SHIFT 4 +#define RT2860_REG_WPDMA_BT_SIZE16 0 +#define RT2860_REG_WPDMA_BT_SIZE32 1 +#define RT2860_REG_WPDMA_BT_SIZE64 2 +#define RT2860_REG_WPDMA_BT_SIZE128 3 + +/* + * RT2860_REG_SCHDMA_WPDMA_RST_IDX flags + */ +#define RT2860_REG_RST_IDX_RX (1 << 16) +#define RT2860_REG_RST_IDX_TX_MGMT (1 << 5) +#define RT2860_REG_RST_IDX_TX_HCCA (1 << 4) +#define RT2860_REG_RST_IDX_TX_AC3 (1 << 3) +#define RT2860_REG_RST_IDX_TX_AC2 (1 << 2) +#define RT2860_REG_RST_IDX_TX_AC1 (1 << 1) +#define RT2860_REG_RST_IDX_TX_AC0 (1 << 0) + +/* + * RT2860_REG_SCHDMA_DELAY_INT_CFG flags + */ +#define RT2860_REG_INT_TX_DELAY_ENABLE (1 << 31) +#define RT2860_REG_INT_TX_MAX_PINT_SHIFT 24 +#define RT2860_REG_INT_TX_MAX_PINT_MASK 0x7 +#define RT2860_REG_INT_TX_MAX_PTIME_SHIFT 16 +#define RT2860_REG_INT_TX_MAX_PTIME_MASK 0x8 +#define RT2860_REG_INT_RX_DELAY_ENABLE (1 << 15) +#define RT2860_REG_INT_RX_MAX_PINT_SHIFT 8 +#define RT2860_REG_INT_RX_MAX_PINT_MASK 0x7 +#define RT2860_REG_INT_RX_MAX_PTIME_SHIFT 0 +#define RT2860_REG_INT_RX_MAX_PTIME_MASK 0x8 + +/* + * RT2860_REG_PBF_SYS_CTRL flags + */ +#define RT2860_REG_HST_PM_SEL (1 << 16) +#define RT2860_REG_MCU_READY (1 << 7) +#define RT2860_REG_MCU_RESET (1 << 0) + +/* + * RT2860_REG_PBF_TXRXQ_PCNT flags + */ +#define RT2860_REG_RXQ_PCNT_SHIFT 24 +#define RT2860_REG_RXQ_PCNT_MASK 0xff +#define RT2860_REG_TX2Q_PCNT_SHIFT 16 +#define RT2860_REG_TX2Q_PCNT_MASK 0xff +#define RT2860_REG_TX1Q_PCNT_SHIFT 8 +#define RT2860_REG_TX1Q_PCNT_MASK 0xff +#define RT2860_REG_TX0Q_PCNT_SHIFT 0 +#define RT2860_REG_TX0Q_PCNT_MASK 0xff + +/* + * RT2860_REG_SYS_CTRL flags + */ +#define RT2860_REG_RX_ENABLE (1 << 3) +#define RT2860_REG_TX_ENABLE (1 << 2) +#define RT2860_REG_BBP_HRST (1 << 1) +#define RT2860_REG_MAC_SRST (1 << 0) + +/* + * RT2872_REG_RF_CSR_CFG flags + */ +#define RT2872_REG_RF_CSR_BUSY (1 << 17) +#define RT2872_REG_RF_CSR_KICK (1 << 17) +#define RT2872_REG_RF_CSR_WRITE (1 << 16) +#define RT2872_REG_RF_ID_SHIFT 8 +#define RT2872_REG_RF_ID_MASK 0x1f +#define RT2872_REG_RF_VAL_SHIFT 0 +#define RT2872_REG_RF_VAL_MASK 0xff + +/* + * RT2860_REG_BBP_CSR_CFG flags + */ +#define RT2860_REG_BBP_RW_MODE_PARALLEL (1 << 19) +#define RT2860_REG_BBP_PAR_DUR (1 << 19) +#define RT2860_REG_BBP_CSR_BUSY (1 << 17) +#define RT2860_REG_BBP_CSR_KICK (1 << 17) +#define RT2860_REG_BBP_CSR_READ (1 << 16) +#define RT2860_REG_BBP_REG_SHIFT 8 +#define RT2860_REG_BBP_REG_MASK 0xff +#define RT2860_REG_BBP_VAL_SHIFT 0 +#define RT2860_REG_BBP_VAL_MASK 0xff + +/* + * RT2860_REG_RF_CSR_CFG0 flags + */ +#define RT2860_REG_RF_BUSY (1 << 31) + +/* + * RT2860_REG_BCN_TIME_CFG flags + */ +#define RT2860_REG_BCN_TX_ENABLE (1 << 20) +#define RT2860_REG_TBTT_TIMER_ENABLE (1 << 19) +#define RT2860_REG_TSF_TIMER_ENABLE (1 << 16) +#define RT2860_REG_TSF_SYNC_MODE_SHIFT 17 +#define RT2860_REG_TSF_SYNC_MODE_MASK 0x3 +#define RT2860_REG_TSF_SYNC_MODE_DISABLE 0 +#define RT2860_REG_TSF_SYNC_MODE_STA 1 +#define RT2860_REG_TSF_SYNC_MODE_IBSS 2 +#define RT2860_REG_TSF_SYNC_MODE_HOSTAP 3 + +/* + * RT2860_REG_STATUS_CFG flags + */ +#define RT2860_REG_STATUS_RX_BUSY (1 << 1) +#define RT2860_REG_STATUS_TX_BUSY (1 << 0) + +/* + * RT2860_REG_TX_PIN_CFG flags + */ +#define RT2860_REG_TRSW_ENABLE (1 << 18) +#define RT2860_REG_RFTR_ENABLE (1 << 16) +#define RT2860_REG_LNA_PE_G1_ENABLE (1 << 11) +#define RT2860_REG_LNA_PE_A1_ENABLE (1 << 10) +#define RT2860_REG_LNA_PE_G0_ENABLE (1 << 9) +#define RT2860_REG_LNA_PE_A0_ENABLE (1 << 8) +#define RT2860_REG_PA_PE_G1_ENABLE (1 << 3) +#define RT2860_REG_PA_PE_A1_ENABLE (1 << 2) +#define RT2860_REG_PA_PE_G0_ENABLE (1 << 1) +#define RT2860_REG_PA_PE_A0_ENABLE (1 << 0) + +/* + * RT2860_REG_TX_BAND_CFG flags + */ +#define RT2860_REG_TX_BAND_BG (1 << 2) +#define RT2860_REG_TX_BAND_A (1 << 1) +#define RT2860_REG_TX_BAND_HT40_ABOVE (1 << 0) +#define RT2860_REG_TX_BAND_HT40_BELOW (0 << 0) + +/* + * RT2860_REG_TX_RTS_CFG flags + */ +#define RT2860_REG_TX_RTS_THRESHOLD_SHIFT 8 +#define RT2860_REG_TX_RTS_THRESHOLD_MASK 0xffff + +/* + * RT2860_REG_TX_CCK_PROT_CFG + * RT2860_REG_TX_OFDM_PROT_CFG + * RT2860_REG_TX_MM20_PROT_CFG + * RT2860_REG_TX_MM40_PROT_CFG + * RT2860_REG_TX_GF20_PROT_CFG + * RT2860_REG_TX_GF40_PROT_CFG flags + */ +#define RT2860_REG_RTSTH_ENABLE (1 << 26) +#define RT2860_REG_TXOP_ALLOW_GF40 (1 << 25) +#define RT2860_REG_TXOP_ALLOW_GF20 (1 << 24) +#define RT2860_REG_TXOP_ALLOW_MM40 (1 << 23) +#define RT2860_REG_TXOP_ALLOW_MM20 (1 << 22) +#define RT2860_REG_TXOP_ALLOW_OFDM (1 << 21) +#define RT2860_REG_TXOP_ALLOW_CCK (1 << 20) +#define RT2860_REG_TXOP_ALLOW_ALL (0x3f << 20) +#define RT2860_REG_PROT_NAV_NONE (0 << 18) +#define RT2860_REG_PROT_NAV_SHORT (1 << 18) +#define RT2860_REG_PROT_NAV_LONG (2 << 18) +#define RT2860_REG_PROT_CTRL_NONE (0 << 16) +#define RT2860_REG_PROT_CTRL_RTS_CTS (1 << 16) +#define RT2860_REG_PROT_CTRL_CTS (2 << 16) +#define RT2860_REG_PROT_PHYMODE_SHIFT 14 +#define RT2860_REG_PROT_PHYMODE_MASK 0x3 +#define RT2860_REG_PROT_PHYMODE_CCK 0 +#define RT2860_REG_PROT_PHYMODE_OFDM 1 +#define RT2860_REG_PROT_MCS_SHIFT 0 +#define RT2860_REG_PROT_MCS_MASK 0x7f + +/* + * RT2860_REG_RX_FILTER_CFG flags + */ +#define RT2860_REG_RX_FILTER_DROP_CTRL_RSV (1 << 16) +#define RT2860_REG_RX_FILTER_DROP_BAR (1 << 15) +#define RT2860_REG_RX_FILTER_DROP_BA (1 << 14) +#define RT2860_REG_RX_FILTER_DROP_PSPOLL (1 << 13) +#define RT2860_REG_RX_FILTER_DROP_RTS (1 << 12) +#define RT2860_REG_RX_FILTER_DROP_CTS (1 << 11) +#define RT2860_REG_RX_FILTER_DROP_ACK (1 << 10) +#define RT2860_REG_RX_FILTER_DROP_CFEND (1 << 9) +#define RT2860_REG_RX_FILTER_DROP_CFACK (1 << 8) +#define RT2860_REG_RX_FILTER_DROP_DUPL (1 << 7) +#define RT2860_REG_RX_FILTER_DROP_BCAST (1 << 6) +#define RT2860_REG_RX_FILTER_DROP_MCAST (1 << 5) +#define RT2860_REG_RX_FILTER_DROP_VER_ERR (1 << 4) +#define RT2860_REG_RX_FILTER_DROP_NOT_MYBSS (1 << 3) +#define RT2860_REG_RX_FILTER_DROP_UC_NOME (1 << 2) +#define RT2860_REG_RX_FILTER_DROP_PHY_ERR (1 << 1) +#define RT2860_REG_RX_FILTER_DROP_CRC_ERR (1 << 0) + +/* + * RT2860_REG_AUTO_RSP_CFG flags + */ +#define RT2860_REG_CCK_SHORT_ENABLE (1 << 4) + +/* + * RT2860_REG_TX_STA_FIFO flags + */ +#define RT2860_REG_TX_STA_FIFO_MCS_SHIFT 16 +#define RT2860_REG_TX_STA_FIFO_MCS_MASK 0x7f +#define RT2860_REG_TX_STA_FIFO_WCID_SHIFT 8 +#define RT2860_REG_TX_STA_FIFO_WCID_MASK 0xff +#define RT2860_REG_TX_STA_FIFO_PID_SHIFT 1 +#define RT2860_REG_TX_STA_FIFO_PID_MASK 0xf +#define RT2860_REG_TX_STA_FIFO_ACK_REQ (1 << 7) +#define RT2860_REG_TX_STA_FIFO_AGG (1 << 6) +#define RT2860_REG_TX_STA_FIFO_TX_OK (1 << 5) +#define RT2860_REG_TX_STA_FIFO_VALID (1 << 0) + +/* + * RT2860_REG_WCID_ATTR flags + */ +#define RT2860_REG_VAP_SHIFT 4 +#define RT2860_REG_VAP_MASK 0x7 +#define RT2860_REG_CIPHER_MODE_SHIFT 1 +#define RT2860_REG_CIPHER_MODE_MASK 0x7 +#define RT2860_REG_CIPHER_MODE_NONE 0 +#define RT2860_REG_CIPHER_MODE_WEP40 1 +#define RT2860_REG_CIPHER_MODE_WEP104 2 +#define RT2860_REG_CIPHER_MODE_TKIP 3 +#define RT2860_REG_CIPHER_MODE_AES_CCMP 4 +#define RT2860_REG_CIPHER_MODE_CKIP40 5 +#define RT2860_REG_CIPHER_MODE_CKIP104 6 +#define RT2860_REG_CIPHER_MODE_CKIP128 7 +#define RT2860_REG_PKEY_ENABLE (1 << 0) + +/* + * RT2860_REG_H2M_MAILBOX flags + */ +#define RT2860_REG_H2M_BUSY (1 << 24) +#define RT2860_REG_H2M_TOKEN_POWERSAVE 1 +#define RT2860_REG_H2M_TOKEN_RADIOOFF 2 +#define RT2860_REG_H2M_TOKEN_WAKEUP 3 +#define RT2860_REG_H2M_TOKEN_NO_INTR 0xff + +/* + * RT2860_REG_H2M_MAILBOX_CID flags + */ +#define RT2860_REG_H2M_CID0_SHIFT 0 +#define RT2860_REG_H2M_CID1_SHIFT 8 +#define RT2860_REG_H2M_CID2_SHIFT 16 +#define RT2860_REG_H2M_CID3_SHIFT 24 +#define RT2860_REG_H2M_CID_MASK 0xff + +#endif /* #ifndef _RT2860_REG_H_ */ Index: sys/dev/rt2860/rt2860_rf.h =================================================================== --- /dev/null +++ sys/dev/rt2860/rt2860_rf.h @@ -0,0 +1,49 @@ + +/*- + * Copyright (c) 2009-2010 Alexander Egorenkov + * Copyright (c) 2009 Damien Bergamini + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RT2860_RF_H_ +#define _RT2860_RF_H_ + +#include + +const char *rt2860_rf_name(int rf_rev); + +void rt2860_rf_select_chan_group(struct rt2860_softc *sc, + struct ieee80211_channel *c); + +void rt2860_rf_set_chan(struct rt2860_softc *sc, + struct ieee80211_channel *c); + +uint8_t rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg); + +void rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val); + +void rt3090_set_chan(struct rt2860_softc *sc, u_int chan); + +int rt3090_rf_init(struct rt2860_softc *sc); + +void rt3090_set_rx_antenna(struct rt2860_softc *, int); + +void rt3090_rf_wakeup(struct rt2860_softc *sc); + +int rt3090_filter_calib(struct rt2860_softc *sc, uint8_t init, uint8_t target, + uint8_t *val); + +void rt3090_rf_setup(struct rt2860_softc *sc); + +#endif /* #ifndef _RT2860_RF_H_ */ Index: sys/dev/rt2860/rt2860_rf.c =================================================================== --- /dev/null +++ sys/dev/rt2860/rt2860_rf.c @@ -0,0 +1,1148 @@ + +/*- + * Copyright (c) 2009-2010 Alexander Egorenkov + * Copyright (c) 2009 Damien Bergamini + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include +#include +#include +#include +#include + +static void rt2872_rf_set_chan(struct rt2860_softc *sc, struct ieee80211_channel *c); + +extern uint8_t rt3052_rf_default[]; + +/* + * Static variables + */ + +static const struct rt2860_rf_prog +{ + uint8_t chan; + uint32_t r1, r2, r3, r4; +} rt2860_rf_2850[] = +{ + { 1, 0x98402ecc, 0x984c0786, 0x9816b455, 0x9800510b }, + { 2, 0x98402ecc, 0x984c0786, 0x98168a55, 0x9800519f }, + { 3, 0x98402ecc, 0x984c078a, 0x98168a55, 0x9800518b }, + { 4, 0x98402ecc, 0x984c078a, 0x98168a55, 0x9800519f }, + { 5, 0x98402ecc, 0x984c078e, 0x98168a55, 0x9800518b }, + { 6, 0x98402ecc, 0x984c078e, 0x98168a55, 0x9800519f }, + { 7, 0x98402ecc, 0x984c0792, 0x98168a55, 0x9800518b }, + { 8, 0x98402ecc, 0x984c0792, 0x98168a55, 0x9800519f }, + { 9, 0x98402ecc, 0x984c0796, 0x98168a55, 0x9800518b }, + { 10, 0x98402ecc, 0x984c0796, 0x98168a55, 0x9800519f }, + { 11, 0x98402ecc, 0x984c079a, 0x98168a55, 0x9800518b }, + { 12, 0x98402ecc, 0x984c079a, 0x98168a55, 0x9800519f }, + { 13, 0x98402ecc, 0x984c079e, 0x98168a55, 0x9800518b }, + { 14, 0x98402ecc, 0x984c07a2, 0x98168a55, 0x98005193 }, + { 36, 0x98402ecc, 0x984c099a, 0x98158a55, 0x980ed1a3 }, + { 38, 0x98402ecc, 0x984c099e, 0x98158a55, 0x980ed193 }, + { 40, 0x98402ec8, 0x984c0682, 0x98158a55, 0x980ed183 }, + { 44, 0x98402ec8, 0x984c0682, 0x98158a55, 0x980ed1a3 }, + { 46, 0x98402ec8, 0x984c0686, 0x98158a55, 0x980ed18b }, + { 48, 0x98402ec8, 0x984c0686, 0x98158a55, 0x980ed19b }, + { 52, 0x98402ec8, 0x984c068a, 0x98158a55, 0x980ed193 }, + { 54, 0x98402ec8, 0x984c068a, 0x98158a55, 0x980ed1a3 }, + { 56, 0x98402ec8, 0x984c068e, 0x98158a55, 0x980ed18b }, + { 60, 0x98402ec8, 0x984c0692, 0x98158a55, 0x980ed183 }, + { 62, 0x98402ec8, 0x984c0692, 0x98158a55, 0x980ed193 }, + { 64, 0x98402ec8, 0x984c0692, 0x98158a55, 0x980ed1a3 }, + { 100, 0x98402ec8, 0x984c06b2, 0x98178a55, 0x980ed783 }, + { 102, 0x98402ec8, 0x985c06b2, 0x98578a55, 0x980ed793 }, + { 104, 0x98402ec8, 0x985c06b2, 0x98578a55, 0x980ed1a3 }, + { 108, 0x98402ecc, 0x985c0a32, 0x98578a55, 0x980ed193 }, + { 110, 0x98402ecc, 0x984c0a36, 0x98178a55, 0x980ed183 }, + { 112, 0x98402ecc, 0x984c0a36, 0x98178a55, 0x980ed19b }, + { 116, 0x98402ecc, 0x984c0a3a, 0x98178a55, 0x980ed1a3 }, + { 118, 0x98402ecc, 0x984c0a3e, 0x98178a55, 0x980ed193 }, + { 120, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed183 }, + { 124, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed193 }, + { 126, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed15b }, + { 128, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed1a3 }, + { 132, 0x98402ec4, 0x984c0386, 0x98178a55, 0x980ed18b }, + { 134, 0x98402ec4, 0x984c0386, 0x98178a55, 0x980ed193 }, + { 136, 0x98402ec4, 0x984c0386, 0x98178a55, 0x980ed19b }, + { 140, 0x98402ec4, 0x984c038a, 0x98178a55, 0x980ed183 }, + { 149, 0x98402ec4, 0x984c038a, 0x98178a55, 0x980ed1a7 }, + { 151, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed187 }, + { 153, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed18f }, + { 157, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed19f }, + { 159, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed1a7 }, + { 161, 0x98402ec4, 0x984c0392, 0x98178a55, 0x980ed187 }, + { 165, 0x98402ec4, 0x984c0392, 0x98178a55, 0x980ed197 }, + { 184, 0x95002ccc, 0x9500491e, 0x9509be55, 0x950c0a0b }, + { 188, 0x95002ccc, 0x95004922, 0x9509be55, 0x950c0a13 }, + { 192, 0x95002ccc, 0x95004926, 0x9509be55, 0x950c0a1b }, + { 196, 0x95002ccc, 0x9500492a, 0x9509be55, 0x950c0a23 }, + { 208, 0x95002ccc, 0x9500493a, 0x9509be55, 0x950c0a13 }, + { 212, 0x95002ccc, 0x9500493e, 0x9509be55, 0x950c0a1b }, + { 216, 0x95002ccc, 0x95004982, 0x9509be55, 0x950c0a23 }, +}; + +static const struct rfprog { + uint8_t chan; + uint32_t r1, r2, r3, r4; +} rt2860_rf2850[] = { + { 1, 0x100bb3, 0x1301e1, 0x05a014, 0x001402 }, + { 2, 0x100bb3, 0x1301e1, 0x05a014, 0x001407 }, + { 3, 0x100bb3, 0x1301e2, 0x05a014, 0x001402 }, + { 4, 0x100bb3, 0x1301e2, 0x05a014, 0x001407 }, + { 5, 0x100bb3, 0x1301e3, 0x05a014, 0x001402 }, + { 6, 0x100bb3, 0x1301e3, 0x05a014, 0x001407 }, + { 7, 0x100bb3, 0x1301e4, 0x05a014, 0x001402 }, + { 8, 0x100bb3, 0x1301e4, 0x05a014, 0x001407 }, + { 9, 0x100bb3, 0x1301e5, 0x05a014, 0x001402 }, + { 10, 0x100bb3, 0x1301e5, 0x05a014, 0x001407 }, + { 11, 0x100bb3, 0x1301e6, 0x05a014, 0x001402 }, + { 12, 0x100bb3, 0x1301e6, 0x05a014, 0x001407 }, + { 13, 0x100bb3, 0x1301e7, 0x05a014, 0x001402 }, + { 14, 0x100bb3, 0x1301e8, 0x05a014, 0x001404 }, + { 36, 0x100bb3, 0x130266, 0x056014, 0x001408 }, + { 38, 0x100bb3, 0x130267, 0x056014, 0x001404 }, + { 40, 0x100bb2, 0x1301a0, 0x056014, 0x001400 }, + { 44, 0x100bb2, 0x1301a0, 0x056014, 0x001408 }, + { 46, 0x100bb2, 0x1301a1, 0x056014, 0x001402 }, + { 48, 0x100bb2, 0x1301a1, 0x056014, 0x001406 }, + { 52, 0x100bb2, 0x1301a2, 0x056014, 0x001404 }, + { 54, 0x100bb2, 0x1301a2, 0x056014, 0x001408 }, + { 56, 0x100bb2, 0x1301a3, 0x056014, 0x001402 }, + { 60, 0x100bb2, 0x1301a4, 0x056014, 0x001400 }, + { 62, 0x100bb2, 0x1301a4, 0x056014, 0x001404 }, + { 64, 0x100bb2, 0x1301a4, 0x056014, 0x001408 }, + { 100, 0x100bb2, 0x1301ac, 0x05e014, 0x001400 }, + { 102, 0x100bb2, 0x1701ac, 0x15e014, 0x001404 }, + { 104, 0x100bb2, 0x1701ac, 0x15e014, 0x001408 }, + { 108, 0x100bb3, 0x17028c, 0x15e014, 0x001404 }, + { 110, 0x100bb3, 0x13028d, 0x05e014, 0x001400 }, + { 112, 0x100bb3, 0x13028d, 0x05e014, 0x001406 }, + { 116, 0x100bb3, 0x13028e, 0x05e014, 0x001408 }, + { 118, 0x100bb3, 0x13028f, 0x05e014, 0x001404 }, + { 120, 0x100bb1, 0x1300e0, 0x05e014, 0x001400 }, + { 124, 0x100bb1, 0x1300e0, 0x05e014, 0x001404 }, + { 126, 0x100bb1, 0x1300e0, 0x05e014, 0x001406 }, + { 128, 0x100bb1, 0x1300e0, 0x05e014, 0x001408 }, + { 132, 0x100bb1, 0x1300e1, 0x05e014, 0x001402 }, + { 134, 0x100bb1, 0x1300e1, 0x05e014, 0x001404 }, + { 136, 0x100bb1, 0x1300e1, 0x05e014, 0x001406 }, + { 140, 0x100bb1, 0x1300e2, 0x05e014, 0x001400 }, + { 149, 0x100bb1, 0x1300e2, 0x05e014, 0x001409 }, + { 151, 0x100bb1, 0x1300e3, 0x05e014, 0x001401 }, + { 153, 0x100bb1, 0x1300e3, 0x05e014, 0x001403 }, + { 157, 0x100bb1, 0x1300e3, 0x05e014, 0x001407 }, + { 159, 0x100bb1, 0x1300e3, 0x05e014, 0x001409 }, + { 161, 0x100bb1, 0x1300e4, 0x05e014, 0x001401 }, + { 165, 0x100bb1, 0x1300e4, 0x05e014, 0x001405 }, + { 167, 0x100bb1, 0x1300f4, 0x05e014, 0x001407 }, + { 169, 0x100bb1, 0x1300f4, 0x05e014, 0x001409 }, + { 171, 0x100bb1, 0x1300f5, 0x05e014, 0x001401 }, + { 173, 0x100bb1, 0x1300f5, 0x05e014, 0x001403 } +}; + +static const struct rt2860_rf_fi3020 +{ + uint8_t channel, n, r, k; +} rt2860_rf_fi3020[] = +{ + /* 802.11g */ + {1, 241, 2, 2}, + {2, 241, 2, 7}, + {3, 242, 2, 2}, + {4, 242, 2, 7}, + {5, 243, 2, 2}, + {6, 243, 2, 7}, + {7, 244, 2, 2}, + {8, 244, 2, 7}, + {9, 245, 2, 2}, + {10, 245, 2, 7}, + {11, 246, 2, 2}, + {12, 246, 2, 7}, + {13, 247, 2, 2}, + {14, 248, 2, 4}, + + /* 802.11 UNI / HyperLan 2 */ + {36, 0x56, 0, 4}, + {38, 0x56, 0, 6}, + {40, 0x56, 0, 8}, + {44, 0x57, 0, 0}, + {46, 0x57, 0, 2}, + {48, 0x57, 0, 4}, + {52, 0x57, 0, 8}, + {54, 0x57, 0, 10}, + {56, 0x58, 0, 0}, + {60, 0x58, 0, 4}, + {62, 0x58, 0, 6}, + {64, 0x58, 0, 8}, + + /* 802.11 HyperLan 2 */ + {100, 0x5b, 0, 8}, + {102, 0x5b, 0, 10}, + {104, 0x5c, 0, 0}, + {108, 0x5c, 0, 4}, + {110, 0x5c, 0, 6}, + {112, 0x5c, 0, 8}, + {116, 0x5d, 0, 0}, + {118, 0x5d, 0, 2}, + {120, 0x5d, 0, 4}, + {124, 0x5d, 0, 8}, + {126, 0x5d, 0, 10}, + {128, 0x5e, 0, 0}, + {132, 0x5e, 0, 4}, + {134, 0x5e, 0, 6}, + {136, 0x5e, 0, 8}, + {140, 0x5f, 0, 0}, + + /* 802.11 UNII */ + {149, 0x5f, 0, 9}, + {151, 0x5f, 0, 11}, + {153, 0x60, 0, 1}, + {157, 0x60, 0, 5}, + {159, 0x60, 0, 7}, + {161, 0x60, 0, 9}, + {165, 0x61, 0, 1}, + {167, 0x61, 0, 3}, + {169, 0x61, 0, 5}, + {171, 0x61, 0, 7}, + {173, 0x61, 0, 9}, +}; + +static const struct { + uint8_t reg; + uint8_t val; +} rt3090_def_rf[] = { + { 4, 0x40 }, + { 5, 0x03 }, + { 6, 0x02 }, + { 7, 0x70 }, + { 9, 0x0f }, + { 10, 0x41 }, + { 11, 0x21 }, + { 12, 0x7b }, + { 14, 0x90 }, + { 15, 0x58 }, + { 16, 0xb3 }, + { 17, 0x92 }, + { 18, 0x2c }, + { 19, 0x02 }, + { 20, 0xba }, + { 21, 0xdb }, + { 24, 0x16 }, + { 25, 0x01 }, + { 29, 0x1f } +}; + +struct { + uint8_t n, r, k; +} rt3090_freqs[] = { + { 0xf1, 2, 2 }, + { 0xf1, 2, 7 }, + { 0xf2, 2, 2 }, + { 0xf2, 2, 7 }, + { 0xf3, 2, 2 }, + { 0xf3, 2, 7 }, + { 0xf4, 2, 2 }, + { 0xf4, 2, 7 }, + { 0xf5, 2, 2 }, + { 0xf5, 2, 7 }, + { 0xf6, 2, 2 }, + { 0xf6, 2, 7 }, + { 0xf7, 2, 2 }, + { 0xf8, 2, 4 }, + { 0x56, 0, 4 }, + { 0x56, 0, 6 }, + { 0x56, 0, 8 }, + { 0x57, 0, 0 }, + { 0x57, 0, 2 }, + { 0x57, 0, 4 }, + { 0x57, 0, 8 }, + { 0x57, 0, 10 }, + { 0x58, 0, 0 }, + { 0x58, 0, 4 }, + { 0x58, 0, 6 }, + { 0x58, 0, 8 }, + { 0x5b, 0, 8 }, + { 0x5b, 0, 10 }, + { 0x5c, 0, 0 }, + { 0x5c, 0, 4 }, + { 0x5c, 0, 6 }, + { 0x5c, 0, 8 }, + { 0x5d, 0, 0 }, + { 0x5d, 0, 2 }, + { 0x5d, 0, 4 }, + { 0x5d, 0, 8 }, + { 0x5d, 0, 10 }, + { 0x5e, 0, 0 }, + { 0x5e, 0, 4 }, + { 0x5e, 0, 6 }, + { 0x5e, 0, 8 }, + { 0x5f, 0, 0 }, + { 0x5f, 0, 9 }, + { 0x5f, 0, 11 }, + { 0x60, 0, 1 }, + { 0x60, 0, 5 }, + { 0x60, 0, 7 }, + { 0x60, 0, 9 }, + { 0x61, 0, 1 }, + { 0x61, 0, 3 }, + { 0x61, 0, 5 }, + { 0x61, 0, 7 }, + { 0x61, 0, 9 } +}; + + + +uint8_t +rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg) +{ + uint32_t tmp; + int ntries; + + for (ntries = 0; ntries < 100; ntries++) { + if (!(rt2860_io_mac_read(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) + break; + DELAY(1); + } + if (ntries == 100) { + device_printf(sc->dev, "could not read RF register\n"); + return 0xff; + } + tmp = RT3070_RF_KICK | reg << 8; + rt2860_io_mac_write(sc, RT3070_RF_CSR_CFG, tmp); + + for (ntries = 0; ntries < 100; ntries++) { + tmp = rt2860_io_mac_read(sc, RT3070_RF_CSR_CFG); + if (!(tmp & RT3070_RF_KICK)) + break; + DELAY(1); + } + if (ntries == 100) { + device_printf(sc->dev, "could not read RF register\n"); + return 0xff; + } + return tmp & 0xff; +} + +void +rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) +{ + uint32_t tmp; + int ntries; + + for (ntries = 0; ntries < 10; ntries++) { + if (!(rt2860_io_mac_read(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) + break; + DELAY(10); + } + if (ntries == 10) { + device_printf(sc->dev, "could not write to RF\n"); + return; + } + + tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; + rt2860_io_mac_write(sc, RT3070_RF_CSR_CFG, tmp); +} + +/* + * rt2860_rf_name + */ +const char *rt2860_rf_name(int rf_rev) +{ + switch (rf_rev) + { + case RT2860_EEPROM_RF_2820: + return "RT2820 2.4G 2T3R"; + + case RT2860_EEPROM_RF_2850: + return "RT2850 2.4G/5G 2T3R"; + + case RT2860_EEPROM_RF_2720: + return "RT2720 2.4G 1T2R"; + + case RT2860_EEPROM_RF_2750: + return "RT2750 2.4G/5G 1T2R"; + + case RT2860_EEPROM_RF_3020: + return "RT3020 2.4G 1T1R"; + + case RT2860_EEPROM_RF_2020: + return "RT2020 2.4G B/G"; + + case RT2860_EEPROM_RF_3021: + return "RT3021 2.4G 1T2R"; + + case RT2860_EEPROM_RF_3022: + return "RT3022 2.4G 2T2R"; + + case RT2860_EEPROM_RF_3052: + return "RT3052 2.4G/5G 2T2R"; + + case RT2860_EEPROM_RF_2853: + return "RT2853 2.4G.5G 3T3R"; + + case RT2860_EEPROM_RF_3320: + return "RT3320 2.4G 1T1R with PA"; + + case RT2860_EEPROM_RF_3322: + return "RT3322 2.4G 2T2R with PA"; + + case RT2860_EEPROM_RF_3053: + return "RT3053 2.4G/5G 3T3R"; + + default: + return "unknown"; + } +} + +/* + * rt2860_rf_select_chan_group + */ +void rt2860_rf_select_chan_group(struct rt2860_softc *sc, + struct ieee80211_channel *c) +{ + struct ieee80211com *ic; + int chan, group; + uint32_t tmp; + + ic = &sc->sc_ic; + + chan = ieee80211_chan2ieee(ic, c); + if (chan == 0 || chan == IEEE80211_CHAN_ANY) + return; + + if (chan <= 14) + group = 0; + else if (chan <= 64) + group = 1; + else if (chan <= 128) + group = 2; + else + group = 3; + + rt2860_io_bbp_write(sc, 62, 0x37 - sc->lna_gain[group]); + rt2860_io_bbp_write(sc, 63, 0x37 - sc->lna_gain[group]); + rt2860_io_bbp_write(sc, 64, 0x37 - sc->lna_gain[group]); + rt2860_io_bbp_write(sc, 86, 0x00); + + if (group == 0) + { + if (sc->ext_lna_2ghz) + { + rt2860_io_bbp_write(sc, 82, 0x62); + rt2860_io_bbp_write(sc, 75, 0x46); + } + else + { + rt2860_io_bbp_write(sc, 82, 0x84); + rt2860_io_bbp_write(sc, 75, 0x50); + } + } + else + { + rt2860_io_bbp_write(sc, 82, 0xf2); + + if (sc->ext_lna_5ghz) + rt2860_io_bbp_write(sc, 75, 0x46); + else + rt2860_io_bbp_write(sc, 75, 0x50); + } + + if (group == 0) + { + tmp = 0x2e + sc->lna_gain[group]; + } + else + { + if ((ic->ic_flags & IEEE80211_F_SCAN) || !IEEE80211_IS_CHAN_HT40(c)) + tmp = 0x32 + sc->lna_gain[group] * 5 / 3; + else + tmp = 0x3a + sc->lna_gain[group] * 5 / 3; + } + + rt2860_io_bbp_write(sc, 66, tmp); + + tmp = RT2860_REG_RFTR_ENABLE | + RT2860_REG_TRSW_ENABLE | + RT2860_REG_LNA_PE_G1_ENABLE | + RT2860_REG_LNA_PE_A1_ENABLE | + RT2860_REG_LNA_PE_G0_ENABLE | + RT2860_REG_LNA_PE_A0_ENABLE; + + if (group == 0) + tmp |= RT2860_REG_PA_PE_G1_ENABLE | + RT2860_REG_PA_PE_G0_ENABLE; + else + tmp |= RT2860_REG_PA_PE_A1_ENABLE | + RT2860_REG_PA_PE_A0_ENABLE; + + if (sc->ntxpath == 1) + tmp &= ~(RT2860_REG_PA_PE_G1_ENABLE | RT2860_REG_PA_PE_A1_ENABLE); + + if (sc->nrxpath == 1) + tmp &= ~(RT2860_REG_LNA_PE_G1_ENABLE | RT2860_REG_LNA_PE_A1_ENABLE); + + rt2860_io_mac_write(sc, RT2860_REG_TX_PIN_CFG, tmp); + + tmp = rt2860_io_mac_read(sc, RT2860_REG_TX_BAND_CFG); + + tmp &= ~(RT2860_REG_TX_BAND_BG | RT2860_REG_TX_BAND_A | RT2860_REG_TX_BAND_HT40_ABOVE); + + if (group == 0) + tmp |= RT2860_REG_TX_BAND_BG; + else + tmp |= RT2860_REG_TX_BAND_A; + + /* set central channel position */ + + if (IEEE80211_IS_CHAN_HT40U(c)) + tmp |= RT2860_REG_TX_BAND_HT40_BELOW; + else if (IEEE80211_IS_CHAN_HT40D(c)) + tmp |= RT2860_REG_TX_BAND_HT40_ABOVE; + else + tmp |= RT2860_REG_TX_BAND_HT40_BELOW; + + rt2860_io_mac_write(sc, RT2860_REG_TX_BAND_CFG, tmp); + + /* set bandwidth (20MHz or 40MHz) */ + + tmp = rt2860_io_bbp_read(sc, 4); + + tmp &= ~0x18; + + if (IEEE80211_IS_CHAN_HT40(c)) + tmp |= 0x10; + + rt2860_io_bbp_write(sc, 4, tmp); + + /* set central channel position */ + + tmp = rt2860_io_bbp_read(sc, 3); + + tmp &= ~0x20; + + if (IEEE80211_IS_CHAN_HT40D(c)) + tmp |= 0x20; + + rt2860_io_bbp_write(sc, 3, tmp); + +// if (sc->mac_rev == 0x28600100) + if (sc->mac_rev == 0x28600102) + { + if (!IEEE80211_IS_CHAN_HT40(c)) + { + rt2860_io_bbp_write(sc, 69, 0x16); + rt2860_io_bbp_write(sc, 70, 0x08); + rt2860_io_bbp_write(sc, 73, 0x12); + } + else + { + rt2860_io_bbp_write(sc, 69, 0x1a); + rt2860_io_bbp_write(sc, 70, 0x0a); + rt2860_io_bbp_write(sc, 73, 0x16); + } + } + +} + +void +rt3090_set_chan(struct rt2860_softc *sc, u_int chan) +{ + int8_t txpow1, txpow2; + uint8_t rf; + int i; + + KASSERT((chan >= 1 && chan <= 14), "RT3090 is 2GHz only"); /* RT3090 is 2GHz only */ + + /* find the settings for this channel (we know it exists) */ + for (i = 0; rt2860_rf2850[i].chan != chan; i++); + + /* use Tx power values from EEPROM */ + txpow1 = sc->txpow1[i]; + txpow2 = sc->txpow2[i]; + + rt3090_rf_write(sc, 2, rt3090_freqs[i].n); + rf = rt3090_rf_read(sc, 3); + rf = (rf & ~0x0f) | rt3090_freqs[i].k; + rt3090_rf_write(sc, 3, rf); + rf = rt3090_rf_read(sc, 6); + rf = (rf & ~0x03) | rt3090_freqs[i].r; + rt3090_rf_write(sc, 6, rf); + + /* set Tx0 power */ + rf = rt3090_rf_read(sc, 12); + rf = (rf & ~0x1f) | txpow1; + rt3090_rf_write(sc, 12, rf); + + /* set Tx1 power */ + rf = rt3090_rf_read(sc, 13); + rf = (rf & ~0x1f) | txpow2; + rt3090_rf_write(sc, 13, rf); + + rf = rt3090_rf_read(sc, 1); + rf &= ~0xfc; + if (sc->ntxpath == 1) + rf |= RT3070_TX1_PD | RT3070_TX2_PD; + else if (sc->ntxpath == 2) + rf |= RT3070_TX2_PD; + if (sc->nrxpath == 1) + rf |= RT3070_RX1_PD | RT3070_RX2_PD; + else if (sc->nrxpath == 2) + rf |= RT3070_RX2_PD; + rt3090_rf_write(sc, 1, rf); + + /* set RF offset */ + rf = rt3090_rf_read(sc, 23); + rf = (rf & ~0x7f) | sc->rf_freq_off; + rt3090_rf_write(sc, 23, rf); + + /* program RF filter */ + rf = rt3090_rf_read(sc, 24); /* Tx */ + rf = (rf & ~0x3f) | sc->rf24_20mhz; + rt3090_rf_write(sc, 24, rf); + rf = rt3090_rf_read(sc, 31); /* Rx */ + rf = (rf & ~0x3f) | sc->rf24_20mhz; + rt3090_rf_write(sc, 31, rf); + + /* enable RF tuning */ + rf = rt3090_rf_read(sc, 7); + rt3090_rf_write(sc, 7, rf | RT3070_TUNE); +} + +int +rt3090_rf_init(struct rt2860_softc *sc) +{ + uint32_t tmp; + uint8_t rf, bbp; + int i; + + rf = rt3090_rf_read(sc, 30); + /* toggle RF R30 bit 7 */ + rt3090_rf_write(sc, 30, rf | 0x80); + DELAY(1000); + rt3090_rf_write(sc, 30, rf & ~0x80); + + tmp = rt2860_io_mac_read(sc, RT3070_LDO_CFG0); + tmp &= ~0x1f000000; + if (sc->patch_dac && (sc->mac_rev & 0x0000ffff) < 0x0211) + tmp |= 0x0d000000; /* 1.35V */ + else + tmp |= 0x01000000; /* 1.2V */ + rt2860_io_mac_write(sc, RT3070_LDO_CFG0, tmp); + + /* patch LNA_PE_G1 */ + tmp = rt2860_io_mac_read(sc, RT3070_GPIO_SWITCH); + rt2860_io_mac_write(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); + + /* initialize RF registers to default value */ + for (i = 0; i < (sizeof(rt3090_def_rf)/2); i++) { + rt3090_rf_write(sc, rt3090_def_rf[i].reg, + rt3090_def_rf[i].val); + } + + /* select 20MHz bandwidth */ + rt3090_rf_write(sc, 31, 0x14); + + rf = rt3090_rf_read(sc, 6); + rt3090_rf_write(sc, 6, rf | 0x40); + + if ((sc->mac_rev & 0xffff0000) != 0x35930000) { + /* calibrate filter for 20MHz bandwidth */ + sc->rf24_20mhz = 0x1f; /* default value */ + rt3090_filter_calib(sc, 0x07, 0x16, &sc->rf24_20mhz); + + /* select 40MHz bandwidth */ + bbp = rt2860_io_bbp_read(sc, 4); + rt2860_io_bbp_write(sc, 4, (bbp & ~0x08) | 0x10); + rf = rt3090_rf_read(sc, 31); + rt3090_rf_write(sc, 31, rf | 0x20); + + /* calibrate filter for 40MHz bandwidth */ + sc->rf24_40mhz = 0x2f; /* default value */ + rt3090_filter_calib(sc, 0x27, 0x19, &sc->rf24_40mhz); + + /* go back to 20MHz bandwidth */ + bbp = rt2860_io_bbp_read(sc, 4); + rt2860_io_bbp_write(sc, 4, bbp & ~0x18); + } + if ((sc->mac_rev & 0x0000ffff) < 0x0211) + rt3090_rf_write(sc, 27, 0x03); + + tmp = rt2860_io_mac_read(sc, RT3070_OPT_14); + rt2860_io_mac_write(sc, RT3070_OPT_14, tmp | 1); + + if (sc->rf_rev == RT2860_EEPROM_RF_3020) + rt3090_set_rx_antenna(sc, 0); + + bbp = rt2860_io_bbp_read(sc, 138); + if ((sc->mac_rev & 0xffff0000) == 0x35930000) { + if (sc->ntxpath == 1) + bbp |= 0x60; /* turn off DAC1 and DAC2 */ + else if (sc->ntxpath == 2) + bbp |= 0x40; /* turn off DAC2 */ + if (sc->nrxpath == 1) + bbp &= ~0x06; /* turn off ADC1 and ADC2 */ + else if (sc->nrxpath == 2) + bbp &= ~0x04; /* turn off ADC2 */ + } else { + if (sc->ntxpath == 1) + bbp |= 0x20; /* turn off DAC1 */ + if (sc->nrxpath == 1) + bbp &= ~0x02; /* turn off ADC1 */ + } + rt2860_io_bbp_write(sc, 138, bbp); + + rf = rt3090_rf_read(sc, 1); + rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); + rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; + rt3090_rf_write(sc, 1, rf); + + rf = rt3090_rf_read(sc, 15); + rt3090_rf_write(sc, 15, rf & ~RT3070_TX_LO2); + + rf = rt3090_rf_read(sc, 17); + rf &= ~RT3070_TX_LO1; + if ((sc->mac_rev & 0x0000ffff) >= 0x0211 && !sc->ext_lna_2ghz) + rf |= 0x20; /* fix for long range Rx issue */ + if (sc->txmixgain_2ghz >= 2) + rf = (rf & ~0x7) | sc->txmixgain_2ghz; + rt3090_rf_write(sc, 17, rf); + + rf = rt3090_rf_read(sc, 20); + rt3090_rf_write(sc, 20, rf & ~RT3070_RX_LO1); + + rf = rt3090_rf_read(sc, 21); + rt3090_rf_write(sc, 21, rf & ~RT3070_RX_LO2); + + return 0; +} + +void +rt3090_set_rx_antenna(struct rt2860_softc *sc, int aux) +{ + uint32_t tmp; + + if (aux) { + tmp = rt2860_io_mac_read(sc, RT2860_REG_EEPROM_CSR); + rt2860_io_mac_write(sc, RT2860_REG_EEPROM_CSR, tmp & ~RT2860_REG_EESK); + tmp = rt2860_io_mac_read(sc, RT2860_REG_SCHDMA_GPIO_CTRL_CFG); + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_GPIO_CTRL_CFG, (tmp & ~0x0808) | 0x08); + } else { + tmp = rt2860_io_mac_read(sc, RT2860_REG_EEPROM_CSR); + rt2860_io_mac_write(sc, RT2860_REG_EEPROM_CSR, tmp | RT2860_REG_EESK); + tmp = rt2860_io_mac_read(sc, RT2860_REG_SCHDMA_GPIO_CTRL_CFG); + rt2860_io_mac_write(sc, RT2860_REG_SCHDMA_GPIO_CTRL_CFG, tmp & ~0x0808); + } +} + +void +rt3090_rf_wakeup(struct rt2860_softc *sc) +{ + uint32_t tmp; + uint8_t rf; + + if ((sc->mac_rev & 0xffff0000) == 0x35930000) { + /* enable VCO */ + rf = rt3090_rf_read(sc, 1); + rt3090_rf_write(sc, 1, rf | RT3593_VCO); + + /* initiate VCO calibration */ + rf = rt3090_rf_read(sc, 3); + rt3090_rf_write(sc, 3, rf | RT3593_VCOCAL); + + /* enable VCO bias current control */ + rf = rt3090_rf_read(sc, 6); + rt3090_rf_write(sc, 6, rf | RT3593_VCO_IC); + + /* initiate res calibration */ + rf = rt3090_rf_read(sc, 2); + rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); + + /* set reference current control to 0.33 mA */ + rf = rt3090_rf_read(sc, 22); + rf &= ~RT3593_CP_IC_MASK; + rf |= 1 << RT3593_CP_IC_SHIFT; + rt3090_rf_write(sc, 22, rf); + + /* enable RX CTB */ + rf = rt3090_rf_read(sc, 46); + rt3090_rf_write(sc, 46, rf | RT3593_RX_CTB); + + rf = rt3090_rf_read(sc, 20); + rf &= ~(RT3593_LDO_RF_VC_MASK | RT3593_LDO_PLL_VC_MASK); + rt3090_rf_write(sc, 20, rf); + } else { + /* enable RF block */ + rf = rt3090_rf_read(sc, 1); + rt3090_rf_write(sc, 1, rf | RT3070_RF_BLOCK); + + /* enable VCO bias current control */ + rf = rt3090_rf_read(sc, 7); + rt3090_rf_write(sc, 7, rf | 0x30); + + rf = rt3090_rf_read(sc, 9); + rt3090_rf_write(sc, 9, rf | 0x0e); + + /* enable RX CTB */ + rf = rt3090_rf_read(sc, 21); + rt3090_rf_write(sc, 21, rf | RT3070_RX_CTB); + + /* fix Tx to Rx IQ glitch by raising RF voltage */ + rf = rt3090_rf_read(sc, 27); + rf &= ~0x77; + if ((sc->mac_rev & 0x0000ffff) < 0x0211) + rf |= 0x03; + rt3090_rf_write(sc, 27, rf); + } + if (sc->patch_dac && (sc->mac_rev & 0x0000ffff) < 0x0211) { + tmp = rt2860_io_mac_read(sc, RT3070_LDO_CFG0); + tmp = (tmp & ~0x1f000000) | 0x0d000000; + rt2860_io_mac_write(sc, RT3070_LDO_CFG0, tmp); + } +} + +int +rt3090_filter_calib(struct rt2860_softc *sc, uint8_t init, uint8_t target, + uint8_t *val) +{ + uint8_t rf22, rf24; + uint8_t bbp55_pb, bbp55_sb, delta; + int ntries; + + /* program filter */ + rf24 = rt3090_rf_read(sc, 24); + rf24 = (rf24 & 0xc0) | init; /* initial filter value */ + rt3090_rf_write(sc, 24, rf24); + + /* enable baseband loopback mode */ + rf22 = rt3090_rf_read(sc, 22); + rt3090_rf_write(sc, 22, rf22 | RT3070_BB_LOOPBACK); + + /* set power and frequency of passband test tone */ + rt2860_io_bbp_write(sc, 24, 0x00); + for (ntries = 0; ntries < 100; ntries++) { + /* transmit test tone */ + rt2860_io_bbp_write(sc, 25, 0x90); + DELAY(1000); + /* read received power */ + bbp55_pb = rt2860_io_bbp_read(sc, 55); + if (bbp55_pb != 0) + break; + } + if (ntries == 100) + return ETIMEDOUT; + + /* set power and frequency of stopband test tone */ + rt2860_io_bbp_write(sc, 24, 0x06); + for (ntries = 0; ntries < 100; ntries++) { + /* transmit test tone */ + rt2860_io_bbp_write(sc, 25, 0x90); + DELAY(1000); + /* read received power */ + bbp55_sb = rt2860_io_bbp_read(sc, 55); + + delta = bbp55_pb - bbp55_sb; + if (delta > target) + break; + + /* reprogram filter */ + rf24++; + rt3090_rf_write(sc, 24, rf24); + } + if (ntries < 100) { + if (rf24 != init) + rf24--; /* backtrack */ + *val = rf24; + rt3090_rf_write(sc, 24, rf24); + } + + /* restore initial state */ + rt2860_io_bbp_write(sc, 24, 0x00); + + /* disable baseband loopback mode */ + rf22 = rt3090_rf_read(sc, 22); + rt3090_rf_write(sc, 22, rf22 & ~RT3070_BB_LOOPBACK); + + return 0; +} + +void +rt3090_rf_setup(struct rt2860_softc *sc) +{ + uint8_t bbp; + int i; + + if ((sc->mac_rev & 0x0000ffff) >= 0x0211) { + /* enable DC filter */ + rt2860_io_bbp_write(sc, 103, 0xc0); + + /* improve power consumption */ + bbp = rt2860_io_bbp_read(sc, 31); + rt2860_io_bbp_write(sc, 31, bbp & ~0x03); + } + + rt2860_io_mac_write(sc, RT2860_REG_TX_SW_CFG1, 0); + if ((sc->mac_rev & 0x0000ffff) < 0x0211) { + rt2860_io_mac_write(sc, RT2860_REG_TX_SW_CFG2, + sc->patch_dac ? 0x2c : 0x0f); + } else + rt2860_io_mac_write(sc, RT2860_REG_TX_SW_CFG2, 0); + + /* initialize RF registers from ROM */ + for (i = 0; i < 10; i++) { + if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) + continue; + rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); + } +} + + +/* + * rt2860_rf_set_chan + */ +void rt2860_rf_set_chan(struct rt2860_softc *sc, + struct ieee80211_channel *c) +{ + struct ieee80211com *ic; + const struct rt2860_rf_prog *prog; + uint32_t r1, r2, r3, r4; + int8_t txpow1, txpow2; + int i, chan; + + if (sc->mac_rev == 0x28720200) { + rt2872_rf_set_chan(sc, c); + return; + } + + ic = &sc->sc_ic; + prog = rt2860_rf_2850; + + /* get central channel position */ + + chan = ieee80211_chan2ieee(ic, c); + + if ((sc->mac_rev & 0xffff0000) >= 0x30710000) { + rt3090_set_chan(sc, chan); + return; + } + + if (IEEE80211_IS_CHAN_HT40U(c)) + chan += 2; + else if (IEEE80211_IS_CHAN_HT40D(c)) + chan -= 2; + + RT2860_DPRINTF(sc, RT2860_DEBUG_CHAN, + "%s: RF set channel: channel=%u, HT%s%s\n", + device_get_nameunit(sc->dev), + ieee80211_chan2ieee(ic, c), + !IEEE80211_IS_CHAN_HT(c) ? " disabled" : + IEEE80211_IS_CHAN_HT20(c) ? "20": + IEEE80211_IS_CHAN_HT40U(c) ? "40U" : "40D", + (ic->ic_flags & IEEE80211_F_SCAN) ? ", scanning" : ""); + + if (chan == 0 || chan == IEEE80211_CHAN_ANY) + return; + + for (i = 0; prog[i].chan != chan; i++); + + r1 = prog[i].r1; + r2 = prog[i].r2; + r3 = prog[i].r3; + r4 = prog[i].r4; + + txpow1 = sc->txpow1[i]; + txpow2 = sc->txpow2[i]; + + if (sc->ntxpath == 1) + r2 |= (1 << 14); + + if (sc->nrxpath == 2) + r2 |= (1 << 6); + else if (sc->nrxpath == 1) + r2 |= (1 << 17) | (1 << 6); + + if (IEEE80211_IS_CHAN_2GHZ(c)) + { + r3 = (r3 & 0xffffc1ff) | (txpow1 << 9); + r4 = (r4 & ~0x001f87c0) | (sc->rf_freq_off << 15) | + (txpow2 << 6); + } + else + { + r3 = r3 & 0xffffc1ff; + r4 = (r4 & ~0x001f87c0) | (sc->rf_freq_off << 15); + + if (txpow1 >= RT2860_EEPROM_TXPOW_5GHZ_MIN && txpow1 < 0) + { + txpow1 = (-RT2860_EEPROM_TXPOW_5GHZ_MIN + txpow1); + if (txpow1 > RT2860_EEPROM_TXPOW_5GHZ_MAX) + txpow1 = RT2860_EEPROM_TXPOW_5GHZ_MAX; + + r3 |= (txpow1 << 10); + } + else + { + if (txpow1 > RT2860_EEPROM_TXPOW_5GHZ_MAX) + txpow1 = RT2860_EEPROM_TXPOW_5GHZ_MAX; + + r3 |= (txpow1 << 10) | (1 << 9); + } + + if (txpow2 >= RT2860_EEPROM_TXPOW_5GHZ_MIN && txpow2 < 0) + { + txpow2 = (-RT2860_EEPROM_TXPOW_5GHZ_MIN + txpow2); + if (txpow2 > RT2860_EEPROM_TXPOW_5GHZ_MAX) + txpow2 = RT2860_EEPROM_TXPOW_5GHZ_MAX; + + r4 |= (txpow2 << 7); + } + else + { + if (txpow2 > RT2860_EEPROM_TXPOW_5GHZ_MAX) + txpow2 = RT2860_EEPROM_TXPOW_5GHZ_MAX; + + r4 |= (txpow2 << 7) | (1 << 6); + } + } + + if (!(ic->ic_flags & IEEE80211_F_SCAN) && IEEE80211_IS_CHAN_HT40(c)) + r4 |= (1 << 21); + + rt2860_io_rf_write(sc, RT2860_REG_RF_R1, r1); + rt2860_io_rf_write(sc, RT2860_REG_RF_R2, r2); + rt2860_io_rf_write(sc, RT2860_REG_RF_R3, r3 & ~(1 << 2)); + rt2860_io_rf_write(sc, RT2860_REG_RF_R4, r4); + + DELAY(200); + + rt2860_io_rf_write(sc, RT2860_REG_RF_R1, r1); + rt2860_io_rf_write(sc, RT2860_REG_RF_R2, r2); + rt2860_io_rf_write(sc, RT2860_REG_RF_R3, r3 | (1 << 2)); + rt2860_io_rf_write(sc, RT2860_REG_RF_R4, r4); + + DELAY(200); + + rt2860_io_rf_write(sc, RT2860_REG_RF_R1, r1); + rt2860_io_rf_write(sc, RT2860_REG_RF_R2, r2); + rt2860_io_rf_write(sc, RT2860_REG_RF_R3, r3 & ~(1 << 2)); + rt2860_io_rf_write(sc, RT2860_REG_RF_R4, r4); + + rt2860_rf_select_chan_group(sc, c); + + DELAY(1000); +} + +/* + * rt2872_rf_set_chan + */ +static void +rt2872_rf_set_chan(struct rt2860_softc *sc, + struct ieee80211_channel *c) +{ + struct ieee80211com *ic; + const struct rt2860_rf_prog *prog; + uint32_t r1, r2, r3, r4; + uint32_t r6, r7, r12, r13, r23, r24; + int8_t txpow1, txpow2; + int i, chan; + + ic = &sc->sc_ic; + prog = rt2860_rf_2850; + + /* get central channel position */ + + chan = ieee80211_chan2ieee(ic, c); + + if (IEEE80211_IS_CHAN_HT40U(c)) + chan += 2; + else if (IEEE80211_IS_CHAN_HT40D(c)) + chan -= 2; + + RT2860_DPRINTF(sc, RT2860_DEBUG_CHAN, + "%s: RF set channel: channel=%u, HT%s%s\n", + device_get_nameunit(sc->dev), + ieee80211_chan2ieee(ic, c), + !IEEE80211_IS_CHAN_HT(c) ? " disabled" : + IEEE80211_IS_CHAN_HT20(c) ? "20": + IEEE80211_IS_CHAN_HT40U(c) ? "40U" : "40D", + (ic->ic_flags & IEEE80211_F_SCAN) ? ", scanning" : ""); + + if (chan == 0 || chan == IEEE80211_CHAN_ANY) + return; + + for (i = 0; prog[i].chan != chan; i++); + + r1 = prog[i].r1; + r2 = prog[i].r2; + r3 = prog[i].r3; + r4 = prog[i].r4; + +// txpow1 = sc->txpow1[i]; +// txpow2 = sc->txpow2[i]; + txpow1 = 30; + txpow2 = 30; + r3 = 16; + + for (i = 0; rt2860_rf_fi3020[i].channel != chan; i++); + + /* Programm channel parameters */ + r2 = rt2860_rf_fi3020[i].n; + rt2860_io_rf_write(sc, 2 , r2 ); + r3 = rt2860_rf_fi3020[i].k; + rt2860_io_rf_write(sc, 3 , r3 ); + + r6 = (rt3052_rf_default[6] & 0xFC) | (rt2860_rf_fi3020[i].r & 0x03); + rt2860_io_rf_write(sc, 6 , r6 ); + + /* Set Tx Power */ + r12 = (rt3052_rf_default[12] & 0xE0) | (txpow1 & 0x1f); + rt2860_io_rf_write(sc, 12, r12); + + /* Set Tx1 Power */ + r13 = (rt3052_rf_default[13] & 0xE0) | (txpow2 & 0x1f); + rt2860_io_rf_write(sc, 13, r13); + + /* Set RF offset */ + r23 = (rt3052_rf_default[23] & 0x80) | (sc->rf_freq_off); + rt2860_io_rf_write(sc, 23, r23); + + /* Set BW */ + r24 = (rt3052_rf_default[24] & 0xDF); + if (!(ic->ic_flags & IEEE80211_F_SCAN) && IEEE80211_IS_CHAN_HT40(c)) + r24 |= 0x20; + rt2860_io_rf_write(sc, 24, r24); + + /* Enable RF tuning */ + r7 = (rt3052_rf_default[7]) | 1; + rt2860_io_rf_write(sc, 7 , r7 ); + + /* Antenna */ +/* + r1 = (rt3052_rf_default[1] & 0xab) | ((sc->nrxpath == 1)?0x10:0) | + ((sc->ntxpath == 1)?0x20:0); + rt2860_io_rf_write(sc, 1 , r1 ); +*/ + r1 = (rt3052_rf_default[1] & 0xab) | 0x10; + rt2860_io_rf_write(sc, 1 , r1 ); + r1 = (r1 & 0x57) | 0x20; + rt2860_io_rf_write(sc, 1 , r1 ); + + DELAY(200); + + rt2860_rf_select_chan_group(sc, c); + + DELAY(1000); +} + Index: sys/dev/rt2860/rt2860_rxdesc.h =================================================================== --- /dev/null +++ sys/dev/rt2860/rt2860_rxdesc.h @@ -0,0 +1,62 @@ + +/*- + * Copyright (c) 2009-2010 Alexander Egorenkov + * Copyright (c) 2009 Damien Bergamini + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RT2860_RXDESC_H_ +#define _RT2860_RXDESC_H_ + +#define RT2860_RXDESC_SDL0_DDONE (1 << 15) + +#define RT2860_RXDESC_FLAGS_LAST_AMSDU (1 << 19) +#define RT2860_RXDESC_FLAGS_CIPHER_ALG (1 << 18) +#define RT2860_RXDESC_FLAGS_PLCP_RSSIL (1 << 17) +#define RT2860_RXDESC_FLAGS_DECRYPTED (1 << 16) +#define RT2860_RXDESC_FLAGS_AMPDU (1 << 15) +#define RT2860_RXDESC_FLAGS_L2PAD (1 << 14) +#define RT2860_RXDESC_FLAGS_RSSI (1 << 13) +#define RT2860_RXDESC_FLAGS_HTC (1 << 12) +#define RT2860_RXDESC_FLAGS_AMSDU (1 << 11) +#define RT2860_RXDESC_FLAGS_CRC_ERR (1 << 8) +#define RT2860_RXDESC_FLAGS_MYBSS (1 << 7) +#define RT2860_RXDESC_FLAGS_BCAST (1 << 6) +#define RT2860_RXDESC_FLAGS_MCAST (1 << 5) +#define RT2860_RXDESC_FLAGS_U2M (1 << 4) +#define RT2860_RXDESC_FLAGS_FRAG (1 << 3) +#define RT2860_RXDESC_FLAGS_NULL_DATA (1 << 2) +#define RT2860_RXDESC_FLAGS_DATA (1 << 1) +#define RT2860_RXDESC_FLAGS_BA (1 << 0) + +#define RT2860_RXDESC_FLAGS_CIPHER_ERR_SHIFT 9 +#define RT2860_RXDESC_FLAGS_CIPHER_ERR_MASK 0x3 +#define RT2860_RXDESC_FLAGS_CIPHER_ERR_NONE 0 +#define RT2860_RXDESC_FLAGS_CIPHER_ERR_ICV 1 +#define RT2860_RXDESC_FLAGS_CIPHER_ERR_MIC 2 +#define RT2860_RXDESC_FLAGS_CIPHER_ERR_INVALID_KEY 3 + +#define RT2860_RXDESC_FLAGS_PLCP_SIGNAL_SHIFT 20 +#define RT2860_RXDESC_FLAGS_PLCP_SIGNAL_MASK 0xfff + +struct rt2860_rxdesc +{ + uint32_t sdp0; + uint16_t sdl1; + uint16_t sdl0; + uint32_t sdp1; + uint32_t flags; +} __packed; + +#endif /* #ifndef _RT2860_RXDESC_H_ */ Index: sys/dev/rt2860/rt2860_rxwi.h =================================================================== --- /dev/null +++ sys/dev/rt2860/rt2860_rxwi.h @@ -0,0 +1,79 @@ + +/*- + * Copyright (c) 2009-2010 Alexander Egorenkov + * Copyright (c) 2009 Damien Bergamini + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RT2860_RXWI_H_ +#define _RT2860_RXWI_H_ + +#define RT2860_RXWI_KEYIDX_SHIFT 0 +#define RT2860_RXWI_KEYIDX_MASK 0x3 + +#define RT2860_RXWI_BSSIDX_SHIFT 2 +#define RT2860_RXWI_BSSIDX_MASK 0x7 + +#define RT2860_RXWI_UDF_SHIFT 5 +#define RT2860_RXWI_UDF_MASK 0x7 + +#define RT2860_RXWI_SIZE_SHIFT 0 +#define RT2860_RXWI_SIZE_MASK 0xfff + +#define RT2860_RXWI_TID_SHIFT 12 +#define RT2860_RXWI_TID_MASK 0xf + +#define RT2860_RXWI_FRAG_SHIFT 0 +#define RT2860_RXWI_FRAG_MASK 0xf + +#define RT2860_RXWI_SEQ_SHIFT 4 +#define RT2860_RXWI_SEQ_MASK 0xfff + +#define RT2860_RXWI_MCS_SHIFT 0 +#define RT2860_RXWI_MCS_MASK 0x7f +#define RT2860_RXWI_MCS_SHOTPRE (1 << 3) + +#define RT2860_RXWI_BW_SHIFT 7 +#define RT2860_RXWI_BW_MASK 0x1 +#define RT2860_RXWI_BW_20 0 +#define RT2860_RXWI_BW_40 1 + +#define RT2860_RXWI_SHORTGI_SHIFT 0 +#define RT2860_RXWI_SHORTGI_MASK 0x1 + +#define RT2860_RXWI_STBC_SHIFT 1 +#define RT2860_RXWI_STBC_MASK 0x3 + +#define RT2860_RXWI_PHYMODE_SHIFT 6 +#define RT2860_RXWI_PHYMODE_MASK 0x3 +#define RT2860_RXWI_PHYMODE_CCK 0 +#define RT2860_RXWI_PHYMODE_OFDM 1 +#define RT2860_RXWI_PHYMODE_HT_MIXED 2 +#define RT2860_RXWI_PHYMODE_HT_GF 3 + +struct rt2860_rxwi +{ + uint8_t wcid; + uint8_t udf_bssidx_keyidx; + uint16_t tid_size; + uint16_t seq_frag; + uint8_t bw_mcs; + uint8_t phymode_stbc_shortgi; + uint8_t rssi[3]; + uint8_t reserved1; + uint8_t snr[2]; + uint16_t reserved2; +} __packed; + +#endif /* #ifndef _RT2860_RXWI_H_ */ Index: sys/dev/rt2860/rt2860_softc.h =================================================================== --- /dev/null +++ sys/dev/rt2860/rt2860_softc.h @@ -0,0 +1,437 @@ + +/*- + * Copyright (c) 2009-2010 Alexander Egorenkov + * Copyright (c) 2009 Damien Bergamini + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RT2860_SOFTC_H_ +#define _RT2860_SOFTC_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +//#include "opt_rt2860.h" +#define RT2860_DEBUG +//#define RT2860_HW_CRYPTO + +#include +#include +#include +#include + +#define RT_CHIPID_RT3050 0x3050 +#define RT_CHIPID_RT3052 0x3052 + +#define RT2860_SOFTC_LOCK(sc) mtx_lock(&(sc)->lock) +#define RT2860_SOFTC_UNLOCK(sc) \ + mtx_unlock(&(sc)->lock) +#define RT2860_SOFTC_ASSERT_LOCKED(sc) \ + mtx_assert(&(sc)->lock, MA_OWNED) + +#define RT2860_SOFTC_TX_RING_LOCK(ring) mtx_lock(&(ring)->lock) +#define RT2860_SOFTC_TX_RING_UNLOCK(ring) \ + mtx_unlock(&(ring)->lock) +#define RT2860_SOFTC_TX_RING_ASSERT_LOCKED(ring) \ + mtx_assert(&(ring)->lock, MA_OWNED) + +#define RT2860_SOFTC_FLAGS_UCODE_LOADED (1 << 0) + +#define RT2860_SOFTC_LED_OFF_COUNT 3 + +#define RT2860_SOFTC_RSSI_OFF_COUNT 3 + +#define RT2860_SOFTC_LNA_GAIN_COUNT 4 + +#define RT2860_SOFTC_TXPOW_COUNT 50 + +#define RT2860_SOFTC_TXPOW_RATE_COUNT 5 + +#define RT2860_SOFTC_TSSI_COUNT 9 + +#define RT2860_SOFTC_BBP_EEPROM_COUNT 8 + +#define RT2860_SOFTC_RSSI_COUNT 3 + +#define RT2860_SOFTC_STAID_COUNT 64 + +#define RT2860_SOFTC_TX_RING_COUNT 6 + +#define RT2860_SOFTC_RX_RING_DATA_COUNT 128 + +#define RT2860_SOFTC_MAX_SCATTER 10 + +#define RT2860_SOFTC_TX_RING_DATA_COUNT 256 +#define RT2860_SOFTC_TX_RING_DESC_COUNT \ + (RT2860_SOFTC_TX_RING_DATA_COUNT * RT2860_SOFTC_MAX_SCATTER) + +#define RT2860_SOFTC_RX_RADIOTAP_PRESENT \ + ((1 << IEEE80211_RADIOTAP_FLAGS) | \ + (1 << IEEE80211_RADIOTAP_RATE) | \ + (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \ + (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) | \ + (1 << IEEE80211_RADIOTAP_ANTENNA) | \ + (1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL) | \ + (1 << IEEE80211_RADIOTAP_XCHANNEL)) + +#define RT2860_SOFTC_TX_RADIOTAP_PRESENT \ + ((1 << IEEE80211_RADIOTAP_FLAGS) | \ + (1 << IEEE80211_RADIOTAP_RATE) | \ + (1 << IEEE80211_RADIOTAP_XCHANNEL)) + +struct rt2860_softc_rx_data +{ + bus_dmamap_t dma_map; + struct mbuf *m; +}; + +struct rt2860_softc_rx_ring +{ + bus_dma_tag_t desc_dma_tag; + bus_dmamap_t desc_dma_map; + bus_addr_t desc_phys_addr; + struct rt2860_rxdesc *desc; + bus_dma_tag_t data_dma_tag; + bus_dmamap_t spare_dma_map; + struct rt2860_softc_rx_data data[RT2860_SOFTC_RX_RING_DATA_COUNT]; + int cur; +}; + +struct rt2860_softc_tx_data +{ + bus_dmamap_t dma_map; + struct ieee80211_node *ni; + struct mbuf *m; +}; + +struct rt2860_softc_tx_ring +{ + struct mtx lock; + bus_dma_tag_t desc_dma_tag; + bus_dmamap_t desc_dma_map; + bus_addr_t desc_phys_addr; + struct rt2860_txdesc *desc; + int desc_queued; + int desc_cur; + int desc_next; + bus_dma_tag_t seg0_dma_tag; + bus_dmamap_t seg0_dma_map; + bus_addr_t seg0_phys_addr; + uint8_t *seg0; + bus_dma_tag_t data_dma_tag; + struct rt2860_softc_tx_data data[RT2860_SOFTC_TX_RING_DATA_COUNT]; + int data_queued; + int data_cur; + int data_next; + int qid; +}; + +struct rt2860_softc_node +{ + struct ieee80211_node ni; + + uint8_t staid; + + uint8_t last_rssi[RT2860_SOFTC_RSSI_COUNT]; + int8_t last_rssi_dbm[RT2860_SOFTC_RSSI_COUNT]; +}; + +struct rt2860_softc_vap +{ + struct ieee80211vap vap; + + struct ieee80211_beacon_offsets beacon_offsets; + struct mbuf *beacon_mbuf; + struct rt2860_txwi beacon_txwi; + + struct rt2860_amrr amrr; + + int (*newstate)(struct ieee80211vap *vap, + enum ieee80211_state nstate, int arg); +}; + +struct rt2860_softc_rx_radiotap_header +{ + struct ieee80211_radiotap_header ihdr; + uint8_t flags; + uint8_t rate; + int8_t dbm_antsignal; + int8_t dbm_antnoise; + uint8_t antenna; + uint8_t antsignal; + uint8_t pad[2]; + uint32_t chan_flags; + uint16_t chan_freq; + uint8_t chan_ieee; + int8_t chan_maxpow; +} __packed; + +struct rt2860_softc_tx_radiotap_header +{ + struct ieee80211_radiotap_header ihdr; + uint8_t flags; + uint8_t rate; + uint8_t pad[2]; + uint32_t chan_flags; + uint16_t chan_freq; + uint8_t chan_ieee; + int8_t chan_maxpow; +} __packed; + +struct rt2860_softc +{ + struct ieee80211com sc_ic; + + struct mtx lock; + + struct mbufq sc_snd; + + uint32_t flags; + uint32_t sc_flags; +#define RT2860_ENABLED (1 << 0) +#define RT2860_ADVANCED_PS (1 << 1) +#define RT2860_PCIE (1 << 2) +#define RT2860_RUNNING (1 << 3) + + device_t dev; + + int pid; + + int mem_rid; + struct resource *mem; + + int irq_rid; + struct resource *irq; + void *irqh; + + bus_space_tag_t bst; + bus_space_handle_t bsh; + + int nvaps; + int napvaps; + int nadhocvaps; + int nstavaps; + int nwdsvaps; + + void (*node_cleanup)(struct ieee80211_node *ni); + + int (*recv_action)(struct ieee80211_node *ni, + const struct ieee80211_frame *wh, + const uint8_t *frm, const uint8_t *efrm); + + int (*send_action)(struct ieee80211_node *ni, + int cat, int act, void *sa); + + int (*addba_response)(struct ieee80211_node *ni, + struct ieee80211_tx_ampdu *tap, + int status, int baparamset, int batimeout); + + void (*addba_stop)(struct ieee80211_node *ni, + struct ieee80211_tx_ampdu *tap); + + int (*ampdu_rx_start)(struct ieee80211_node *ni, + struct ieee80211_rx_ampdu *rap, + int baparamset, int batimeout, int baseqctl); + + void (*ampdu_rx_stop)(struct ieee80211_node *ni, + struct ieee80211_rx_ampdu *rap); + + struct rt2860_amrr_node amrr_node[RT2860_SOFTC_STAID_COUNT]; + + uint32_t mac_rev; + uint8_t eeprom_addr_num; + uint16_t eeprom_rev; + uint8_t rf_rev; + + uint8_t mac_addr[IEEE80211_ADDR_LEN]; + + uint8_t ntxpath; + uint8_t nrxpath; + + int hw_radio_cntl; + int tx_agc_cntl; + int ext_lna_2ghz; + int ext_lna_5ghz; + + uint8_t country_2ghz; + uint8_t country_5ghz; + + uint8_t rf_freq_off; + + uint8_t led_cntl; + uint16_t led_off[RT2860_SOFTC_LED_OFF_COUNT]; + + int8_t rssi_off_2ghz[RT2860_SOFTC_RSSI_OFF_COUNT]; + int8_t rssi_off_5ghz[RT2860_SOFTC_RSSI_OFF_COUNT]; + + int8_t lna_gain[RT2860_SOFTC_LNA_GAIN_COUNT]; + + int8_t txpow1[RT2860_SOFTC_TXPOW_COUNT]; + int8_t txpow2[RT2860_SOFTC_TXPOW_COUNT]; + + int8_t txpow_rate_delta_2ghz; + int8_t txpow_rate_delta_5ghz; + uint32_t txpow_rate_20mhz[RT2860_SOFTC_TXPOW_RATE_COUNT]; + uint32_t txpow_rate_40mhz_2ghz[RT2860_SOFTC_TXPOW_RATE_COUNT]; + uint32_t txpow_rate_40mhz_5ghz[RT2860_SOFTC_TXPOW_RATE_COUNT]; + + int tx_agc_cntl_2ghz; + int tx_agc_cntl_5ghz; + + uint8_t tssi_2ghz[RT2860_SOFTC_TSSI_COUNT]; + uint8_t tssi_step_2ghz; + uint8_t tssi_5ghz[RT2860_SOFTC_TSSI_COUNT]; + uint8_t tssi_step_5ghz; + + struct + { + uint8_t val; + uint8_t reg; + } __packed bbp_eeprom[RT2860_SOFTC_BBP_EEPROM_COUNT], rf[10]; + + uint16_t powersave_level; + + uint8_t staid_mask[RT2860_SOFTC_STAID_COUNT / NBBY]; + + uint32_t intr_enable_mask; + uint32_t intr_disable_mask; + uint32_t intr_pending_mask; + + struct task rx_done_task; + int rx_process_limit; + + struct task tx_done_task; + + struct task fifo_sta_full_task; + + struct task periodic_task; + struct callout periodic_ch; + unsigned long periodic_round; + + struct taskqueue *taskqueue; + + struct rt2860_softc_rx_ring rx_ring; + + struct rt2860_softc_tx_ring tx_ring[RT2860_SOFTC_TX_RING_COUNT]; + int tx_ring_mgtqid; + + struct callout tx_watchdog_ch; + int tx_timer; + + struct rt2860_softc_rx_radiotap_header rxtap; + struct rt2860_softc_tx_radiotap_header txtap; + + /* statistic counters */ + + int interrupts; + int tx_coherent_interrupts; + int rx_coherent_interrupts; + int txrx_coherent_interrupts; + int fifo_sta_full_interrupts; + int rx_interrupts; + int rx_delay_interrupts; + int tx_interrupts[RT2860_SOFTC_TX_RING_COUNT]; + int tx_delay_interrupts; + int pre_tbtt_interrupts; + int tbtt_interrupts; + int mcu_cmd_interrupts; + int auto_wakeup_interrupts; + int gp_timer_interrupts; + + int tx_data_queue_full[RT2860_SOFTC_TX_RING_COUNT]; + + int tx_watchdog_timeouts; + + int tx_defrag_packets; + + int no_tx_desc_avail; + + int rx_mbuf_alloc_errors; + int rx_mbuf_dmamap_errors; + + int tx_queue_not_empty[2]; + + int tx_beacons; + int tx_noretryok; + int tx_retryok; + int tx_failed; + int tx_underflows; + int tx_zerolen; + int tx_nonagg; + int tx_agg; + int tx_ampdu; + int tx_mpdu_zero_density; + int tx_ampdu_sessions; + + int rx_packets; + int rx_ampdu; + int rx_ampdu_retries; + int rx_mpdu_zero_density; + int rx_ampdu_sessions; + int rx_amsdu; + int rx_crc_errors; + int rx_phy_errors; + int rx_false_ccas; + int rx_plcp_errors; + int rx_dup_packets; + int rx_fifo_overflows; + int rx_cipher_no_errors; + int rx_cipher_icv_errors; + int rx_cipher_mic_errors; + int rx_cipher_invalid_key_errors; + + int tx_stbc; + + uint8_t rf24_20mhz; + uint8_t rf24_40mhz; + uint8_t patch_dac; + uint8_t txmixgain_2ghz; + uint8_t txmixgain_5ghz; + +#ifdef RT2860_DEBUG + int debug; +#endif +}; + +#endif /* #ifndef _RT2860_SOFTC_H_ */ Index: sys/dev/rt2860/rt2860_txdesc.h =================================================================== --- /dev/null +++ sys/dev/rt2860/rt2860_txdesc.h @@ -0,0 +1,48 @@ + +/*- + * Copyright (c) 2009-2010 Alexander Egorenkov + * Copyright (c) 2009 Damien Bergamini + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RT2860_TXDESC_H_ +#define _RT2860_TXDESC_H_ + +#define RT2860_TXDESC_SDL1_BURST (1 << 15) +#define RT2860_TXDESC_SDL1_LASTSEG (1 << 14) + +#define RT2860_TXDESC_SDL0_DDONE (1 << 15) +#define RT2860_TXDESC_SDL0_LASTSEG (1 << 14) + +#define RT2860_TXDESC_FLAGS_SHIFT 0 +#define RT2860_TXDESC_FLAGS_MASK 0xf9 +#define RT2860_TXDESC_FLAGS_WI_VALID (1 << 0) + +#define RT2860_TXDESC_QSEL_SHIFT 1 +#define RT2860_TXDESC_QSEL_MASK 0x3 +#define RT2860_TXDESC_QSEL_MGMT 0 +#define RT2860_TXDESC_QSEL_HCCA 1 +#define RT2860_TXDESC_QSEL_EDCA 2 + +struct rt2860_txdesc +{ + uint32_t sdp0; + uint16_t sdl1; + uint16_t sdl0; + uint32_t sdp1; + uint8_t reserved[3]; + uint8_t qsel_flags; +} __packed; + +#endif /* #ifndef _RT2860_TXDESC_H_ */ Index: sys/dev/rt2860/rt2860_txwi.h =================================================================== --- /dev/null +++ sys/dev/rt2860/rt2860_txwi.h @@ -0,0 +1,92 @@ + +/*- + * Copyright (c) 2009-2010 Alexander Egorenkov + * Copyright (c) 2009 Damien Bergamini + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RT2860_TXWI_H_ +#define _RT2860_TXWI_H_ + +#define RT2860_TXWI_FLAGS_SHIFT 0 +#define RT2860_TXWI_FLAGS_MASK 0x1f +#define RT2860_TXWI_FLAGS_AMPDU (1 << 4) +#define RT2860_TXWI_FLAGS_TS (1 << 3) +#define RT2860_TXWI_FLAGS_CFACK (1 << 2) +#define RT2860_TXWI_FLAGS_MIMOPS (1 << 1) +#define RT2860_TXWI_FLAGS_FRAG (1 << 0) + +#define RT2860_TXWI_MPDU_DENSITY_SHIFT 5 +#define RT2860_TXWI_MPDU_DENSITY_MASK 0x7 + +#define RT2860_TXWI_TXOP_SHIFT 0 +#define RT2860_TXWI_TXOP_MASK 0x3 +#define RT2860_TXWI_TXOP_HT 0 +#define RT2860_TXWI_TXOP_PIFS 1 +#define RT2860_TXWI_TXOP_SIFS 2 +#define RT2860_TXWI_TXOP_BACKOFF 3 + +#define RT2860_TXWI_MCS_SHIFT 0 +#define RT2860_TXWI_MCS_MASK 0x7f +#define RT2860_TXWI_MCS_SHOTPRE (1 << 3) + +#define RT2860_TXWI_BW_SHIFT 7 +#define RT2860_TXWI_BW_MASK 0x1 +#define RT2860_TXWI_BW_20 0 +#define RT2860_TXWI_BW_40 1 + +#define RT2860_TXWI_SHORTGI_SHIFT 0 +#define RT2860_TXWI_SHORTGI_MASK 0x1 + +#define RT2860_TXWI_STBC_SHIFT 1 +#define RT2860_TXWI_STBC_MASK 0x3 + +#define RT2860_TXWI_IFS_SHIFT 3 +#define RT2860_TXWI_IFS_MASK 0x1 + +#define RT2860_TXWI_PHYMODE_SHIFT 6 +#define RT2860_TXWI_PHYMODE_MASK 0x3 +#define RT2860_TXWI_PHYMODE_CCK 0 +#define RT2860_TXWI_PHYMODE_OFDM 1 +#define RT2860_TXWI_PHYMODE_HT_MIXED 2 +#define RT2860_TXWI_PHYMODE_HT_GF 3 + +#define RT2860_TXWI_XFLAGS_SHIFT 0 +#define RT2860_TXWI_XFLAGS_MASK 0x3 +#define RT2860_TXWI_XFLAGS_NSEQ (1 << 1) +#define RT2860_TXWI_XFLAGS_ACK (1 << 0) + +#define RT2860_TXWI_BAWIN_SIZE_SHIFT 2 +#define RT2860_TXWI_BAWIN_SIZE_MASK 0x3f + +#define RT2860_TXWI_MPDU_LEN_SHIFT 0 +#define RT2860_TXWI_MPDU_LEN_MASK 0xfff + +#define RT2860_TXWI_PID_SHIFT 12 +#define RT2860_TXWI_PID_MASK 0xf + +struct rt2860_txwi +{ + uint8_t mpdu_density_flags; + uint8_t txop; + uint8_t bw_mcs; + uint8_t phymode_ifs_stbc_shortgi; + uint8_t bawin_size_xflags; + uint8_t wcid; + uint16_t pid_mpdu_len; + uint32_t iv; + uint32_t eiv; +} __packed; + +#endif /* #ifndef _RT2860_TXWI_H_ */ Index: sys/fs/nfs/nfs_commonsubs.c =================================================================== --- sys/fs/nfs/nfs_commonsubs.c +++ sys/fs/nfs/nfs_commonsubs.c @@ -79,6 +79,7 @@ extern volatile int nfsrv_devidcnt; extern int nfscl_debuglevel; extern struct nfsdevicehead nfsrv_devidhead; +extern struct nfsstatsv1 nfsstatsv1; SYSCTL_DECL(_vfs_nfs); SYSCTL_INT(_vfs_nfs, OID_AUTO, enable_uidtostring, CTLFLAG_RW, @@ -189,7 +190,7 @@ * marked 0 in this array, the code will still work, just not quite as * efficiently.) */ -int nfs_bigreply[NFSV41_NPROCS] = { 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, +static int nfs_bigreply[NFSV41_NPROCS] = { 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 }; @@ -204,6 +205,362 @@ int *, int *); static void nfsrv_refstrbigenough(int, u_char **, u_char **, int *); +static struct { + int op; + int opcnt; + const u_char *tag; + int taglen; +} nfsv4_opmap[NFSV41_NPROCS] = { + { 0, 1, "Null", 4 }, + { NFSV4OP_GETATTR, 1, "Getattr", 7, }, + { NFSV4OP_SETATTR, 2, "Setattr", 7, }, + { NFSV4OP_LOOKUP, 3, "Lookup", 6, }, + { NFSV4OP_ACCESS, 2, "Access", 6, }, + { NFSV4OP_READLINK, 2, "Readlink", 8, }, + { NFSV4OP_READ, 1, "Read", 4, }, + { NFSV4OP_WRITE, 2, "Write", 5, }, + { NFSV4OP_OPEN, 5, "Open", 4, }, + { NFSV4OP_CREATE, 5, "Create", 6, }, + { NFSV4OP_CREATE, 1, "Create", 6, }, + { NFSV4OP_CREATE, 3, "Create", 6, }, + { NFSV4OP_REMOVE, 1, "Remove", 6, }, + { NFSV4OP_REMOVE, 1, "Remove", 6, }, + { NFSV4OP_SAVEFH, 5, "Rename", 6, }, + { NFSV4OP_SAVEFH, 4, "Link", 4, }, + { NFSV4OP_READDIR, 2, "Readdir", 7, }, + { NFSV4OP_READDIR, 2, "Readdir", 7, }, + { NFSV4OP_GETATTR, 1, "Getattr", 7, }, + { NFSV4OP_GETATTR, 1, "Getattr", 7, }, + { NFSV4OP_GETATTR, 1, "Getattr", 7, }, + { NFSV4OP_COMMIT, 2, "Commit", 6, }, + { NFSV4OP_LOOKUPP, 3, "Lookupp", 7, }, + { NFSV4OP_SETCLIENTID, 1, "SetClientID", 11, }, + { NFSV4OP_SETCLIENTIDCFRM, 1, "SetClientIDConfirm", 18, }, + { NFSV4OP_LOCK, 1, "Lock", 4, }, + { NFSV4OP_LOCKU, 1, "LockU", 5, }, + { NFSV4OP_OPEN, 2, "Open", 4, }, + { NFSV4OP_CLOSE, 1, "Close", 5, }, + { NFSV4OP_OPENCONFIRM, 1, "Openconfirm", 11, }, + { NFSV4OP_LOCKT, 1, "LockT", 5, }, + { NFSV4OP_OPENDOWNGRADE, 1, "Opendowngrade", 13, }, + { NFSV4OP_RENEW, 1, "Renew", 5, }, + { NFSV4OP_PUTROOTFH, 1, "Dirpath", 7, }, + { NFSV4OP_RELEASELCKOWN, 1, "Rellckown", 9, }, + { NFSV4OP_DELEGRETURN, 1, "Delegret", 8, }, + { NFSV4OP_DELEGRETURN, 3, "DelegRemove", 11, }, + { NFSV4OP_DELEGRETURN, 7, "DelegRename1", 12, }, + { NFSV4OP_DELEGRETURN, 9, "DelegRename2", 12, }, + { NFSV4OP_GETATTR, 1, "Getacl", 6, }, + { NFSV4OP_SETATTR, 1, "Setacl", 6, }, + { NFSV4OP_EXCHANGEID, 1, "ExchangeID", 10, }, + { NFSV4OP_CREATESESSION, 1, "CreateSession", 13, }, + { NFSV4OP_DESTROYSESSION, 1, "DestroySession", 14, }, + { NFSV4OP_DESTROYCLIENTID, 1, "DestroyClient", 13, }, + { NFSV4OP_FREESTATEID, 1, "FreeStateID", 11, }, + { NFSV4OP_LAYOUTGET, 1, "LayoutGet", 9, }, + { NFSV4OP_GETDEVINFO, 1, "GetDeviceInfo", 13, }, + { NFSV4OP_LAYOUTCOMMIT, 1, "LayoutCommit", 12, }, + { NFSV4OP_LAYOUTRETURN, 1, "LayoutReturn", 12, }, + { NFSV4OP_RECLAIMCOMPL, 1, "ReclaimComplete", 15, }, + { NFSV4OP_WRITE, 1, "WriteDS", 7, }, + { NFSV4OP_READ, 1, "ReadDS", 6, }, + { NFSV4OP_COMMIT, 1, "CommitDS", 8, }, + { NFSV4OP_OPEN, 3, "OpenLayoutGet", 13, }, + { NFSV4OP_OPEN, 8, "CreateLayGet", 12, }, +}; + +/* + * NFS RPCS that have large request message size. + */ +static int nfs_bigrequest[NFSV41_NPROCS] = { + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 +}; + +/* + * Start building a request. Mostly just put the first file handle in + * place. + */ +APPLESTATIC void +nfscl_reqstart(struct nfsrv_descript *nd, int procnum, struct nfsmount *nmp, + u_int8_t *nfhp, int fhlen, u_int32_t **opcntpp, struct nfsclsession *sep, + int vers, int minorvers) +{ + struct mbuf *mb; + u_int32_t *tl; + int opcnt; + nfsattrbit_t attrbits; + + /* + * First, fill in some of the fields of nd. + */ + nd->nd_slotseq = NULL; + if (vers == NFS_VER4) { + nd->nd_flag = ND_NFSV4 | ND_NFSCL; + if (minorvers == NFSV41_MINORVERSION) + nd->nd_flag |= ND_NFSV41; + } else if (vers == NFS_VER3) + nd->nd_flag = ND_NFSV3 | ND_NFSCL; + else { + if (NFSHASNFSV4(nmp)) { + nd->nd_flag = ND_NFSV4 | ND_NFSCL; + if (NFSHASNFSV4N(nmp)) + nd->nd_flag |= ND_NFSV41; + } else if (NFSHASNFSV3(nmp)) + nd->nd_flag = ND_NFSV3 | ND_NFSCL; + else + nd->nd_flag = ND_NFSV2 | ND_NFSCL; + } + nd->nd_procnum = procnum; + nd->nd_repstat = 0; + + /* + * Get the first mbuf for the request. + */ + if (nfs_bigrequest[procnum]) + NFSMCLGET(mb, M_WAITOK); + else + NFSMGET(mb); + mbuf_setlen(mb, 0); + nd->nd_mreq = nd->nd_mb = mb; + nd->nd_bpos = NFSMTOD(mb, caddr_t); + + /* + * And fill the first file handle into the request. + */ + if (nd->nd_flag & ND_NFSV4) { + opcnt = nfsv4_opmap[procnum].opcnt + + nfsv4_opflag[nfsv4_opmap[procnum].op].needscfh; + if ((nd->nd_flag & ND_NFSV41) != 0) { + opcnt += nfsv4_opflag[nfsv4_opmap[procnum].op].needsseq; + if (procnum == NFSPROC_RENEW) + /* + * For the special case of Renew, just do a + * Sequence Op. + */ + opcnt = 1; + else if (procnum == NFSPROC_WRITEDS || + procnum == NFSPROC_COMMITDS) + /* + * For the special case of a Writeor Commit to + * a DS, the opcnt == 3, for Sequence, PutFH, + * Write/Commit. + */ + opcnt = 3; + } + /* + * What should the tag really be? + */ + (void) nfsm_strtom(nd, nfsv4_opmap[procnum].tag, + nfsv4_opmap[procnum].taglen); + NFSM_BUILD(tl, u_int32_t *, 2 * NFSX_UNSIGNED); + if ((nd->nd_flag & ND_NFSV41) != 0) + *tl++ = txdr_unsigned(NFSV41_MINORVERSION); + else + *tl++ = txdr_unsigned(NFSV4_MINORVERSION); + if (opcntpp != NULL) + *opcntpp = tl; + *tl = txdr_unsigned(opcnt); + if ((nd->nd_flag & ND_NFSV41) != 0 && + nfsv4_opflag[nfsv4_opmap[procnum].op].needsseq > 0) { + if (nfsv4_opflag[nfsv4_opmap[procnum].op].loopbadsess > + 0) + nd->nd_flag |= ND_LOOPBADSESS; + NFSM_BUILD(tl, u_int32_t *, NFSX_UNSIGNED); + *tl = txdr_unsigned(NFSV4OP_SEQUENCE); + if (sep == NULL) { + sep = nfsmnt_mdssession(nmp); + nfsv4_setsequence(nmp, nd, sep, + nfs_bigreply[procnum]); + } else + nfsv4_setsequence(nmp, nd, sep, + nfs_bigreply[procnum]); + } + if (nfsv4_opflag[nfsv4_opmap[procnum].op].needscfh > 0) { + NFSM_BUILD(tl, u_int32_t *, NFSX_UNSIGNED); + *tl = txdr_unsigned(NFSV4OP_PUTFH); + (void) nfsm_fhtom(nd, nfhp, fhlen, 0); + if (nfsv4_opflag[nfsv4_opmap[procnum].op].needscfh + == 2 && procnum != NFSPROC_WRITEDS && + procnum != NFSPROC_COMMITDS) { + NFSM_BUILD(tl, u_int32_t *, NFSX_UNSIGNED); + *tl = txdr_unsigned(NFSV4OP_GETATTR); + /* + * For Lookup Ops, we want all the directory + * attributes, so we can load the name cache. + */ + if (procnum == NFSPROC_LOOKUP || + procnum == NFSPROC_LOOKUPP) + NFSGETATTR_ATTRBIT(&attrbits); + else { + NFSWCCATTR_ATTRBIT(&attrbits); + nd->nd_flag |= ND_V4WCCATTR; + } + (void) nfsrv_putattrbit(nd, &attrbits); + } + } + if (procnum != NFSPROC_RENEW || + (nd->nd_flag & ND_NFSV41) == 0) { + NFSM_BUILD(tl, u_int32_t *, NFSX_UNSIGNED); + *tl = txdr_unsigned(nfsv4_opmap[procnum].op); + } + } else { + (void) nfsm_fhtom(nd, nfhp, fhlen, 0); + } + if (procnum < NFSV41_NPROCS) + NFSINCRGLOBAL(nfsstatsv1.rpccnt[procnum]); +} + +/* + * Put a state Id in the mbuf list. + */ +APPLESTATIC void +nfsm_stateidtom(struct nfsrv_descript *nd, nfsv4stateid_t *stateidp, int flag) +{ + nfsv4stateid_t *st; + + NFSM_BUILD(st, nfsv4stateid_t *, NFSX_STATEID); + if (flag == NFSSTATEID_PUTALLZERO) { + st->seqid = 0; + st->other[0] = 0; + st->other[1] = 0; + st->other[2] = 0; + } else if (flag == NFSSTATEID_PUTALLONE) { + st->seqid = 0xffffffff; + st->other[0] = 0xffffffff; + st->other[1] = 0xffffffff; + st->other[2] = 0xffffffff; + } else if (flag == NFSSTATEID_PUTSEQIDZERO) { + st->seqid = 0; + st->other[0] = stateidp->other[0]; + st->other[1] = stateidp->other[1]; + st->other[2] = stateidp->other[2]; + } else { + st->seqid = stateidp->seqid; + st->other[0] = stateidp->other[0]; + st->other[1] = stateidp->other[1]; + st->other[2] = stateidp->other[2]; + } +} + +/* + * Fill in the setable attributes. The full argument indicates whether + * to fill in them all or just mode and time. + */ +void +nfscl_fillsattr(struct nfsrv_descript *nd, struct vattr *vap, + struct vnode *vp, int flags, u_int32_t rdev) +{ + u_int32_t *tl; + struct nfsv2_sattr *sp; + nfsattrbit_t attrbits; + + switch (nd->nd_flag & (ND_NFSV2 | ND_NFSV3 | ND_NFSV4)) { + case ND_NFSV2: + NFSM_BUILD(sp, struct nfsv2_sattr *, NFSX_V2SATTR); + if (vap->va_mode == (mode_t)VNOVAL) + sp->sa_mode = newnfs_xdrneg1; + else + sp->sa_mode = vtonfsv2_mode(vap->va_type, vap->va_mode); + if (vap->va_uid == (uid_t)VNOVAL) + sp->sa_uid = newnfs_xdrneg1; + else + sp->sa_uid = txdr_unsigned(vap->va_uid); + if (vap->va_gid == (gid_t)VNOVAL) + sp->sa_gid = newnfs_xdrneg1; + else + sp->sa_gid = txdr_unsigned(vap->va_gid); + if (flags & NFSSATTR_SIZE0) + sp->sa_size = 0; + else if (flags & NFSSATTR_SIZENEG1) + sp->sa_size = newnfs_xdrneg1; + else if (flags & NFSSATTR_SIZERDEV) + sp->sa_size = txdr_unsigned(rdev); + else + sp->sa_size = txdr_unsigned(vap->va_size); + txdr_nfsv2time(&vap->va_atime, &sp->sa_atime); + txdr_nfsv2time(&vap->va_mtime, &sp->sa_mtime); + break; + case ND_NFSV3: + if (vap->va_mode != (mode_t)VNOVAL) { + NFSM_BUILD(tl, u_int32_t *, 2 * NFSX_UNSIGNED); + *tl++ = newnfs_true; + *tl = txdr_unsigned(vap->va_mode); + } else { + NFSM_BUILD(tl, u_int32_t *, NFSX_UNSIGNED); + *tl = newnfs_false; + } + if ((flags & NFSSATTR_FULL) && vap->va_uid != (uid_t)VNOVAL) { + NFSM_BUILD(tl, u_int32_t *, 2 * NFSX_UNSIGNED); + *tl++ = newnfs_true; + *tl = txdr_unsigned(vap->va_uid); + } else { + NFSM_BUILD(tl, u_int32_t *, NFSX_UNSIGNED); + *tl = newnfs_false; + } + if ((flags & NFSSATTR_FULL) && vap->va_gid != (gid_t)VNOVAL) { + NFSM_BUILD(tl, u_int32_t *, 2 * NFSX_UNSIGNED); + *tl++ = newnfs_true; + *tl = txdr_unsigned(vap->va_gid); + } else { + NFSM_BUILD(tl, u_int32_t *, NFSX_UNSIGNED); + *tl = newnfs_false; + } + if ((flags & NFSSATTR_FULL) && vap->va_size != VNOVAL) { + NFSM_BUILD(tl, u_int32_t *, 3 * NFSX_UNSIGNED); + *tl++ = newnfs_true; + txdr_hyper(vap->va_size, tl); + } else { + NFSM_BUILD(tl, u_int32_t *, NFSX_UNSIGNED); + *tl = newnfs_false; + } + if (vap->va_atime.tv_sec != VNOVAL) { + if ((vap->va_vaflags & VA_UTIMES_NULL) == 0) { + NFSM_BUILD(tl, u_int32_t *, 3 * NFSX_UNSIGNED); + *tl++ = txdr_unsigned(NFSV3SATTRTIME_TOCLIENT); + txdr_nfsv3time(&vap->va_atime, tl); + } else { + NFSM_BUILD(tl, u_int32_t *, NFSX_UNSIGNED); + *tl = txdr_unsigned(NFSV3SATTRTIME_TOSERVER); + } + } else { + NFSM_BUILD(tl, u_int32_t *, NFSX_UNSIGNED); + *tl = txdr_unsigned(NFSV3SATTRTIME_DONTCHANGE); + } + if (vap->va_mtime.tv_sec != VNOVAL) { + if ((vap->va_vaflags & VA_UTIMES_NULL) == 0) { + NFSM_BUILD(tl, u_int32_t *, 3 * NFSX_UNSIGNED); + *tl++ = txdr_unsigned(NFSV3SATTRTIME_TOCLIENT); + txdr_nfsv3time(&vap->va_mtime, tl); + } else { + NFSM_BUILD(tl, u_int32_t *, NFSX_UNSIGNED); + *tl = txdr_unsigned(NFSV3SATTRTIME_TOSERVER); + } + } else { + NFSM_BUILD(tl, u_int32_t *, NFSX_UNSIGNED); + *tl = txdr_unsigned(NFSV3SATTRTIME_DONTCHANGE); + } + break; + case ND_NFSV4: + NFSZERO_ATTRBIT(&attrbits); + if (vap->va_mode != (mode_t)VNOVAL) + NFSSETBIT_ATTRBIT(&attrbits, NFSATTRBIT_MODE); + if ((flags & NFSSATTR_FULL) && vap->va_uid != (uid_t)VNOVAL) + NFSSETBIT_ATTRBIT(&attrbits, NFSATTRBIT_OWNER); + if ((flags & NFSSATTR_FULL) && vap->va_gid != (gid_t)VNOVAL) + NFSSETBIT_ATTRBIT(&attrbits, NFSATTRBIT_OWNERGROUP); + if ((flags & NFSSATTR_FULL) && vap->va_size != VNOVAL) + NFSSETBIT_ATTRBIT(&attrbits, NFSATTRBIT_SIZE); + if (vap->va_atime.tv_sec != VNOVAL) + NFSSETBIT_ATTRBIT(&attrbits, NFSATTRBIT_TIMEACCESSSET); + if (vap->va_mtime.tv_sec != VNOVAL) + NFSSETBIT_ATTRBIT(&attrbits, NFSATTRBIT_TIMEMODIFYSET); + (void) nfsv4_fillattr(nd, vp->v_mount, vp, NULL, vap, NULL, 0, + &attrbits, NULL, NULL, 0, 0, 0, 0, (uint64_t)0, NULL); + break; + } +} #ifndef APPLE /* Index: sys/fs/nfs/nfs_var.h =================================================================== --- sys/fs/nfs/nfs_var.h +++ sys/fs/nfs/nfs_var.h @@ -298,6 +298,11 @@ void nfsrc_trimcache(uint64_t, uint32_t, int); /* nfs_commonsubs.c */ +void nfscl_reqstart(struct nfsrv_descript *, int, struct nfsmount *, + u_int8_t *, int, u_int32_t **, struct nfsclsession *, int, int); +void nfsm_stateidtom(struct nfsrv_descript *, nfsv4stateid_t *, int); +void nfscl_fillsattr(struct nfsrv_descript *, struct vattr *, + vnode_t, int, u_int32_t); void newnfs_init(void); int nfsaddr_match(int, union nethostaddr *, NFSSOCKADDR_T); int nfsaddr2_match(NFSSOCKADDR_T, NFSSOCKADDR_T); @@ -347,11 +352,7 @@ /* nfs_clcomsubs.c */ void nfsm_uiombuf(struct nfsrv_descript *, struct uio *, int); struct mbuf *nfsm_uiombuflist(struct uio *, int, struct mbuf **, char **); -void nfscl_reqstart(struct nfsrv_descript *, int, struct nfsmount *, - u_int8_t *, int, u_int32_t **, struct nfsclsession *, int, int); nfsuint64 *nfscl_getcookie(struct nfsnode *, off_t off, int); -void nfscl_fillsattr(struct nfsrv_descript *, struct vattr *, - vnode_t, int, u_int32_t); u_int8_t *nfscl_getmyip(struct nfsmount *, struct in6_addr *, int *); int nfsm_getfh(struct nfsrv_descript *, struct nfsfh **); int nfscl_mtofh(struct nfsrv_descript *, struct nfsfh **, @@ -363,7 +364,6 @@ int nfsm_loadattr(struct nfsrv_descript *, struct nfsvattr *); int nfscl_request(struct nfsrv_descript *, vnode_t, NFSPROC_T *, struct ucred *, void *); -void nfsm_stateidtom(struct nfsrv_descript *, nfsv4stateid_t *, int); /* nfs_nfsdsubs.c */ void nfsd_fhtovp(struct nfsrv_descript *, struct nfsrvfh *, int, Index: sys/fs/nfs/nfsport.h =================================================================== --- sys/fs/nfs/nfsport.h +++ sys/fs/nfs/nfsport.h @@ -1054,6 +1054,27 @@ */ #define nfsds_failerr(e) ((e) == ENXIO || (e) == EIO) +/* + * Get a pointer to the MDS session, which is always the first element + * in the list. + * This macro can only be safely used when the NFSLOCKMNT() lock is held. + * The inline function can be used when the lock isn't held. + */ +#define NFSMNT_MDSSESSION(m) (&(TAILQ_FIRST(&((m)->nm_sess))->nfsclds_sess)) + +static __inline struct nfsclsession * +nfsmnt_mdssession(struct nfsmount *nmp) +{ + struct nfsclsession *tsep; + + tsep = NULL; + mtx_lock(&nmp->nm_mtx); + if (TAILQ_FIRST(&nmp->nm_sess) != NULL) + tsep = NFSMNT_MDSSESSION(nmp); + mtx_unlock(&nmp->nm_mtx); + return (tsep); +} + #endif /* _KERNEL */ #endif /* _NFS_NFSPORT_H */ Index: sys/fs/nfsclient/nfs_clcomsubs.c =================================================================== --- sys/fs/nfsclient/nfs_clcomsubs.c +++ sys/fs/nfsclient/nfs_clcomsubs.c @@ -49,217 +49,10 @@ extern int ncl_mbuf_mlen; extern enum vtype newnv2tov_type[8]; extern enum vtype nv34tov_type[8]; -extern int nfs_bigreply[NFSV41_NPROCS]; NFSCLSTATEMUTEX; #endif /* !APPLEKEXT */ static nfsuint64 nfs_nullcookie = {{ 0, 0 }}; -static struct { - int op; - int opcnt; - const u_char *tag; - int taglen; -} nfsv4_opmap[NFSV41_NPROCS] = { - { 0, 1, "Null", 4 }, - { NFSV4OP_GETATTR, 1, "Getattr", 7, }, - { NFSV4OP_SETATTR, 2, "Setattr", 7, }, - { NFSV4OP_LOOKUP, 3, "Lookup", 6, }, - { NFSV4OP_ACCESS, 2, "Access", 6, }, - { NFSV4OP_READLINK, 2, "Readlink", 8, }, - { NFSV4OP_READ, 1, "Read", 4, }, - { NFSV4OP_WRITE, 2, "Write", 5, }, - { NFSV4OP_OPEN, 5, "Open", 4, }, - { NFSV4OP_CREATE, 5, "Create", 6, }, - { NFSV4OP_CREATE, 1, "Create", 6, }, - { NFSV4OP_CREATE, 3, "Create", 6, }, - { NFSV4OP_REMOVE, 1, "Remove", 6, }, - { NFSV4OP_REMOVE, 1, "Remove", 6, }, - { NFSV4OP_SAVEFH, 5, "Rename", 6, }, - { NFSV4OP_SAVEFH, 4, "Link", 4, }, - { NFSV4OP_READDIR, 2, "Readdir", 7, }, - { NFSV4OP_READDIR, 2, "Readdir", 7, }, - { NFSV4OP_GETATTR, 1, "Getattr", 7, }, - { NFSV4OP_GETATTR, 1, "Getattr", 7, }, - { NFSV4OP_GETATTR, 1, "Getattr", 7, }, - { NFSV4OP_COMMIT, 2, "Commit", 6, }, - { NFSV4OP_LOOKUPP, 3, "Lookupp", 7, }, - { NFSV4OP_SETCLIENTID, 1, "SetClientID", 11, }, - { NFSV4OP_SETCLIENTIDCFRM, 1, "SetClientIDConfirm", 18, }, - { NFSV4OP_LOCK, 1, "Lock", 4, }, - { NFSV4OP_LOCKU, 1, "LockU", 5, }, - { NFSV4OP_OPEN, 2, "Open", 4, }, - { NFSV4OP_CLOSE, 1, "Close", 5, }, - { NFSV4OP_OPENCONFIRM, 1, "Openconfirm", 11, }, - { NFSV4OP_LOCKT, 1, "LockT", 5, }, - { NFSV4OP_OPENDOWNGRADE, 1, "Opendowngrade", 13, }, - { NFSV4OP_RENEW, 1, "Renew", 5, }, - { NFSV4OP_PUTROOTFH, 1, "Dirpath", 7, }, - { NFSV4OP_RELEASELCKOWN, 1, "Rellckown", 9, }, - { NFSV4OP_DELEGRETURN, 1, "Delegret", 8, }, - { NFSV4OP_DELEGRETURN, 3, "DelegRemove", 11, }, - { NFSV4OP_DELEGRETURN, 7, "DelegRename1", 12, }, - { NFSV4OP_DELEGRETURN, 9, "DelegRename2", 12, }, - { NFSV4OP_GETATTR, 1, "Getacl", 6, }, - { NFSV4OP_SETATTR, 1, "Setacl", 6, }, - { NFSV4OP_EXCHANGEID, 1, "ExchangeID", 10, }, - { NFSV4OP_CREATESESSION, 1, "CreateSession", 13, }, - { NFSV4OP_DESTROYSESSION, 1, "DestroySession", 14, }, - { NFSV4OP_DESTROYCLIENTID, 1, "DestroyClient", 13, }, - { NFSV4OP_FREESTATEID, 1, "FreeStateID", 11, }, - { NFSV4OP_LAYOUTGET, 1, "LayoutGet", 9, }, - { NFSV4OP_GETDEVINFO, 1, "GetDeviceInfo", 13, }, - { NFSV4OP_LAYOUTCOMMIT, 1, "LayoutCommit", 12, }, - { NFSV4OP_LAYOUTRETURN, 1, "LayoutReturn", 12, }, - { NFSV4OP_RECLAIMCOMPL, 1, "ReclaimComplete", 15, }, - { NFSV4OP_WRITE, 1, "WriteDS", 7, }, - { NFSV4OP_READ, 1, "ReadDS", 6, }, - { NFSV4OP_COMMIT, 1, "CommitDS", 8, }, - { NFSV4OP_OPEN, 3, "OpenLayoutGet", 13, }, - { NFSV4OP_OPEN, 8, "CreateLayGet", 12, }, -}; - -/* - * NFS RPCS that have large request message size. - */ -static int nfs_bigrequest[NFSV41_NPROCS] = { - 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 -}; - -/* - * Start building a request. Mostly just put the first file handle in - * place. - */ -APPLESTATIC void -nfscl_reqstart(struct nfsrv_descript *nd, int procnum, struct nfsmount *nmp, - u_int8_t *nfhp, int fhlen, u_int32_t **opcntpp, struct nfsclsession *sep, - int vers, int minorvers) -{ - struct mbuf *mb; - u_int32_t *tl; - int opcnt; - nfsattrbit_t attrbits; - - /* - * First, fill in some of the fields of nd. - */ - nd->nd_slotseq = NULL; - if (vers == NFS_VER4) { - nd->nd_flag = ND_NFSV4 | ND_NFSCL; - if (minorvers == NFSV41_MINORVERSION) - nd->nd_flag |= ND_NFSV41; - } else if (vers == NFS_VER3) - nd->nd_flag = ND_NFSV3 | ND_NFSCL; - else { - if (NFSHASNFSV4(nmp)) { - nd->nd_flag = ND_NFSV4 | ND_NFSCL; - if (NFSHASNFSV4N(nmp)) - nd->nd_flag |= ND_NFSV41; - } else if (NFSHASNFSV3(nmp)) - nd->nd_flag = ND_NFSV3 | ND_NFSCL; - else - nd->nd_flag = ND_NFSV2 | ND_NFSCL; - } - nd->nd_procnum = procnum; - nd->nd_repstat = 0; - - /* - * Get the first mbuf for the request. - */ - if (nfs_bigrequest[procnum]) - NFSMCLGET(mb, M_WAITOK); - else - NFSMGET(mb); - mbuf_setlen(mb, 0); - nd->nd_mreq = nd->nd_mb = mb; - nd->nd_bpos = NFSMTOD(mb, caddr_t); - - /* - * And fill the first file handle into the request. - */ - if (nd->nd_flag & ND_NFSV4) { - opcnt = nfsv4_opmap[procnum].opcnt + - nfsv4_opflag[nfsv4_opmap[procnum].op].needscfh; - if ((nd->nd_flag & ND_NFSV41) != 0) { - opcnt += nfsv4_opflag[nfsv4_opmap[procnum].op].needsseq; - if (procnum == NFSPROC_RENEW) - /* - * For the special case of Renew, just do a - * Sequence Op. - */ - opcnt = 1; - else if (procnum == NFSPROC_WRITEDS || - procnum == NFSPROC_COMMITDS) - /* - * For the special case of a Writeor Commit to - * a DS, the opcnt == 3, for Sequence, PutFH, - * Write/Commit. - */ - opcnt = 3; - } - /* - * What should the tag really be? - */ - (void) nfsm_strtom(nd, nfsv4_opmap[procnum].tag, - nfsv4_opmap[procnum].taglen); - NFSM_BUILD(tl, u_int32_t *, 2 * NFSX_UNSIGNED); - if ((nd->nd_flag & ND_NFSV41) != 0) - *tl++ = txdr_unsigned(NFSV41_MINORVERSION); - else - *tl++ = txdr_unsigned(NFSV4_MINORVERSION); - if (opcntpp != NULL) - *opcntpp = tl; - *tl = txdr_unsigned(opcnt); - if ((nd->nd_flag & ND_NFSV41) != 0 && - nfsv4_opflag[nfsv4_opmap[procnum].op].needsseq > 0) { - if (nfsv4_opflag[nfsv4_opmap[procnum].op].loopbadsess > - 0) - nd->nd_flag |= ND_LOOPBADSESS; - NFSM_BUILD(tl, u_int32_t *, NFSX_UNSIGNED); - *tl = txdr_unsigned(NFSV4OP_SEQUENCE); - if (sep == NULL) { - sep = nfsmnt_mdssession(nmp); - nfsv4_setsequence(nmp, nd, sep, - nfs_bigreply[procnum]); - } else - nfsv4_setsequence(nmp, nd, sep, - nfs_bigreply[procnum]); - } - if (nfsv4_opflag[nfsv4_opmap[procnum].op].needscfh > 0) { - NFSM_BUILD(tl, u_int32_t *, NFSX_UNSIGNED); - *tl = txdr_unsigned(NFSV4OP_PUTFH); - (void) nfsm_fhtom(nd, nfhp, fhlen, 0); - if (nfsv4_opflag[nfsv4_opmap[procnum].op].needscfh - == 2 && procnum != NFSPROC_WRITEDS && - procnum != NFSPROC_COMMITDS) { - NFSM_BUILD(tl, u_int32_t *, NFSX_UNSIGNED); - *tl = txdr_unsigned(NFSV4OP_GETATTR); - /* - * For Lookup Ops, we want all the directory - * attributes, so we can load the name cache. - */ - if (procnum == NFSPROC_LOOKUP || - procnum == NFSPROC_LOOKUPP) - NFSGETATTR_ATTRBIT(&attrbits); - else { - NFSWCCATTR_ATTRBIT(&attrbits); - nd->nd_flag |= ND_V4WCCATTR; - } - (void) nfsrv_putattrbit(nd, &attrbits); - } - } - if (procnum != NFSPROC_RENEW || - (nd->nd_flag & ND_NFSV41) == 0) { - NFSM_BUILD(tl, u_int32_t *, NFSX_UNSIGNED); - *tl = txdr_unsigned(nfsv4_opmap[procnum].op); - } - } else { - (void) nfsm_fhtom(nd, nfhp, fhlen, 0); - } - if (procnum < NFSV41_NPROCS) - NFSINCRGLOBAL(nfsstatsv1.rpccnt[procnum]); -} /* * copies a uio scatter/gather list to an mbuf chain. @@ -430,8 +223,9 @@ NFSM_DISSECT(fp, struct nfs_fattr *, NFSX_V3FATTR); nap->na_type = nfsv34tov_type(fp->fa_type); nap->na_mode = fxdr_unsigned(u_short, fp->fa_mode); - nap->na_rdev = makedev(fxdr_unsigned(u_char, fp->fa3_rdev.specdata1), - fxdr_unsigned(u_char, fp->fa3_rdev.specdata2)); + nap->na_rdev = NFSMAKEDEV( + fxdr_unsigned(int, fp->fa3_rdev.specdata1), + fxdr_unsigned(int, fp->fa3_rdev.specdata2)); nap->na_nlink = fxdr_unsigned(uint32_t, fp->fa_nlink); nap->na_uid = fxdr_unsigned(uid_t, fp->fa_uid); nap->na_gid = fxdr_unsigned(gid_t, fp->fa_gid); @@ -594,38 +388,6 @@ } /* - * Put a state Id in the mbuf list. - */ -APPLESTATIC void -nfsm_stateidtom(struct nfsrv_descript *nd, nfsv4stateid_t *stateidp, int flag) -{ - nfsv4stateid_t *st; - - NFSM_BUILD(st, nfsv4stateid_t *, NFSX_STATEID); - if (flag == NFSSTATEID_PUTALLZERO) { - st->seqid = 0; - st->other[0] = 0; - st->other[1] = 0; - st->other[2] = 0; - } else if (flag == NFSSTATEID_PUTALLONE) { - st->seqid = 0xffffffff; - st->other[0] = 0xffffffff; - st->other[1] = 0xffffffff; - st->other[2] = 0xffffffff; - } else if (flag == NFSSTATEID_PUTSEQIDZERO) { - st->seqid = 0; - st->other[0] = stateidp->other[0]; - st->other[1] = stateidp->other[1]; - st->other[2] = stateidp->other[2]; - } else { - st->seqid = stateidp->seqid; - st->other[0] = stateidp->other[0]; - st->other[1] = stateidp->other[1]; - st->other[2] = stateidp->other[2]; - } -} - -/* * Initialize the owner/delegation sleep lock. */ APPLESTATIC void Index: sys/fs/nfsclient/nfs_clport.c =================================================================== --- sys/fs/nfsclient/nfs_clport.c +++ sys/fs/nfsclient/nfs_clport.c @@ -819,124 +819,6 @@ } /* - * Fill in the setable attributes. The full argument indicates whether - * to fill in them all or just mode and time. - */ -void -nfscl_fillsattr(struct nfsrv_descript *nd, struct vattr *vap, - struct vnode *vp, int flags, u_int32_t rdev) -{ - u_int32_t *tl; - struct nfsv2_sattr *sp; - nfsattrbit_t attrbits; - - switch (nd->nd_flag & (ND_NFSV2 | ND_NFSV3 | ND_NFSV4)) { - case ND_NFSV2: - NFSM_BUILD(sp, struct nfsv2_sattr *, NFSX_V2SATTR); - if (vap->va_mode == (mode_t)VNOVAL) - sp->sa_mode = newnfs_xdrneg1; - else - sp->sa_mode = vtonfsv2_mode(vap->va_type, vap->va_mode); - if (vap->va_uid == (uid_t)VNOVAL) - sp->sa_uid = newnfs_xdrneg1; - else - sp->sa_uid = txdr_unsigned(vap->va_uid); - if (vap->va_gid == (gid_t)VNOVAL) - sp->sa_gid = newnfs_xdrneg1; - else - sp->sa_gid = txdr_unsigned(vap->va_gid); - if (flags & NFSSATTR_SIZE0) - sp->sa_size = 0; - else if (flags & NFSSATTR_SIZENEG1) - sp->sa_size = newnfs_xdrneg1; - else if (flags & NFSSATTR_SIZERDEV) - sp->sa_size = txdr_unsigned(rdev); - else - sp->sa_size = txdr_unsigned(vap->va_size); - txdr_nfsv2time(&vap->va_atime, &sp->sa_atime); - txdr_nfsv2time(&vap->va_mtime, &sp->sa_mtime); - break; - case ND_NFSV3: - if (vap->va_mode != (mode_t)VNOVAL) { - NFSM_BUILD(tl, u_int32_t *, 2 * NFSX_UNSIGNED); - *tl++ = newnfs_true; - *tl = txdr_unsigned(vap->va_mode); - } else { - NFSM_BUILD(tl, u_int32_t *, NFSX_UNSIGNED); - *tl = newnfs_false; - } - if ((flags & NFSSATTR_FULL) && vap->va_uid != (uid_t)VNOVAL) { - NFSM_BUILD(tl, u_int32_t *, 2 * NFSX_UNSIGNED); - *tl++ = newnfs_true; - *tl = txdr_unsigned(vap->va_uid); - } else { - NFSM_BUILD(tl, u_int32_t *, NFSX_UNSIGNED); - *tl = newnfs_false; - } - if ((flags & NFSSATTR_FULL) && vap->va_gid != (gid_t)VNOVAL) { - NFSM_BUILD(tl, u_int32_t *, 2 * NFSX_UNSIGNED); - *tl++ = newnfs_true; - *tl = txdr_unsigned(vap->va_gid); - } else { - NFSM_BUILD(tl, u_int32_t *, NFSX_UNSIGNED); - *tl = newnfs_false; - } - if ((flags & NFSSATTR_FULL) && vap->va_size != VNOVAL) { - NFSM_BUILD(tl, u_int32_t *, 3 * NFSX_UNSIGNED); - *tl++ = newnfs_true; - txdr_hyper(vap->va_size, tl); - } else { - NFSM_BUILD(tl, u_int32_t *, NFSX_UNSIGNED); - *tl = newnfs_false; - } - if (vap->va_atime.tv_sec != VNOVAL) { - if ((vap->va_vaflags & VA_UTIMES_NULL) == 0) { - NFSM_BUILD(tl, u_int32_t *, 3 * NFSX_UNSIGNED); - *tl++ = txdr_unsigned(NFSV3SATTRTIME_TOCLIENT); - txdr_nfsv3time(&vap->va_atime, tl); - } else { - NFSM_BUILD(tl, u_int32_t *, NFSX_UNSIGNED); - *tl = txdr_unsigned(NFSV3SATTRTIME_TOSERVER); - } - } else { - NFSM_BUILD(tl, u_int32_t *, NFSX_UNSIGNED); - *tl = txdr_unsigned(NFSV3SATTRTIME_DONTCHANGE); - } - if (vap->va_mtime.tv_sec != VNOVAL) { - if ((vap->va_vaflags & VA_UTIMES_NULL) == 0) { - NFSM_BUILD(tl, u_int32_t *, 3 * NFSX_UNSIGNED); - *tl++ = txdr_unsigned(NFSV3SATTRTIME_TOCLIENT); - txdr_nfsv3time(&vap->va_mtime, tl); - } else { - NFSM_BUILD(tl, u_int32_t *, NFSX_UNSIGNED); - *tl = txdr_unsigned(NFSV3SATTRTIME_TOSERVER); - } - } else { - NFSM_BUILD(tl, u_int32_t *, NFSX_UNSIGNED); - *tl = txdr_unsigned(NFSV3SATTRTIME_DONTCHANGE); - } - break; - case ND_NFSV4: - NFSZERO_ATTRBIT(&attrbits); - if (vap->va_mode != (mode_t)VNOVAL) - NFSSETBIT_ATTRBIT(&attrbits, NFSATTRBIT_MODE); - if ((flags & NFSSATTR_FULL) && vap->va_uid != (uid_t)VNOVAL) - NFSSETBIT_ATTRBIT(&attrbits, NFSATTRBIT_OWNER); - if ((flags & NFSSATTR_FULL) && vap->va_gid != (gid_t)VNOVAL) - NFSSETBIT_ATTRBIT(&attrbits, NFSATTRBIT_OWNERGROUP); - if ((flags & NFSSATTR_FULL) && vap->va_size != VNOVAL) - NFSSETBIT_ATTRBIT(&attrbits, NFSATTRBIT_SIZE); - if (vap->va_atime.tv_sec != VNOVAL) - NFSSETBIT_ATTRBIT(&attrbits, NFSATTRBIT_TIMEACCESSSET); - if (vap->va_mtime.tv_sec != VNOVAL) - NFSSETBIT_ATTRBIT(&attrbits, NFSATTRBIT_TIMEMODIFYSET); - (void) nfsv4_fillattr(nd, vp->v_mount, vp, NULL, vap, NULL, 0, - &attrbits, NULL, NULL, 0, 0, 0, 0, (uint64_t)0, NULL); - break; - } -} - -/* * nfscl_request() - mostly a wrapper for newnfs_request(). */ int Index: sys/fs/nfsclient/nfsmount.h =================================================================== --- sys/fs/nfsclient/nfsmount.h +++ sys/fs/nfsclient/nfsmount.h @@ -116,27 +116,6 @@ */ #define VFSTONFS(mp) ((struct nfsmount *)((mp)->mnt_data)) -/* - * Get a pointer to the MDS session, which is always the first element - * in the list. - * This macro can only be safely used when the NFSLOCKMNT() lock is held. - * The inline function can be used when the lock isn't held. - */ -#define NFSMNT_MDSSESSION(m) (&(TAILQ_FIRST(&((m)->nm_sess))->nfsclds_sess)) - -static __inline struct nfsclsession * -nfsmnt_mdssession(struct nfsmount *nmp) -{ - struct nfsclsession *tsep; - - tsep = NULL; - mtx_lock(&nmp->nm_mtx); - if (TAILQ_FIRST(&nmp->nm_sess) != NULL) - tsep = NFSMNT_MDSSESSION(nmp); - mtx_unlock(&nmp->nm_mtx); - return (tsep); -} - #ifndef NFS_DEFAULT_NAMETIMEO #define NFS_DEFAULT_NAMETIMEO 60 #endif Index: sys/gnu/dts/arm/am335x-boneblue.dts =================================================================== --- sys/gnu/dts/arm/am335x-boneblue.dts +++ sys/gnu/dts/arm/am335x-boneblue.dts @@ -342,7 +342,7 @@ }; baseboard_eeprom: baseboard_eeprom@50 { - compatible = "at,24c256"; + compatible = "atmel,24c256"; reg = <0x50>; #address-cells = <1>; Index: sys/gnu/dts/arm/am335x-pdu001.dts =================================================================== --- /dev/null +++ sys/gnu/dts/arm/am335x-pdu001.dts @@ -0,0 +1,595 @@ +/* + * pdu001.dts + * + * EETS GmbH PDU001 board device tree file + * + * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/ + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "am33xx.dtsi" +#include +#include + +/ { + model = "EETS,PDU001"; + compatible = "ti,am33xx"; + + chosen { + stdout-path = &uart3; + }; + + cpus { + cpu@0 { + cpu0-supply = <&vdd1_reg>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + vbat: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + regulator-boot-on; + }; + + lis3_reg: fixedregulator@1 { + compatible = "regulator-fixed"; + regulator-name = "lis3_reg"; + regulator-boot-on; + }; + + panel { + compatible = "ti,tilcdc,panel"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins_s0>; + panel-info { + ac-bias = <255>; + ac-bias-intrpt = <0>; + dma-burst-sz = <16>; + bpp = <16>; + fdd = <0x80>; + sync-edge = <0>; + sync-ctrl = <1>; + raster-order = <0>; + fifo-th = <0>; + }; + + display-timings { + 240x320p16 { + clock-frequency = <6500000>; + hactive = <240>; + vactive = <320>; + hfront-porch = <6>; + hback-porch = <6>; + hsync-len = <1>; + vback-porch = <6>; + vfront-porch = <6>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <1>; + de-active = <0>; + }; + }; + }; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&clkout2_pin>; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */ + AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */ + >; + }; + + i2c2_pins: pinmux_i2c2_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_clk.i2c2_sda */ + AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d0.i2c2_scl */ + >; + }; + + spi1_pins: pinmux_spi1_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_sclk */ + AM33XX_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ + AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ + AM33XX_IOPAD(0x99C, PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x96C, PIN_OUTPUT | MUX_MODE7) /* uart0_rtsn.gpio1_9 */ + AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ + AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE1) /* spi0_cs1.uart3_rxd */ + AM33XX_IOPAD(0x964, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */ + >; + }; + + clkout2_pin: pinmux_clkout2_pin { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Port 1 (emac0) */ + AM33XX_IOPAD(0x908, PIN_INPUT | MUX_MODE0) /* mii1_col.mii1_col */ + AM33XX_IOPAD(0x90C, PIN_INPUT | MUX_MODE0) /* mii1_crs.mii1_crs */ + AM33XX_IOPAD(0x910, PIN_INPUT | MUX_MODE0) /* mii1_rxer.mii1_rxer */ + AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE0) /* mii1_txen.mii1_txen */ + AM33XX_IOPAD(0x918, PIN_INPUT | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */ + AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE0) /* mii1_txd3.mii1_txd3 */ + AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE0) /* mii1_txd2.mii1_txd2 */ + AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE0) /* mii1_txd1.mii1_txd1 */ + AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE0) /* mii1_txd0.mii1_txd0 */ + AM33XX_IOPAD(0x92c, PIN_INPUT | MUX_MODE0) /* mii1_txclk.mii1_txclk */ + AM33XX_IOPAD(0x930, PIN_INPUT | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */ + AM33XX_IOPAD(0x934, PIN_INPUT | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */ + AM33XX_IOPAD(0x938, PIN_INPUT | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */ + AM33XX_IOPAD(0x93c, PIN_INPUT | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */ + AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */ + + /* Port 2 (emac1) */ + AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1) /* mii2_txen.gpmc_a0 */ + AM33XX_IOPAD(0x844, PIN_INPUT | MUX_MODE1) /* mii2_rxdv.gpmc_a1 */ + AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1) /* mii2_txd3.gpmc_a2 */ + AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE1) /* mii2_txd2.gpmc_a3 */ + AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1) /* mii2_txd1.gpmc_a4 */ + AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1) /* mii2_txd0.gpmc_a5 */ + AM33XX_IOPAD(0x858, PIN_INPUT | MUX_MODE1) /* mii2_txclk.gpmc_a6 */ + AM33XX_IOPAD(0x85c, PIN_INPUT | MUX_MODE1) /* mii2_rxclk.gpmc_a7 */ + AM33XX_IOPAD(0x860, PIN_INPUT | MUX_MODE1) /* mii2_rxd3.gpmc_a8 */ + AM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE1) /* mii2_rxd2.gpmc_a9 */ + AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE1) /* mii2_rxd1.gpmc_a10 */ + AM33XX_IOPAD(0x86C, PIN_INPUT | MUX_MODE1) /* mii2_rxd0.gpmc_a11 */ + AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE1) /* mii2_crs.gpmc_wait0 */ + AM33XX_IOPAD(0x874, PIN_INPUT | MUX_MODE1) /* mii2_rxer.gpmc_wpn */ + AM33XX_IOPAD(0x878, PIN_INPUT | MUX_MODE1) /* mii2_col.gpmc_ben1 */ + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + /* eMMC */ + pinctrl-single,pins = < + AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3 */ + AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2 */ + AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1 */ + AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0 */ + AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk */ + AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd */ + >; + }; + + mmc2_pins: pinmux_mmc2_pins { + /* SD cardcage */ + pinctrl-single,pins = < + AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + /* card change signal for frontpanel SD cardcage */ + AM33XX_IOPAD(0x890, PIN_INPUT | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ + >; + }; + + lcd_pins_s0: lcd_pins_s0 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ + AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ + AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ + AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ + AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ + AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ + AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ + AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ + AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ + AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ + AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ + AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ + AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ + AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ + AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ + AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ + AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */ + AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */ + AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */ + AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ + >; + }; + + dcan0_pins: pinmux_dcan0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */ + AM33XX_IOPAD(0x97c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart1_rtsn.d_can0_rx */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + rts-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + rs485-rts-active-high; + rs485-rts-delay = <0 0>; + linux,rs485-enabled-at-boot-time; + + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@2d { + reg = <0x2d>; + }; + + m2_eeprom: m2_eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + status = "okay"; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + status = "okay"; + clock-frequency = <100000>; + + board_24aa025e48: board_24aa025e48@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + + backplane_24aa025e48: backplane_24aa025e48@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + }; + + pca9532: pca9532@60 { + compatible = "nxp,pca9532"; + reg = <0x60>; + psc0 = <0x97>; + pwm0 = <0x80>; + psc1 = <0x97>; + pwm1 = <0x10>; + + run.red@0 { + type = ; + }; + run.green@1 { + type = ; + default-state = "on"; + }; + s2.red@2 { + type = ; + }; + s2.green@3 { + type = ; + }; + s1.yellow@4 { + type = ; + }; + s1.green@5 { + type = ; + }; + }; + + pca9530: pca9530@61 { + compatible = "nxp,pca9530"; + reg = <0x61>; + + tft-panel@0 { + type = ; + linux,default-trigger = "backlight"; + default-state = "on"; + }; + }; + + mcp79400: mcp79400@6f { + compatible = "microchip,mcp7940x"; + reg = <0x6f>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + status = "okay"; + clock-frequency = <100000>; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + ti,pindir-d0-out-d1-in; + status = "okay"; + + cfaf240320a032t { + compatible = "orisetech,otm3225a"; + reg = <0>; + spi-max-frequency = <1000000>; + // SPI mode 3 + spi-cpol; + spi-cpha; + status = "okay"; + }; +}; + +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&cppi41dma { + status = "okay"; +}; + +/* + * Disable soc's rtc as we have no VBAT for it. This makes the board + * rtc (Microchip MCP79400) the default rtc device 'rtc0'. + */ +&rtc { + status = "disabled"; +}; + +&lcdc { + status = "okay"; +}; + +&elm { + status = "okay"; +}; + +#include "tps65910.dtsi" + +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + regulators { + vrtc_reg: regulator@0 { + regulator-name = "ldo_vrtc"; + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-name = "buck_vdd_ddr"; + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + /* VDD_MPU voltage limits */ + regulator-name = "buck_vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1312500>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + /* VDD_CORE voltage limits */ + regulator-name = "buck_vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-name = "boost_res"; + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-name = "ldo_vdig1"; + regulator-always-on; + }; + + vdig2_reg: regulator@6 { + regulator-name = "ldo_vdig2"; + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-name = "ldo_vpll"; + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-name = "ldo_vdac"; + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-name = "ldo_vaux1"; + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-name = "ldo_vaux2"; + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-name = "ldo_vaux33"; + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-name = "ldo_vmmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vbb_reg: regulator@13 { + regulator-name = "bat_vbb"; + }; + }; +}; + +&mac { + pinctrl-names = "default"; + pinctrl-0 = <&cpsw_default>; + dual_emac; /* no switch, two distinct MACs */ + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&davinci_mdio_default>; + status = "okay"; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + phy-mode = "mii"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <1>; + phy-mode = "mii"; + dual_emac_res_vlan = <2>; +}; + +&tscadc { + status = "okay"; + tsc { + ti,wires = <4>; + ti,x-plate-resistance = <200>; + ti,coordinate-readouts = <5>; + ti,wire-config = <0x01 0x10 0x22 0x33>; + ti,charge-delay = <0x400>; + }; + + adc { + ti,adc-channels = <4 5 6 7>; + }; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmc_reg>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + non-removable; +}; + +&mmc2 { + status = "okay"; + vmmc-supply = <&vmmc_reg>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; +}; + +&sham { + status = "okay"; +}; + +&aes { + status = "okay"; +}; + +&dcan0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dcan0_pins>; +}; Index: sys/gnu/dts/arm/am33xx.dtsi =================================================================== --- sys/gnu/dts/arm/am33xx.dtsi +++ sys/gnu/dts/arm/am33xx.dtsi @@ -147,6 +147,8 @@ mpu { compatible = "ti,omap3-mpu"; ti,hwmods = "mpu"; + pm-sram = <&pm_sram_code + &pm_sram_data>; }; }; @@ -905,6 +907,21 @@ ocmcram: ocmcram@40300000 { compatible = "mmio-sram"; reg = <0x40300000 0x10000>; /* 64k */ + ranges = <0x0 0x40300000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + pm_sram_code: pm-sram-code@0 { + compatible = "ti,sram"; + reg = <0x0 0x1000>; + protect-exec; + }; + + pm_sram_data: pm-sram-data@1000 { + compatible = "ti,sram"; + reg = <0x1000 0x1000>; + pool; + }; }; elm: elm@48080000 { @@ -945,6 +962,10 @@ compatible = "ti,emif-am3352"; reg = <0x4c000000 0x1000000>; ti,hwmods = "emif"; + interrupts = <101>; + sram = <&pm_sram_code + &pm_sram_data>; + ti,no-idle; }; gpmc: gpmc@50000000 { Index: sys/gnu/dts/arm/am4372.dtsi =================================================================== --- sys/gnu/dts/arm/am4372.dtsi +++ sys/gnu/dts/arm/am4372.dtsi @@ -92,6 +92,16 @@ }; }; + soc { + compatible = "ti,omap-infra"; + mpu { + compatible = "ti,omap4-mpu"; + ti,hwmods = "mpu"; + pm-sram = <&pm_sram_code + &pm_sram_data>; + }; + }; + gic: interrupt-controller@48241000 { compatible = "arm,cortex-a9-gic"; interrupt-controller; @@ -143,6 +153,7 @@ #size-cells = <1>; ranges; ti,hwmods = "l3_main"; + ti,no-idle; reg = <0x44000000 0x400000 0x44800000 0x400000>; interrupts = , @@ -237,6 +248,10 @@ compatible = "ti,emif-am4372"; reg = <0x4c000000 0x1000000>; ti,hwmods = "emif"; + interrupts = ; + ti,no-idle; + sram = <&pm_sram_code + &pm_sram_data>; }; edma: edma@49000000 { @@ -1141,6 +1156,21 @@ ocmcram: ocmcram@40300000 { compatible = "mmio-sram"; reg = <0x40300000 0x40000>; /* 256k */ + ranges = <0x0 0x40300000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + + pm_sram_code: pm-sram-code@0 { + compatible = "ti,sram"; + reg = <0x0 0x1000>; + protect-exec; + }; + + pm_sram_data: pm-sram-data@1000 { + compatible = "ti,sram"; + reg = <0x1000 0x1000>; + pool; + }; }; dcan0: can@481cc000 { Index: sys/gnu/dts/arm/am437x-gp-evm.dts =================================================================== --- sys/gnu/dts/arm/am437x-gp-evm.dts +++ sys/gnu/dts/arm/am437x-gp-evm.dts @@ -805,7 +805,7 @@ }; &usb1 { - dr_mode = "peripheral"; + dr_mode = "otg"; status = "okay"; }; Index: sys/gnu/dts/arm/am437x-sk-evm.dts =================================================================== --- sys/gnu/dts/arm/am437x-sk-evm.dts +++ sys/gnu/dts/arm/am437x-sk-evm.dts @@ -600,7 +600,7 @@ }; &usb1 { - dr_mode = "peripheral"; + dr_mode = "otg"; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&usb1_pins>; Index: sys/gnu/dts/arm/am43x-epos-evm.dts =================================================================== --- sys/gnu/dts/arm/am43x-epos-evm.dts +++ sys/gnu/dts/arm/am43x-epos-evm.dts @@ -856,7 +856,7 @@ }; &usb1 { - dr_mode = "peripheral"; + dr_mode = "otg"; status = "okay"; }; Index: sys/gnu/dts/arm/am571x-idk.dts =================================================================== --- sys/gnu/dts/arm/am571x-idk.dts +++ sys/gnu/dts/arm/am571x-idk.dts @@ -10,8 +10,8 @@ #include "dra72x.dtsi" #include #include -#include "am57xx-idk-common.dtsi" #include "dra72x-mmc-iodelay.dtsi" +#include "am57xx-idk-common.dtsi" / { model = "TI AM5718 IDK"; Index: sys/gnu/dts/arm/am572x-idk.dts =================================================================== --- sys/gnu/dts/arm/am572x-idk.dts +++ sys/gnu/dts/arm/am572x-idk.dts @@ -9,9 +9,8 @@ /dts-v1/; #include "dra74x.dtsi" -#include "am572x-idk-common.dtsi" -#include "am57xx-idk-common.dtsi" #include "dra74x-mmc-iodelay.dtsi" +#include "am572x-idk-common.dtsi" / { model = "TI AM5728 IDK"; Index: sys/gnu/dts/arm/am57xx-beagle-x15-common.dtsi =================================================================== --- sys/gnu/dts/arm/am57xx-beagle-x15-common.dtsi +++ sys/gnu/dts/arm/am57xx-beagle-x15-common.dtsi @@ -442,6 +442,7 @@ pinctrl-0 = <&mmc2_pins_default>; vmmc-supply = <&vdd_3v3>; + vqmmc-supply = <&vdd_3v3>; bus-width = <8>; ti,non-removable; cap-mmc-dual-data-rate; Index: sys/gnu/dts/arm/am57xx-idk-common.dtsi =================================================================== --- sys/gnu/dts/arm/am57xx-idk-common.dtsi +++ sys/gnu/dts/arm/am57xx-idk-common.dtsi @@ -115,6 +115,17 @@ DRA7XX_CORE_IOPAD(0x37d4, MUX_MODE15 | PULL_UP) /* dcan1_rx.off */ >; }; + + mmc1_pins_default: mmc1_pins_default { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; }; &i2c1 { @@ -410,6 +421,7 @@ &mmc2 { status = "okay"; vmmc-supply = <&v3_3d>; + vqmmc-supply = <&v3_3d>; bus-width = <8>; ti,non-removable; max-frequency = <96000000>; Index: sys/gnu/dts/arm/animeo_ip.dts =================================================================== --- sys/gnu/dts/arm/animeo_ip.dts +++ sys/gnu/dts/arm/animeo_ip.dts @@ -24,7 +24,7 @@ }; chosen { - linux,stdout-path = &usart2; + stdout-path = &usart2; }; memory { Index: sys/gnu/dts/arm/arm-realview-eb.dtsi =================================================================== --- sys/gnu/dts/arm/arm-realview-eb.dtsi +++ sys/gnu/dts/arm/arm-realview-eb.dtsi @@ -143,6 +143,43 @@ port1-otg; }; + bridge { + compatible = "ti,ths8134a", "ti,ths8134"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vga_bridge_in: endpoint { + remote-endpoint = <&clcd_pads>; + }; + }; + + port@1 { + reg = <1>; + + vga_bridge_out: endpoint { + remote-endpoint = <&vga_con_in>; + }; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + port { + vga_con_in: endpoint { + remote-endpoint = <&vga_bridge_out>; + }; + }; + }; + /* These peripherals are inside the FPGA */ fpga { #address-cells = <1>; @@ -409,36 +446,15 @@ interrupt-names = "combined"; clocks = <&oscclk0>, <&pclk>; clock-names = "clcdclk", "apb_pclk"; + /* 1024x768 16bpp @65MHz works fine */ + max-memory-bandwidth = <95000000>; port { clcd_pads: endpoint { - remote-endpoint = <&clcd_panel>; + remote-endpoint = <&vga_bridge_in>; arm,pl11x,tft-r0g0b0-pads = <0 8 16>; }; }; - - panel { - compatible = "panel-dpi"; - - port { - clcd_panel: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - - /* Standard 640x480 VGA timings */ - panel-timing { - clock-frequency = <25175000>; - hactive = <640>; - hback-porch = <48>; - hfront-porch = <16>; - hsync-len = <96>; - vactive = <480>; - vback-porch = <33>; - vfront-porch = <10>; - vsync-len = <2>; - }; - }; }; }; }; Index: sys/gnu/dts/arm/arm-realview-pb1176.dts =================================================================== --- sys/gnu/dts/arm/arm-realview-pb1176.dts +++ sys/gnu/dts/arm/arm-realview-pb1176.dts @@ -161,6 +161,43 @@ port1-otg; }; + bridge { + compatible = "ti,ths8134a", "ti,ths8134"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vga_bridge_in: endpoint { + remote-endpoint = <&clcd_pads>; + }; + }; + + port@1 { + reg = <1>; + + vga_bridge_out: endpoint { + remote-endpoint = <&vga_con_in>; + }; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + port { + vga_con_in: endpoint { + remote-endpoint = <&vga_bridge_out>; + }; + }; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -403,36 +440,15 @@ interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; clocks = <&oscclk0>, <&pclk>; clock-names = "clcdclk", "apb_pclk"; + /* 1024x768 16bpp @65MHz works fine */ + max-memory-bandwidth = <95000000>; port { clcd_pads: endpoint { - remote-endpoint = <&clcd_panel>; + remote-endpoint = <&vga_bridge_in>; arm,pl11x,tft-r0g0b0-pads = <0 8 16>; }; }; - - panel { - compatible = "panel-dpi"; - - port { - clcd_panel: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - - /* Standard 640x480 VGA timings */ - panel-timing { - clock-frequency = <25175000>; - hactive = <640>; - hback-porch = <48>; - hfront-porch = <16>; - hsync-len = <96>; - vactive = <480>; - vback-porch = <33>; - vfront-porch = <10>; - vsync-len = <2>; - }; - }; }; }; @@ -564,7 +580,5 @@ clocks = <&pclk>; clock-names = "apb_pclk"; }; - - }; }; Index: sys/gnu/dts/arm/arm-realview-pb11mp.dts =================================================================== --- sys/gnu/dts/arm/arm-realview-pb11mp.dts +++ sys/gnu/dts/arm/arm-realview-pb11mp.dts @@ -242,6 +242,49 @@ bank-width = <4>; }; + bridge { + compatible = "ti,ths8134a", "ti,ths8134"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vga_bridge_in: endpoint { + remote-endpoint = <&clcd_pads>; + }; + }; + + port@1 { + reg = <1>; + + vga_bridge_out: endpoint { + remote-endpoint = <&vga_con_in>; + }; + }; + }; + }; + + vga { + /* + * This DDC I2C is connected directly to the DVI portions + * of the connector, so it's not really working when the + * monitor is connected to the VGA connector. + */ + compatible = "vga-connector"; + ddc-i2c-bus = <&i2c1>; + + port { + vga_con_in: endpoint { + remote-endpoint = <&vga_bridge_out>; + }; + }; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -575,6 +618,13 @@ clock-names = "apb_pclk"; }; + i2c1: i2c@10016000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "arm,versatile-i2c"; + reg = <0x10016000 0x1000>; + }; + rtc: rtc@10017000 { compatible = "arm,pl031", "arm,primecell"; reg = <0x10017000 0x1000>; @@ -609,37 +659,15 @@ interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&oscclk4>, <&pclk>; clock-names = "clcdclk", "apb_pclk"; - max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */ + /* 1024x768 16bpp @65MHz works fine */ + max-memory-bandwidth = <95000000>; port { clcd_pads: endpoint { - remote-endpoint = <&clcd_panel>; + remote-endpoint = <&vga_bridge_in>; arm,pl11x,tft-r0g0b0-pads = <0 8 16>; }; }; - - panel { - compatible = "panel-dpi"; - - port { - clcd_panel: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - - /* Standard 640x480 VGA timings */ - panel-timing { - clock-frequency = <25175000>; - hactive = <640>; - hback-porch = <48>; - hfront-porch = <16>; - hsync-len = <96>; - vactive = <480>; - vback-porch = <33>; - vfront-porch = <10>; - vsync-len = <2>; - }; - }; }; /* Index: sys/gnu/dts/arm/arm-realview-pbx.dtsi =================================================================== --- sys/gnu/dts/arm/arm-realview-pbx.dtsi +++ sys/gnu/dts/arm/arm-realview-pbx.dtsi @@ -34,7 +34,8 @@ serial1 = &serial1; serial2 = &serial2; serial3 = &serial3; - i2c0 = &i2c; + i2c0 = &i2c0; + i2c1 = &i2c1; }; memory { @@ -158,6 +159,49 @@ port1-otg; }; + bridge { + compatible = "ti,ths8134a", "ti,ths8134"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vga_bridge_in: endpoint { + remote-endpoint = <&clcd_pads>; + }; + }; + + port@1 { + reg = <1>; + + vga_bridge_out: endpoint { + remote-endpoint = <&vga_con_in>; + }; + }; + }; + }; + + vga { + /* + * This DDC I2C is connected directly to the DVI portions + * of the connector, so it's not really working when the + * monitor is connected to the VGA connector. + */ + compatible = "vga-connector"; + ddc-i2c-bus = <&i2c1>; + + port { + vga_con_in: endpoint { + remote-endpoint = <&vga_bridge_out>; + }; + }; + }; + soc: soc@0 { compatible = "arm,realview-pbx-soc", "simple-bus"; #address-cells = <1>; @@ -285,7 +329,7 @@ <&timclk>; }; - i2c: i2c@10002000 { + i2c0: i2c@10002000 { #address-cells = <1>; #size-cells = <0>; compatible = "arm,versatile-i2c"; @@ -396,7 +440,12 @@ clock-names = "apb_pclk"; }; - /* DVI serial bus control is at 10016000 */ + i2c1: i2c@10016000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "arm,versatile-i2c"; + reg = <0x10016000 0x1000>; + }; rtc: rtc@10017000 { compatible = "arm,pl031", "arm,primecell"; @@ -506,36 +555,15 @@ interrupt-names = "combined"; clocks = <&oscclk4>, <&pclk>; clock-names = "clcdclk", "apb_pclk"; + /* 1024x768 16bpp @65MHz works fine */ + max-memory-bandwidth = <95000000>; port { clcd_pads: endpoint { - remote-endpoint = <&clcd_panel>; + remote-endpoint = <&vga_bridge_in>; arm,pl11x,tft-r0g0b0-pads = <0 8 16>; }; }; - - panel { - compatible = "panel-dpi"; - - port { - clcd_panel: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - - /* Standard 640x480 VGA timings */ - panel-timing { - clock-frequency = <25175000>; - hactive = <640>; - hback-porch = <48>; - hfront-porch = <16>; - hsync-len = <96>; - vactive = <480>; - vback-porch = <33>; - vfront-porch = <10>; - vsync-len = <2>; - }; - }; }; }; }; Index: sys/gnu/dts/arm/armada-370-db.dts =================================================================== --- sys/gnu/dts/arm/armada-370-db.dts +++ sys/gnu/dts/arm/armada-370-db.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Marvell Armada 370 evaluation board * (DB-88F6710-BP-DDR3) @@ -8,44 +9,6 @@ * Gregory CLEMENT * Thomas Petazzoni * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * * Note: this Device Tree assumes that the bootloader has remapped the * internal registers to 0xf1000000 (instead of the default * 0xd0000000). The 0xf1000000 is the default used by the recent, Index: sys/gnu/dts/arm/armada-370-dlink-dns327l.dts =================================================================== --- sys/gnu/dts/arm/armada-370-dlink-dns327l.dts +++ sys/gnu/dts/arm/armada-370-dlink-dns327l.dts @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for D-Link DNS-327L * * Copyright (C) 2015, Andrew Andrianov - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /* Remaining unsolved: Index: sys/gnu/dts/arm/armada-370-mirabox.dts =================================================================== --- sys/gnu/dts/arm/armada-370-mirabox.dts +++ sys/gnu/dts/arm/armada-370-mirabox.dts @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Globalscale Mirabox * * Gregory CLEMENT - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; Index: sys/gnu/dts/arm/armada-370-netgear-rn102.dts =================================================================== --- sys/gnu/dts/arm/armada-370-netgear-rn102.dts +++ sys/gnu/dts/arm/armada-370-netgear-rn102.dts @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for NETGEAR ReadyNAS 102 * * Copyright (C) 2013, Arnaud EBALARD - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; @@ -103,7 +66,7 @@ status = "okay"; - isl12057: isl12057@68 { + isl12057: rtc@68 { compatible = "isil,isl12057"; reg = <0x68>; wakeup-source; Index: sys/gnu/dts/arm/armada-370-netgear-rn104.dts =================================================================== --- sys/gnu/dts/arm/armada-370-netgear-rn104.dts +++ sys/gnu/dts/arm/armada-370-netgear-rn104.dts @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for NETGEAR ReadyNAS 104 * * Copyright (C) 2013, Arnaud EBALARD - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; @@ -105,7 +68,7 @@ status = "okay"; - isl12057: isl12057@68 { + isl12057: rtc@68 { compatible = "isil,isl12057"; reg = <0x68>; wakeup-source; Index: sys/gnu/dts/arm/armada-370-rd.dts =================================================================== --- sys/gnu/dts/arm/armada-370-rd.dts +++ sys/gnu/dts/arm/armada-370-rd.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Marvell Armada 370 Reference Design board * (RD-88F6710-A1) @@ -6,44 +7,6 @@ * * Copyright (C) 2013 Florian Fainelli * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * * Note: this Device Tree assumes that the bootloader has remapped the * internal registers to 0xf1000000 (instead of the default * 0xd0000000). The 0xf1000000 is the default used by the recent, @@ -56,6 +19,7 @@ /dts-v1/; #include +#include #include #include "armada-370.dtsi" @@ -243,6 +207,8 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x10>; + interrupt-controller; + #interrupt-cells = <2>; ports { #address-cells = <1>; @@ -278,6 +244,35 @@ }; }; }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switchphy0: switchphy@0 { + reg = <0>; + interrupt-parent = <&switch>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + }; + + switchphy1: switchphy@1 { + reg = <1>; + interrupt-parent = <&switch>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + }; + + switchphy2: switchphy@2 { + reg = <2>; + interrupt-parent = <&switch>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + }; + + switchphy3: switchphy@3 { + reg = <3>; + interrupt-parent = <&switch>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; + }; + }; }; }; Index: sys/gnu/dts/arm/armada-370-seagate-nas-2bay.dts =================================================================== --- sys/gnu/dts/arm/armada-370-seagate-nas-2bay.dts +++ sys/gnu/dts/arm/armada-370-seagate-nas-2bay.dts @@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree file for Seagate NAS 2-Bay (Armada 370 SoC). * * Copyright (C) 2015 Seagate * * Author: Vincent Donnefort - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /* Index: sys/gnu/dts/arm/armada-370-seagate-nas-4bay.dts =================================================================== --- sys/gnu/dts/arm/armada-370-seagate-nas-4bay.dts +++ sys/gnu/dts/arm/armada-370-seagate-nas-4bay.dts @@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree file for Seagate NAS 4-Bay (Armada 370 SoC). * * Copyright (C) 2015 Seagate * * Author: Vincent Donnefort - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /* Index: sys/gnu/dts/arm/armada-370-seagate-nas-xbay.dtsi =================================================================== --- sys/gnu/dts/arm/armada-370-seagate-nas-xbay.dtsi +++ sys/gnu/dts/arm/armada-370-seagate-nas-xbay.dtsi @@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree common file for the Seagate NAS 2 and 4-bay (Armada 370 SoC). * * Copyright (C) 2015 Seagate * * Author: Vincent Donnefort - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /* Index: sys/gnu/dts/arm/armada-370-seagate-personal-cloud-2bay.dts =================================================================== --- sys/gnu/dts/arm/armada-370-seagate-personal-cloud-2bay.dts +++ sys/gnu/dts/arm/armada-370-seagate-personal-cloud-2bay.dts @@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree file for Seagate Personal Cloud NAS 2-Bay (Armada 370 SoC). * * Copyright (C) 2015 Seagate * * Author: Simon Guinot - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /* Index: sys/gnu/dts/arm/armada-370-seagate-personal-cloud.dts =================================================================== --- sys/gnu/dts/arm/armada-370-seagate-personal-cloud.dts +++ sys/gnu/dts/arm/armada-370-seagate-personal-cloud.dts @@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree file for Seagate Personal Cloud NAS (Armada 370 SoC). * * Copyright (C) 2015 Seagate * * Author: Simon Guinot - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /* Index: sys/gnu/dts/arm/armada-370-seagate-personal-cloud.dtsi =================================================================== --- sys/gnu/dts/arm/armada-370-seagate-personal-cloud.dtsi +++ sys/gnu/dts/arm/armada-370-seagate-personal-cloud.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree common file for the Seagate Personal Cloud NAS 1 and 2-Bay * (Armada 370 SoC). @@ -5,10 +6,6 @@ * Copyright (C) 2015 Seagate * * Author: Simon Guinot - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /* Index: sys/gnu/dts/arm/armada-370-synology-ds213j.dts =================================================================== --- sys/gnu/dts/arm/armada-370-synology-ds213j.dts +++ sys/gnu/dts/arm/armada-370-synology-ds213j.dts @@ -1,46 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Synology DS213j * * Copyright (C) 2014, Arnaud EBALARD * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * * Note: this Device Tree assumes that the bootloader has remapped the * internal registers to 0xf1000000 (instead of the old 0xd0000000). * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot Index: sys/gnu/dts/arm/armada-370-xp.dtsi =================================================================== --- sys/gnu/dts/arm/armada-370-xp.dtsi +++ sys/gnu/dts/arm/armada-370-xp.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell Armada 370 and Armada XP SoC * @@ -8,44 +9,6 @@ * Thomas Petazzoni * Ben Dooks * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * * This file contains the definitions that are common to the Armada * 370 and Armada XP SoC. */ Index: sys/gnu/dts/arm/armada-370.dtsi =================================================================== --- sys/gnu/dts/arm/armada-370.dtsi +++ sys/gnu/dts/arm/armada-370.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell Armada 370 family SoC * @@ -7,44 +8,6 @@ * Gregory CLEMENT * Thomas Petazzoni * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * * Contains definitions specific to the Armada 370 SoC that are not * common to all Armada SoCs. */ Index: sys/gnu/dts/arm/armada-375-db.dts =================================================================== --- sys/gnu/dts/arm/armada-375-db.dts +++ sys/gnu/dts/arm/armada-375-db.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Marvell Armada 375 evaluation board * (DB-88F6720) @@ -6,44 +7,6 @@ * * Gregory CLEMENT * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; Index: sys/gnu/dts/arm/armada-375.dtsi =================================================================== --- sys/gnu/dts/arm/armada-375.dtsi +++ sys/gnu/dts/arm/armada-375.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell Armada 375 family SoC * @@ -5,44 +6,6 @@ * * Gregory CLEMENT * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include Index: sys/gnu/dts/arm/armada-380.dtsi =================================================================== --- sys/gnu/dts/arm/armada-380.dtsi +++ sys/gnu/dts/arm/armada-380.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell Armada 380 SoC. * @@ -6,44 +7,6 @@ * Lior Amsalem * Gregory CLEMENT * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include "armada-38x.dtsi" Index: sys/gnu/dts/arm/armada-385-db-ap.dts =================================================================== --- sys/gnu/dts/arm/armada-385-db-ap.dts +++ sys/gnu/dts/arm/armada-385-db-ap.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree file for Marvell Armada 385 Access Point Development board * (DB-88F6820-AP) @@ -5,38 +6,6 @@ * Copyright (C) 2014 Marvell * * Nadav Haklai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; Index: sys/gnu/dts/arm/armada-385-linksys-caiman.dts =================================================================== --- sys/gnu/dts/arm/armada-385-linksys-caiman.dts +++ sys/gnu/dts/arm/armada-385-linksys-caiman.dts @@ -1,40 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree include for the Linksys WRT1200AC (Caiman) * * Copyright (C) 2015 Imre Kaloz - * - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; Index: sys/gnu/dts/arm/armada-385-linksys-cobra.dts =================================================================== --- sys/gnu/dts/arm/armada-385-linksys-cobra.dts +++ sys/gnu/dts/arm/armada-385-linksys-cobra.dts @@ -1,40 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree file for the Linksys WRT1900ACv2 (Cobra) * * Copyright (C) 2015 Imre Kaloz - * - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; Index: sys/gnu/dts/arm/armada-385-linksys-rango.dts =================================================================== --- sys/gnu/dts/arm/armada-385-linksys-rango.dts +++ sys/gnu/dts/arm/armada-385-linksys-rango.dts @@ -1,40 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree file for the Linksys WRT3200ACM (Rango) * * Copyright (C) 2016 Imre Kaloz - * - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; Index: sys/gnu/dts/arm/armada-385-linksys-shelby.dts =================================================================== --- sys/gnu/dts/arm/armada-385-linksys-shelby.dts +++ sys/gnu/dts/arm/armada-385-linksys-shelby.dts @@ -1,40 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree file for the Linksys WRT1900ACS (Shelby) * * Copyright (C) 2015 Imre Kaloz - * - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; Index: sys/gnu/dts/arm/armada-385-linksys.dtsi =================================================================== --- sys/gnu/dts/arm/armada-385-linksys.dtsi +++ sys/gnu/dts/arm/armada-385-linksys.dtsi @@ -1,40 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree include file for Armada 385 based Linksys boards * * Copyright (C) 2015 Imre Kaloz - * - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include @@ -282,3 +250,8 @@ status = "okay"; usb-phy = <&usb3_1_phy>; }; + +&rtc { + /* No crystal connected to the internal RTC */ + status = "disabled"; +}; Index: sys/gnu/dts/arm/armada-385-synology-ds116.dts =================================================================== --- sys/gnu/dts/arm/armada-385-synology-ds116.dts +++ sys/gnu/dts/arm/armada-385-synology-ds116.dts @@ -1,39 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree file for Synology DS116 NAS * * Copyright (C) 2017 Willy Tarreau - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; Index: sys/gnu/dts/arm/armada-385-turris-omnia.dts =================================================================== --- sys/gnu/dts/arm/armada-385-turris-omnia.dts +++ sys/gnu/dts/arm/armada-385-turris-omnia.dts @@ -1,43 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree file for the Turris Omnia * * Copyright (C) 2016 Uwe Kleine-König * Copyright (C) 2016 Tomas Hlavacek * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* * Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf */ Index: sys/gnu/dts/arm/armada-385.dtsi =================================================================== --- sys/gnu/dts/arm/armada-385.dtsi +++ sys/gnu/dts/arm/armada-385.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell Armada 385 SoC. * @@ -6,44 +7,6 @@ * Lior Amsalem * Gregory CLEMENT * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include "armada-38x.dtsi" Index: sys/gnu/dts/arm/armada-388-clearfog-base.dts =================================================================== --- sys/gnu/dts/arm/armada-388-clearfog-base.dts +++ sys/gnu/dts/arm/armada-388-clearfog-base.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree file for SolidRun Clearfog Base revision A1 rev 2.0 (88F6828) * @@ -7,43 +8,6 @@ * the A1 rev 2.0 of the board, which does not represent final * production board. Things will change, don't expect this file to * remain compatible info the future. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; Index: sys/gnu/dts/arm/armada-388-clearfog-pro.dts =================================================================== --- sys/gnu/dts/arm/armada-388-clearfog-pro.dts +++ sys/gnu/dts/arm/armada-388-clearfog-pro.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828) * @@ -7,43 +8,6 @@ * the A1 rev 2.0 of the board, which does not represent final * production board. Things will change, don't expect this file to * remain compatible info the future. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include "armada-388-clearfog.dts" Index: sys/gnu/dts/arm/armada-388-clearfog.dts =================================================================== --- sys/gnu/dts/arm/armada-388-clearfog.dts +++ sys/gnu/dts/arm/armada-388-clearfog.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828) * @@ -7,43 +8,6 @@ * the A1 rev 2.0 of the board, which does not represent final * production board. Things will change, don't expect this file to * remain compatible info the future. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; Index: sys/gnu/dts/arm/armada-388-clearfog.dtsi =================================================================== --- sys/gnu/dts/arm/armada-388-clearfog.dtsi +++ sys/gnu/dts/arm/armada-388-clearfog.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree include file for SolidRun Clearfog 88F6828 based boards * @@ -7,43 +8,6 @@ * the A1 rev 2.0 of the board, which does not represent final * production board. Things will change, don't expect this file to * remain compatible info the future. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include "armada-388.dtsi" @@ -117,6 +81,16 @@ }; }; }; + + sfp: sfp { + compatible = "sff,sfp"; + i2c-bus = <&i2c1>; + los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <2000>; + }; }; ð1 { @@ -133,18 +107,14 @@ bm,pool-long = <3>; bm,pool-short = <1>; buffer-manager = <&bm>; + managed = "in-band-status"; phy-mode = "sgmii"; + sfp = <&sfp>; status = "okay"; - - fixed-link { - speed = <1000>; - full-duplex; - }; }; &i2c0 { - /* Is there anything on this? */ - clock-frequency = <100000>; + clock-frequency = <400000>; pinctrl-0 = <&i2c0_pins>; pinctrl-names = "default"; status = "okay"; @@ -209,43 +179,13 @@ output-low; line-name = "m.2 devslp"; }; - sfp_los { - /* SFP loss of signal */ - gpio-hog; - gpios = <12 GPIO_ACTIVE_HIGH>; - input; - line-name = "sfp-los"; - }; - sfp_tx_fault { - /* SFP laser fault */ - gpio-hog; - gpios = <13 GPIO_ACTIVE_HIGH>; - input; - line-name = "sfp-tx-fault"; - }; - sfp_tx_disable { - /* SFP transmit disable */ - gpio-hog; - gpios = <14 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "sfp-tx-disable"; - }; - sfp_mod_def0 { - /* SFP module present */ - gpio-hog; - gpios = <15 GPIO_ACTIVE_LOW>; - input; - line-name = "sfp-mod-def0"; - }; }; - /* The MCP3021 is 100kHz clock only */ + /* The MCP3021 supports standard and fast modes */ mikrobus_adc: mcp3021@4c { compatible = "microchip,mcp3021"; reg = <0x4c>; }; - - /* Also something at 0x64 */ }; &i2c1 { Index: sys/gnu/dts/arm/armada-388-db.dts =================================================================== --- sys/gnu/dts/arm/armada-388-db.dts +++ sys/gnu/dts/arm/armada-388-db.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Marvell Armada 388 evaluation board * (DB-88F6820) @@ -5,44 +6,6 @@ * Copyright (C) 2014 Marvell * * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; Index: sys/gnu/dts/arm/armada-388-gp.dts =================================================================== --- sys/gnu/dts/arm/armada-388-gp.dts +++ sys/gnu/dts/arm/armada-388-gp.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree file for Marvell Armada 385 development board * (RD-88F6820-GP) @@ -5,38 +6,6 @@ * Copyright (C) 2014 Marvell * * Gregory CLEMENT - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; Index: sys/gnu/dts/arm/armada-388-rd.dts =================================================================== --- sys/gnu/dts/arm/armada-388-rd.dts +++ sys/gnu/dts/arm/armada-388-rd.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Marvell Armada 388 Reference Design board * (RD-88F6820-AP) @@ -6,44 +7,6 @@ * * Gregory CLEMENT * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; Index: sys/gnu/dts/arm/armada-388.dtsi =================================================================== --- sys/gnu/dts/arm/armada-388.dtsi +++ sys/gnu/dts/arm/armada-388.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell Armada 388 SoC. * @@ -5,39 +6,6 @@ * * Gregory CLEMENT * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * * The main difference with the Armada 385 is that the 388 can handle two more * SATA ports. So we can reuse the dtsi of the Armada 385, override the pinctrl * property and the name of the SoC, and add the second SATA host which control Index: sys/gnu/dts/arm/armada-38x-solidrun-microsom.dtsi =================================================================== --- sys/gnu/dts/arm/armada-38x-solidrun-microsom.dtsi +++ sys/gnu/dts/arm/armada-38x-solidrun-microsom.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree file for SolidRun Armada 38x Microsom * @@ -7,43 +8,6 @@ * the A1 rev 2.0 of the board, which does not represent final * production board. Things will change, don't expect this file to * remain compatible info the future. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include #include Index: sys/gnu/dts/arm/armada-38x.dtsi =================================================================== --- sys/gnu/dts/arm/armada-38x.dtsi +++ sys/gnu/dts/arm/armada-38x.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell Armada 38x family of SoCs. * @@ -6,44 +7,6 @@ * Lior Amsalem * Gregory CLEMENT * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include "skeleton.dtsi" Index: sys/gnu/dts/arm/armada-390-db.dts =================================================================== --- sys/gnu/dts/arm/armada-390-db.dts +++ sys/gnu/dts/arm/armada-390-db.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Marvell Armada 390 Development Board * (DB-88F6920) @@ -5,44 +6,6 @@ * Copyright (C) 2016 Marvell * * Grzegorz Jaszczyk - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; Index: sys/gnu/dts/arm/armada-390.dtsi =================================================================== --- sys/gnu/dts/arm/armada-390.dtsi +++ sys/gnu/dts/arm/armada-390.dtsi @@ -1,47 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell Armada 390 SoC. * * Copyright (C) 2015 Marvell * * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include "armada-39x.dtsi" Index: sys/gnu/dts/arm/armada-395-gp.dts =================================================================== --- sys/gnu/dts/arm/armada-395-gp.dts +++ sys/gnu/dts/arm/armada-395-gp.dts @@ -1,41 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree file for Marvell Armada 395 GP board * * Copyright (C) 2016 Marvell * * Grzegorz Jaszczyk - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; Index: sys/gnu/dts/arm/armada-395.dtsi =================================================================== --- sys/gnu/dts/arm/armada-395.dtsi +++ sys/gnu/dts/arm/armada-395.dtsi @@ -1,47 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell Armada 395 SoC. * * Copyright (C) 2016 Marvell * * Grzegorz Jaszczyk - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include "armada-39x.dtsi" Index: sys/gnu/dts/arm/armada-398-db.dts =================================================================== --- sys/gnu/dts/arm/armada-398-db.dts +++ sys/gnu/dts/arm/armada-398-db.dts @@ -1,47 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell Armada 398 Development Board * * Copyright (C) 2015 Marvell * * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; Index: sys/gnu/dts/arm/armada-398.dtsi =================================================================== --- sys/gnu/dts/arm/armada-398.dtsi +++ sys/gnu/dts/arm/armada-398.dtsi @@ -1,47 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell Armada 398 SoC. * * Copyright (C) 2015 Marvell * * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include "armada-395.dtsi" Index: sys/gnu/dts/arm/armada-39x.dtsi =================================================================== --- sys/gnu/dts/arm/armada-39x.dtsi +++ sys/gnu/dts/arm/armada-39x.dtsi @@ -1,47 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell Armada 39x family of SoCs. * * Copyright (C) 2015 Marvell * * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include "skeleton.dtsi" Index: sys/gnu/dts/arm/armada-xp-98dx3236.dtsi =================================================================== --- sys/gnu/dts/arm/armada-xp-98dx3236.dtsi +++ sys/gnu/dts/arm/armada-xp-98dx3236.dtsi @@ -1,46 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell 98dx3236 family SoC * * Copyright (C) 2016 Allied Telesis Labs * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * * Contains definitions specific to the 98dx3236 SoC that are not * common to all Armada XP SoCs. */ Index: sys/gnu/dts/arm/armada-xp-98dx3336.dtsi =================================================================== --- sys/gnu/dts/arm/armada-xp-98dx3336.dtsi +++ sys/gnu/dts/arm/armada-xp-98dx3336.dtsi @@ -1,46 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell 98dx3336 family SoC * * Copyright (C) 2016 Allied Telesis Labs * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * * Contains definitions specific to the 98dx3236 SoC that are not * common to all Armada XP SoCs. */ Index: sys/gnu/dts/arm/armada-xp-98dx4251.dtsi =================================================================== --- sys/gnu/dts/arm/armada-xp-98dx4251.dtsi +++ sys/gnu/dts/arm/armada-xp-98dx4251.dtsi @@ -1,46 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell 98dx4521 family SoC * * Copyright (C) 2016 Allied Telesis Labs * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * * Contains definitions specific to the 98dx4521 SoC that are not * common to all Armada XP SoCs. */ Index: sys/gnu/dts/arm/armada-xp-axpwifiap.dts =================================================================== --- sys/gnu/dts/arm/armada-xp-axpwifiap.dts +++ sys/gnu/dts/arm/armada-xp-axpwifiap.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Marvell RD-AXPWiFiAP. * @@ -9,44 +10,6 @@ * Copyright (C) 2013 Marvell * * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; Index: sys/gnu/dts/arm/armada-xp-db-dxbc2.dts =================================================================== --- sys/gnu/dts/arm/armada-xp-db-dxbc2.dts +++ sys/gnu/dts/arm/armada-xp-db-dxbc2.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for DB-DXBC2 board * @@ -5,44 +6,6 @@ * * Based on armada-xp-db.dts * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * * Note: this Device Tree assumes that the bootloader has remapped the * internal registers to 0xf1000000 (instead of the default * 0xd0000000). The 0xf1000000 is the default used by the recent, Index: sys/gnu/dts/arm/armada-xp-db-xc3-24g4xg.dts =================================================================== --- sys/gnu/dts/arm/armada-xp-db-xc3-24g4xg.dts +++ sys/gnu/dts/arm/armada-xp-db-xc3-24g4xg.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for DB-XC3-24G4XG board * @@ -5,44 +6,6 @@ * * Based on armada-xp-db.dts * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * * Note: this Device Tree assumes that the bootloader has remapped the * internal registers to 0xf1000000 (instead of the default * 0xd0000000). The 0xf1000000 is the default used by the recent, Index: sys/gnu/dts/arm/armada-xp-db.dts =================================================================== --- sys/gnu/dts/arm/armada-xp-db.dts +++ sys/gnu/dts/arm/armada-xp-db.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Marvell Armada XP evaluation board * (DB-78460-BP) @@ -8,43 +9,6 @@ * Gregory CLEMENT * Thomas Petazzoni * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. * * Note: this Device Tree assumes that the bootloader has remapped the * internal registers to 0xf1000000 (instead of the default Index: sys/gnu/dts/arm/armada-xp-gp.dts =================================================================== --- sys/gnu/dts/arm/armada-xp-gp.dts +++ sys/gnu/dts/arm/armada-xp-gp.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Marvell Armada XP development board * (DB-MV784MP-GP) @@ -8,44 +9,6 @@ * Gregory CLEMENT * Thomas Petazzoni * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * * Note: this Device Tree assumes that the bootloader has remapped the * internal registers to 0xf1000000 (instead of the default * 0xd0000000). The 0xf1000000 is the default used by the recent, Index: sys/gnu/dts/arm/armada-xp-lenovo-ix4-300d.dts =================================================================== --- sys/gnu/dts/arm/armada-xp-lenovo-ix4-300d.dts +++ sys/gnu/dts/arm/armada-xp-lenovo-ix4-300d.dts @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Lenovo Iomega ix4-300d * * Copyright (C) 2014, Benoit Masson - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; Index: sys/gnu/dts/arm/armada-xp-linksys-mamba.dts =================================================================== --- sys/gnu/dts/arm/armada-xp-linksys-mamba.dts +++ sys/gnu/dts/arm/armada-xp-linksys-mamba.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree file for the Linksys WRT1900AC (Mamba). * @@ -13,38 +14,6 @@ * Copyright (C) 2013 Marvell * * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; Index: sys/gnu/dts/arm/armada-xp-matrix.dts =================================================================== --- sys/gnu/dts/arm/armada-xp-matrix.dts +++ sys/gnu/dts/arm/armada-xp-matrix.dts @@ -1,47 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Marvell Armada XP Matrix board * * Copyright (C) 2013 Marvell * * Lior Amsalem - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; Index: sys/gnu/dts/arm/armada-xp-mv78230.dtsi =================================================================== --- sys/gnu/dts/arm/armada-xp-mv78230.dtsi +++ sys/gnu/dts/arm/armada-xp-mv78230.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell Armada XP family SoC * @@ -5,44 +6,6 @@ * * Thomas Petazzoni * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * * Contains definitions specific to the Armada XP MV78230 SoC that are not * common to all Armada XP SoCs. */ Index: sys/gnu/dts/arm/armada-xp-mv78260.dtsi =================================================================== --- sys/gnu/dts/arm/armada-xp-mv78260.dtsi +++ sys/gnu/dts/arm/armada-xp-mv78260.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell Armada XP family SoC * @@ -5,44 +6,6 @@ * * Thomas Petazzoni * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * * Contains definitions specific to the Armada XP MV78260 SoC that are not * common to all Armada XP SoCs. */ Index: sys/gnu/dts/arm/armada-xp-mv78460.dtsi =================================================================== --- sys/gnu/dts/arm/armada-xp-mv78460.dtsi +++ sys/gnu/dts/arm/armada-xp-mv78460.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell Armada XP family SoC * @@ -5,44 +6,6 @@ * * Thomas Petazzoni * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * * Contains definitions specific to the Armada XP MV78460 SoC that are not * common to all Armada XP SoCs. */ Index: sys/gnu/dts/arm/armada-xp-netgear-rn2120.dts =================================================================== --- sys/gnu/dts/arm/armada-xp-netgear-rn2120.dts +++ sys/gnu/dts/arm/armada-xp-netgear-rn2120.dts @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for NETGEAR ReadyNAS 2120 * * Copyright (C) 2013, Arnaud EBALARD - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; @@ -115,7 +78,7 @@ reg = <0x4c>; }; - isl12057: isl12057@68 { + isl12057: rtc@68 { compatible = "isil,isl12057"; reg = <0x68>; wakeup-source; Index: sys/gnu/dts/arm/armada-xp-openblocks-ax3-4.dts =================================================================== --- sys/gnu/dts/arm/armada-xp-openblocks-ax3-4.dts +++ sys/gnu/dts/arm/armada-xp-openblocks-ax3-4.dts @@ -1,47 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for OpenBlocks AX3-4 board * * Copyright (C) 2012 Marvell * * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; Index: sys/gnu/dts/arm/armada-xp-synology-ds414.dts =================================================================== --- sys/gnu/dts/arm/armada-xp-synology-ds414.dts +++ sys/gnu/dts/arm/armada-xp-synology-ds414.dts @@ -1,46 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Synology DS414 * * Copyright (C) 2014, Arnaud EBALARD * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * * Note: this Device Tree assumes that the bootloader has remapped the * internal registers to 0xf1000000 (instead of the old 0xd0000000). * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot Index: sys/gnu/dts/arm/armada-xp.dtsi =================================================================== --- sys/gnu/dts/arm/armada-xp.dtsi +++ sys/gnu/dts/arm/armada-xp.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell Armada XP family SoC * @@ -8,44 +9,6 @@ * Thomas Petazzoni * Ben Dooks * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * * Contains definitions specific to the Armada XP SoC that are not * common to all Armada SoCs. */ Index: sys/gnu/dts/arm/artpec6-devboard.dts =================================================================== --- sys/gnu/dts/arm/artpec6-devboard.dts +++ sys/gnu/dts/arm/artpec6-devboard.dts @@ -26,7 +26,7 @@ memory { device_type = "memory"; - reg = <0x0 0x10000000>; + reg = <0x0 0x40000000>; }; }; @@ -59,6 +59,7 @@ mdio { #address-cells = <0x1>; #size-cells = <0x0>; + compatible = "snps,dwmac-mdio"; phy1: phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; device_type = "ethernet-phy"; Index: sys/gnu/dts/arm/artpec6.dtsi =================================================================== --- sys/gnu/dts/arm/artpec6.dtsi +++ sys/gnu/dts/arm/artpec6.dtsi @@ -41,6 +41,7 @@ */ #include +#include #include #include "skeleton.dtsi" @@ -98,7 +99,7 @@ clock-frequency = <125000000>; }; - clkctrl: clkctrl@0xf8000000 { + clkctrl: clkctrl@f8000000 { #clock-cells = <1>; compatible = "axis,artpec6-clkctrl"; reg = <0xf8000000 0x48>; @@ -153,6 +154,10 @@ interrupt-affinity = <&cpu0>, <&cpu1>; }; + /* + * Both pci nodes cannot be enabled at the same time, + * leave the unwanted node as disabled. + */ pcie: pcie@f8050000 { compatible = "axis,artpec6-pcie", "snps,dw-pcie"; reg = <0xf8050000 0x2000 @@ -180,28 +185,146 @@ status = "disabled"; }; + pcie_ep: pcie_ep@f8050000 { + compatible = "axis,artpec6-pcie-ep", "snps,dw-pcie"; + reg = <0xf8050000 0x2000 + 0xf8051000 0x2000 + 0xf8040000 0x1000 + 0xc0000000 0x20000000>; + reg-names = "dbi", "dbi2", "phy", "addr_space"; + num-ib-windows = <6>; + num-ob-windows = <2>; + num-lanes = <2>; + axis,syscon-pcie = <&syscon>; + status = "disabled"; + }; + + pinctrl: pinctrl@f801d000 { + compatible = "axis,artpec6-pinctrl"; + reg = <0xf801d000 0x400>; + + pinctrl_uart0: uart0grp { + function = "uart0"; + groups = "uart0grp2"; + bias-pull-up; + }; + pinctrl_uart1: uart1grp { + function = "uart1"; + groups = "uart1grp0"; + bias-pull-up; + }; + pinctrl_uart2: uart2grp { + function = "uart2"; + groups = "uart2grp1"; + bias-pull-up; + }; + pinctrl_uart3: uart3grp { + function = "uart3"; + groups = "uart3grp0"; + bias-pull-up; + }; + }; + amba@0 { compatible = "simple-bus"; #address-cells = <0x1>; #size-cells = <0x1>; ranges; - dma-ranges = <0x80000000 0x00000000 0x40000000>; - dma-coherent; + dma-ranges; + + crypto@f4264000 { + compatible = "axis,artpec6-crypto"; + reg = <0xf4264000 0x4000>; + interrupts = ; + }; + + dma0: dma@f8019000 { + compatible = "renesas,nbpfaxi64dmac8b16"; + reg = <0xf8019000 0x400>; + interrupts = , /* error */ + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch12", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&clkctrl ARTPEC6_CLK_DMA_ACLK>; + #dma-cells = <2>; + dma-channels = <8>; + dma-requests = <8>; + }; + dma1: dma@f8019400 { + compatible = "renesas,nbpfaxi64dmac8b16"; + reg = <0xf8019400 0x400>; + interrupts = , /* error */ + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch12", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&clkctrl ARTPEC6_CLK_DMA_ACLK>; + #dma-cells = <2>; + dma-channels = <8>; + dma-requests = <8>; + }; ethernet: ethernet@f8010000 { - clock-names = "phy_ref_clk", "apb_pclk"; - clocks = <ð_phy_ref_clk>, - <&clkctrl ARTPEC6_CLK_ETH_ACLK>; - compatible = "snps,dwc-qos-ethernet-4.10"; - interrupts = ; + clock-names = "stmmaceth", "ptp_ref"; + clocks = <&clkctrl ARTPEC6_CLK_ETH_ACLK>, + <&clkctrl ARTPEC6_CLK_PTP_REF>; + compatible = "snps,dwmac-4.10a", "snps,dwmac"; + interrupts = , + ; + interrupt-names = "macirq", "eth_lpi"; reg = <0xf8010000 0x4000>; - snps,write-requests = <2>; - snps,read-requests = <16>; + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,txpbl = <8>; snps,rxpbl = <2>; + snps,aal; + snps,tso; status = "disabled"; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <1>; + snps,rd_osr_lmt = <15>; + /* If FB is disabled, the AXI master chooses + * a burst length of any value less than the + * maximum enabled burst length + * (all lesser burst length enables are redundant). + */ + snps,blen = <0 0 0 0 16 0 0>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; }; uart0: serial@f8036000 { @@ -211,6 +334,11 @@ clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, <&clkctrl ARTPEC6_CLK_UART_PCLK>; clock-names = "uart_clk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + dmas = <&dma0 4 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>, + <&dma0 5 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>; + dma-names = "rx", "tx"; status = "disabled"; }; uart1: serial@f8037000 { @@ -220,6 +348,11 @@ clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, <&clkctrl ARTPEC6_CLK_UART_PCLK>; clock-names = "uart_clk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + dmas = <&dma0 6 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>, + <&dma0 7 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>; + dma-names = "rx", "tx"; status = "disabled"; }; uart2: serial@f8038000 { @@ -229,6 +362,11 @@ clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, <&clkctrl ARTPEC6_CLK_UART_PCLK>; clock-names = "uart_clk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + dmas = <&dma1 0 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>, + <&dma1 1 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>; + dma-names = "rx", "tx"; status = "disabled"; }; uart3: serial@f8039000 { @@ -238,6 +376,11 @@ clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, <&clkctrl ARTPEC6_CLK_UART_PCLK>; clock-names = "uart_clk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + dmas = <&dma1 2 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>, + <&dma1 3 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>; + dma-names = "rx", "tx"; status = "disabled"; }; }; Index: sys/gnu/dts/arm/aspeed-bmc-arm-centriq2400-rep.dts =================================================================== --- /dev/null +++ sys/gnu/dts/arm/aspeed-bmc-arm-centriq2400-rep.dts @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include + +/ { + model = "Qualcomm Centriq 2400 REP AST2520"; + compatible = "qualcomm,centriq2400-rep-bmc", "aspeed,ast2500"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlyprintk"; + }; + + memory { + reg = <0x80000000 0x40000000>; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 8>; + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 7>; + }; + + leds { + compatible = "gpio-leds"; + + uid_led { + label = "UID_LED"; + gpios = <&gpio ASPEED_GPIO(Q, 5) GPIO_ACTIVE_LOW>; + }; + + ras_error_led { + label = "RAS_ERROR_LED"; + gpios = <&gpio ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>; + }; + + system_fault { + label = "System_fault"; + gpios = <&gpio ASPEED_GPIO(A, 1) GPIO_ACTIVE_LOW>; + }; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + flash@0 { + status = "okay"; + }; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2ck_default + &pinctrl_spi2miso_default + &pinctrl_spi2mosi_default + &pinctrl_spi2cs0_default>; +}; + +&uart3 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>; + current-speed = <115200>; +}; + +&uart5 { + status = "okay"; +}; + +&mac0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + tmp421@1e { + compatible = "ti,tmp421"; + reg = <0x1e>; + }; + tmp421@2a { + compatible = "ti,tmp421"; + reg = <0x2a>; + }; + tmp421@4e { + compatible = "ti,tmp421"; + reg = <0x4e>; + }; + tmp421@1c { + compatible = "ti,tmp421"; + reg = <0x1c>; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; + + tmp421@1d { + compatible = "ti,tmp421"; + reg = <0x1d>; + }; + tmp421@1f { + compatible = "ti,tmp421"; + reg = <0x1f>; + }; + tmp421@4d { + compatible = "ti,tmp421"; + reg = <0x4d>; + }; + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; + nvt210@4c { + compatible = "nvt210"; + reg = <0x4c>; + }; + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + pagesize = <128>; + }; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; + + pca9641@70 { + compatible = "nxp,pca9641"; + reg = <0x70>; + i2c-arb { + #address-cells = <1>; + #size-cells = <0>; + tmp421@1d { + compatible = "tmp421"; + reg = <0x1d>; + }; + adm1278@12 { + compatible = "adi,adm1278"; + reg = <0x12>; + Rsense = <500>; + }; + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + ds1100@58 { + compatible = "ds1100"; + reg = <0x58>; + }; + }; + }; +}; + +&i2c9 { + status = "okay"; +}; + +&vuart { + status = "okay"; +}; + +&gfx { + status = "okay"; +}; + +&pinctrl { + aspeed,external-nodes = <&gfx &lhc>; +}; + +&gpio { + pin_gpio_c7 { + gpio-hog; + gpios = ; + output; + line-name = "BIOS_SPI_MUX_S"; + }; +}; Index: sys/gnu/dts/arm/aspeed-bmc-opp-palmetto.dts =================================================================== --- sys/gnu/dts/arm/aspeed-bmc-opp-palmetto.dts +++ sys/gnu/dts/arm/aspeed-bmc-opp-palmetto.dts @@ -2,6 +2,7 @@ /dts-v1/; #include "aspeed-g4.dtsi" +#include / { model = "Palmetto BMC"; @@ -26,6 +27,32 @@ reg = <0x5f000000 0x01000000>; /* 16M */ }; }; + + leds { + compatible = "gpio-leds"; + + heartbeat { + gpios = <&gpio ASPEED_GPIO(R, 4) GPIO_ACTIVE_LOW>; + }; + + power { + gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>; + }; + + identify { + gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + checkstop { + label = "checkstop"; + gpios = <&gpio ASPEED_GPIO(P, 5) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; }; &fmc { @@ -40,6 +67,9 @@ &spi { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1debug_default>; + flash@0 { status = "okay"; m25p,fast-read; @@ -47,6 +77,29 @@ }; }; +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flbusy_default &pinctrl_flwp_default + + &pinctrl_vgahs_default &pinctrl_vgavs_default + &pinctrl_ddcclk_default &pinctrl_ddcdat_default>; +}; + +&uart1 { + /* Rear RS-232 connector */ + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ndtr1_default + &pinctrl_ndsr1_default + &pinctrl_ncts1_default + &pinctrl_ndcd1_default + &pinctrl_nri1_default>; +}; + &uart5 { status = "okay"; }; @@ -111,3 +164,156 @@ &vuart { status = "okay"; }; + +&ibt { + status = "okay"; +}; + +&gpio { + pin_func_mode0 { + gpio-hog; + gpios = ; + output-low; + line-name = "func_mode0"; + }; + + pin_func_mode1 { + gpio-hog; + gpios = ; + output-low; + line-name = "func_mode1"; + }; + + pin_func_mode2 { + gpio-hog; + gpios = ; + output-low; + line-name = "func_mode2"; + }; + + pin_gpio_a0 { + gpio-hog; + gpios = ; + input; + line-name = "BMC_FAN_RESERVED_N"; + }; + + pin_gpio_a1 { + gpio-hog; + gpios = ; + output-high; + line-name = "APSS_WDT_N"; + }; + + pin_gpio_b1 { + gpio-hog; + gpios = ; + output-high; + line-name = "APSS_BOOT_MODE"; + }; + + pin_gpio_b2 { + gpio-hog; + gpios = ; + output-high; + line-name = "APSS_RESET_N"; + }; + + pin_gpio_b7 { + gpio-hog; + gpios = ; + output-high; + line-name = "SPIVID_STBY_RESET_N"; + }; + + pin_gpio_d1 { + gpio-hog; + gpios = ; + output-high; + line-name = "BMC_POWER_UP"; + }; + + pin_gpio_f1 { + gpio-hog; + gpios = ; + input; + line-name = "BMC_BATTERY_TEST"; + }; + + pin_gpio_f4 { + gpio-hog; + gpios = ; + input; + line-name = "AST_HW_FAULT_N"; + }; + + pin_gpio_f5 { + gpio-hog; + gpios = ; + input; + line-name = "AST_SYS_FAULT_N"; + }; + + pin_gpio_f7 { + gpio-hog; + gpios = ; + output-high; + line-name = "BMC_FULL_SPEED_N"; + }; + + pin_gpio_g3 { + gpio-hog; + gpios = ; + output-high; + line-name = "BMC_FAN_ERROR_N"; + }; + + pin_gpio_g4 { + gpio-hog; + gpios = ; + input; + line-name = "BMC_WDT_RST1_P"; + }; + + pin_gpio_g5 { + gpio-hog; + gpios = ; + input; + line-name = "BMC_WDT_RST2_P"; + }; + + pin_gpio_h0 { + gpio-hog; + gpios = ; + input; + line-name = "PE_SLOT_TEST_EN_N"; + }; + + pin_gpio_h1 { + gpio-hog; + gpios = ; + input; + line-name = "BMC_RTCRST_N"; + }; + + pin_gpio_h2 { + gpio-hog; + gpios = ; + output-high; + line-name = "SYS_PWROK_BMC"; + }; + + pin_gpio_h6 { + gpio-hog; + gpios = ; + output-high; + line-name = "SCM1_FSI0_DATA_EN"; + }; + + pin_gpio_h7 { + gpio-hog; + gpios = ; + output-high; + line-name = "BMC_TPM_INT_N"; + }; +}; Index: sys/gnu/dts/arm/aspeed-bmc-opp-romulus.dts =================================================================== --- sys/gnu/dts/arm/aspeed-bmc-opp-romulus.dts +++ sys/gnu/dts/arm/aspeed-bmc-opp-romulus.dts @@ -184,9 +184,9 @@ &i2c12 { status = "okay"; - max31785@52 { - compatible = "maxim,max31785"; - reg = <0x52>; + w83773g@4c { + compatible = "nuvoton,w83773g"; + reg = <0x4c>; }; }; @@ -203,6 +203,12 @@ output-low; line-name = "nic_func_mode1"; }; + seq_cont { + gpio-hog; + gpios = ; + output-low; + line-name = "seq_cont"; + }; }; &vuart { @@ -257,3 +263,7 @@ aspeed,fan-tach-ch = /bits/ 8 <0x0e>; }; }; + +&ibt { + status = "okay"; +}; Index: sys/gnu/dts/arm/aspeed-bmc-opp-witherspoon.dts =================================================================== --- sys/gnu/dts/arm/aspeed-bmc-opp-witherspoon.dts +++ sys/gnu/dts/arm/aspeed-bmc-opp-witherspoon.dts @@ -546,3 +546,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdtrst1_default>; }; + +&ibt { + status = "okay"; +}; Index: sys/gnu/dts/arm/aspeed-bmc-opp-zaius.dts =================================================================== --- sys/gnu/dts/arm/aspeed-bmc-opp-zaius.dts +++ sys/gnu/dts/arm/aspeed-bmc-opp-zaius.dts @@ -424,3 +424,7 @@ aspeed,fan-tach-ch = /bits/ 8 <0x03>; }; }; + +&ibt { + status = "okay"; +}; Index: sys/gnu/dts/arm/aspeed-g4.dtsi =================================================================== --- sys/gnu/dts/arm/aspeed-g4.dtsi +++ sys/gnu/dts/arm/aspeed-g4.dtsi @@ -167,6 +167,7 @@ reg-shift = <2>; interrupts = <9>; clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; + resets = <&lpc_reset 4>; no-loopback-test; status = "disabled"; }; @@ -238,6 +239,7 @@ lpc_ctrl: lpc-ctrl@0 { compatible = "aspeed,ast2400-lpc-ctrl"; reg = <0x0 0x80>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; @@ -252,6 +254,19 @@ compatible = "aspeed,ast2400-lhc"; reg = <0x20 0x24 0x48 0x8>; }; + + lpc_reset: reset-controller@18 { + compatible = "aspeed,ast2400-lpc-reset"; + reg = <0x18 0x4>; + #reset-cells = <1>; + }; + + ibt: ibt@c0 { + compatible = "aspeed,ast2400-ibt-bmc"; + reg = <0xc0 0x18>; + interrupts = <8>; + status = "disabled"; + }; }; }; @@ -261,6 +276,7 @@ reg-shift = <2>; interrupts = <32>; clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; + resets = <&lpc_reset 5>; no-loopback-test; status = "disabled"; }; @@ -271,6 +287,7 @@ reg-shift = <2>; interrupts = <33>; clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; + resets = <&lpc_reset 6>; no-loopback-test; status = "disabled"; }; @@ -281,6 +298,7 @@ reg-shift = <2>; interrupts = <34>; clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; + resets = <&lpc_reset 7>; no-loopback-test; status = "disabled"; }; Index: sys/gnu/dts/arm/aspeed-g5.dtsi =================================================================== --- sys/gnu/dts/arm/aspeed-g5.dtsi +++ sys/gnu/dts/arm/aspeed-g5.dtsi @@ -210,6 +210,7 @@ reg-shift = <2>; interrupts = <9>; clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; + resets = <&lpc_reset 4>; no-loopback-test; status = "disabled"; }; @@ -269,7 +270,7 @@ #address-cells = <1>; #size-cells = <1>; - ranges = <0 0x1e789000 0x1000>; + ranges = <0x0 0x1e789000 0x1000>; lpc_bmc: lpc-bmc@0 { compatible = "aspeed,ast2500-lpc-bmc"; @@ -279,16 +280,16 @@ lpc_host: lpc-host@80 { compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"; reg = <0x80 0x1e0>; + reg-io-width = <4>; #address-cells = <1>; #size-cells = <1>; - ranges = <0 0x80 0x1e0>; - - reg-io-width = <4>; + ranges = <0x0 0x80 0x1e0>; lpc_ctrl: lpc-ctrl@0 { compatible = "aspeed,ast2500-lpc-ctrl"; reg = <0x0 0x80>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; @@ -303,6 +304,19 @@ compatible = "aspeed,ast2500-lhc"; reg = <0x20 0x24 0x48 0x8>; }; + + lpc_reset: reset-controller@18 { + compatible = "aspeed,ast2500-lpc-reset"; + reg = <0x18 0x4>; + #reset-cells = <1>; + }; + + ibt: ibt@c0 { + compatible = "aspeed,ast2500-ibt-bmc"; + reg = <0xc0 0x18>; + interrupts = <8>; + status = "disabled"; + }; }; }; @@ -312,6 +326,7 @@ reg-shift = <2>; interrupts = <32>; clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; + resets = <&lpc_reset 5>; no-loopback-test; status = "disabled"; }; @@ -322,6 +337,7 @@ reg-shift = <2>; interrupts = <33>; clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; + resets = <&lpc_reset 6>; no-loopback-test; status = "disabled"; }; @@ -332,6 +348,7 @@ reg-shift = <2>; interrupts = <34>; clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; + resets = <&lpc_reset 7>; no-loopback-test; status = "disabled"; }; Index: sys/gnu/dts/arm/at91-nattis-2-natte-2.dts =================================================================== --- sys/gnu/dts/arm/at91-nattis-2-natte-2.dts +++ sys/gnu/dts/arm/at91-nattis-2-natte-2.dts @@ -109,7 +109,32 @@ port { panel_input: endpoint { - remote-endpoint = <&hlcdc_panel_output>; + remote-endpoint = <&lvds_encoder_output>; + }; + }; + }; + + lvds-encoder { + compatible = "lvds-encoder"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_encoder_input: endpoint { + remote-endpoint = <&hlcdc_output>; + }; + }; + + port@1 { + reg = <1>; + + lvds_encoder_output: endpoint { + remote-endpoint = <&panel_input>; + }; }; }; }; @@ -146,7 +171,7 @@ }; eeprom@50 { - compatible = "nxp,24c02"; + compatible = "nxp,se97b", "atmel,24c02"; reg = <0x50>; pagesize = <16>; }; @@ -176,8 +201,8 @@ &pinctrl_lcd_hipow0>; port@0 { - hlcdc_panel_output: endpoint { - remote-endpoint = <&panel_input>; + hlcdc_output: endpoint { + remote-endpoint = <&lvds_encoder_input>; }; }; }; @@ -216,29 +241,34 @@ reg = <0x0 0x40000>; }; - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0x80000>; + barebox@40000 { + label = "barebox"; + reg = <0x40000 0x60000>; + }; + + bareboxenv@c0000 { + label = "bareboxenv"; + reg = <0xc0000 0x40000>; }; - bootloaderenv@c0000 { - label = "bootloader env"; - reg = <0xc0000 0xc0000>; + bareboxenv2@100000 { + label = "bareboxenv2"; + reg = <0x100000 0x40000>; }; - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; + oftree@180000 { + label = "oftree"; + reg = <0x180000 0x20000>; }; kernel@200000 { label = "kernel"; - reg = <0x200000 0x600000>; + reg = <0x200000 0x500000>; }; rootfs@800000 { label = "rootfs"; - reg = <0x800000 0x0f800000>; + reg = <0x800000 0x1f800000>; }; }; }; Index: sys/gnu/dts/arm/at91-sama5d2_ptc_ek.dts =================================================================== --- sys/gnu/dts/arm/at91-sama5d2_ptc_ek.dts +++ sys/gnu/dts/arm/at91-sama5d2_ptc_ek.dts @@ -230,7 +230,7 @@ status = "okay"; at24@50 { - compatible = "24c02"; + compatible = "atmel,24c02"; reg = <0x50>; pagesize = <8>; }; Index: sys/gnu/dts/arm/at91-tse850-3.dts =================================================================== --- sys/gnu/dts/arm/at91-tse850-3.dts +++ sys/gnu/dts/arm/at91-tse850-3.dts @@ -234,6 +234,7 @@ compatible = "ti,pcm5142"; reg = <0x4c>; + #sound-dai-cells = <0>; AVDD-supply = <®_3v3>; DVDD-supply = <®_3v3>; @@ -246,7 +247,7 @@ }; eeprom@50 { - compatible = "nxp,24c02", "atmel,24c02"; + compatible = "nxp,se97b", "atmel,24c02"; reg = <0x50>; pagesize = <16>; }; Index: sys/gnu/dts/arm/at91rm9200.dtsi =================================================================== --- sys/gnu/dts/arm/at91rm9200.dtsi +++ sys/gnu/dts/arm/at91rm9200.dtsi @@ -493,8 +493,8 @@ uart0 { pinctrl_uart0: uart0-0 { atmel,pins = - ; /* PA18 periph A */ + ; }; pinctrl_uart0_cts: uart0_cts-0 { @@ -511,8 +511,8 @@ uart1 { pinctrl_uart1: uart1-0 { atmel,pins = - ; /* PB21 periph A */ + ; }; pinctrl_uart1_rts: uart1_rts-0 { @@ -545,8 +545,8 @@ uart2 { pinctrl_uart2: uart2-0 { atmel,pins = - ; /* PA23 periph A with pullup */ + ; }; pinctrl_uart2_rts: uart2_rts-0 { @@ -563,8 +563,8 @@ uart3 { pinctrl_uart3: uart3-0 { atmel,pins = - ; /* PA6 periph B */ + ; }; pinctrl_uart3_rts: uart3_rts-0 { Index: sys/gnu/dts/arm/at91sam9260.dtsi =================================================================== --- sys/gnu/dts/arm/at91sam9260.dtsi +++ sys/gnu/dts/arm/at91sam9260.dtsi @@ -434,8 +434,8 @@ usart0 { pinctrl_usart0: usart0-0 { atmel,pins = - ; /* PB5 periph A */ + ; }; pinctrl_usart0_rts: usart0_rts-0 { @@ -468,8 +468,8 @@ usart1 { pinctrl_usart1: usart1-0 { atmel,pins = - ; /* PB7 periph A */ + ; }; pinctrl_usart1_rts: usart1_rts-0 { @@ -486,8 +486,8 @@ usart2 { pinctrl_usart2: usart2-0 { atmel,pins = - ; /* PB9 periph A */ + ; }; pinctrl_usart2_rts: usart2_rts-0 { @@ -504,8 +504,8 @@ usart3 { pinctrl_usart3: usart3-0 { atmel,pins = - ; /* PB11 periph A */ + ; }; pinctrl_usart3_rts: usart3_rts-0 { @@ -522,16 +522,16 @@ uart0 { pinctrl_uart0: uart0-0 { atmel,pins = - ; /* PA30 periph B */ + ; }; }; uart1 { pinctrl_uart1: uart1-0 { atmel,pins = - ; /* PB13 periph A */ + ; }; }; Index: sys/gnu/dts/arm/at91sam9260ek.dts =================================================================== --- sys/gnu/dts/arm/at91sam9260ek.dts +++ sys/gnu/dts/arm/at91sam9260ek.dts @@ -201,7 +201,7 @@ status = "okay"; 24c512@50 { - compatible = "24c512"; + compatible = "atmel,24c512"; reg = <0x50>; }; }; Index: sys/gnu/dts/arm/at91sam9261.dtsi =================================================================== --- sys/gnu/dts/arm/at91sam9261.dtsi +++ sys/gnu/dts/arm/at91sam9261.dtsi @@ -328,8 +328,8 @@ usart0 { pinctrl_usart0: usart0-0 { atmel,pins = - , - ; + , + ; }; pinctrl_usart0_rts: usart0_rts-0 { @@ -346,8 +346,8 @@ usart1 { pinctrl_usart1: usart1-0 { atmel,pins = - , - ; + , + ; }; pinctrl_usart1_rts: usart1_rts-0 { @@ -364,8 +364,8 @@ usart2 { pinctrl_usart2: usart2-0 { atmel,pins = - , - ; + , + ; }; pinctrl_usart2_rts: usart2_rts-0 { Index: sys/gnu/dts/arm/at91sam9263.dtsi =================================================================== --- sys/gnu/dts/arm/at91sam9263.dtsi +++ sys/gnu/dts/arm/at91sam9263.dtsi @@ -437,8 +437,8 @@ usart0 { pinctrl_usart0: usart0-0 { atmel,pins = - ; /* PA27 periph A */ + ; }; pinctrl_usart0_rts: usart0_rts-0 { @@ -455,8 +455,8 @@ usart1 { pinctrl_usart1: usart1-0 { atmel,pins = - ; /* PD1 periph A */ + ; }; pinctrl_usart1_rts: usart1_rts-0 { @@ -473,8 +473,8 @@ usart2 { pinctrl_usart2: usart2-0 { atmel,pins = - ; /* PD3 periph A */ + ; }; pinctrl_usart2_rts: usart2_rts-0 { Index: sys/gnu/dts/arm/at91sam9263ek.dts =================================================================== --- sys/gnu/dts/arm/at91sam9263ek.dts +++ sys/gnu/dts/arm/at91sam9263ek.dts @@ -250,7 +250,7 @@ status = "okay"; 24c512@50 { - compatible = "24c512"; + compatible = "atmel,24c512"; reg = <0x50>; pagesize = <128>; }; Index: sys/gnu/dts/arm/at91sam9g20ek_common.dtsi =================================================================== --- sys/gnu/dts/arm/at91sam9g20ek_common.dtsi +++ sys/gnu/dts/arm/at91sam9g20ek_common.dtsi @@ -211,7 +211,7 @@ status = "okay"; 24c512@50 { - compatible = "24c512"; + compatible = "atmel,24c512"; reg = <0x50>; }; Index: sys/gnu/dts/arm/at91sam9g25.dtsi =================================================================== --- sys/gnu/dts/arm/at91sam9g25.dtsi +++ sys/gnu/dts/arm/at91sam9g25.dtsi @@ -21,7 +21,7 @@ atmel,mux-mask = < /* A B C */ 0xffffffff 0xffe0399f 0xc000001c /* pioA */ - 0x0007ffff 0x8000fe3f 0x00000000 /* pioB */ + 0x0007ffff 0x00047e3f 0x00000000 /* pioB */ 0x80000000 0x07c0ffff 0xb83fffff /* pioC */ 0x003fffff 0x003f8000 0x00000000 /* pioD */ >; Index: sys/gnu/dts/arm/at91sam9g45.dtsi =================================================================== --- sys/gnu/dts/arm/at91sam9g45.dtsi +++ sys/gnu/dts/arm/at91sam9g45.dtsi @@ -555,8 +555,8 @@ usart0 { pinctrl_usart0: usart0-0 { atmel,pins = - ; /* PB18 periph A */ + ; }; pinctrl_usart0_rts: usart0_rts-0 { @@ -573,8 +573,8 @@ uart1 { pinctrl_usart1: usart1-0 { atmel,pins = - ; /* PB5 periph A */ + ; }; pinctrl_usart1_rts: usart1_rts-0 { @@ -591,8 +591,8 @@ usart2 { pinctrl_usart2: usart2-0 { atmel,pins = - ; /* PB7 periph A */ + ; }; pinctrl_usart2_rts: usart2_rts-0 { @@ -609,8 +609,8 @@ usart3 { pinctrl_usart3: usart3-0 { atmel,pins = - ; /* PB8 periph A */ + ; }; pinctrl_usart3_rts: usart3_rts-0 { Index: sys/gnu/dts/arm/at91sam9n12.dtsi =================================================================== --- sys/gnu/dts/arm/at91sam9n12.dtsi +++ sys/gnu/dts/arm/at91sam9n12.dtsi @@ -641,8 +641,8 @@ uart1 { pinctrl_uart1: uart1-0 { atmel,pins = - ; /* PC16 periph C */ + ; }; }; Index: sys/gnu/dts/arm/at91sam9rl.dtsi =================================================================== --- sys/gnu/dts/arm/at91sam9rl.dtsi +++ sys/gnu/dts/arm/at91sam9rl.dtsi @@ -1,7 +1,8 @@ /* * at91sam9rl.dtsi - Device Tree Include file for AT91SAM9RL family SoC * - * Copyright (C) 2014 Alexandre Belloni + * Copyright (C) 2014 Microchip + * Alexandre Belloni * * Licensed under GPLv2 or later. */ @@ -719,8 +720,8 @@ usart1 { pinctrl_usart1: usart1-0 { atmel,pins = - , - ; + , + ; }; pinctrl_usart1_rts: usart1_rts-0 { @@ -742,8 +743,8 @@ usart2 { pinctrl_usart2: usart2-0 { atmel,pins = - , - ; + , + ; }; pinctrl_usart2_rts: usart2_rts-0 { @@ -765,8 +766,8 @@ usart3 { pinctrl_usart3: usart3-0 { atmel,pins = - , - ; + , + ; }; pinctrl_usart3_rts: usart3_rts-0 { Index: sys/gnu/dts/arm/at91sam9rlek.dts =================================================================== --- sys/gnu/dts/arm/at91sam9rlek.dts +++ sys/gnu/dts/arm/at91sam9rlek.dts @@ -1,7 +1,8 @@ /* * at91sam9rlek.dts - Device Tree file for Atmel at91sam9rl reference board * - * Copyright (C) 2014 Alexandre Belloni + * Copyright (C) 2014 Microchip + * Alexandre Belloni * * Licensed under GPLv2 only */ Index: sys/gnu/dts/arm/at91sam9x5.dtsi =================================================================== --- sys/gnu/dts/arm/at91sam9x5.dtsi +++ sys/gnu/dts/arm/at91sam9x5.dtsi @@ -520,8 +520,8 @@ usart0 { pinctrl_usart0: usart0-0 { atmel,pins = - ; /* PA1 periph A */ + ; }; pinctrl_usart0_rts: usart0_rts-0 { @@ -543,8 +543,8 @@ usart1 { pinctrl_usart1: usart1-0 { atmel,pins = - ; /* PA6 periph A */ + ; }; pinctrl_usart1_rts: usart1_rts-0 { @@ -566,8 +566,8 @@ usart2 { pinctrl_usart2: usart2-0 { atmel,pins = - ; /* PA8 periph A */ + ; }; pinctrl_usart2_rts: usart2_rts-0 { Index: sys/gnu/dts/arm/at91sam9x5_usart3.dtsi =================================================================== --- sys/gnu/dts/arm/at91sam9x5_usart3.dtsi +++ sys/gnu/dts/arm/at91sam9x5_usart3.dtsi @@ -21,8 +21,8 @@ usart3 { pinctrl_usart3: usart3-0 { atmel,pins = - ; /* PC23 periph B */ + ; }; pinctrl_usart3_rts: usart3_rts-0 { Index: sys/gnu/dts/arm/atlas7-evb.dts =================================================================== --- sys/gnu/dts/arm/atlas7-evb.dts +++ sys/gnu/dts/arm/atlas7-evb.dts @@ -73,7 +73,7 @@ btm { uart6: uart@11000000 { status = "okay"; - sirf,uart-has-rtscts; + uart-has-rtscts; }; }; Index: sys/gnu/dts/arm/axp209.dtsi =================================================================== --- sys/gnu/dts/arm/axp209.dtsi +++ sys/gnu/dts/arm/axp209.dtsi @@ -58,6 +58,11 @@ status = "disabled"; }; + axp_adc: adc { + compatible = "x-powers,axp209-adc"; + #io-channel-cells = <1>; + }; + axp_gpio: gpio { compatible = "x-powers,axp209-gpio"; gpio-controller; Index: sys/gnu/dts/arm/axp22x.dtsi =================================================================== --- sys/gnu/dts/arm/axp22x.dtsi +++ sys/gnu/dts/arm/axp22x.dtsi @@ -57,6 +57,11 @@ status = "disabled"; }; + axp_adc: adc { + compatible = "x-powers,axp221-adc"; + #io-channel-cells = <1>; + }; + battery_power_supply: battery-power-supply { compatible = "x-powers,axp221-battery-power-supply"; status = "disabled"; Index: sys/gnu/dts/arm/axp81x.dtsi =================================================================== --- sys/gnu/dts/arm/axp81x.dtsi +++ sys/gnu/dts/arm/axp81x.dtsi @@ -48,7 +48,12 @@ interrupt-controller; #interrupt-cells = <1>; - axp_gpio: axp-gpio { + axp_adc: adc { + compatible = "x-powers,axp813-adc"; + #io-channel-cells = <1>; + }; + + axp_gpio: gpio { compatible = "x-powers,axp813-gpio"; gpio-controller; #gpio-cells = <2>; @@ -64,6 +69,11 @@ }; }; + battery_power_supply: battery-power-supply { + compatible = "x-powers,axp813-battery-power-supply"; + status = "disabled"; + }; + regulators { /* Default work frequency for buck regulators */ x-powers,dcdc-freq = <3000>; Index: sys/gnu/dts/arm/bcm-cygnus.dtsi =================================================================== --- sys/gnu/dts/arm/bcm-cygnus.dtsi +++ sys/gnu/dts/arm/bcm-cygnus.dtsi @@ -69,7 +69,7 @@ timer@20200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x20200 0x100>; - interrupts = ; + interrupts = ; clocks = <&periph_clk>; }; Index: sys/gnu/dts/arm/bcm2835-rpi-zero-w.dts =================================================================== --- sys/gnu/dts/arm/bcm2835-rpi-zero-w.dts +++ sys/gnu/dts/arm/bcm2835-rpi-zero-w.dts @@ -12,7 +12,7 @@ /dts-v1/; #include "bcm2835.dtsi" #include "bcm2835-rpi.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" +#include "bcm283x-rpi-usb-otg.dtsi" / { compatible = "raspberrypi,model-zero-w", "brcm,bcm2835"; @@ -131,6 +131,18 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_gpio14>; + pinctrl-0 = <&uart0_gpio32 &uart0_ctsrts_gpio30>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <2000000>; + shutdown-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_gpio14>; status = "okay"; }; Index: sys/gnu/dts/arm/bcm2835-rpi.dtsi =================================================================== --- sys/gnu/dts/arm/bcm2835-rpi.dtsi +++ sys/gnu/dts/arm/bcm2835-rpi.dtsi @@ -18,7 +18,9 @@ soc { firmware: firmware { - compatible = "raspberrypi,bcm2835-firmware"; + compatible = "raspberrypi,bcm2835-firmware", "simple-bus"; + #address-cells = <0>; + #size-cells = <0>; mboxes = <&mailbox>; }; @@ -27,6 +29,12 @@ firmware = <&firmware>; #power-domain-cells = <1>; }; + + mailbox@7e00b840 { + compatible = "brcm,bcm2835-vchiq"; + reg = <0x7e00b840 0xf>; + interrupts = <0 2>; + }; }; }; Index: sys/gnu/dts/arm/bcm2837-rpi-3-b.dts =================================================================== --- sys/gnu/dts/arm/bcm2837-rpi-3-b.dts +++ sys/gnu/dts/arm/bcm2837-rpi-3-b.dts @@ -25,6 +25,23 @@ }; }; +&firmware { + expgpio: gpio { + compatible = "raspberrypi,firmware-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "BT_ON", + "WL_ON", + "STATUS_LED", + "LAN_RUN", + "HPD_N", + "CAM_GPIO0", + "CAM_GPIO1", + "PWR_LOW_N"; + status = "okay"; + }; +}; + /* uart0 communicates with the BT module */ &uart0 { pinctrl-names = "default"; Index: sys/gnu/dts/arm/bcm283x.dtsi =================================================================== --- sys/gnu/dts/arm/bcm283x.dtsi +++ sys/gnu/dts/arm/bcm283x.dtsi @@ -223,6 +223,7 @@ gpclk2_gpio43: gpclk2_gpio43 { brcm,pins = <43>; brcm,function = ; + brcm,pull = ; }; i2c0_gpio0: i2c0_gpio0 { @@ -252,7 +253,7 @@ jtag_gpio4: jtag_gpio4 { brcm,pins = <4 5 6 12 13>; - brcm,function = ; + brcm,function = ; }; jtag_gpio22: jtag_gpio22 { brcm,pins = <22 23 24 25 26 27>; @@ -335,10 +336,12 @@ uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 { brcm,pins = <30 31>; brcm,function = ; + brcm,pull = ; }; uart0_gpio32: uart0_gpio32 { brcm,pins = <32 33>; brcm,function = ; + brcm,pull = ; }; uart0_gpio36: uart0_gpio36 { brcm,pins = <36 37>; @@ -397,8 +400,8 @@ i2s: i2s@7e203000 { compatible = "brcm,bcm2835-i2s"; - reg = <0x7e203000 0x20>, - <0x7e101098 0x02>; + reg = <0x7e203000 0x24>; + clocks = <&clocks BCM2835_CLOCK_PCM>; dmas = <&dma 2>, <&dma 3>; @@ -438,6 +441,17 @@ interrupts = <2 14>; /* pwa1 */ }; + dpi: dpi@7e208000 { + compatible = "brcm,bcm2835-dpi"; + reg = <0x7e208000 0x8c>; + clocks = <&clocks BCM2835_CLOCK_VPU>, + <&clocks BCM2835_CLOCK_DPI>; + clock-names = "core", "pixel"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + dsi0: dsi@7e209000 { compatible = "brcm,bcm2835-dsi0"; reg = <0x7e209000 0x78>; Index: sys/gnu/dts/arm/bcm47081-buffalo-wzr-900dhp.dts =================================================================== --- sys/gnu/dts/arm/bcm47081-buffalo-wzr-900dhp.dts +++ sys/gnu/dts/arm/bcm47081-buffalo-wzr-900dhp.dts @@ -35,6 +35,74 @@ 0x88000000 0x08000000>; }; + spi { + compatible = "spi-gpio"; + num-chipselects = <1>; + gpio-sck = <&chipcommon 7 0>; + gpio-mosi = <&chipcommon 4 0>; + cs-gpios = <&chipcommon 6 0>; + #address-cells = <1>; + #size-cells = <0>; + + hc595: gpio_spi@0 { + compatible = "fairchild,74hc595"; + reg = <0>; + registers-number = <1>; + spi-max-frequency = <100000>; + + gpio-controller; + #gpio-cells = <2>; + + }; + }; + + leds { + compatible = "gpio-leds"; + + usb { + label = "bcm53xx:green:usb"; + gpios = <&hc595 0 GPIO_ACTIVE_HIGH>; + }; + + power0 { + label = "bcm53xx:green:power"; + gpios = <&hc595 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + power1 { + label = "bcm53xx:red:power"; + gpios = <&hc595 2 GPIO_ACTIVE_HIGH>; + }; + + router0 { + label = "bcm53xx:green:router"; + gpios = <&hc595 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + router1 { + label = "bcm53xx:amber:router"; + gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; + }; + + wan { + label = "bcm53xx:green:wan"; + gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + wireless0 { + label = "bcm53xx:green:wireless"; + gpios = <&hc595 6 GPIO_ACTIVE_HIGH>; + }; + + wireless1 { + label = "bcm53xx:amber:wireless"; + gpios = <&hc595 7 GPIO_ACTIVE_HIGH>; + }; + }; + gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; Index: sys/gnu/dts/arm/bcm958622hr.dts =================================================================== --- sys/gnu/dts/arm/bcm958622hr.dts +++ sys/gnu/dts/arm/bcm958622hr.dts @@ -204,10 +204,10 @@ reg = <4>; }; - port@5 { - ethernet = <&amac0>; + port@8 { + ethernet = <&amac2>; label = "cpu"; - reg = <5>; + reg = <8>; fixed-link { speed = <1000>; full-duplex; Index: sys/gnu/dts/arm/bcm958623hr.dts =================================================================== --- sys/gnu/dts/arm/bcm958623hr.dts +++ sys/gnu/dts/arm/bcm958623hr.dts @@ -208,10 +208,10 @@ reg = <4>; }; - port@5 { - ethernet = <&amac0>; + port@8 { + ethernet = <&amac2>; label = "cpu"; - reg = <5>; + reg = <8>; fixed-link { speed = <1000>; full-duplex; Index: sys/gnu/dts/arm/bcm958625hr.dts =================================================================== --- sys/gnu/dts/arm/bcm958625hr.dts +++ sys/gnu/dts/arm/bcm958625hr.dts @@ -210,10 +210,10 @@ reg = <4>; }; - port@5 { - ethernet = <&amac0>; + port@8 { + ethernet = <&amac2>; label = "cpu"; - reg = <5>; + reg = <8>; fixed-link { speed = <1000>; full-duplex; Index: sys/gnu/dts/arm/bcm958625k.dts =================================================================== --- sys/gnu/dts/arm/bcm958625k.dts +++ sys/gnu/dts/arm/bcm958625k.dts @@ -245,10 +245,10 @@ reg = <4>; }; - port@5 { - ethernet = <&amac0>; + port@8 { + ethernet = <&amac2>; label = "cpu"; - reg = <5>; + reg = <8>; fixed-link { speed = <1000>; full-duplex; Index: sys/gnu/dts/arm/bcm988312hr.dts =================================================================== --- sys/gnu/dts/arm/bcm988312hr.dts +++ sys/gnu/dts/arm/bcm988312hr.dts @@ -216,10 +216,10 @@ reg = <4>; }; - port@5 { - ethernet = <&amac0>; + port@8 { + ethernet = <&amac2>; label = "cpu"; - reg = <5>; + reg = <8>; fixed-link { speed = <1000>; full-duplex; Index: sys/gnu/dts/arm/da850-evm.dts =================================================================== --- sys/gnu/dts/arm/da850-evm.dts +++ sys/gnu/dts/arm/da850-evm.dts @@ -15,11 +15,16 @@ compatible = "ti,da850-evm", "ti,da850"; model = "DA850/AM1808/OMAP-L138 EVM"; + chosen { + stdout-path = &serial2; + }; + aliases { serial0 = &serial0; serial1 = &serial1; serial2 = &serial2; ethernet0 = ð0; + spi0 = &spi1; }; soc@1c00000 { Index: sys/gnu/dts/arm/da850-lcdk.dts =================================================================== --- sys/gnu/dts/arm/da850-lcdk.dts +++ sys/gnu/dts/arm/da850-lcdk.dts @@ -21,8 +21,8 @@ stdout-path = "serial2:115200n8"; }; - memory { - device_type = "memory"; + memory@c0000000 { + /* 128 MB DDR2 SDRAM @ 0xc0000000 */ reg = <0xc0000000 0x08000000>; }; Index: sys/gnu/dts/arm/da850-lego-ev3.dts =================================================================== --- sys/gnu/dts/arm/da850-lego-ev3.dts +++ sys/gnu/dts/arm/da850-lego-ev3.dts @@ -184,6 +184,23 @@ io-channel-names = "voltage", "current"; rechargeable-gpios = <&gpio 136 GPIO_ACTIVE_LOW>; }; + + /* ARM local RAM */ + memory@ffff0000 { + compatible = "syscon", "simple-mfd"; + reg = <0xffff0000 0x2000>; /* 8k */ + + /* + * The I2C bootloader looks for this magic value to either + * boot normally or boot into a firmware update mode. + */ + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x1ffc>; + mode-normal = <0x00000000>; + mode-loader = <0x5555aaaa>; + }; + }; }; &pmx_core { @@ -293,7 +310,7 @@ * EEPROM contains the first stage bootloader, HW ID and Bluetooth MAC. */ eeprom@50 { - compatible = "microchip,24c128"; + compatible = "microchip,24c128", "atmel,24c128"; pagesize = <64>; read-only; reg = <0x50>; Index: sys/gnu/dts/arm/da850.dtsi =================================================================== --- sys/gnu/dts/arm/da850.dtsi +++ sys/gnu/dts/arm/da850.dtsi @@ -7,10 +7,19 @@ * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ -#include "skeleton.dtsi" #include / { + #address-cells = <1>; + #size-cells = <1>; + chosen { }; + aliases { }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x0>; + }; + arm { #address-cells = <1>; #size-cells = <1>; @@ -46,8 +55,6 @@ pmx_core: pinmux@14120 { compatible = "pinctrl-single"; reg = <0x14120 0x50>; - #address-cells = <1>; - #size-cells = <0>; #pinctrl-cells = <2>; pinctrl-single,bit-per-mux; pinctrl-single,register-width = <32>; Index: sys/gnu/dts/arm/dm8148-evm.dts =================================================================== --- sys/gnu/dts/arm/dm8148-evm.dts +++ sys/gnu/dts/arm/dm8148-evm.dts @@ -10,7 +10,7 @@ / { model = "DM8148 EVM"; - compatible = "ti,dm8148-evm", "ti,dm8148"; + compatible = "ti,dm8148-evm", "ti,dm8148", "ti,dm814"; memory@80000000 { device_type = "memory"; Index: sys/gnu/dts/arm/dm8148-t410.dts =================================================================== --- sys/gnu/dts/arm/dm8148-t410.dts +++ sys/gnu/dts/arm/dm8148-t410.dts @@ -9,7 +9,7 @@ / { model = "HP t410 Smart Zero Client"; - compatible = "hp,t410", "ti,dm8148"; + compatible = "hp,t410", "ti,dm8148", "ti,dm814"; memory@80000000 { device_type = "memory"; Index: sys/gnu/dts/arm/dm8168-evm.dts =================================================================== --- sys/gnu/dts/arm/dm8168-evm.dts +++ sys/gnu/dts/arm/dm8168-evm.dts @@ -10,7 +10,7 @@ / { model = "DM8168 EVM"; - compatible = "ti,dm8168-evm", "ti,dm8168"; + compatible = "ti,dm8168-evm", "ti,dm8168", "ti,dm816"; memory@80000000 { device_type = "memory"; Index: sys/gnu/dts/arm/dra62x-j5eco-evm.dts =================================================================== --- sys/gnu/dts/arm/dra62x-j5eco-evm.dts +++ sys/gnu/dts/arm/dra62x-j5eco-evm.dts @@ -10,7 +10,7 @@ / { model = "DRA62x J5 Eco EVM"; - compatible = "ti,dra62x-j5eco-evm", "ti,dra62x", "ti,dm8148"; + compatible = "ti,dra62x-j5eco-evm", "ti,dra62x", "ti,dm8148", "ti,dm814"; memory@80000000 { device_type = "memory"; Index: sys/gnu/dts/arm/dra7-evm.dts =================================================================== --- sys/gnu/dts/arm/dra7-evm.dts +++ sys/gnu/dts/arm/dra7-evm.dts @@ -87,33 +87,6 @@ DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ >; }; - - mmc1_pins_default: mmc1_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc2_pins_default: mmc2_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; }; &i2c1 { @@ -350,6 +323,7 @@ &mmc2 { status = "okay"; vmmc-supply = <&evm_1v8_sw>; + vqmmc-supply = <&evm_1v8_sw>; bus-width = <8>; pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v"; pinctrl-0 = <&mmc2_pins_default>; Index: sys/gnu/dts/arm/dra7.dtsi =================================================================== --- sys/gnu/dts/arm/dra7.dtsi +++ sys/gnu/dts/arm/dra7.dtsi @@ -92,8 +92,6 @@ clock-latency = <300000>; /* From omap-cpufreq driver */ /* cooling options */ - cooling-min-level = <0>; - cooling-max-level = <2>; #cooling-cells = <2>; /* min followed by max */ vbb-supply = <&abb_mpu>; Index: sys/gnu/dts/arm/dra71-evm.dts =================================================================== --- sys/gnu/dts/arm/dra71-evm.dts +++ sys/gnu/dts/arm/dra71-evm.dts @@ -24,13 +24,13 @@ regulator-name = "vddshv8"; regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; regulator-boot-on; vin-supply = <&evm_5v0>; gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; states = <1800000 0x0 - 3000000 0x1>; + 3300000 0x1>; }; evm_1v8_sw: fixedregulator-evm_1v8 { @@ -50,6 +50,19 @@ }; }; +&dra7_pmx_core { + mmc1_pins_default: mmc1_pins_default { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; +}; + &i2c1 { status = "okay"; clock-frequency = <400000>; Index: sys/gnu/dts/arm/dra76-evm.dts =================================================================== --- sys/gnu/dts/arm/dra76-evm.dts +++ sys/gnu/dts/arm/dra76-evm.dts @@ -9,6 +9,7 @@ #include "dra76x.dtsi" #include "dra7-evm-common.dtsi" +#include "dra76x-mmc-iodelay.dtsi" #include / { @@ -100,46 +101,6 @@ }; }; -&dra7_pmx_core { - mmc1_pins_default: mmc1_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc2_pins_default: mmc2_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; -}; - &i2c1 { status = "okay"; clock-frequency = <400000>; @@ -353,16 +314,21 @@ * is always hardwired. */ cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; + pinctrl-names = "default", "hs"; pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_hs>; }; &mmc2 { status = "okay"; vmmc-supply = <&vio_1v8>; + vqmmc-supply = <&vio_1v8>; bus-width = <8>; - pinctrl-names = "default"; + pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_default>; + pinctrl-2 = <&mmc2_pins_default>; + pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_conf>; }; /* No RTC on this device */ Index: sys/gnu/dts/arm/dra76x-mmc-iodelay.dtsi =================================================================== --- /dev/null +++ sys/gnu/dts/arm/dra76x-mmc-iodelay.dtsi @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Texas Instruments +// MMC IOdelay values for TI's DRA76x and AM576x SoCs. +// Author: Sekhar Nori + +/* + * Rules for modifying this file: + * a) Update of this file should typically correspond to a datamanual revision. + * Datamanual revision that was used should be updated in comment below. + * If there is no update to datamanual, do not update the values. If you + * need to use values different from that recommended by the datamanual + * for your design, then you should consider adding values to the device- + * -tree file for your board directly. + * b) We keep the mode names as close to the datamanual as possible. So + * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v, + * we follow that in code too. + * c) If the values change between multiple revisions of silicon, we add + * a revision tag to both the new and old entry. Use 'rev11' for PG 1.1, + * 'rev20' for PG 2.0 and so on. + * d) The node name and node label should be the exact same string. This is + * to curb naming creativity and achieve consistency. + * + * Datamanual Revisions: + * + * DRA76x Silicon Revision 1.0: SPRS993A, Revised July 2017 + * + */ + +&dra7_pmx_core { + mmc1_pins_default: mmc1_pins_default { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_hs: mmc1_pins_hs { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_sdr50: mmc1_pins_sdr50 { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_ddr50: mmc1_pins_ddr50 { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc2_pins_default: mmc2_pins_default { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + mmc2_pins_hs200: mmc2_pins_hs200 { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + mmc3_pins_default: mmc3_pins_default { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ + DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ + DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ + DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ + DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ + DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ + >; + }; + + mmc4_pins_hs: mmc4_pins_hs { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ + DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ + DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ + DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ + DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ + DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ + >; + }; +}; + +&dra7_iodelay_core { + + /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */ + mmc1_iodelay_ddr_conf: mmc1_iodelay_ddr_conf { + pinctrl-pin-array = < + 0x618 A_DELAY_PS(489) G_DELAY_PS(0) /* CFG_MMC1_CLK_IN */ + 0x624 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */ + 0x630 A_DELAY_PS(374) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */ + 0x63c A_DELAY_PS(31) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */ + 0x648 A_DELAY_PS(56) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */ + 0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */ + 0x620 A_DELAY_PS(1355) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ + 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ + 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ + 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ + 0x638 A_DELAY_PS(0) G_DELAY_PS(4) /* CFG_MMC1_DAT0_OUT */ + 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ + 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ + 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ + 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ + 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ + 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ + >; + }; + + /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */ + mmc1_iodelay_sdr104_conf: mmc1_iodelay_sdr104_conf { + pinctrl-pin-array = < + 0x620 A_DELAY_PS(892) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ + 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ + 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ + 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ + 0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ + 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ + 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ + 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ + 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ + 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ + 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ + >; + }; + + /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */ + mmc2_iodelay_hs200_conf: mmc2_iodelay_hs200_conf { + pinctrl-pin-array = < + 0x190 A_DELAY_PS(384) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ + 0x194 A_DELAY_PS(0) G_DELAY_PS(174) /* CFG_GPMC_A19_OUT */ + 0x1a8 A_DELAY_PS(410) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ + 0x1ac A_DELAY_PS(85) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ + 0x1b4 A_DELAY_PS(468) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ + 0x1b8 A_DELAY_PS(139) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ + 0x1c0 A_DELAY_PS(676) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ + 0x1c4 A_DELAY_PS(69) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ + 0x1d0 A_DELAY_PS(1062) G_DELAY_PS(154) /* CFG_GPMC_A23_OUT */ + 0x1d8 A_DELAY_PS(640) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ + 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ + 0x1e4 A_DELAY_PS(356) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ + 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ + 0x1f0 A_DELAY_PS(579) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ + 0x1f4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ + 0x1fc A_DELAY_PS(435) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ + 0x200 A_DELAY_PS(36) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ + 0x364 A_DELAY_PS(759) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ + 0x368 A_DELAY_PS(72) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ + >; + }; + + /* Corresponds to MMC3_MANUAL1 in datamanual */ + mmc3_iodelay_manual1_conf: mmc3_iodelay_manual1_conf { + pinctrl-pin-array = < + 0x678 A_DELAY_PS(0) G_DELAY_PS(386) /* CFG_MMC3_CLK_IN */ + 0x680 A_DELAY_PS(605) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */ + 0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */ + 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */ + 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */ + 0x690 A_DELAY_PS(171) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */ + 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */ + 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */ + 0x69c A_DELAY_PS(221) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */ + 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */ + 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */ + 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */ + 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */ + 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */ + 0x6b4 A_DELAY_PS(474) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */ + 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */ + 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */ + >; + }; + + /* Corresponds to MMC3_MANUAL2 in datamanual */ + mmc3_iodelay_sdr50_conf: mmc3_iodelay_sdr50_conf { + pinctrl-pin-array = < + 0x678 A_DELAY_PS(852) G_DELAY_PS(0) /* CFG_MMC3_CLK_IN */ + 0x680 A_DELAY_PS(94) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */ + 0x684 A_DELAY_PS(122) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */ + 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */ + 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */ + 0x690 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */ + 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */ + 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */ + 0x69c A_DELAY_PS(57) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */ + 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */ + 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */ + 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */ + 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */ + 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */ + 0x6b4 A_DELAY_PS(375) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */ + 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */ + 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */ + >; + }; + + /* Corresponds to MMC4_MANUAL1 in datamanual */ + mmc4_iodelay_manual1_conf: mmc4_iodelay_manual1_conf { + pinctrl-pin-array = < + 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ + 0x848 A_DELAY_PS(1147) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ + 0x84c A_DELAY_PS(1834) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ + 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ + 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ + 0x870 A_DELAY_PS(2165) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ + 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ + 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ + 0x87c A_DELAY_PS(1929) G_DELAY_PS(64) /* CFG_UART2_RTSN_IN */ + 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ + 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ + 0x888 A_DELAY_PS(1935) G_DELAY_PS(128) /* CFG_UART2_RXD_IN */ + 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ + 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ + 0x894 A_DELAY_PS(2172) G_DELAY_PS(44) /* CFG_UART2_TXD_IN */ + 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ + 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ + >; + }; + + /* Corresponds to MMC4_DS_MANUAL1 in datamanual */ + mmc4_iodelay_default_conf: mmc4_iodelay_default_conf { + pinctrl-pin-array = < + 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ + 0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ + 0x84c A_DELAY_PS(307) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ + 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ + 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ + 0x870 A_DELAY_PS(785) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ + 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ + 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ + 0x87c A_DELAY_PS(613) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */ + 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ + 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ + 0x888 A_DELAY_PS(683) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */ + 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ + 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ + 0x894 A_DELAY_PS(835) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */ + 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ + 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ + >; + }; +}; Index: sys/gnu/dts/arm/emev2-kzm9d.dts =================================================================== --- sys/gnu/dts/arm/emev2-kzm9d.dts +++ sys/gnu/dts/arm/emev2-kzm9d.dts @@ -38,28 +38,28 @@ #size-cells = <0>; one { - debounce_interval = <50>; + debounce-interval = <50>; wakeup-source; label = "DSW2-1"; linux,code = ; gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; }; two { - debounce_interval = <50>; + debounce-interval = <50>; wakeup-source; label = "DSW2-2"; linux,code = ; gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; }; three { - debounce_interval = <50>; + debounce-interval = <50>; wakeup-source; label = "DSW2-3"; linux,code = ; gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; }; four { - debounce_interval = <50>; + debounce-interval = <50>; wakeup-source; label = "DSW2-4"; linux,code = ; Index: sys/gnu/dts/arm/exynos-mfc-reserved-memory.dtsi =================================================================== --- sys/gnu/dts/arm/exynos-mfc-reserved-memory.dtsi +++ sys/gnu/dts/arm/exynos-mfc-reserved-memory.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's Exynos SoC MFC (Video Codec) reserved memory common definition. * * Copyright (c) 2016 Samsung Electronics Co., Ltd - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ / { Index: sys/gnu/dts/arm/exynos-syscon-restart.dtsi =================================================================== --- sys/gnu/dts/arm/exynos-syscon-restart.dtsi +++ sys/gnu/dts/arm/exynos-syscon-restart.dtsi @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's Exynos SoC syscon reboot/poweroff nodes common definition. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ / { Index: sys/gnu/dts/arm/exynos3250-artik5.dtsi =================================================================== --- sys/gnu/dts/arm/exynos3250-artik5.dtsi +++ sys/gnu/dts/arm/exynos3250-artik5.dtsi @@ -245,6 +245,7 @@ regulator-name = "VLDO23_1.8V"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-always-on; }; ldo24_reg: LDO24 { @@ -316,6 +317,41 @@ status = "okay"; }; +&mshc_1 { + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + non-removable; + keep-power-in-suspend; + fifo-depth = <0x40>; + vqmmc-supply = <&ldo11_reg>; + /* + * Voltage negotiation is broken for the SDIO periph so we + * can't actually set the voltage here. + * vmmc-supply = <&ldo23_reg>; + */ + card-detect-delay = <500>; + clock-frequency = <100000000>; + max-frequency = <100000000>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 1>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd1_cmd &sd1_clk &sd1_bus1 &sd1_bus4 &wlanen>; + bus-width = <4>; + status = "okay"; +}; + +&pinctrl_1 { + wlanen: wlanen { + samsung,pins = "gpx2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-val = <1>; + }; +}; + &rtc { clocks = <&cmu CLK_RTC>, <&s2mps14_osc S2MPS11_CLK_AP>; clock-names = "rtc", "rtc_src"; Index: sys/gnu/dts/arm/exynos3250.dtsi =================================================================== --- sys/gnu/dts/arm/exynos3250.dtsi +++ sys/gnu/dts/arm/exynos3250.dtsi @@ -161,34 +161,39 @@ syscon = <&pmu_system_controller>; }; - pd_cam: cam-power-domain@10023c00 { + pd_cam: power-domain@10023c00 { compatible = "samsung,exynos4210-pd"; reg = <0x10023C00 0x20>; #power-domain-cells = <0>; + label = "CAM"; }; - pd_mfc: mfc-power-domain@10023c40 { + pd_mfc: power-domain@10023c40 { compatible = "samsung,exynos4210-pd"; reg = <0x10023C40 0x20>; #power-domain-cells = <0>; + label = "MFC"; }; - pd_g3d: g3d-power-domain@10023c60 { + pd_g3d: power-domain@10023c60 { compatible = "samsung,exynos4210-pd"; reg = <0x10023C60 0x20>; #power-domain-cells = <0>; + label = "G3D"; }; - pd_lcd0: lcd0-power-domain@10023c80 { + pd_lcd0: power-domain@10023c80 { compatible = "samsung,exynos4210-pd"; reg = <0x10023C80 0x20>; #power-domain-cells = <0>; + label = "LCD0"; }; - pd_isp: isp-power-domain@10023ca0 { + pd_isp: power-domain@10023ca0 { compatible = "samsung,exynos4210-pd"; reg = <0x10023CA0 0x20>; #power-domain-cells = <0>; + label = "ISP"; }; cmu: clock-controller@10030000 { Index: sys/gnu/dts/arm/exynos4.dtsi =================================================================== --- sys/gnu/dts/arm/exynos4.dtsi +++ sys/gnu/dts/arm/exynos4.dtsi @@ -52,961 +52,976 @@ serial3 = &serial_3; }; - clock_audss: clock-controller@3810000 { - compatible = "samsung,exynos4210-audss-clock"; - reg = <0x03810000 0x0C>; - #clock-cells = <1>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, - <&clock CLK_SCLK_AUDIO0>, <&clock CLK_SCLK_AUDIO0>; - clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; - }; - - i2s0: i2s@3830000 { - compatible = "samsung,s5pv210-i2s"; - reg = <0x03830000 0x100>; - clocks = <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_DOUT_AUD_BUS>, - <&clock_audss EXYNOS_SCLK_I2S>; - clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; - #clock-cells = <1>; - clock-output-names = "i2s_cdclk0"; - dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>; - dma-names = "tx", "rx", "tx-sec"; - samsung,idma-addr = <0x03000000>; - #sound-dai-cells = <1>; - status = "disabled"; - }; + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; - chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; - reg = <0x10000000 0x100>; - }; + clock_audss: clock-controller@3810000 { + compatible = "samsung,exynos4210-audss-clock"; + reg = <0x03810000 0x0C>; + #clock-cells = <1>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, + <&clock CLK_SCLK_AUDIO0>, + <&clock CLK_SCLK_AUDIO0>; + clock-names = "pll_ref", "pll_in", "sclk_audio", + "sclk_pcm_in"; + }; - scu: snoop-control-unit@10500000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x10500000 0x2000>; - }; + i2s0: i2s@3830000 { + compatible = "samsung,s5pv210-i2s"; + reg = <0x03830000 0x100>; + clocks = <&clock_audss EXYNOS_I2S_BUS>, + <&clock_audss EXYNOS_DOUT_AUD_BUS>, + <&clock_audss EXYNOS_SCLK_I2S>; + clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; + #clock-cells = <1>; + clock-output-names = "i2s_cdclk0"; + dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>; + dma-names = "tx", "rx", "tx-sec"; + samsung,idma-addr = <0x03000000>; + #sound-dai-cells = <1>; + status = "disabled"; + }; - memory-controller@12570000 { - compatible = "samsung,exynos4210-srom"; - reg = <0x12570000 0x14>; - }; + chipid@10000000 { + compatible = "samsung,exynos4210-chipid"; + reg = <0x10000000 0x100>; + }; - mipi_phy: video-phy { - compatible = "samsung,s5pv210-mipi-video-phy"; - #phy-cells = <1>; - syscon = <&pmu_system_controller>; - }; + scu: snoop-control-unit@10500000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x10500000 0x2000>; + }; - pd_mfc: mfc-power-domain@10023c40 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023C40 0x20>; - #power-domain-cells = <0>; - label = "MFC"; - }; + memory-controller@12570000 { + compatible = "samsung,exynos4210-srom"; + reg = <0x12570000 0x14>; + }; - pd_g3d: g3d-power-domain@10023c60 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023C60 0x20>; - #power-domain-cells = <0>; - label = "G3D"; - }; + mipi_phy: video-phy { + compatible = "samsung,s5pv210-mipi-video-phy"; + #phy-cells = <1>; + syscon = <&pmu_system_controller>; + }; - pd_lcd0: lcd0-power-domain@10023c80 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023C80 0x20>; - #power-domain-cells = <0>; - label = "LCD0"; - }; + pd_mfc: mfc-power-domain@10023c40 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023C40 0x20>; + #power-domain-cells = <0>; + label = "MFC"; + }; - pd_tv: tv-power-domain@10023c20 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023C20 0x20>; - #power-domain-cells = <0>; - power-domains = <&pd_lcd0>; - label = "TV"; - }; + pd_g3d: g3d-power-domain@10023c60 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023C60 0x20>; + #power-domain-cells = <0>; + label = "G3D"; + }; - pd_cam: cam-power-domain@10023c00 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023C00 0x20>; - #power-domain-cells = <0>; - label = "CAM"; - }; + pd_lcd0: lcd0-power-domain@10023c80 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023C80 0x20>; + #power-domain-cells = <0>; + label = "LCD0"; + }; - pd_gps: gps-power-domain@10023ce0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023CE0 0x20>; - #power-domain-cells = <0>; - label = "GPS"; - }; + pd_tv: tv-power-domain@10023c20 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023C20 0x20>; + #power-domain-cells = <0>; + power-domains = <&pd_lcd0>; + label = "TV"; + }; - pd_gps_alive: gps-alive-power-domain@10023d00 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023D00 0x20>; - #power-domain-cells = <0>; - label = "GPS alive"; - }; + pd_cam: cam-power-domain@10023c00 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023C00 0x20>; + #power-domain-cells = <0>; + label = "CAM"; + }; - gic: interrupt-controller@10490000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x10490000 0x10000>, <0x10480000 0x10000>; - }; + pd_gps: gps-power-domain@10023ce0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023CE0 0x20>; + #power-domain-cells = <0>; + label = "GPS"; + }; - combiner: interrupt-controller@10440000 { - compatible = "samsung,exynos4210-combiner"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0x10440000 0x1000>; - }; + pd_gps_alive: gps-alive-power-domain@10023d00 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023D00 0x20>; + #power-domain-cells = <0>; + label = "GPS alive"; + }; - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupt-parent = <&combiner>; - interrupts = <2 2>, <3 2>; - }; + gic: interrupt-controller@10490000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x10490000 0x10000>, <0x10480000 0x10000>; + }; - sys_reg: syscon@10010000 { - compatible = "samsung,exynos4-sysreg", "syscon"; - reg = <0x10010000 0x400>; - }; + combiner: interrupt-controller@10440000 { + compatible = "samsung,exynos4210-combiner"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0x10440000 0x1000>; + }; - pmu_system_controller: system-controller@10020000 { - compatible = "samsung,exynos4210-pmu", "syscon"; - reg = <0x10020000 0x4000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - }; + pmu: pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&combiner>; + interrupts = <2 2>, <3 2>; + }; - dsi_0: dsi@11c80000 { - compatible = "samsung,exynos4210-mipi-dsi"; - reg = <0x11C80000 0x10000>; - interrupts = ; - power-domains = <&pd_lcd0>; - phys = <&mipi_phy 1>; - phy-names = "dsim"; - clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>; - clock-names = "bus_clk", "sclk_mipi"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; + sys_reg: syscon@10010000 { + compatible = "samsung,exynos4-sysreg", "syscon"; + reg = <0x10010000 0x400>; + }; - camera { - compatible = "samsung,fimc", "simple-bus"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - #clock-cells = <1>; - clock-output-names = "cam_a_clkout", "cam_b_clkout"; - ranges; + pmu_system_controller: system-controller@10020000 { + compatible = "samsung,exynos4210-pmu", "syscon"; + reg = <0x10020000 0x4000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + }; - fimc_0: fimc@11800000 { - compatible = "samsung,exynos4210-fimc"; - reg = <0x11800000 0x1000>; - interrupts = ; - clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>; - clock-names = "fimc", "sclk_fimc"; - power-domains = <&pd_cam>; - samsung,sysreg = <&sys_reg>; - iommus = <&sysmmu_fimc0>; + dsi_0: dsi@11c80000 { + compatible = "samsung,exynos4210-mipi-dsi"; + reg = <0x11C80000 0x10000>; + interrupts = ; + power-domains = <&pd_lcd0>; + phys = <&mipi_phy 1>; + phy-names = "dsim"; + clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>; + clock-names = "bus_clk", "sclk_mipi"; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; - fimc_1: fimc@11810000 { - compatible = "samsung,exynos4210-fimc"; - reg = <0x11810000 0x1000>; - interrupts = ; - clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>; - clock-names = "fimc", "sclk_fimc"; - power-domains = <&pd_cam>; - samsung,sysreg = <&sys_reg>; - iommus = <&sysmmu_fimc1>; + camera: camera { + compatible = "samsung,fimc", "simple-bus"; status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + #clock-cells = <1>; + clock-output-names = "cam_a_clkout", "cam_b_clkout"; + ranges; + + fimc_0: fimc@11800000 { + compatible = "samsung,exynos4210-fimc"; + reg = <0x11800000 0x1000>; + interrupts = ; + clocks = <&clock CLK_FIMC0>, + <&clock CLK_SCLK_FIMC0>; + clock-names = "fimc", "sclk_fimc"; + power-domains = <&pd_cam>; + samsung,sysreg = <&sys_reg>; + iommus = <&sysmmu_fimc0>; + status = "disabled"; + }; + + fimc_1: fimc@11810000 { + compatible = "samsung,exynos4210-fimc"; + reg = <0x11810000 0x1000>; + interrupts = ; + clocks = <&clock CLK_FIMC1>, + <&clock CLK_SCLK_FIMC1>; + clock-names = "fimc", "sclk_fimc"; + power-domains = <&pd_cam>; + samsung,sysreg = <&sys_reg>; + iommus = <&sysmmu_fimc1>; + status = "disabled"; + }; + + fimc_2: fimc@11820000 { + compatible = "samsung,exynos4210-fimc"; + reg = <0x11820000 0x1000>; + interrupts = ; + clocks = <&clock CLK_FIMC2>, + <&clock CLK_SCLK_FIMC2>; + clock-names = "fimc", "sclk_fimc"; + power-domains = <&pd_cam>; + samsung,sysreg = <&sys_reg>; + iommus = <&sysmmu_fimc2>; + status = "disabled"; + }; + + fimc_3: fimc@11830000 { + compatible = "samsung,exynos4210-fimc"; + reg = <0x11830000 0x1000>; + interrupts = ; + clocks = <&clock CLK_FIMC3>, + <&clock CLK_SCLK_FIMC3>; + clock-names = "fimc", "sclk_fimc"; + power-domains = <&pd_cam>; + samsung,sysreg = <&sys_reg>; + iommus = <&sysmmu_fimc3>; + status = "disabled"; + }; + + csis_0: csis@11880000 { + compatible = "samsung,exynos4210-csis"; + reg = <0x11880000 0x4000>; + interrupts = ; + clocks = <&clock CLK_CSIS0>, + <&clock CLK_SCLK_CSIS0>; + clock-names = "csis", "sclk_csis"; + bus-width = <4>; + power-domains = <&pd_cam>; + phys = <&mipi_phy 0>; + phy-names = "csis"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + csis_1: csis@11890000 { + compatible = "samsung,exynos4210-csis"; + reg = <0x11890000 0x4000>; + interrupts = ; + clocks = <&clock CLK_CSIS1>, + <&clock CLK_SCLK_CSIS1>; + clock-names = "csis", "sclk_csis"; + bus-width = <2>; + power-domains = <&pd_cam>; + phys = <&mipi_phy 2>; + phy-names = "csis"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; }; - fimc_2: fimc@11820000 { - compatible = "samsung,exynos4210-fimc"; - reg = <0x11820000 0x1000>; - interrupts = ; - clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>; - clock-names = "fimc", "sclk_fimc"; - power-domains = <&pd_cam>; - samsung,sysreg = <&sys_reg>; - iommus = <&sysmmu_fimc2>; + rtc: rtc@10070000 { + compatible = "samsung,s3c6410-rtc"; + reg = <0x10070000 0x100>; + interrupt-parent = <&pmu_system_controller>; + interrupts = , + ; + clocks = <&clock CLK_RTC>; + clock-names = "rtc"; status = "disabled"; }; - fimc_3: fimc@11830000 { - compatible = "samsung,exynos4210-fimc"; - reg = <0x11830000 0x1000>; - interrupts = ; - clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>; - clock-names = "fimc", "sclk_fimc"; - power-domains = <&pd_cam>; - samsung,sysreg = <&sys_reg>; - iommus = <&sysmmu_fimc3>; + keypad: keypad@100a0000 { + compatible = "samsung,s5pv210-keypad"; + reg = <0x100A0000 0x100>; + interrupts = ; + clocks = <&clock CLK_KEYIF>; + clock-names = "keypad"; status = "disabled"; }; - csis_0: csis@11880000 { - compatible = "samsung,exynos4210-csis"; - reg = <0x11880000 0x4000>; - interrupts = ; - clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>; - clock-names = "csis", "sclk_csis"; - bus-width = <4>; - power-domains = <&pd_cam>; - phys = <&mipi_phy 0>; - phy-names = "csis"; + sdhci_0: sdhci@12510000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12510000 0x100>; + interrupts = ; + clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; + clock-names = "hsmmc", "mmc_busclk.2"; status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; }; - csis_1: csis@11890000 { - compatible = "samsung,exynos4210-csis"; - reg = <0x11890000 0x4000>; - interrupts = ; - clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>; - clock-names = "csis", "sclk_csis"; - bus-width = <2>; - power-domains = <&pd_cam>; - phys = <&mipi_phy 2>; - phy-names = "csis"; + sdhci_1: sdhci@12520000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12520000 0x100>; + interrupts = ; + clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; + clock-names = "hsmmc", "mmc_busclk.2"; status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; }; - }; - - rtc: rtc@10070000 { - compatible = "samsung,s3c6410-rtc"; - reg = <0x10070000 0x100>; - interrupt-parent = <&pmu_system_controller>; - interrupts = , - ; - clocks = <&clock CLK_RTC>; - clock-names = "rtc"; - status = "disabled"; - }; - - keypad: keypad@100a0000 { - compatible = "samsung,s5pv210-keypad"; - reg = <0x100A0000 0x100>; - interrupts = ; - clocks = <&clock CLK_KEYIF>; - clock-names = "keypad"; - status = "disabled"; - }; - - sdhci_0: sdhci@12510000 { - compatible = "samsung,exynos4210-sdhci"; - reg = <0x12510000 0x100>; - interrupts = ; - clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; - clock-names = "hsmmc", "mmc_busclk.2"; - status = "disabled"; - }; - sdhci_1: sdhci@12520000 { - compatible = "samsung,exynos4210-sdhci"; - reg = <0x12520000 0x100>; - interrupts = ; - clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; - clock-names = "hsmmc", "mmc_busclk.2"; - status = "disabled"; - }; - - sdhci_2: sdhci@12530000 { - compatible = "samsung,exynos4210-sdhci"; - reg = <0x12530000 0x100>; - interrupts = ; - clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; - clock-names = "hsmmc", "mmc_busclk.2"; - status = "disabled"; - }; - - sdhci_3: sdhci@12540000 { - compatible = "samsung,exynos4210-sdhci"; - reg = <0x12540000 0x100>; - interrupts = ; - clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; - clock-names = "hsmmc", "mmc_busclk.2"; - status = "disabled"; - }; - - exynos_usbphy: exynos-usbphy@125b0000 { - compatible = "samsung,exynos4210-usb2-phy"; - reg = <0x125B0000 0x100>; - samsung,pmureg-phandle = <&pmu_system_controller>; - clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>; - clock-names = "phy", "ref"; - #phy-cells = <1>; - status = "disabled"; - }; - - hsotg: hsotg@12480000 { - compatible = "samsung,s3c6400-hsotg"; - reg = <0x12480000 0x20000>; - interrupts = ; - clocks = <&clock CLK_USB_DEVICE>; - clock-names = "otg"; - phys = <&exynos_usbphy 0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; + sdhci_2: sdhci@12530000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12530000 0x100>; + interrupts = ; + clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; + clock-names = "hsmmc", "mmc_busclk.2"; + status = "disabled"; + }; - ehci: ehci@12580000 { - compatible = "samsung,exynos4210-ehci"; - reg = <0x12580000 0x100>; - interrupts = ; - clocks = <&clock CLK_USB_HOST>; - clock-names = "usbhost"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - phys = <&exynos_usbphy 1>; + sdhci_3: sdhci@12540000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12540000 0x100>; + interrupts = ; + clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; + clock-names = "hsmmc", "mmc_busclk.2"; status = "disabled"; }; - port@1 { - reg = <1>; - phys = <&exynos_usbphy 2>; + + exynos_usbphy: exynos-usbphy@125b0000 { + compatible = "samsung,exynos4210-usb2-phy"; + reg = <0x125B0000 0x100>; + samsung,pmureg-phandle = <&pmu_system_controller>; + clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>; + clock-names = "phy", "ref"; + #phy-cells = <1>; status = "disabled"; }; - port@2 { - reg = <2>; - phys = <&exynos_usbphy 3>; + + hsotg: hsotg@12480000 { + compatible = "samsung,s3c6400-hsotg"; + reg = <0x12480000 0x20000>; + interrupts = ; + clocks = <&clock CLK_USB_DEVICE>; + clock-names = "otg"; + phys = <&exynos_usbphy 0>; + phy-names = "usb2-phy"; status = "disabled"; }; - }; - ohci: ohci@12590000 { - compatible = "samsung,exynos4210-ohci"; - reg = <0x12590000 0x100>; - interrupts = ; - clocks = <&clock CLK_USB_HOST>; - clock-names = "usbhost"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - phys = <&exynos_usbphy 1>; + ehci: ehci@12580000 { + compatible = "samsung,exynos4210-ehci"; + reg = <0x12580000 0x100>; + interrupts = ; + clocks = <&clock CLK_USB_HOST>; + clock-names = "usbhost"; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + phys = <&exynos_usbphy 1>; + status = "disabled"; + }; + port@1 { + reg = <1>; + phys = <&exynos_usbphy 2>; + status = "disabled"; + }; + port@2 { + reg = <2>; + phys = <&exynos_usbphy 3>; + status = "disabled"; + }; }; - }; - i2s1: i2s@13960000 { - compatible = "samsung,s3c6410-i2s"; - reg = <0x13960000 0x100>; - clocks = <&clock CLK_I2S1>; - clock-names = "iis"; - #clock-cells = <1>; - clock-output-names = "i2s_cdclk1"; - dmas = <&pdma1 12>, <&pdma1 11>; - dma-names = "tx", "rx"; - #sound-dai-cells = <1>; - status = "disabled"; - }; + ohci: ohci@12590000 { + compatible = "samsung,exynos4210-ohci"; + reg = <0x12590000 0x100>; + interrupts = ; + clocks = <&clock CLK_USB_HOST>; + clock-names = "usbhost"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + phys = <&exynos_usbphy 1>; + status = "disabled"; + }; + }; - i2s2: i2s@13970000 { - compatible = "samsung,s3c6410-i2s"; - reg = <0x13970000 0x100>; - clocks = <&clock CLK_I2S2>; - clock-names = "iis"; - #clock-cells = <1>; - clock-output-names = "i2s_cdclk2"; - dmas = <&pdma0 14>, <&pdma0 13>; - dma-names = "tx", "rx"; - #sound-dai-cells = <1>; - status = "disabled"; - }; + i2s1: i2s@13960000 { + compatible = "samsung,s3c6410-i2s"; + reg = <0x13960000 0x100>; + clocks = <&clock CLK_I2S1>; + clock-names = "iis"; + #clock-cells = <1>; + clock-output-names = "i2s_cdclk1"; + dmas = <&pdma1 12>, <&pdma1 11>; + dma-names = "tx", "rx"; + #sound-dai-cells = <1>; + status = "disabled"; + }; - mfc: codec@13400000 { - compatible = "samsung,mfc-v5"; - reg = <0x13400000 0x10000>; - interrupts = ; - power-domains = <&pd_mfc>; - clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>; - clock-names = "mfc", "sclk_mfc"; - iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; - iommu-names = "left", "right"; - }; + i2s2: i2s@13970000 { + compatible = "samsung,s3c6410-i2s"; + reg = <0x13970000 0x100>; + clocks = <&clock CLK_I2S2>; + clock-names = "iis"; + #clock-cells = <1>; + clock-output-names = "i2s_cdclk2"; + dmas = <&pdma0 14>, <&pdma0 13>; + dma-names = "tx", "rx"; + #sound-dai-cells = <1>; + status = "disabled"; + }; - serial_0: serial@13800000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13800000 0x100>; - interrupts = ; - clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma0 15>, <&pdma0 16>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + mfc: codec@13400000 { + compatible = "samsung,mfc-v5"; + reg = <0x13400000 0x10000>; + interrupts = ; + power-domains = <&pd_mfc>; + clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>; + clock-names = "mfc", "sclk_mfc"; + iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; + iommu-names = "left", "right"; + }; - serial_1: serial@13810000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13810000 0x100>; - interrupts = ; - clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma1 15>, <&pdma1 16>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + serial_0: serial@13800000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13800000 0x100>; + interrupts = ; + clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; + dmas = <&pdma0 15>, <&pdma0 16>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - serial_2: serial@13820000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13820000 0x100>; - interrupts = ; - clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma0 17>, <&pdma0 18>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + serial_1: serial@13810000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13810000 0x100>; + interrupts = ; + clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; + clock-names = "uart", "clk_uart_baud0"; + dmas = <&pdma1 15>, <&pdma1 16>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - serial_3: serial@13830000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13830000 0x100>; - interrupts = ; - clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma1 17>, <&pdma1 18>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + serial_2: serial@13820000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13820000 0x100>; + interrupts = ; + clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; + clock-names = "uart", "clk_uart_baud0"; + dmas = <&pdma0 17>, <&pdma0 18>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - i2c_0: i2c@13860000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13860000 0x100>; - interrupts = ; - clocks = <&clock CLK_I2C0>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; - status = "disabled"; - }; + serial_3: serial@13830000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13830000 0x100>; + interrupts = ; + clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; + clock-names = "uart", "clk_uart_baud0"; + dmas = <&pdma1 17>, <&pdma1 18>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - i2c_1: i2c@13870000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13870000 0x100>; - interrupts = ; - clocks = <&clock CLK_I2C1>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_bus>; - status = "disabled"; - }; + i2c_0: i2c@13860000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x13860000 0x100>; + interrupts = ; + clocks = <&clock CLK_I2C0>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_bus>; + status = "disabled"; + }; - i2c_2: i2c@13880000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13880000 0x100>; - interrupts = ; - clocks = <&clock CLK_I2C2>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_bus>; - status = "disabled"; - }; + i2c_1: i2c@13870000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x13870000 0x100>; + interrupts = ; + clocks = <&clock CLK_I2C1>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_bus>; + status = "disabled"; + }; - i2c_3: i2c@13890000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13890000 0x100>; - interrupts = ; - clocks = <&clock CLK_I2C3>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_bus>; - status = "disabled"; - }; + i2c_2: i2c@13880000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x13880000 0x100>; + interrupts = ; + clocks = <&clock CLK_I2C2>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_bus>; + status = "disabled"; + }; - i2c_4: i2c@138a0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138A0000 0x100>; - interrupts = ; - clocks = <&clock CLK_I2C4>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_bus>; - status = "disabled"; - }; + i2c_3: i2c@13890000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x13890000 0x100>; + interrupts = ; + clocks = <&clock CLK_I2C3>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_bus>; + status = "disabled"; + }; - i2c_5: i2c@138b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138B0000 0x100>; - interrupts = ; - clocks = <&clock CLK_I2C5>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_bus>; - status = "disabled"; - }; + i2c_4: i2c@138a0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x138A0000 0x100>; + interrupts = ; + clocks = <&clock CLK_I2C4>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_bus>; + status = "disabled"; + }; - i2c_6: i2c@138c0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138C0000 0x100>; - interrupts = ; - clocks = <&clock CLK_I2C6>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_bus>; - status = "disabled"; - }; + i2c_5: i2c@138b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x138B0000 0x100>; + interrupts = ; + clocks = <&clock CLK_I2C5>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_bus>; + status = "disabled"; + }; - i2c_7: i2c@138d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138D0000 0x100>; - interrupts = ; - clocks = <&clock CLK_I2C7>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_bus>; - status = "disabled"; - }; + i2c_6: i2c@138c0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x138C0000 0x100>; + interrupts = ; + clocks = <&clock CLK_I2C6>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_bus>; + status = "disabled"; + }; - i2c_8: i2c@138e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-hdmiphy-i2c"; - reg = <0x138E0000 0x100>; - interrupts = ; - clocks = <&clock CLK_I2C_HDMI>; - clock-names = "i2c"; - status = "disabled"; - - hdmi_i2c_phy: hdmiphy@38 { - compatible = "exynos4210-hdmiphy"; - reg = <0x38>; + i2c_7: i2c@138d0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x138D0000 0x100>; + interrupts = ; + clocks = <&clock CLK_I2C7>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_bus>; + status = "disabled"; }; - }; - spi_0: spi@13920000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13920000 0x100>; - interrupts = ; - dmas = <&pdma0 7>, <&pdma0 6>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_bus>; - status = "disabled"; - }; + i2c_8: i2c@138e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-hdmiphy-i2c"; + reg = <0x138E0000 0x100>; + interrupts = ; + clocks = <&clock CLK_I2C_HDMI>; + clock-names = "i2c"; + status = "disabled"; - spi_1: spi@13930000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13930000 0x100>; - interrupts = ; - dmas = <&pdma1 7>, <&pdma1 6>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - status = "disabled"; - }; + hdmi_i2c_phy: hdmiphy@38 { + compatible = "exynos4210-hdmiphy"; + reg = <0x38>; + }; + }; - spi_2: spi@13940000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13940000 0x100>; - interrupts = ; - dmas = <&pdma0 9>, <&pdma0 8>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_bus>; - status = "disabled"; - }; + spi_0: spi@13920000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x13920000 0x100>; + interrupts = ; + dmas = <&pdma0 7>, <&pdma0 6>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; + clock-names = "spi", "spi_busclk0"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus>; + status = "disabled"; + }; - pwm: pwm@139d0000 { - compatible = "samsung,exynos4210-pwm"; - reg = <0x139D0000 0x1000>; - interrupts = , - , - , - , - ; - clocks = <&clock CLK_PWM>; - clock-names = "timers"; - #pwm-cells = <3>; - status = "disabled"; - }; + spi_1: spi@13930000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x13930000 0x100>; + interrupts = ; + dmas = <&pdma1 7>, <&pdma1 6>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; + clock-names = "spi", "spi_busclk0"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + status = "disabled"; + }; - amba { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; + spi_2: spi@13940000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x13940000 0x100>; + interrupts = ; + dmas = <&pdma0 9>, <&pdma0 8>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; + clock-names = "spi", "spi_busclk0"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_bus>; + status = "disabled"; + }; - pdma0: pdma@12680000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12680000 0x1000>; - interrupts = ; - clocks = <&clock CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - pdma1: pdma@12690000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12690000 0x1000>; - interrupts = ; - clocks = <&clock CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - mdma1: mdma@12850000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12850000 0x1000>; - interrupts = ; - clocks = <&clock CLK_MDMA>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; + pwm: pwm@139d0000 { + compatible = "samsung,exynos4210-pwm"; + reg = <0x139D0000 0x1000>; + interrupts = , + , + , + , + ; + clocks = <&clock CLK_PWM>; + clock-names = "timers"; + #pwm-cells = <3>; + status = "disabled"; }; - }; - fimd: fimd@11c00000 { - compatible = "samsung,exynos4210-fimd"; - interrupt-parent = <&combiner>; - reg = <0x11c00000 0x20000>; - interrupt-names = "fifo", "vsync", "lcd_sys"; - interrupts = <11 0>, <11 1>, <11 2>; - clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>; - clock-names = "sclk_fimd", "fimd"; - power-domains = <&pd_lcd0>; - iommus = <&sysmmu_fimd0>; - samsung,sysreg = <&sys_reg>; - status = "disabled"; - }; + amba { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + pdma0: pdma@12680000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12680000 0x1000>; + interrupts = ; + clocks = <&clock CLK_PDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + pdma1: pdma@12690000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12690000 0x1000>; + interrupts = ; + clocks = <&clock CLK_PDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + mdma1: mdma@12850000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12850000 0x1000>; + interrupts = ; + clocks = <&clock CLK_MDMA>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <1>; + }; + }; - tmu: tmu@100c0000 { - #include "exynos4412-tmu-sensor-conf.dtsi" - }; + fimd: fimd@11c00000 { + compatible = "samsung,exynos4210-fimd"; + interrupt-parent = <&combiner>; + reg = <0x11c00000 0x20000>; + interrupt-names = "fifo", "vsync", "lcd_sys"; + interrupts = <11 0>, <11 1>, <11 2>; + clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>; + clock-names = "sclk_fimd", "fimd"; + power-domains = <&pd_lcd0>; + iommus = <&sysmmu_fimd0>; + samsung,sysreg = <&sys_reg>; + status = "disabled"; + }; - jpeg_codec: jpeg-codec@11840000 { - compatible = "samsung,exynos4210-jpeg"; - reg = <0x11840000 0x1000>; - interrupts = ; - clocks = <&clock CLK_JPEG>; - clock-names = "jpeg"; - power-domains = <&pd_cam>; - iommus = <&sysmmu_jpeg>; - }; + tmu: tmu@100c0000 { + interrupt-parent = <&combiner>; + reg = <0x100C0000 0x100>; + interrupts = <2 4>; + status = "disabled"; + #include "exynos4412-tmu-sensor-conf.dtsi" + }; - rotator: rotator@12810000 { - compatible = "samsung,exynos4210-rotator"; - reg = <0x12810000 0x64>; - interrupts = ; - clocks = <&clock CLK_ROTATOR>; - clock-names = "rotator"; - iommus = <&sysmmu_rotator>; - }; + jpeg_codec: jpeg-codec@11840000 { + compatible = "samsung,exynos4210-jpeg"; + reg = <0x11840000 0x1000>; + interrupts = ; + clocks = <&clock CLK_JPEG>; + clock-names = "jpeg"; + power-domains = <&pd_cam>; + iommus = <&sysmmu_jpeg>; + }; - hdmi: hdmi@12d00000 { - compatible = "samsung,exynos4210-hdmi"; - reg = <0x12D00000 0x70000>; - interrupts = ; - clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy", - "mout_hdmi"; - clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, - <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, - <&clock CLK_MOUT_HDMI>; - phy = <&hdmi_i2c_phy>; - power-domains = <&pd_tv>; - samsung,syscon-phandle = <&pmu_system_controller>; - #sound-dai-cells = <0>; - status = "disabled"; - }; + rotator: rotator@12810000 { + compatible = "samsung,exynos4210-rotator"; + reg = <0x12810000 0x64>; + interrupts = ; + clocks = <&clock CLK_ROTATOR>; + clock-names = "rotator"; + iommus = <&sysmmu_rotator>; + }; - hdmicec: cec@100b0000 { - compatible = "samsung,s5p-cec"; - reg = <0x100B0000 0x200>; - interrupts = ; - clocks = <&clock CLK_HDMI_CEC>; - clock-names = "hdmicec"; - samsung,syscon-phandle = <&pmu_system_controller>; - hdmi-phandle = <&hdmi>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "disabled"; - }; + hdmi: hdmi@12d00000 { + compatible = "samsung,exynos4210-hdmi"; + reg = <0x12D00000 0x70000>; + interrupts = ; + clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", + "sclk_hdmiphy", "mout_hdmi"; + clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, + <&clock CLK_SCLK_PIXEL>, + <&clock CLK_SCLK_HDMIPHY>, + <&clock CLK_MOUT_HDMI>; + phy = <&hdmi_i2c_phy>; + power-domains = <&pd_tv>; + samsung,syscon-phandle = <&pmu_system_controller>; + #sound-dai-cells = <0>; + status = "disabled"; + }; - mixer: mixer@12c10000 { - compatible = "samsung,exynos4210-mixer"; - interrupts = ; - reg = <0x12C10000 0x2100>, <0x12c00000 0x300>; - power-domains = <&pd_tv>; - iommus = <&sysmmu_tv>; - status = "disabled"; - }; + hdmicec: cec@100b0000 { + compatible = "samsung,s5p-cec"; + reg = <0x100B0000 0x200>; + interrupts = ; + clocks = <&clock CLK_HDMI_CEC>; + clock-names = "hdmicec"; + samsung,syscon-phandle = <&pmu_system_controller>; + hdmi-phandle = <&hdmi>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "disabled"; + }; - ppmu_dmc0: ppmu_dmc0@106a0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x106a0000 0x2000>; - clocks = <&clock CLK_PPMUDMC0>; - clock-names = "ppmu"; - status = "disabled"; - }; + mixer: mixer@12c10000 { + compatible = "samsung,exynos4210-mixer"; + interrupts = ; + reg = <0x12C10000 0x2100>, <0x12c00000 0x300>; + power-domains = <&pd_tv>; + iommus = <&sysmmu_tv>; + status = "disabled"; + }; - ppmu_dmc1: ppmu_dmc1@106b0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x106b0000 0x2000>; - clocks = <&clock CLK_PPMUDMC1>; - clock-names = "ppmu"; - status = "disabled"; - }; + ppmu_dmc0: ppmu_dmc0@106a0000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x106a0000 0x2000>; + clocks = <&clock CLK_PPMUDMC0>; + clock-names = "ppmu"; + status = "disabled"; + }; - ppmu_cpu: ppmu_cpu@106c0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x106c0000 0x2000>; - clocks = <&clock CLK_PPMUCPU>; - clock-names = "ppmu"; - status = "disabled"; - }; + ppmu_dmc1: ppmu_dmc1@106b0000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x106b0000 0x2000>; + clocks = <&clock CLK_PPMUDMC1>; + clock-names = "ppmu"; + status = "disabled"; + }; - ppmu_acp: ppmu_acp@10ae0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x106e0000 0x2000>; - status = "disabled"; - }; + ppmu_cpu: ppmu_cpu@106c0000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x106c0000 0x2000>; + clocks = <&clock CLK_PPMUCPU>; + clock-names = "ppmu"; + status = "disabled"; + }; - ppmu_rightbus: ppmu_rightbus@112a0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x112a0000 0x2000>; - clocks = <&clock CLK_PPMURIGHT>; - clock-names = "ppmu"; - status = "disabled"; - }; + ppmu_rightbus: ppmu_rightbus@112a0000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x112a0000 0x2000>; + clocks = <&clock CLK_PPMURIGHT>; + clock-names = "ppmu"; + status = "disabled"; + }; - ppmu_leftbus: ppmu_leftbus0@116a0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x116a0000 0x2000>; - clocks = <&clock CLK_PPMULEFT>; - clock-names = "ppmu"; - status = "disabled"; - }; + ppmu_leftbus: ppmu_leftbus0@116a0000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x116a0000 0x2000>; + clocks = <&clock CLK_PPMULEFT>; + clock-names = "ppmu"; + status = "disabled"; + }; - ppmu_camif: ppmu_camif@11ac0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x11ac0000 0x2000>; - clocks = <&clock CLK_PPMUCAMIF>; - clock-names = "ppmu"; - status = "disabled"; - }; + ppmu_camif: ppmu_camif@11ac0000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x11ac0000 0x2000>; + clocks = <&clock CLK_PPMUCAMIF>; + clock-names = "ppmu"; + status = "disabled"; + }; - ppmu_lcd0: ppmu_lcd0@11e40000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x11e40000 0x2000>; - clocks = <&clock CLK_PPMULCD0>; - clock-names = "ppmu"; - status = "disabled"; - }; + ppmu_lcd0: ppmu_lcd0@11e40000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x11e40000 0x2000>; + clocks = <&clock CLK_PPMULCD0>; + clock-names = "ppmu"; + status = "disabled"; + }; - ppmu_fsys: ppmu_g3d@12630000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x12630000 0x2000>; - status = "disabled"; - }; + ppmu_fsys: ppmu_g3d@12630000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x12630000 0x2000>; + status = "disabled"; + }; - ppmu_image: ppmu_image@12aa0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x12aa0000 0x2000>; - clocks = <&clock CLK_PPMUIMAGE>; - clock-names = "ppmu"; - status = "disabled"; - }; + ppmu_image: ppmu_image@12aa0000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x12aa0000 0x2000>; + clocks = <&clock CLK_PPMUIMAGE>; + clock-names = "ppmu"; + status = "disabled"; + }; - ppmu_tv: ppmu_tv@12e40000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x12e40000 0x2000>; - clocks = <&clock CLK_PPMUTV>; - clock-names = "ppmu"; - status = "disabled"; - }; + ppmu_tv: ppmu_tv@12e40000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x12e40000 0x2000>; + clocks = <&clock CLK_PPMUTV>; + clock-names = "ppmu"; + status = "disabled"; + }; - ppmu_g3d: ppmu_g3d@13220000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x13220000 0x2000>; - clocks = <&clock CLK_PPMUG3D>; - clock-names = "ppmu"; - status = "disabled"; - }; + ppmu_g3d: ppmu_g3d@13220000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x13220000 0x2000>; + clocks = <&clock CLK_PPMUG3D>; + clock-names = "ppmu"; + status = "disabled"; + }; - ppmu_mfc_left: ppmu_mfc_left@13660000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x13660000 0x2000>; - clocks = <&clock CLK_PPMUMFC_L>; - clock-names = "ppmu"; - status = "disabled"; - }; + ppmu_mfc_left: ppmu_mfc_left@13660000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x13660000 0x2000>; + clocks = <&clock CLK_PPMUMFC_L>; + clock-names = "ppmu"; + status = "disabled"; + }; - ppmu_mfc_right: ppmu_mfc_right@13670000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x13670000 0x2000>; - clocks = <&clock CLK_PPMUMFC_R>; - clock-names = "ppmu"; - status = "disabled"; - }; + ppmu_mfc_right: ppmu_mfc_right@13670000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x13670000 0x2000>; + clocks = <&clock CLK_PPMUMFC_R>; + clock-names = "ppmu"; + status = "disabled"; + }; - sysmmu_mfc_l: sysmmu@13620000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13620000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 5>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; - power-domains = <&pd_mfc>; - #iommu-cells = <0>; - }; + sysmmu_mfc_l: sysmmu@13620000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13620000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <5 5>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; + power-domains = <&pd_mfc>; + #iommu-cells = <0>; + }; - sysmmu_mfc_r: sysmmu@13630000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13630000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 6>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; - power-domains = <&pd_mfc>; - #iommu-cells = <0>; - }; + sysmmu_mfc_r: sysmmu@13630000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13630000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <5 6>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; + power-domains = <&pd_mfc>; + #iommu-cells = <0>; + }; - sysmmu_tv: sysmmu@12e20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12E20000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 4>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>; - power-domains = <&pd_tv>; - #iommu-cells = <0>; - }; + sysmmu_tv: sysmmu@12e20000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x12E20000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <5 4>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>; + power-domains = <&pd_tv>; + #iommu-cells = <0>; + }; - sysmmu_fimc0: sysmmu@11a20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11A20000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>; - power-domains = <&pd_cam>; - #iommu-cells = <0>; - }; + sysmmu_fimc0: sysmmu@11a20000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11A20000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>; + power-domains = <&pd_cam>; + #iommu-cells = <0>; + }; - sysmmu_fimc1: sysmmu@11a30000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11A30000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 3>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>; - power-domains = <&pd_cam>; - #iommu-cells = <0>; - }; + sysmmu_fimc1: sysmmu@11a30000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11A30000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 3>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>; + power-domains = <&pd_cam>; + #iommu-cells = <0>; + }; - sysmmu_fimc2: sysmmu@11a40000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11A40000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 4>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>; - power-domains = <&pd_cam>; - #iommu-cells = <0>; - }; + sysmmu_fimc2: sysmmu@11a40000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11A40000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 4>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>; + power-domains = <&pd_cam>; + #iommu-cells = <0>; + }; - sysmmu_fimc3: sysmmu@11a50000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11A50000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 5>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>; - power-domains = <&pd_cam>; - #iommu-cells = <0>; - }; + sysmmu_fimc3: sysmmu@11a50000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11A50000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 5>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>; + power-domains = <&pd_cam>; + #iommu-cells = <0>; + }; - sysmmu_jpeg: sysmmu@11a60000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11A60000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 6>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; - power-domains = <&pd_cam>; - #iommu-cells = <0>; - }; + sysmmu_jpeg: sysmmu@11a60000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11A60000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 6>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; + power-domains = <&pd_cam>; + #iommu-cells = <0>; + }; - sysmmu_rotator: sysmmu@12a30000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12A30000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; - #iommu-cells = <0>; - }; + sysmmu_rotator: sysmmu@12a30000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x12A30000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <5 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_ROTATOR>, + <&clock CLK_ROTATOR>; + #iommu-cells = <0>; + }; - sysmmu_fimd0: sysmmu@11e20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11E20000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>; - power-domains = <&pd_lcd0>; - #iommu-cells = <0>; - }; + sysmmu_fimd0: sysmmu@11e20000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11E20000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <5 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>; + power-domains = <&pd_lcd0>; + #iommu-cells = <0>; + }; - sss: sss@10830000 { - compatible = "samsung,exynos4210-secss"; - reg = <0x10830000 0x300>; - interrupts = ; - clocks = <&clock CLK_SSS>; - clock-names = "secss"; - }; + sss: sss@10830000 { + compatible = "samsung,exynos4210-secss"; + reg = <0x10830000 0x300>; + interrupts = ; + clocks = <&clock CLK_SSS>; + clock-names = "secss"; + }; - prng: rng@10830400 { - compatible = "samsung,exynos4-rng"; - reg = <0x10830400 0x200>; - clocks = <&clock CLK_SSS>; - clock-names = "secss"; + prng: rng@10830400 { + compatible = "samsung,exynos4-rng"; + reg = <0x10830400 0x200>; + clocks = <&clock CLK_SSS>; + clock-names = "secss"; + }; }; }; Index: sys/gnu/dts/arm/exynos4210-pinctrl.dtsi =================================================================== --- sys/gnu/dts/arm/exynos4210-pinctrl.dtsi +++ sys/gnu/dts/arm/exynos4210-pinctrl.dtsi @@ -13,853 +13,851 @@ #include -/ { - pinctrl@11400000 { - gpa0: gpa0 { - gpio-controller; - #gpio-cells = <2>; +&pinctrl_0 { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb: gpb { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe0: gpe0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe1: gpe1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe2: gpe2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe3: gpe3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe4: gpe4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf2: gpf2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf3: gpf3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart0_data: uart0-data { + samsung,pins = "gpa0-0", "gpa0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart0_fctl: uart0-fctl { + samsung,pins = "gpa0-2", "gpa0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart1_data: uart1-data { + samsung,pins = "gpa0-4", "gpa0-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart1_fctl: uart1-fctl { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c2_bus: i2c2-bus { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart2_data: uart2-data { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart2_fctl: uart2-fctl { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart_audio_a: uart-audio-a { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c3_bus: i2c3-bus { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart3_data: uart3-data { + samsung,pins = "gpa1-4", "gpa1-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart_audio_b: uart-audio-b { + samsung,pins = "gpa1-4", "gpa1-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi0_bus: spi0-bus { + samsung,pins = "gpb-0", "gpb-2", "gpb-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c4_bus: i2c4-bus { + samsung,pins = "gpb-2", "gpb-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi1_bus: spi1-bus { + samsung,pins = "gpb-4", "gpb-6", "gpb-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c5_bus: i2c5-bus { + samsung,pins = "gpb-6", "gpb-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2s1_bus: i2s1-bus { + samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", + "gpc0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pcm1_bus: pcm1-bus { + samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", + "gpc0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + ac97_bus: ac97-bus { + samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", + "gpc0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2s2_bus: i2s2-bus { + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", + "gpc1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pcm2_bus: pcm2-bus { + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", + "gpc1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spdif_bus: spdif-bus { + samsung,pins = "gpc1-0", "gpc1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c6_bus: i2c6-bus { + samsung,pins = "gpc1-3", "gpc1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi2_bus: spi2-bus { + samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c7_bus: i2c7-bus { + samsung,pins = "gpd0-2", "gpd0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c0_bus: i2c0-bus { + samsung,pins = "gpd1-0", "gpd1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c1_bus: i2c1-bus { + samsung,pins = "gpd1-2", "gpd1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm0_out: pwm0-out { + samsung,pins = "gpd0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm1_out: pwm1-out { + samsung,pins = "gpd0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm2_out: pwm2-out { + samsung,pins = "gpd0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm3_out: pwm3-out { + samsung,pins = "gpd0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_ctrl: lcd-ctrl { + samsung,pins = "gpd0-0", "gpd0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_sync: lcd-sync { + samsung,pins = "gpf0-0", "gpf0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_en: lcd-en { + samsung,pins = "gpe3-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_clk: lcd-clk { + samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_data16: lcd-data-width16 { + samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", + "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", + "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7", + "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_data18: lcd-data-width18 { + samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1", + "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7", + "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", + "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", + "gpf3-2", "gpf3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_data24: lcd-data-width24 { + samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", + "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", + "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", + "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", + "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", + "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_1 { + gpj0: gpj0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpj1: gpj1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk0: gpk0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk1: gpk1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk2: gpk2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk3: gpk3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpl0: gpl0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpl1: gpl1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpl2: gpl2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpy0: gpy0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy1: gpy1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy2: gpy2 { + gpio-controller; + #gpio-cells = <2>; + }; - gpa1: gpa1 { - gpio-controller; - #gpio-cells = <2>; + gpy3: gpy3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy4: gpy4 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy5: gpy5 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy6: gpy6 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpx0: gpx0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + #interrupt-cells = <2>; + }; + + gpx1: gpx1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + #interrupt-cells = <2>; + }; + + gpx2: gpx2 { + gpio-controller; + #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx3: gpx3 { + gpio-controller; + #gpio-cells = <2>; - gpb: gpb { - gpio-controller; - #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; - interrupt-controller; - #interrupt-cells = <2>; - }; + sd0_clk: sd0-clk { + samsung,pins = "gpk0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; - gpc0: gpc0 { - gpio-controller; - #gpio-cells = <2>; + sd0_cmd: sd0-cmd { + samsung,pins = "gpk0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_cd: sd0-cd { + samsung,pins = "gpk0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus1: sd0-bus-width1 { + samsung,pins = "gpk0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus4: sd0-bus-width4 { + samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus8: sd0-bus-width8 { + samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd4_clk: sd4-clk { + samsung,pins = "gpk0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd4_cmd: sd4-cmd { + samsung,pins = "gpk0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd4_cd: sd4-cd { + samsung,pins = "gpk0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd4_bus1: sd4-bus-width1 { + samsung,pins = "gpk0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd4_bus4: sd4-bus-width4 { + samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd4_bus8: sd4-bus-width8 { + samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_clk: sd1-clk { + samsung,pins = "gpk1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_cmd: sd1-cmd { + samsung,pins = "gpk1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_cd: sd1-cd { + samsung,pins = "gpk1-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_bus1: sd1-bus-width1 { + samsung,pins = "gpk1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_bus4: sd1-bus-width4 { + samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_clk: sd2-clk { + samsung,pins = "gpk2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_cmd: sd2-cmd { + samsung,pins = "gpk2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_cd: sd2-cd { + samsung,pins = "gpk2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus1: sd2-bus-width1 { + samsung,pins = "gpk2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus4: sd2-bus-width4 { + samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus8: sd2-bus-width8 { + samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd3_clk: sd3-clk { + samsung,pins = "gpk3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd3_cmd: sd3-cmd { + samsung,pins = "gpk3-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd3_cd: sd3-cd { + samsung,pins = "gpk3-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd3_bus1: sd3-bus-width1 { + samsung,pins = "gpk3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd3_bus4: sd3-bus-width4 { + samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eint0: ext-int0 { + samsung,pins = "gpx0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eint8: ext-int8 { + samsung,pins = "gpx1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eint15: ext-int15 { + samsung,pins = "gpx1-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eint16: ext-int16 { + samsung,pins = "gpx2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eint31: ext-int31 { + samsung,pins = "gpx3-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_port_a_io: cam-port-a-io { + samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", + "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", + "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_port_a_clk_active: cam-port-a-clk-active { + samsung,pins = "gpj1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_port_a_clk_idle: cam-port-a-clk-idle { + samsung,pins = "gpj1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hdmi_cec: hdmi-cec { + samsung,pins = "gpx3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_2 { + gpz: gpz { + gpio-controller; + #gpio-cells = <2>; + }; + + i2s0_bus: i2s0-bus { + samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", + "gpz-4", "gpz-5", "gpz-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd0: gpd0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe0: gpe0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe1: gpe1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe2: gpe2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe3: gpe3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe4: gpe4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf0: gpf0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf2: gpf2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf3: gpf3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data { - samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_bus: i2c2-bus { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_data: uart2-data { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_fctl: uart2-fctl { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart_audio_a: uart-audio-a { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c3_bus: i2c3-bus { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart3_data: uart3-data { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart_audio_b: uart-audio-b { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpb-0", "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c4_bus: i2c4-bus { - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi1_bus: spi1-bus { - samsung,pins = "gpb-4", "gpb-6", "gpb-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c5_bus: i2c5-bus { - samsung,pins = "gpb-6", "gpb-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s1_bus: i2s1-bus { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm1_bus: pcm1-bus { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - ac97_bus: ac97-bus { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s2_bus: i2s2-bus { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm2_bus: pcm2-bus { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spdif_bus: spdif-bus { - samsung,pins = "gpc1-0", "gpc1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c6_bus: i2c6-bus { - samsung,pins = "gpc1-3", "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi2_bus: spi2-bus { - samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c7_bus: i2c7-bus { - samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c0_bus: i2c0-bus { - samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c1_bus: i2c1-bus { - samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm0_out: pwm0-out { - samsung,pins = "gpd0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm1_out: pwm1-out { - samsung,pins = "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm2_out: pwm2-out { - samsung,pins = "gpd0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm3_out: pwm3-out { - samsung,pins = "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_ctrl: lcd-ctrl { - samsung,pins = "gpd0-0", "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_sync: lcd-sync { - samsung,pins = "gpf0-0", "gpf0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_en: lcd-en { - samsung,pins = "gpe3-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_clk: lcd-clk { - samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_data16: lcd-data-width16 { - samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", - "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", - "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7", - "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_data18: lcd-data-width18 { - samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1", - "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7", - "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", - "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", - "gpf3-2", "gpf3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_data24: lcd-data-width24 { - samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", - "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", - "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", - "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", - "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", - "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - }; - - pinctrl@11000000 { - gpj0: gpj0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj1: gpj1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk0: gpk0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk1: gpk1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk2: gpk2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk3: gpk3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl0: gpl0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl1: gpl1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl2: gpl2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpy0: gpy0 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy1: gpy1 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy2: gpy2 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy3: gpy3 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy4: gpy4 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy5: gpy5 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy6: gpy6 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpx0: gpx0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - ; - #interrupt-cells = <2>; - }; - - gpx1: gpx1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - ; - #interrupt-cells = <2>; - }; - - gpx2: gpx2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx3: gpx3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpk0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpk0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cd: sd0-cd { - samsung,pins = "gpk0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1 { - samsung,pins = "gpk0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4 { - samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8 { - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_clk: sd4-clk { - samsung,pins = "gpk0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_cmd: sd4-cmd { - samsung,pins = "gpk0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_cd: sd4-cd { - samsung,pins = "gpk0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_bus1: sd4-bus-width1 { - samsung,pins = "gpk0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_bus4: sd4-bus-width4 { - samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_bus8: sd4-bus-width8 { - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gpk1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gpk1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cd: sd1-cd { - samsung,pins = "gpk1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1 { - samsung,pins = "gpk1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4 { - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpk2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpk2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd { - samsung,pins = "gpk2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1 { - samsung,pins = "gpk2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4 { - samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus8: sd2-bus-width8 { - samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_clk: sd3-clk { - samsung,pins = "gpk3-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_cmd: sd3-cmd { - samsung,pins = "gpk3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_cd: sd3-cd { - samsung,pins = "gpk3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_bus1: sd3-bus-width1 { - samsung,pins = "gpk3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_bus4: sd3-bus-width4 { - samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint0: ext-int0 { - samsung,pins = "gpx0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint8: ext-int8 { - samsung,pins = "gpx1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint15: ext-int15 { - samsung,pins = "gpx1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint16: ext-int16 { - samsung,pins = "gpx2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint31: ext-int31 { - samsung,pins = "gpx3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_io: cam-port-a-io { - samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", - "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", - "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_clk_active: cam-port-a-clk-active { - samsung,pins = "gpj1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_clk_idle: cam-port-a-clk-idle { - samsung,pins = "gpj1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hdmi_cec: hdmi-cec { - samsung,pins = "gpx3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - }; - - pinctrl@3860000 { - gpz: gpz { - gpio-controller; - #gpio-cells = <2>; - }; - - i2s0_bus: i2s0-bus { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4", "gpz-5", "gpz-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm0_bus: pcm0-bus { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; + pcm0_bus: pcm0-bus { + samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", + "gpz-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; Index: sys/gnu/dts/arm/exynos4210-trats.dts =================================================================== --- sys/gnu/dts/arm/exynos4210-trats.dts +++ sys/gnu/dts/arm/exynos4210-trats.dts @@ -148,43 +148,12 @@ }; }; - camera { - pinctrl-names = "default"; - pinctrl-0 = <>; - status = "okay"; - - fimc_0: fimc@11800000 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC0>, - <&clock CLK_SCLK_FIMC0>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; - }; - - fimc_1: fimc@11810000 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC1>, - <&clock CLK_SCLK_FIMC1>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; - }; - - fimc_2: fimc@11820000 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC2>, - <&clock CLK_SCLK_FIMC2>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; - }; +}; - fimc_3: fimc@11830000 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC3>, - <&clock CLK_SCLK_FIMC3>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; - }; - }; +&camera { + pinctrl-names = "default"; + pinctrl-0 = <>; + status = "okay"; }; &cpu0 { @@ -234,6 +203,38 @@ vbus-supply = <&safe1_sreg>; }; +&fimc_0 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC0>, + <&clock CLK_SCLK_FIMC0>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; +}; + +&fimc_1 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC1>, + <&clock CLK_SCLK_FIMC1>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; +}; + +&fimc_2 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC2>, + <&clock CLK_SCLK_FIMC2>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; +}; + +&fimc_3 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC3>, + <&clock CLK_SCLK_FIMC3>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; +}; + &fimd { status = "okay"; }; @@ -275,6 +276,7 @@ max8997_pmic@66 { compatible = "maxim,max8997-pmic"; + interrupts-extended = <&gpx0 7 0>, <&gpx2 3 0>; reg = <0x66>; interrupt-parent = <&gpx0>; Index: sys/gnu/dts/arm/exynos4210-universal_c210.dts =================================================================== --- sys/gnu/dts/arm/exynos4210-universal_c210.dts +++ sys/gnu/dts/arm/exynos4210-universal_c210.dts @@ -28,24 +28,6 @@ stdout-path = &serial_2; }; - sysram@2020000 { - smp-sysram@0 { - status = "disabled"; - }; - - smp-sysram@5000 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x5000 0x1000>; - }; - - smp-sysram@1f000 { - status = "disabled"; - }; - }; - - mct@10050000 { - compatible = "none"; - }; fixed-rate-clocks { xxti { @@ -173,45 +155,6 @@ }; }; - camera { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <>; - - fimc_0: fimc@11800000 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC0>, - <&clock CLK_SCLK_FIMC0>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; - }; - - fimc_1: fimc@11810000 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC1>, - <&clock CLK_SCLK_FIMC1>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; - }; - - fimc_2: fimc@11820000 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC2>, - <&clock CLK_SCLK_FIMC2>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; - }; - - fimc_3: fimc@11830000 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC3>, - <&clock CLK_SCLK_FIMC3>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; - }; - }; - hdmi_en: voltage-regulator-hdmi-5v { compatible = "regulator-fixed"; regulator-name = "HDMI_5V"; @@ -234,6 +177,13 @@ }; }; +&camera { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <>; +}; + &cpu0 { cpu0-supply = <&vdd_arm_reg>; }; @@ -250,6 +200,38 @@ vbus-supply = <&safeout1_reg>; }; +&fimc_0 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC0>, + <&clock CLK_SCLK_FIMC0>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; +}; + +&fimc_1 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC1>, + <&clock CLK_SCLK_FIMC1>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; +}; + +&fimc_2 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC2>, + <&clock CLK_SCLK_FIMC2>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; +}; + +&fimc_3 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC3>, + <&clock CLK_SCLK_FIMC3>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; +}; + &fimd { pinctrl-0 = <&lcd_clk>, <&lcd_data24>; pinctrl-names = "default"; @@ -501,6 +483,10 @@ status = "okay"; }; +&mct { + compatible = "none"; +}; + &mdma1 { reg = <0x12840000 0x1000>; }; @@ -579,3 +565,18 @@ /delete-property/dmas; /delete-property/dma-names; }; + +&sysram { + smp-sysram@0 { + status = "disabled"; + }; + + smp-sysram@5000 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x5000 0x1000>; + }; + + smp-sysram@1f000 { + status = "disabled"; + }; +}; Index: sys/gnu/dts/arm/exynos4210.dtsi =================================================================== --- sys/gnu/dts/arm/exynos4210.dtsi +++ sys/gnu/dts/arm/exynos4210.dtsi @@ -17,7 +17,6 @@ */ #include "exynos4.dtsi" -#include "exynos4210-pinctrl.dtsi" #include "exynos4-cpu-thermal.dtsi" / { @@ -49,8 +48,6 @@ 400000 975000 200000 950000 >; - cooling-min-level = <4>; - cooling-max-level = <2>; #cooling-cells = <2>; /* min followed by max */ }; @@ -61,365 +58,323 @@ }; }; - sysram: sysram@2020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x20000>; + soc: soc { + sysram: sysram@2020000 { + compatible = "mmio-sram"; + reg = <0x02020000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02020000 0x20000>; - smp-sysram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; - }; + smp-sysram@0 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x0 0x1000>; + }; - smp-sysram@1f000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x1f000 0x1000>; + smp-sysram@1f000 { + compatible = "samsung,exynos4210-sysram-ns"; + reg = <0x1f000 0x1000>; + }; }; - }; - pd_lcd1: lcd1-power-domain@10023ca0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023CA0 0x20>; - #power-domain-cells = <0>; - label = "LCD1"; - }; + pd_lcd1: lcd1-power-domain@10023ca0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023CA0 0x20>; + #power-domain-cells = <0>; + label = "LCD1"; + }; - l2c: l2-cache-controller@10502000 { - compatible = "arm,pl310-cache"; - reg = <0x10502000 0x1000>; - cache-unified; - cache-level = <2>; - arm,tag-latency = <2 2 1>; - arm,data-latency = <2 2 1>; - }; + l2c: l2-cache-controller@10502000 { + compatible = "arm,pl310-cache"; + reg = <0x10502000 0x1000>; + cache-unified; + cache-level = <2>; + arm,tag-latency = <2 2 1>; + arm,data-latency = <2 2 1>; + }; - mct: mct@10050000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x10050000 0x800>; - interrupt-parent = <&mct_map>; - interrupts = <0>, <1>, <2>, <3>, <4>, <5>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; - clock-names = "fin_pll", "mct"; - - mct_map: mct-map { - #interrupt-cells = <1>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>, + mct: mct@10050000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x10050000 0x800>; + interrupt-parent = <&mct_map>; + interrupts = <0>, <1>, <2>, <3>, <4>, <5>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; + clock-names = "fin_pll", "mct"; + + mct_map: mct-map { + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = + <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>, <1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>, <2 &combiner 12 6>, <3 &combiner 12 7>, <4 &gic 0 42 IRQ_TYPE_LEVEL_HIGH>, <5 &gic 0 48 IRQ_TYPE_LEVEL_HIGH>; + }; }; - }; - watchdog: watchdog@10060000 { - compatible = "samsung,s3c6410-wdt"; - reg = <0x10060000 0x100>; - interrupts = ; - clocks = <&clock CLK_WDT>; - clock-names = "watchdog"; - }; - - clock: clock-controller@10030000 { - compatible = "samsung,exynos4210-clock"; - reg = <0x10030000 0x20000>; - #clock-cells = <1>; - }; - - pinctrl_0: pinctrl@11400000 { - compatible = "samsung,exynos4210-pinctrl"; - reg = <0x11400000 0x1000>; - interrupts = ; - }; - - pinctrl_1: pinctrl@11000000 { - compatible = "samsung,exynos4210-pinctrl"; - reg = <0x11000000 0x1000>; - interrupts = ; - - wakup_eint: wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = ; + watchdog: watchdog@10060000 { + compatible = "samsung,s3c6410-wdt"; + reg = <0x10060000 0x100>; + interrupts = ; + clocks = <&clock CLK_WDT>; + clock-names = "watchdog"; }; - }; - pinctrl_2: pinctrl@3860000 { - compatible = "samsung,exynos4210-pinctrl"; - reg = <0x03860000 0x1000>; - }; + clock: clock-controller@10030000 { + compatible = "samsung,exynos4210-clock"; + reg = <0x10030000 0x20000>; + #clock-cells = <1>; + }; - tmu: tmu@100c0000 { - compatible = "samsung,exynos4210-tmu"; - interrupt-parent = <&combiner>; - reg = <0x100C0000 0x100>; - interrupts = <2 4>; - clocks = <&clock CLK_TMU_APBIF>; - clock-names = "tmu_apbif"; - samsung,tmu_gain = <15>; - samsung,tmu_reference_voltage = <7>; - status = "disabled"; - }; + pinctrl_0: pinctrl@11400000 { + compatible = "samsung,exynos4210-pinctrl"; + reg = <0x11400000 0x1000>; + interrupts = ; + }; - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tmu 0>; + pinctrl_1: pinctrl@11000000 { + compatible = "samsung,exynos4210-pinctrl"; + reg = <0x11000000 0x1000>; + interrupts = ; - trips { - cpu_alert0: cpu-alert-0 { - temperature = <85000>; /* millicelsius */ - }; - cpu_alert1: cpu-alert-1 { - temperature = <100000>; /* millicelsius */ - }; - cpu_alert2: cpu-alert-2 { - temperature = <110000>; /* millicelsius */ - }; + wakup_eint: wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = ; }; }; - }; - - g2d: g2d@12800000 { - compatible = "samsung,s5pv210-g2d"; - reg = <0x12800000 0x1000>; - interrupts = ; - clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; - clock-names = "sclk_fimg2d", "fimg2d"; - power-domains = <&pd_lcd0>; - iommus = <&sysmmu_g2d>; - }; - camera { - clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, - <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; - clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; + pinctrl_2: pinctrl@3860000 { + compatible = "samsung,exynos4210-pinctrl"; + reg = <0x03860000 0x1000>; + }; - fimc_0: fimc@11800000 { - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,cam-if; + g2d: g2d@12800000 { + compatible = "samsung,s5pv210-g2d"; + reg = <0x12800000 0x1000>; + interrupts = ; + clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; + clock-names = "sclk_fimg2d", "fimg2d"; + power-domains = <&pd_lcd0>; + iommus = <&sysmmu_g2d>; }; - fimc_1: fimc@11810000 { - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,cam-if; + ppmu_acp: ppmu_acp@10ae0000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10ae0000 0x2000>; + status = "disabled"; }; - fimc_2: fimc@11820000 { - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,lcd-wb; + ppmu_lcd1: ppmu_lcd1@12240000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x12240000 0x2000>; + clocks = <&clock CLK_PPMULCD1>; + clock-names = "ppmu"; + status = "disabled"; }; - fimc_3: fimc@11830000 { - samsung,pix-limits = <1920 8192 1366 1920>; - samsung,rotators = <0>; - samsung,mainscaler-ext; - samsung,lcd-wb; + sysmmu_g2d: sysmmu@12a20000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x12A20000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 7>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; + power-domains = <&pd_lcd0>; + #iommu-cells = <0>; }; - }; - mixer: mixer@12c10000 { - clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer", - "sclk_mixer"; - clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, - <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>, - <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>; - }; + sysmmu_fimd1: sysmmu@12220000 { + compatible = "samsung,exynos-sysmmu"; + interrupt-parent = <&combiner>; + reg = <0x12220000 0x1000>; + interrupts = <5 3>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>; + power-domains = <&pd_lcd1>; + #iommu-cells = <0>; + }; - ppmu_lcd1: ppmu_lcd1@12240000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x12240000 0x2000>; - clocks = <&clock CLK_PPMULCD1>; - clock-names = "ppmu"; - status = "disabled"; - }; + bus_dmc: bus_dmc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_DMC>; + clock-names = "bus"; + operating-points-v2 = <&bus_dmc_opp_table>; + status = "disabled"; + }; - sysmmu_g2d: sysmmu@12a20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12A20000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 7>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; - power-domains = <&pd_lcd0>; - #iommu-cells = <0>; - }; + bus_acp: bus_acp { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_ACP>; + clock-names = "bus"; + operating-points-v2 = <&bus_acp_opp_table>; + status = "disabled"; + }; - sysmmu_fimd1: sysmmu@12220000 { - compatible = "samsung,exynos-sysmmu"; - interrupt-parent = <&combiner>; - reg = <0x12220000 0x1000>; - interrupts = <5 3>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>; - power-domains = <&pd_lcd1>; - #iommu-cells = <0>; - }; + bus_peri: bus_peri { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peri_opp_table>; + status = "disabled"; + }; - bus_dmc: bus_dmc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_DMC>; - clock-names = "bus"; - operating-points-v2 = <&bus_dmc_opp_table>; - status = "disabled"; - }; + bus_fsys: bus_fsys { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK133>; + clock-names = "bus"; + operating-points-v2 = <&bus_fsys_opp_table>; + status = "disabled"; + }; - bus_acp: bus_acp { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_ACP>; - clock-names = "bus"; - operating-points-v2 = <&bus_acp_opp_table>; - status = "disabled"; - }; + bus_display: bus_display { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK160>; + clock-names = "bus"; + operating-points-v2 = <&bus_display_opp_table>; + status = "disabled"; + }; - bus_peri: bus_peri { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK100>; - clock-names = "bus"; - operating-points-v2 = <&bus_peri_opp_table>; - status = "disabled"; - }; + bus_lcd0: bus_lcd0 { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK200>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; - bus_fsys: bus_fsys { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK133>; - clock-names = "bus"; - operating-points-v2 = <&bus_fsys_opp_table>; - status = "disabled"; - }; + bus_leftbus: bus_leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; - bus_display: bus_display { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK160>; - clock-names = "bus"; - operating-points-v2 = <&bus_display_opp_table>; - status = "disabled"; - }; + bus_rightbus: bus_rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; - bus_lcd0: bus_lcd0 { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK200>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; + bus_mfc: bus_mfc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; - bus_leftbus: bus_leftbus { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_GDL>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; + bus_dmc_opp_table: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; - bus_rightbus: bus_rightbus { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_GDR>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_mfc: bus_mfc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_SCLK_MFC>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <1025000>; + }; + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-microvolt = <1050000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1150000>; + }; + }; - bus_dmc_opp_table: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; + bus_acp_opp_table: opp_table2 { + compatible = "operating-points-v2"; + opp-shared; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <1025000>; - }; - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - opp-microvolt = <1050000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1150000>; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + }; }; - }; - bus_acp_opp_table: opp_table2 { - compatible = "operating-points-v2"; - opp-shared; + bus_peri_opp_table: opp_table3 { + compatible = "operating-points-v2"; + opp-shared; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + }; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; }; - }; - bus_peri_opp_table: opp_table3 { - compatible = "operating-points-v2"; - opp-shared; + bus_fsys_opp_table: opp_table4 { + compatible = "operating-points-v2"; + opp-shared; - opp-5000000 { - opp-hz = /bits/ 64 <5000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; + opp-10000000 { + opp-hz = /bits/ 64 <10000000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + }; }; - }; - bus_fsys_opp_table: opp_table4 { - compatible = "operating-points-v2"; - opp-shared; + bus_display_opp_table: opp_table5 { + compatible = "operating-points-v2"; + opp-shared; - opp-10000000 { - opp-hz = /bits/ 64 <10000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + }; }; - }; - bus_display_opp_table: opp_table5 { - compatible = "operating-points-v2"; - opp-shared; + bus_leftbus_opp_table: opp_table6 { + compatible = "operating-points-v2"; + opp-shared; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + }; }; }; - bus_leftbus_opp_table: opp_table6 { - compatible = "operating-points-v2"; - opp-shared; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu 0>; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; + trips { + cpu_alert0: cpu-alert-0 { + temperature = <85000>; /* millicelsius */ + }; + cpu_alert1: cpu-alert-1 { + temperature = <100000>; /* millicelsius */ + }; + cpu_alert2: cpu-alert-2 { + temperature = <110000>; /* millicelsius */ + }; + }; }; }; }; @@ -428,6 +383,12 @@ cpu-offset = <0x8000>; }; +&camera { + clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, + <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; + clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; +}; + &combiner { samsung,combiner-nr = <16>; interrupts = , @@ -448,10 +409,43 @@ ; }; +&fimc_0 { + samsung,pix-limits = <4224 8192 1920 4224>; + samsung,mainscaler-ext; + samsung,cam-if; +}; + +&fimc_1 { + samsung,pix-limits = <4224 8192 1920 4224>; + samsung,mainscaler-ext; + samsung,cam-if; +}; + +&fimc_2 { + samsung,pix-limits = <4224 8192 1920 4224>; + samsung,mainscaler-ext; + samsung,lcd-wb; +}; + +&fimc_3 { + samsung,pix-limits = <1920 8192 1366 1920>; + samsung,rotators = <0>; + samsung,mainscaler-ext; + samsung,lcd-wb; +}; + &mdma1 { power-domains = <&pd_lcd0>; }; +&mixer { + clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer", + "sclk_mixer"; + clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, + <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>, + <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>; +}; + &pmu_system_controller { clock-names = "clkout0", "clkout1", "clkout2", "clkout3", "clkout4", "clkout8", "clkout9"; @@ -468,3 +462,13 @@ &sysmmu_rotator { power-domains = <&pd_lcd0>; }; + +&tmu { + compatible = "samsung,exynos4210-tmu"; + clocks = <&clock CLK_TMU_APBIF>; + clock-names = "tmu_apbif"; + samsung,tmu_gain = <15>; + samsung,tmu_reference_voltage = <7>; +}; + +#include "exynos4210-pinctrl.dtsi" Index: sys/gnu/dts/arm/exynos4412-galaxy-s3.dtsi =================================================================== --- /dev/null +++ sys/gnu/dts/arm/exynos4412-galaxy-s3.dtsi @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4412 based Galaxy S3 board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/dts-v1/; +#include "exynos4412-midas.dtsi" + +/ { + aliases { + i2c9 = &i2c_ak8975; + i2c10 = &i2c_cm36651; + }; + + regulators { + lcd_vdd3_reg: voltage-regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "LCD_VDD_2.2V"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + ps_als_reg: voltage-regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "LED_A_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpj0 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + i2c_ak8975: i2c-gpio-0 { + compatible = "i2c-gpio"; + gpios = <&gpy2 4 GPIO_ACTIVE_HIGH>, <&gpy2 5 GPIO_ACTIVE_HIGH>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ak8975@c { + compatible = "asahi-kasei,ak8975"; + reg = <0x0c>; + gpios = <&gpj0 7 GPIO_ACTIVE_HIGH>; + }; + }; + + i2c_cm36651: i2c-gpio-2 { + compatible = "i2c-gpio"; + gpios = <&gpf0 0 GPIO_ACTIVE_LOW>, <&gpf0 1 GPIO_ACTIVE_LOW>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + cm36651@18 { + compatible = "capella,cm36651"; + reg = <0x18>; + interrupt-parent = <&gpx0>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + vled-supply = <&ps_als_reg>; + }; + }; +}; + +&buck9_reg { + maxim,ena-gpios = <&gpm0 3 GPIO_ACTIVE_HIGH>; +}; + +&cam_af_reg { + gpio = <&gpm0 4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&cam_io_reg { + gpio = <&gpm0 2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&dsi_0 { + status = "okay"; + + panel@0 { + compatible = "samsung,s6e8aa0"; + reg = <0>; + vdd3-supply = <&lcd_vdd3_reg>; + vci-supply = <&ldo25_reg>; + reset-gpios = <&gpf2 1 GPIO_ACTIVE_HIGH>; + power-on-delay= <50>; + reset-delay = <100>; + init-delay = <100>; + flip-horizontal; + flip-vertical; + panel-width-mm = <58>; + panel-height-mm = <103>; + + display-timings { + timing-0 { + clock-frequency = <57153600>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <5>; + hback-porch = <5>; + hsync-len = <5>; + vfront-porch = <13>; + vback-porch = <1>; + vsync-len = <2>; + }; + }; + }; +}; + +&i2c_3 { + mms114-touchscreen@48 { + compatible = "melfas,mms114"; + reg = <0x48>; + interrupt-parent = <&gpm2>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + x-size = <720>; + y-size = <1280>; + avdd-supply = <&ldo23_reg>; + vdd-supply = <&ldo24_reg>; + }; +}; + +&ldo25_reg { + regulator-name = "LCD_VCC_3.3V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + +&s5c73m3 { + standby-gpios = <&gpm0 1 GPIO_ACTIVE_LOW>; /* ISP_STANDBY */ + vdda-supply = <&ldo17_reg>; + status = "okay"; +}; Index: sys/gnu/dts/arm/exynos4412-i9300.dts =================================================================== --- /dev/null +++ sys/gnu/dts/arm/exynos4412-i9300.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4412 based M0 (GT-I9300) board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/dts-v1/; +#include "exynos4412-galaxy-s3.dtsi" + +/ { + model = "Samsung Galaxy S3 (GT-I9300) based on Exynos4412"; + compatible = "samsung,i9300", "samsung,midas", "samsung,exynos4412", "samsung,exynos4"; + + /* bootargs are passed in by bootloader */ + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x40000000>; + }; +}; Index: sys/gnu/dts/arm/exynos4412-i9305.dts =================================================================== --- /dev/null +++ sys/gnu/dts/arm/exynos4412-i9305.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "exynos4412-galaxy-s3.dtsi" + +/ { + model = "Samsung Galaxy S3 (GT-I9305) based on Exynos4412"; + compatible = "samsung,i9305", "samsung,midas", "samsung,exynos4412", "samsung,exynos4"; + + /* bootargs are passed in by bootloader */ + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x80000000>; + }; +}; + +&i2c0_bus { + /* SCL and SDA pins are swapped */ + samsung,pins = "gpd1-1", "gpd1-0"; +}; Index: sys/gnu/dts/arm/exynos4412-itop-elite.dts =================================================================== --- sys/gnu/dts/arm/exynos4412-itop-elite.dts +++ sys/gnu/dts/arm/exynos4412-itop-elite.dts @@ -116,14 +116,6 @@ compatible = "pwm-beeper"; pwms = <&pwm 0 4000000 PWM_POLARITY_INVERTED>; }; - - camera: camera { - pinctrl-0 = <&cam_port_a_clk_active>; - pinctrl-names = "default"; - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_CAM0>; - assigned-clock-parents = <&clock CLK_XUSBXTI>; - }; }; &adc { @@ -131,6 +123,14 @@ status = "okay"; }; +&camera { + pinctrl-0 = <&cam_port_a_clk_active>; + pinctrl-names = "default"; + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_CAM0>; + assigned-clock-parents = <&clock CLK_XUSBXTI>; +}; + &clock_audss { assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, <&clock_audss EXYNOS_MOUT_I2S>, Index: sys/gnu/dts/arm/exynos4412-midas.dtsi =================================================================== --- sys/gnu/dts/arm/exynos4412-midas.dtsi +++ sys/gnu/dts/arm/exynos4412-midas.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's Exynos4412 based Trats 2 board device tree source * @@ -6,11 +7,7 @@ * * Device tree source file for Samsung's Trats 2 board which is based on * Samsung's Exynos4412 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ /dts-v1/; #include "exynos4412.dtsi" @@ -21,23 +18,14 @@ #include / { - model = "Samsung Trats 2 based on Exynos4412"; - compatible = "samsung,trats2", "samsung,exynos4412", "samsung,exynos4"; + compatible = "samsung,midas", "samsung,exynos4412", "samsung,exynos4"; aliases { - i2c9 = &i2c_ak8975; - i2c10 = &i2c_cm36651; i2c11 = &i2c_max77693; i2c12 = &i2c_max77693_fuel; }; - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x40000000>; - }; - chosen { - bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5"; stdout-path = &serial_2; }; @@ -68,17 +56,8 @@ regulator-name = "CAM_SENSOR_A"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; - gpio = <&gpm0 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - lcd_vdd3_reg: voltage-regulator-2 { - compatible = "regulator-fixed"; - regulator-name = "LCD_VDD_2.2V"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>; enable-active-high; + status = "disabled"; }; cam_af_reg: voltage-regulator-3 { @@ -86,17 +65,8 @@ regulator-name = "CAM_AF"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; - gpio = <&gpm0 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - ps_als_reg: voltage-regulator-5 { - compatible = "regulator-fixed"; - regulator-name = "LED_A_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpj0 5 GPIO_ACTIVE_HIGH>; enable-active-high; + status = "disabled"; }; vsil12: voltage-regulator-6 { @@ -157,7 +127,7 @@ gpios = <&gpx0 1 GPIO_ACTIVE_LOW>; linux,code = <139>; label = "ok"; - debounce-inteval = <10>; + debounce-interval = <10>; wakeup-source; }; }; @@ -227,37 +197,6 @@ }; }; - i2c_ak8975: i2c-gpio-0 { - compatible = "i2c-gpio"; - gpios = <&gpy2 4 GPIO_ACTIVE_HIGH>, <&gpy2 5 GPIO_ACTIVE_HIGH>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - ak8975@c { - compatible = "asahi-kasei,ak8975"; - reg = <0x0c>; - gpios = <&gpj0 7 GPIO_ACTIVE_HIGH>; - }; - }; - - i2c_cm36651: i2c-gpio-2 { - compatible = "i2c-gpio"; - gpios = <&gpf0 0 GPIO_ACTIVE_LOW>, <&gpf0 1 GPIO_ACTIVE_LOW>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - - cm36651@18 { - compatible = "capella,cm36651"; - reg = <0x18>; - interrupt-parent = <&gpx0>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - vled-supply = <&ps_als_reg>; - }; - }; - i2c-mhl { compatible = "i2c-gpio"; gpios = <&gpf0 4 GPIO_ACTIVE_HIGH>, <&gpf0 6 GPIO_ACTIVE_HIGH>; @@ -288,18 +227,6 @@ }; }; - camera: camera { - pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>; - pinctrl-names = "default"; - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_CAM0>, - <&clock CLK_MOUT_CAM1>; - assigned-clock-parents = <&clock CLK_XUSBXTI>, - <&clock CLK_XUSBXTI>; - - - }; - wlan_pwrseq: sdhci3-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpj0 0 GPIO_ACTIVE_LOW>; @@ -403,6 +330,16 @@ status = "okay"; }; +&camera { + pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>; + pinctrl-names = "default"; + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_CAM0>, + <&clock CLK_MOUT_CAM1>; + assigned-clock-parents = <&clock CLK_XUSBXTI>, + <&clock CLK_XUSBXTI>; +}; + &cpu0 { cpu0-supply = <&buck2_reg>; }; @@ -454,36 +391,6 @@ samsung,burst-clock-frequency = <500000000>; samsung,esc-clock-frequency = <20000000>; samsung,pll-clock-frequency = <24000000>; - status = "okay"; - - panel@0 { - compatible = "samsung,s6e8aa0"; - reg = <0>; - vdd3-supply = <&lcd_vdd3_reg>; - vci-supply = <&ldo25_reg>; - reset-gpios = <&gpf2 1 GPIO_ACTIVE_HIGH>; - power-on-delay= <50>; - reset-delay = <100>; - init-delay = <100>; - flip-horizontal; - flip-vertical; - panel-width-mm = <58>; - panel-height-mm = <103>; - - display-timings { - timing-0 { - clock-frequency = <57153600>; - hactive = <720>; - vactive = <1280>; - hfront-porch = <5>; - hback-porch = <5>; - hsync-len = <5>; - vfront-porch = <13>; - vback-porch = <1>; - vsync-len = <2>; - }; - }; - }; }; &exynos_usbphy { @@ -528,32 +435,7 @@ pinctrl-names = "default"; status = "okay"; - i2c1_isp: i2c-isp@12140000 { - pinctrl-0 = <&fimc_is_i2c1>; - pinctrl-names = "default"; - - s5k6a3@10 { - compatible = "samsung,s5k6a3"; - reg = <0x10>; - svdda-supply = <&cam_io_reg>; - svddio-supply = <&ldo19_reg>; - afvdd-supply = <&ldo19_reg>; - clock-frequency = <24000000>; - /* CAM_B_CLKOUT */ - clocks = <&camera 1>; - clock-names = "extclk"; - samsung,camclk-out = <1>; - gpios = <&gpm1 6 GPIO_ACTIVE_HIGH>; - - port { - is_s5k6a3_ep: endpoint { - remote-endpoint = <&csis1_ep>; - data-lanes = <1>; - }; - }; - }; }; -}; &fimc_lite_0 { status = "okay"; @@ -605,14 +487,12 @@ pinctrl-names = "default"; status = "okay"; - s5c73m3@3c { + s5c73m3: s5c73m3@3c { compatible = "samsung,s5c73m3"; reg = <0x3c>; - standby-gpios = <&gpm0 1 GPIO_ACTIVE_LOW>; /* ISP_STANDBY */ xshutdown-gpios = <&gpf1 3 GPIO_ACTIVE_LOW>; /* ISP_RESET */ vdd-int-supply = <&buck9_reg>; vddio-cis-supply = <&ldo9_reg>; - vdda-supply = <&ldo17_reg>; vddio-host-supply = <&ldo18_reg>; vdd-af-supply = <&cam_af_reg>; vdd-reg-supply = <&cam_io_reg>; @@ -620,6 +500,7 @@ /* CAM_A_CLKOUT */ clocks = <&camera 0>; clock-names = "cis_extclk"; + status = "disabled"; port { s5c73m3_ep: endpoint { remote-endpoint = <&csis0_ep>; @@ -629,6 +510,32 @@ }; }; +&i2c1_isp { + pinctrl-0 = <&fimc_is_i2c1>; + pinctrl-names = "default"; + + s5k6a3@10 { + compatible = "samsung,s5k6a3"; + reg = <0x10>; + svdda-supply = <&cam_io_reg>; + svddio-supply = <&ldo19_reg>; + afvdd-supply = <&ldo19_reg>; + clock-frequency = <24000000>; + /* CAM_B_CLKOUT */ + clocks = <&camera 1>; + clock-names = "extclk"; + samsung,camclk-out = <1>; + gpios = <&gpm1 6 GPIO_ACTIVE_HIGH>; + + port { + is_s5k6a3_ep: endpoint { + remote-endpoint = <&csis1_ep>; + data-lanes = <1>; + }; + }; + }; +}; + &i2c_3 { samsung,i2c-sda-delay = <100>; samsung,i2c-slave-addr = <0x10>; @@ -636,17 +543,6 @@ pinctrl-0 = <&i2c3_bus>; pinctrl-names = "default"; status = "okay"; - - mms114-touchscreen@48 { - compatible = "melfas,mms114"; - reg = <0x48>; - interrupt-parent = <&gpm2>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - x-size = <720>; - y-size = <1280>; - avdd-supply = <&ldo23_reg>; - vdd-supply = <&ldo24_reg>; - }; }; &i2c_4 { @@ -874,9 +770,7 @@ }; ldo25_reg: LDO25 { - regulator-name = "LCD_VCC_3.3V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; + regulator-name = "LDO25"; }; ldo26_reg: LDO26 { @@ -960,7 +854,6 @@ regulator-name = "CAM_ISP_CORE_1.2V"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1200000>; - maxim,ena-gpios = <&gpm0 3 GPIO_ACTIVE_HIGH>; }; }; }; Index: sys/gnu/dts/arm/exynos4412-n710x.dts =================================================================== --- /dev/null +++ sys/gnu/dts/arm/exynos4412-n710x.dts @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "exynos4412-midas.dtsi" + +/ { + compatible = "samsung,n710x", "samsung,midas", "samsung,exynos4412", "samsung,exynos4"; + model = "Samsung Galaxy Note 2 (GT-N7100, GT-N7105) based on Exynos4412"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x80000000>; + }; + + /* bootargs are passed in by bootloader */ + + regulators { + cam_vdda_reg: voltage-regulator-9 { + compatible = "regulator-fixed"; + regulator-name = "CAM_SENSOR_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&gpm4 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&buck9_reg { + maxim,ena-gpios = <&gpm1 0 GPIO_ACTIVE_HIGH>; +}; + +&cam_af_reg { + gpio = <&gpm1 1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&cam_io_reg { + gpio = <&gpm0 7 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c_3 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <400000>; + pinctrl-0 = <&i2c3_bus>; + pinctrl-names = "default"; + status = "okay"; + + mms152-touchscreen@48 { + compatible = "melfas,mms152"; + reg = <0x48>; + interrupt-parent = <&gpm2>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + x-size = <720>; + y-size = <1280>; + avdd-supply = <&ldo23_reg>; + vdd-supply = <&ldo24_reg>; + }; +}; + +&ldo13_reg { + regulator-name = "VCC_1.8V_LCD"; + regulator-always-on; +}; + +&ldo25_reg { + regulator-name = "VCI_3.0V_LCD"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; +}; + +&s5c73m3 { + standby-gpios = <&gpm0 6 GPIO_ACTIVE_LOW>; /* ISP_STANDBY */ + vdda-supply = <&cam_vdda_reg>; + status = "okay"; +}; Index: sys/gnu/dts/arm/exynos4412-odroid-common.dtsi =================================================================== --- sys/gnu/dts/arm/exynos4412-odroid-common.dtsi +++ sys/gnu/dts/arm/exynos4412-odroid-common.dtsi @@ -61,12 +61,6 @@ reset-gpios = <&gpk1 2 GPIO_ACTIVE_LOW>; }; - camera { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - fixed-rate-clocks { xxti { compatible = "samsung,clock-xxti"; @@ -142,6 +136,12 @@ status = "okay"; }; +&camera { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <>; +}; + &clock_audss { assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, <&clock_audss EXYNOS_MOUT_I2S>, Index: sys/gnu/dts/arm/exynos4412-pinctrl.dtsi =================================================================== --- sys/gnu/dts/arm/exynos4412-pinctrl.dtsi +++ sys/gnu/dts/arm/exynos4412-pinctrl.dtsi @@ -18,964 +18,962 @@ samsung,pin-pud-pdn = ; \ } -/ { - pinctrl_0: pinctrl@11400000 { - gpa0: gpa0 { - gpio-controller; - #gpio-cells = <2>; +&pinctrl_0 { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb: gpb { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc0: gpc0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd0: gpd0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf0: gpf0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf2: gpf2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf3: gpf3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj0: gpj0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj1: gpj1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data { - samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_bus: i2c2-bus { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_data: uart2-data { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_fctl: uart2-fctl { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart_audio_a: uart-audio-a { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c3_bus: i2c3-bus { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart3_data: uart3-data { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart_audio_b: uart-audio-b { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpb-0", "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c4_bus: i2c4-bus { - samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi1_bus: spi1-bus { - samsung,pins = "gpb-4", "gpb-6", "gpb-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c5_bus: i2c5-bus { - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s1_bus: i2s1-bus { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm1_bus: pcm1-bus { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - ac97_bus: ac97-bus { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s2_bus: i2s2-bus { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm2_bus: pcm2-bus { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spdif_bus: spdif-bus { - samsung,pins = "gpc1-0", "gpc1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c6_bus: i2c6-bus { - samsung,pins = "gpc1-3", "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi2_bus: spi2-bus { - samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm0_out: pwm0-out { - samsung,pins = "gpd0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm1_out: pwm1-out { - samsung,pins = "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_ctrl: lcd-ctrl { - samsung,pins = "gpd0-0", "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c7_bus: i2c7-bus { - samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm2_out: pwm2-out { - samsung,pins = "gpd0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm3_out: pwm3-out { - samsung,pins = "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c0_bus: i2c0-bus { - samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - mipi0_clk: mipi0-clk { - samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c1_bus: i2c1-bus { - samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - mipi1_clk: mipi1-clk { - samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_clk: lcd-clk { - samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_data16: lcd-data-width16 { - samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", - "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", - "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7", - "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_data18: lcd-data-width18 { - samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1", - "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7", - "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", - "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", - "gpf3-2", "gpf3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_data24: lcd-data-width24 { - samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", - "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", - "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", - "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", - "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", - "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_ldi: lcd-ldi { - samsung,pins = "gpf3-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_io: cam-port-a-io { - samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", - "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", - "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_clk_active: cam-port-a-clk-active { - samsung,pins = "gpj1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_clk_idle: cam-port-a-clk-idle { - samsung,pins = "gpj1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - }; - - pinctrl_1: pinctrl@11000000 { - gpk0: gpk0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk1: gpk1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk2: gpk2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk3: gpk3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl0: gpl0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl1: gpl1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl2: gpl2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm0: gpm0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm1: gpm1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm2: gpm2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm3: gpm3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm4: gpm4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpy0: gpy0 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy1: gpy1 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy2: gpy2 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy3: gpy3 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy4: gpy4 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy5: gpy5 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy6: gpy6 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpx0: gpx0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - ; - #interrupt-cells = <2>; - }; - - gpx1: gpx1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - ; - #interrupt-cells = <2>; - }; - - gpx2: gpx2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx3: gpx3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpk0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpk0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cd: sd0-cd { - samsung,pins = "gpk0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1 { - samsung,pins = "gpk0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4 { - samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8 { - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_clk: sd4-clk { - samsung,pins = "gpk0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_cmd: sd4-cmd { - samsung,pins = "gpk0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_cd: sd4-cd { - samsung,pins = "gpk0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_bus1: sd4-bus-width1 { - samsung,pins = "gpk0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_bus4: sd4-bus-width4 { - samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_bus8: sd4-bus-width8 { - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gpk1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gpk1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cd: sd1-cd { - samsung,pins = "gpk1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1 { - samsung,pins = "gpk1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4 { - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpk2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpk2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd { - samsung,pins = "gpk2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1 { - samsung,pins = "gpk2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4 { - samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus8: sd2-bus-width8 { - samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_clk: sd3-clk { - samsung,pins = "gpk3-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_cmd: sd3-cmd { - samsung,pins = "gpk3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_cd: sd3-cd { - samsung,pins = "gpk3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_bus1: sd3-bus-width1 { - samsung,pins = "gpk3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_bus4: sd3-bus-width4 { - samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_io: cam-port-b-io { - samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", - "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", - "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_clk_active: cam-port-b-clk-active { - samsung,pins = "gpm2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_clk_idle: cam-port-b-clk-idle { - samsung,pins = "gpm2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint0: ext-int0 { - samsung,pins = "gpx0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint8: ext-int8 { - samsung,pins = "gpx1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint15: ext-int15 { - samsung,pins = "gpx1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint16: ext-int16 { - samsung,pins = "gpx2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint31: ext-int31 { - samsung,pins = "gpx3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_i2c0: fimc-is-i2c0 { - samsung,pins = "gpm4-0", "gpm4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_i2c1: fimc-is-i2c1 { - samsung,pins = "gpm4-2", "gpm4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_uart: fimc-is-uart { - samsung,pins = "gpm3-5", "gpm3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hdmi_cec: hdmi-cec { - samsung,pins = "gpx3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - }; - - pinctrl_2: pinctrl@3860000 { - gpz: gpz { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2s0_bus: i2s0-bus { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4", "gpz-5", "gpz-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm0_bus: pcm0-bus { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - }; - - pinctrl_3: pinctrl@106e0000 { - gpv0: gpv0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv1: gpv1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv2: gpv2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv3: gpv3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv4: gpv4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - c2c_bus: c2c-bus { - samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3", - "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7", - "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3", - "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7", - "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3", - "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7", - "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3", - "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7", - "gpv4-0", "gpv4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb: gpb { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf2: gpf2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf3: gpf3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpj0: gpj0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpj1: gpj1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart0_data: uart0-data { + samsung,pins = "gpa0-0", "gpa0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart0_fctl: uart0-fctl { + samsung,pins = "gpa0-2", "gpa0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart1_data: uart1-data { + samsung,pins = "gpa0-4", "gpa0-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart1_fctl: uart1-fctl { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c2_bus: i2c2-bus { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart2_data: uart2-data { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart2_fctl: uart2-fctl { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart_audio_a: uart-audio-a { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c3_bus: i2c3-bus { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart3_data: uart3-data { + samsung,pins = "gpa1-4", "gpa1-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart_audio_b: uart-audio-b { + samsung,pins = "gpa1-4", "gpa1-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi0_bus: spi0-bus { + samsung,pins = "gpb-0", "gpb-2", "gpb-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c4_bus: i2c4-bus { + samsung,pins = "gpb-0", "gpb-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi1_bus: spi1-bus { + samsung,pins = "gpb-4", "gpb-6", "gpb-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c5_bus: i2c5-bus { + samsung,pins = "gpb-2", "gpb-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2s1_bus: i2s1-bus { + samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", + "gpc0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pcm1_bus: pcm1-bus { + samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", + "gpc0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + ac97_bus: ac97-bus { + samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", + "gpc0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2s2_bus: i2s2-bus { + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", + "gpc1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pcm2_bus: pcm2-bus { + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", + "gpc1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spdif_bus: spdif-bus { + samsung,pins = "gpc1-0", "gpc1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c6_bus: i2c6-bus { + samsung,pins = "gpc1-3", "gpc1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi2_bus: spi2-bus { + samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm0_out: pwm0-out { + samsung,pins = "gpd0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm1_out: pwm1-out { + samsung,pins = "gpd0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_ctrl: lcd-ctrl { + samsung,pins = "gpd0-0", "gpd0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c7_bus: i2c7-bus { + samsung,pins = "gpd0-2", "gpd0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm2_out: pwm2-out { + samsung,pins = "gpd0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm3_out: pwm3-out { + samsung,pins = "gpd0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c0_bus: i2c0-bus { + samsung,pins = "gpd1-0", "gpd1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + mipi0_clk: mipi0-clk { + samsung,pins = "gpd1-0", "gpd1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c1_bus: i2c1-bus { + samsung,pins = "gpd1-2", "gpd1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + mipi1_clk: mipi1-clk { + samsung,pins = "gpd1-2", "gpd1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_clk: lcd-clk { + samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_data16: lcd-data-width16 { + samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", + "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", + "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7", + "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_data18: lcd-data-width18 { + samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1", + "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7", + "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", + "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", + "gpf3-2", "gpf3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_data24: lcd-data-width24 { + samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", + "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", + "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", + "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", + "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", + "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_ldi: lcd-ldi { + samsung,pins = "gpf3-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_port_a_io: cam-port-a-io { + samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", + "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", + "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_port_a_clk_active: cam-port-a-clk-active { + samsung,pins = "gpj1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_port_a_clk_idle: cam-port-a-clk-idle { + samsung,pins = "gpj1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_1 { + gpk0: gpk0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk1: gpk1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk2: gpk2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk3: gpk3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpl0: gpl0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpl1: gpl1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpl2: gpl2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm0: gpm0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm1: gpm1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm2: gpm2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm3: gpm3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm4: gpm4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpy0: gpy0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy1: gpy1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy2: gpy2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy3: gpy3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy4: gpy4 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy5: gpy5 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy6: gpy6 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpx0: gpx0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + #interrupt-cells = <2>; + }; + + gpx1: gpx1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + #interrupt-cells = <2>; + }; + + gpx2: gpx2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx3: gpx3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd0_clk: sd0-clk { + samsung,pins = "gpk0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_cmd: sd0-cmd { + samsung,pins = "gpk0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_cd: sd0-cd { + samsung,pins = "gpk0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus1: sd0-bus-width1 { + samsung,pins = "gpk0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus4: sd0-bus-width4 { + samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus8: sd0-bus-width8 { + samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd4_clk: sd4-clk { + samsung,pins = "gpk0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd4_cmd: sd4-cmd { + samsung,pins = "gpk0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd4_cd: sd4-cd { + samsung,pins = "gpk0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd4_bus1: sd4-bus-width1 { + samsung,pins = "gpk0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd4_bus4: sd4-bus-width4 { + samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd4_bus8: sd4-bus-width8 { + samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_clk: sd1-clk { + samsung,pins = "gpk1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_cmd: sd1-cmd { + samsung,pins = "gpk1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_cd: sd1-cd { + samsung,pins = "gpk1-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_bus1: sd1-bus-width1 { + samsung,pins = "gpk1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_bus4: sd1-bus-width4 { + samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_clk: sd2-clk { + samsung,pins = "gpk2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_cmd: sd2-cmd { + samsung,pins = "gpk2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_cd: sd2-cd { + samsung,pins = "gpk2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus1: sd2-bus-width1 { + samsung,pins = "gpk2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus4: sd2-bus-width4 { + samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus8: sd2-bus-width8 { + samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd3_clk: sd3-clk { + samsung,pins = "gpk3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd3_cmd: sd3-cmd { + samsung,pins = "gpk3-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd3_cd: sd3-cd { + samsung,pins = "gpk3-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd3_bus1: sd3-bus-width1 { + samsung,pins = "gpk3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd3_bus4: sd3-bus-width4 { + samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_port_b_io: cam-port-b-io { + samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", + "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", + "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_port_b_clk_active: cam-port-b-clk-active { + samsung,pins = "gpm2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cam_port_b_clk_idle: cam-port-b-clk-idle { + samsung,pins = "gpm2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eint0: ext-int0 { + samsung,pins = "gpx0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eint8: ext-int8 { + samsung,pins = "gpx1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eint15: ext-int15 { + samsung,pins = "gpx1-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eint16: ext-int16 { + samsung,pins = "gpx2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eint31: ext-int31 { + samsung,pins = "gpx3-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + fimc_is_i2c0: fimc-is-i2c0 { + samsung,pins = "gpm4-0", "gpm4-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + fimc_is_i2c1: fimc-is-i2c1 { + samsung,pins = "gpm4-2", "gpm4-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + fimc_is_uart: fimc-is-uart { + samsung,pins = "gpm3-5", "gpm3-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hdmi_cec: hdmi-cec { + samsung,pins = "gpx3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_2 { + gpz: gpz { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + i2s0_bus: i2s0-bus { + samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", + "gpz-4", "gpz-5", "gpz-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pcm0_bus: pcm0-bus { + samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", + "gpz-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_3 { + gpv0: gpv0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv1: gpv1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv2: gpv2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv3: gpv3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv4: gpv4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + c2c_bus: c2c-bus { + samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3", + "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7", + "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3", + "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7", + "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3", + "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7", + "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3", + "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7", + "gpv4-0", "gpv4-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; Index: sys/gnu/dts/arm/exynos4412-tiny4412.dts =================================================================== --- sys/gnu/dts/arm/exynos4412-tiny4412.dts +++ sys/gnu/dts/arm/exynos4412-tiny4412.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * FriendlyARM's Exynos4412 based TINY4412 board device tree source * @@ -5,11 +6,7 @@ * * Device tree source file for FriendlyARM's TINY4412 board which is based on * Samsung's Exynos4412 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ /dts-v1/; #include "exynos4412.dtsi" Index: sys/gnu/dts/arm/exynos4412-tmu-sensor-conf.dtsi =================================================================== --- sys/gnu/dts/arm/exynos4412-tmu-sensor-conf.dtsi +++ sys/gnu/dts/arm/exynos4412-tmu-sensor-conf.dtsi @@ -1,12 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device tree sources for Exynos4412 TMU sensor configuration * * Copyright (c) 2014 Lukasz Majewski - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * */ #include Index: sys/gnu/dts/arm/exynos4412-trats2.dts =================================================================== --- sys/gnu/dts/arm/exynos4412-trats2.dts +++ sys/gnu/dts/arm/exynos4412-trats2.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Samsung's Exynos4412 based Trats 2 board device tree source * @@ -6,30 +7,14 @@ * * Device tree source file for Samsung's Trats 2 board which is based on * Samsung's Exynos4412 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ /dts-v1/; -#include "exynos4412.dtsi" -#include "exynos4412-ppmu-common.dtsi" -#include -#include -#include -#include +#include "exynos4412-galaxy-s3.dtsi" / { model = "Samsung Trats 2 based on Exynos4412"; - compatible = "samsung,trats2", "samsung,exynos4412", "samsung,exynos4"; - - aliases { - i2c9 = &i2c_ak8975; - i2c10 = &i2c_cm36651; - i2c11 = &i2c_max77693; - i2c12 = &i2c_max77693_fuel; - }; + compatible = "samsung,trats2", "samsung,midas", "samsung,exynos4412", "samsung,exynos4"; memory@40000000 { device_type = "memory"; @@ -38,1378 +23,5 @@ chosen { bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5"; - stdout-path = &serial_2; - }; - - firmware@204f000 { - compatible = "samsung,secure-firmware"; - reg = <0x0204F000 0x1000>; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti", "fixed-clock"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti", "fixed-clock"; - clock-frequency = <24000000>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - cam_io_reg: voltage-regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "CAM_SENSOR_A"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpm0 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - lcd_vdd3_reg: voltage-regulator-2 { - compatible = "regulator-fixed"; - regulator-name = "LCD_VDD_2.2V"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - cam_af_reg: voltage-regulator-3 { - compatible = "regulator-fixed"; - regulator-name = "CAM_AF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpm0 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - ps_als_reg: voltage-regulator-5 { - compatible = "regulator-fixed"; - regulator-name = "LED_A_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpj0 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vsil12: voltage-regulator-6 { - compatible = "regulator-fixed"; - regulator-name = "VSIL_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&buck7_reg>; - }; - - vcc33mhl: voltage-regulator-7 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3.3_MHL"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vcc18mhl: voltage-regulator-8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1.8_MHL"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-down { - gpios = <&gpx3 3 GPIO_ACTIVE_LOW>; - linux,code = <114>; - label = "volume down"; - debounce-interval = <10>; - }; - - key-up { - gpios = <&gpx2 2 GPIO_ACTIVE_LOW>; - linux,code = <115>; - label = "volume up"; - debounce-interval = <10>; - }; - - key-power { - gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; - linux,code = <116>; - label = "power"; - debounce-interval = <10>; - wakeup-source; - }; - - key-ok { - gpios = <&gpx0 1 GPIO_ACTIVE_LOW>; - linux,code = <139>; - label = "ok"; - debounce-inteval = <10>; - wakeup-source; - }; - }; - - i2c_max77693: i2c-gpio-1 { - compatible = "i2c-gpio"; - gpios = <&gpm2 0 GPIO_ACTIVE_HIGH>, <&gpm2 1 GPIO_ACTIVE_HIGH>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - max77693@66 { - compatible = "maxim,max77693"; - interrupt-parent = <&gpx1>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - reg = <0x66>; - - regulators { - esafeout1_reg: ESAFEOUT1 { - regulator-name = "ESAFEOUT1"; - }; - esafeout2_reg: ESAFEOUT2 { - regulator-name = "ESAFEOUT2"; - }; - charger_reg: CHARGER { - regulator-name = "CHARGER"; - regulator-min-microamp = <60000>; - regulator-max-microamp = <2580000>; - }; - }; - - max77693_haptic { - compatible = "maxim,max77693-haptic"; - haptic-supply = <&ldo26_reg>; - pwms = <&pwm 0 38022 0>; - }; - - charger { - compatible = "maxim,max77693-charger"; - - maxim,constant-microvolt = <4350000>; - maxim,min-system-microvolt = <3600000>; - maxim,thermal-regulation-celsius = <100>; - maxim,battery-overcurrent-microamp = <3500000>; - maxim,charge-input-threshold-microvolt = <4300000>; - }; - }; - }; - - i2c_max77693_fuel: i2c-gpio-3 { - compatible = "i2c-gpio"; - gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>, <&gpf1 4 GPIO_ACTIVE_HIGH>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - max77693-fuel-gauge@36 { - compatible = "maxim,max17047"; - interrupt-parent = <&gpx2>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - reg = <0x36>; - - maxim,over-heat-temp = <700>; - maxim,over-volt = <4500>; - }; - }; - - i2c_ak8975: i2c-gpio-0 { - compatible = "i2c-gpio"; - gpios = <&gpy2 4 GPIO_ACTIVE_HIGH>, <&gpy2 5 GPIO_ACTIVE_HIGH>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - ak8975@c { - compatible = "asahi-kasei,ak8975"; - reg = <0x0c>; - gpios = <&gpj0 7 GPIO_ACTIVE_HIGH>; - }; - }; - - i2c_cm36651: i2c-gpio-2 { - compatible = "i2c-gpio"; - gpios = <&gpf0 0 GPIO_ACTIVE_LOW>, <&gpf0 1 GPIO_ACTIVE_LOW>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - - cm36651@18 { - compatible = "capella,cm36651"; - reg = <0x18>; - interrupt-parent = <&gpx0>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - vled-supply = <&ps_als_reg>; - }; - }; - - i2c-mhl { - compatible = "i2c-gpio"; - gpios = <&gpf0 4 GPIO_ACTIVE_HIGH>, <&gpf0 6 GPIO_ACTIVE_HIGH>; - i2c-gpio,delay-us = <100>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&i2c_mhl_bus>; - pinctrl-names = "default"; - status = "okay"; - - sii9234: hdmi-bridge@39 { - compatible = "sil,sii9234"; - avcc33-supply = <&vcc33mhl>; - iovcc18-supply = <&vcc18mhl>; - avcc12-supply = <&vsil12>; - cvcc12-supply = <&vsil12>; - reset-gpios = <&gpf3 4 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpf3>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x39>; - - port { - mhl_to_hdmi: endpoint { - remote-endpoint = <&hdmi_to_mhl>; - }; - }; - }; - }; - - camera: camera { - pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>; - pinctrl-names = "default"; - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_CAM0>, - <&clock CLK_MOUT_CAM1>; - assigned-clock-parents = <&clock CLK_XUSBXTI>, - <&clock CLK_XUSBXTI>; - - - }; - - wlan_pwrseq: sdhci3-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpj0 0 GPIO_ACTIVE_LOW>; - clocks = <&max77686 MAX77686_CLK_PMIC>; - clock-names = "ext_clock"; - }; - - sound { - compatible = "samsung,trats2-audio"; - samsung,i2s-controller = <&i2s0>; - samsung,model = "Trats2"; - samsung,audio-codec = <&wm1811>; - samsung,audio-routing = - "SPK", "SPKOUTLN", - "SPK", "SPKOUTLP", - "SPK", "SPKOUTRN", - "SPK", "SPKOUTRP"; - }; - - thermistor-ap { - compatible = "murata,ncp15wb473"; - pullup-uv = <1800000>; /* VCC_1.8V_AP */ - pullup-ohm = <100000>; /* 100K */ - pulldown-ohm = <100000>; /* 100K */ - io-channels = <&adc 1>; /* AP temperature */ - }; - - thermistor-battery { - compatible = "murata,ncp15wb473"; - pullup-uv = <1800000>; /* VCC_1.8V_AP */ - pullup-ohm = <100000>; /* 100K */ - pulldown-ohm = <100000>; /* 100K */ - io-channels = <&adc 2>; /* Battery temperature */ - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - cooling-maps { - map0 { - /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 7 7>; - }; - map1 { - /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 13 13>; - }; - }; - }; - }; -}; - -&adc { - vdd-supply = <&ldo3_reg>; - status = "okay"; -}; - -&bus_dmc { - devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; - vdd-supply = <&buck1_reg>; - status = "okay"; -}; - -&bus_acp { - devfreq = <&bus_dmc>; - status = "okay"; -}; - -&bus_c2c { - devfreq = <&bus_dmc>; - status = "okay"; -}; - -&bus_leftbus { - devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; - vdd-supply = <&buck3_reg>; - status = "okay"; -}; - -&bus_rightbus { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_display { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_fsys { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_peri { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_mfc { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&csis_0 { - status = "okay"; - vddcore-supply = <&ldo8_reg>; - vddio-supply = <&ldo10_reg>; - assigned-clocks = <&clock CLK_MOUT_CSIS0>, - <&clock CLK_SCLK_CSIS0>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; - - /* Camera C (3) MIPI CSI-2 (CSIS0) */ - port@3 { - reg = <3>; - csis0_ep: endpoint { - remote-endpoint = <&s5c73m3_ep>; - data-lanes = <1 2 3 4>; - samsung,csis-hs-settle = <12>; - }; - }; -}; - -&csis_1 { - status = "okay"; - vddcore-supply = <&ldo8_reg>; - vddio-supply = <&ldo10_reg>; - assigned-clocks = <&clock CLK_MOUT_CSIS1>, - <&clock CLK_SCLK_CSIS1>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; - - /* Camera D (4) MIPI CSI-2 (CSIS1) */ - port@4 { - reg = <4>; - csis1_ep: endpoint { - remote-endpoint = <&is_s5k6a3_ep>; - data-lanes = <1>; - samsung,csis-hs-settle = <18>; - samsung,csis-wclk; - }; - }; -}; - -&dsi_0 { - vddcore-supply = <&ldo8_reg>; - vddio-supply = <&ldo10_reg>; - samsung,burst-clock-frequency = <500000000>; - samsung,esc-clock-frequency = <20000000>; - samsung,pll-clock-frequency = <24000000>; - status = "okay"; - - panel@0 { - compatible = "samsung,s6e8aa0"; - reg = <0>; - vdd3-supply = <&lcd_vdd3_reg>; - vci-supply = <&ldo25_reg>; - reset-gpios = <&gpf2 1 GPIO_ACTIVE_HIGH>; - power-on-delay= <50>; - reset-delay = <100>; - init-delay = <100>; - flip-horizontal; - flip-vertical; - panel-width-mm = <58>; - panel-height-mm = <103>; - - display-timings { - timing-0 { - clock-frequency = <57153600>; - hactive = <720>; - vactive = <1280>; - hfront-porch = <5>; - hback-porch = <5>; - hsync-len = <5>; - vfront-porch = <13>; - vback-porch = <1>; - vsync-len = <2>; - }; - }; - }; -}; - -&exynos_usbphy { - vbus-supply = <&esafeout1_reg>; - status = "okay"; -}; - -&fimc_0 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC0>, - <&clock CLK_SCLK_FIMC0>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; -}; - -&fimc_1 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC1>, - <&clock CLK_SCLK_FIMC1>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; -}; - -&fimc_2 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC2>, - <&clock CLK_SCLK_FIMC2>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; -}; - -&fimc_3 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC3>, - <&clock CLK_SCLK_FIMC3>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; -}; - -&fimc_is { - pinctrl-0 = <&fimc_is_uart>; - pinctrl-names = "default"; - status = "okay"; - - i2c1_isp: i2c-isp@12140000 { - pinctrl-0 = <&fimc_is_i2c1>; - pinctrl-names = "default"; - - s5k6a3@10 { - compatible = "samsung,s5k6a3"; - reg = <0x10>; - svdda-supply = <&cam_io_reg>; - svddio-supply = <&ldo19_reg>; - afvdd-supply = <&ldo19_reg>; - clock-frequency = <24000000>; - /* CAM_B_CLKOUT */ - clocks = <&camera 1>; - clock-names = "extclk"; - samsung,camclk-out = <1>; - gpios = <&gpm1 6 GPIO_ACTIVE_HIGH>; - - port { - is_s5k6a3_ep: endpoint { - remote-endpoint = <&csis1_ep>; - data-lanes = <1>; - }; - }; - }; - }; -}; - -&fimc_lite_0 { - status = "okay"; -}; - -&fimc_lite_1 { - status = "okay"; -}; - -&fimd { - status = "okay"; -}; - -&hdmi { - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd>; - vdd-supply = <&ldo3_reg>; - vdd_osc-supply = <&ldo4_reg>; - vdd_pll-supply = <&ldo3_reg>; - ddc = <&i2c_5>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - hdmi_to_mhl: endpoint { - remote-endpoint = <&mhl_to_hdmi>; - }; - }; - }; -}; - -&hsotg { - vusb_d-supply = <&ldo15_reg>; - vusb_a-supply = <&ldo12_reg>; - dr_mode = "peripheral"; - status = "okay"; -}; - -&i2c_0 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <400000>; - pinctrl-0 = <&i2c0_bus>; - pinctrl-names = "default"; - status = "okay"; - - s5c73m3@3c { - compatible = "samsung,s5c73m3"; - reg = <0x3c>; - standby-gpios = <&gpm0 1 GPIO_ACTIVE_LOW>; /* ISP_STANDBY */ - xshutdown-gpios = <&gpf1 3 GPIO_ACTIVE_LOW>; /* ISP_RESET */ - vdd-int-supply = <&buck9_reg>; - vddio-cis-supply = <&ldo9_reg>; - vdda-supply = <&ldo17_reg>; - vddio-host-supply = <&ldo18_reg>; - vdd-af-supply = <&cam_af_reg>; - vdd-reg-supply = <&cam_io_reg>; - clock-frequency = <24000000>; - /* CAM_A_CLKOUT */ - clocks = <&camera 0>; - clock-names = "cis_extclk"; - port { - s5c73m3_ep: endpoint { - remote-endpoint = <&csis0_ep>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -&i2c_3 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <400000>; - pinctrl-0 = <&i2c3_bus>; - pinctrl-names = "default"; - status = "okay"; - - mms114-touchscreen@48 { - compatible = "melfas,mms114"; - reg = <0x48>; - interrupt-parent = <&gpm2>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - x-size = <720>; - y-size = <1280>; - avdd-supply = <&ldo23_reg>; - vdd-supply = <&ldo24_reg>; - }; -}; - -&i2c_4 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - pinctrl-0 = <&i2c4_bus>; - pinctrl-names = "default"; - status = "okay"; - - wm1811: wm1811@1a { - compatible = "wlf,wm1811"; - reg = <0x1a>; - clocks = <&pmu_system_controller 0>; - clock-names = "MCLK1"; - DCVDD-supply = <&ldo3_reg>; - DBVDD1-supply = <&ldo3_reg>; - wlf,ldo1ena = <&gpj0 4 0>; }; }; - -&i2c_5 { - status = "okay"; -}; - -&i2c_7 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - pinctrl-0 = <&i2c7_bus>; - pinctrl-names = "default"; - status = "okay"; - - max77686: max77686_pmic@9 { - compatible = "maxim,max77686"; - interrupt-parent = <&gpx0>; - interrupts = <7 IRQ_TYPE_NONE>; - reg = <0x09>; - #clock-cells = <1>; - - voltage-regulators { - ldo1_reg: LDO1 { - regulator-name = "VALIVE_1.0V_AP"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "VM1M2_1.2V_AP"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo3_reg: LDO3 { - regulator-name = "VCC_1.8V_AP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "VCC_2.8V_AP"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo5_reg: LDO5 { - regulator-name = "VCC_1.8V_IO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "VMPLL_1.0V_AP"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo7_reg: LDO7 { - regulator-name = "VPLL_1.0V_AP"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo8_reg: LDO8 { - regulator-name = "VMIPI_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo9_reg: LDO9 { - regulator-name = "CAM_ISP_MIPI_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo10_reg: LDO10 { - regulator-name = "VMIPI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo11_reg: LDO11 { - regulator-name = "VABB1_1.95V"; - regulator-min-microvolt = <1950000>; - regulator-max-microvolt = <1950000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo12_reg: LDO12 { - regulator-name = "VUOTG_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo13_reg: LDO13 { - regulator-name = "NFC_AVDD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo14_reg: LDO14 { - regulator-name = "VABB2_1.95V"; - regulator-min-microvolt = <1950000>; - regulator-max-microvolt = <1950000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo15_reg: LDO15 { - regulator-name = "VHSIC_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo16_reg: LDO16 { - regulator-name = "VHSIC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo17_reg: LDO17 { - regulator-name = "CAM_SENSOR_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo18_reg: LDO18 { - regulator-name = "CAM_ISP_SEN_IO_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo19_reg: LDO19 { - regulator-name = "VT_CAM_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo20_reg: LDO20 { - regulator-name = "VDDQ_PRE_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo21_reg: LDO21 { - regulator-name = "VTF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - maxim,ena-gpios = <&gpy2 0 GPIO_ACTIVE_HIGH>; - }; - - ldo22_reg: LDO22 { - regulator-name = "VMEM_VDD_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - maxim,ena-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; - }; - - ldo23_reg: LDO23 { - regulator-name = "TSP_AVDD_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo24_reg: LDO24 { - regulator-name = "TSP_VDD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo25_reg: LDO25 { - regulator-name = "LCD_VCC_3.3V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo26_reg: LDO26 { - regulator-name = "MOTOR_VCC_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck5_reg: BUCK5 { - regulator-name = "VMEM_1.2V_AP"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "VCC_SUB_1.35V"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "VCC_SUB_2.0V"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "VMEM_VDDF_3.0V"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - maxim,ena-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; - }; - - buck9_reg: BUCK9 { - regulator-name = "CAM_ISP_CORE_1.2V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1200000>; - maxim,ena-gpios = <&gpm0 3 GPIO_ACTIVE_HIGH>; - }; - }; - }; -}; - -&i2c_8 { - status = "okay"; -}; - -&i2s0 { - pinctrl-0 = <&i2s0_bus>; - pinctrl-names = "default"; - status = "okay"; -}; - -&mixer { - status = "okay"; -}; - -&mshc_0 { - broken-cd; - non-removable; - card-detect-delay = <200>; - vmmc-supply = <&ldo22_reg>; - clock-frequency = <400000000>; - samsung,dw-mshc-ciu-div = <0>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; - pinctrl-names = "default"; - status = "okay"; - bus-width = <8>; - cap-mmc-highspeed; -}; - -&pmu_system_controller { - assigned-clocks = <&pmu_system_controller 0>; - assigned-clock-parents = <&clock CLK_XUSBXTI>; -}; - -&pinctrl_0 { - pinctrl-names = "default"; - pinctrl-0 = <&sleep0>; - - mhl_int: mhl-int { - samsung,pins = "gpf3-5"; - samsung,pin-pud = ; - }; - - i2c_mhl_bus: i2c-mhl-bus { - samsung,pins = "gpf0-4", "gpf0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sleep0: sleep-states { - PIN_SLP(gpa0-0, INPUT, NONE); - PIN_SLP(gpa0-1, OUT0, NONE); - PIN_SLP(gpa0-2, INPUT, NONE); - PIN_SLP(gpa0-3, INPUT, UP); - PIN_SLP(gpa0-4, INPUT, NONE); - PIN_SLP(gpa0-5, INPUT, DOWN); - PIN_SLP(gpa0-6, INPUT, DOWN); - PIN_SLP(gpa0-7, INPUT, UP); - - PIN_SLP(gpa1-0, INPUT, DOWN); - PIN_SLP(gpa1-1, INPUT, DOWN); - PIN_SLP(gpa1-2, INPUT, DOWN); - PIN_SLP(gpa1-3, INPUT, DOWN); - PIN_SLP(gpa1-4, INPUT, DOWN); - PIN_SLP(gpa1-5, INPUT, DOWN); - - PIN_SLP(gpb-0, INPUT, NONE); - PIN_SLP(gpb-1, INPUT, NONE); - PIN_SLP(gpb-2, INPUT, NONE); - PIN_SLP(gpb-3, INPUT, NONE); - PIN_SLP(gpb-4, INPUT, DOWN); - PIN_SLP(gpb-5, INPUT, UP); - PIN_SLP(gpb-6, INPUT, DOWN); - PIN_SLP(gpb-7, INPUT, DOWN); - - PIN_SLP(gpc0-0, INPUT, DOWN); - PIN_SLP(gpc0-1, INPUT, DOWN); - PIN_SLP(gpc0-2, INPUT, DOWN); - PIN_SLP(gpc0-3, INPUT, DOWN); - PIN_SLP(gpc0-4, INPUT, DOWN); - - PIN_SLP(gpc1-0, INPUT, NONE); - PIN_SLP(gpc1-1, PREV, NONE); - PIN_SLP(gpc1-2, INPUT, NONE); - PIN_SLP(gpc1-3, INPUT, NONE); - PIN_SLP(gpc1-4, INPUT, NONE); - - PIN_SLP(gpd0-0, INPUT, DOWN); - PIN_SLP(gpd0-1, INPUT, DOWN); - PIN_SLP(gpd0-2, INPUT, NONE); - PIN_SLP(gpd0-3, INPUT, NONE); - - PIN_SLP(gpd1-0, INPUT, DOWN); - PIN_SLP(gpd1-1, INPUT, DOWN); - PIN_SLP(gpd1-2, INPUT, NONE); - PIN_SLP(gpd1-3, INPUT, NONE); - - PIN_SLP(gpf0-0, INPUT, NONE); - PIN_SLP(gpf0-1, INPUT, NONE); - PIN_SLP(gpf0-2, INPUT, DOWN); - PIN_SLP(gpf0-3, INPUT, DOWN); - PIN_SLP(gpf0-4, INPUT, NONE); - PIN_SLP(gpf0-5, INPUT, DOWN); - PIN_SLP(gpf0-6, INPUT, NONE); - PIN_SLP(gpf0-7, INPUT, DOWN); - - PIN_SLP(gpf1-0, INPUT, DOWN); - PIN_SLP(gpf1-1, INPUT, DOWN); - PIN_SLP(gpf1-2, INPUT, DOWN); - PIN_SLP(gpf1-3, INPUT, DOWN); - PIN_SLP(gpf1-4, INPUT, NONE); - PIN_SLP(gpf1-5, INPUT, NONE); - PIN_SLP(gpf1-6, INPUT, DOWN); - PIN_SLP(gpf1-7, PREV, NONE); - - PIN_SLP(gpf2-0, PREV, NONE); - PIN_SLP(gpf2-1, INPUT, DOWN); - PIN_SLP(gpf2-2, INPUT, DOWN); - PIN_SLP(gpf2-3, INPUT, DOWN); - PIN_SLP(gpf2-4, INPUT, DOWN); - PIN_SLP(gpf2-5, INPUT, DOWN); - PIN_SLP(gpf2-6, INPUT, NONE); - PIN_SLP(gpf2-7, INPUT, NONE); - - PIN_SLP(gpf3-0, INPUT, NONE); - PIN_SLP(gpf3-1, PREV, NONE); - PIN_SLP(gpf3-2, PREV, NONE); - PIN_SLP(gpf3-3, PREV, NONE); - PIN_SLP(gpf3-4, OUT1, NONE); - PIN_SLP(gpf3-5, INPUT, DOWN); - - PIN_SLP(gpj0-0, PREV, NONE); - PIN_SLP(gpj0-1, PREV, NONE); - PIN_SLP(gpj0-2, PREV, NONE); - PIN_SLP(gpj0-3, INPUT, DOWN); - PIN_SLP(gpj0-4, PREV, NONE); - PIN_SLP(gpj0-5, PREV, NONE); - PIN_SLP(gpj0-6, INPUT, DOWN); - PIN_SLP(gpj0-7, INPUT, DOWN); - - PIN_SLP(gpj1-0, INPUT, DOWN); - PIN_SLP(gpj1-1, PREV, NONE); - PIN_SLP(gpj1-2, PREV, NONE); - PIN_SLP(gpj1-3, INPUT, DOWN); - PIN_SLP(gpj1-4, INPUT, DOWN); - }; -}; - -&pinctrl_1 { - pinctrl-names = "default"; - pinctrl-0 = <&sleep1>; - - hdmi_hpd: hdmi-hpd { - samsung,pins = "gpx3-7"; - samsung,pin-pud = ; - }; - - sleep1: sleep-states { - PIN_SLP(gpk0-0, PREV, NONE); - PIN_SLP(gpk0-1, PREV, NONE); - PIN_SLP(gpk0-2, OUT0, NONE); - PIN_SLP(gpk0-3, PREV, NONE); - PIN_SLP(gpk0-4, PREV, NONE); - PIN_SLP(gpk0-5, PREV, NONE); - PIN_SLP(gpk0-6, PREV, NONE); - - PIN_SLP(gpk1-0, INPUT, DOWN); - PIN_SLP(gpk1-1, INPUT, DOWN); - PIN_SLP(gpk1-2, INPUT, DOWN); - PIN_SLP(gpk1-3, PREV, NONE); - PIN_SLP(gpk1-4, PREV, NONE); - PIN_SLP(gpk1-5, PREV, NONE); - PIN_SLP(gpk1-6, PREV, NONE); - - PIN_SLP(gpk2-0, INPUT, DOWN); - PIN_SLP(gpk2-1, INPUT, DOWN); - PIN_SLP(gpk2-2, INPUT, DOWN); - PIN_SLP(gpk2-3, INPUT, DOWN); - PIN_SLP(gpk2-4, INPUT, DOWN); - PIN_SLP(gpk2-5, INPUT, DOWN); - PIN_SLP(gpk2-6, INPUT, DOWN); - - PIN_SLP(gpk3-0, OUT0, NONE); - PIN_SLP(gpk3-1, INPUT, NONE); - PIN_SLP(gpk3-2, INPUT, DOWN); - PIN_SLP(gpk3-3, INPUT, NONE); - PIN_SLP(gpk3-4, INPUT, NONE); - PIN_SLP(gpk3-5, INPUT, NONE); - PIN_SLP(gpk3-6, INPUT, NONE); - - PIN_SLP(gpl0-0, INPUT, DOWN); - PIN_SLP(gpl0-1, INPUT, DOWN); - PIN_SLP(gpl0-2, INPUT, DOWN); - PIN_SLP(gpl0-3, INPUT, DOWN); - PIN_SLP(gpl0-4, PREV, NONE); - PIN_SLP(gpl0-6, PREV, NONE); - - PIN_SLP(gpl1-0, INPUT, DOWN); - PIN_SLP(gpl1-1, INPUT, DOWN); - PIN_SLP(gpl2-0, INPUT, DOWN); - PIN_SLP(gpl2-1, INPUT, DOWN); - PIN_SLP(gpl2-2, INPUT, DOWN); - PIN_SLP(gpl2-3, INPUT, DOWN); - PIN_SLP(gpl2-4, INPUT, DOWN); - PIN_SLP(gpl2-5, INPUT, DOWN); - PIN_SLP(gpl2-6, PREV, NONE); - PIN_SLP(gpl2-7, INPUT, DOWN); - - PIN_SLP(gpm0-0, INPUT, DOWN); - PIN_SLP(gpm0-1, INPUT, DOWN); - PIN_SLP(gpm0-2, INPUT, DOWN); - PIN_SLP(gpm0-3, INPUT, DOWN); - PIN_SLP(gpm0-4, INPUT, DOWN); - PIN_SLP(gpm0-5, INPUT, DOWN); - PIN_SLP(gpm0-6, INPUT, DOWN); - PIN_SLP(gpm0-7, INPUT, DOWN); - - PIN_SLP(gpm1-0, INPUT, DOWN); - PIN_SLP(gpm1-1, INPUT, DOWN); - PIN_SLP(gpm1-2, INPUT, NONE); - PIN_SLP(gpm1-3, INPUT, NONE); - PIN_SLP(gpm1-4, INPUT, NONE); - PIN_SLP(gpm1-5, INPUT, NONE); - PIN_SLP(gpm1-6, INPUT, DOWN); - - PIN_SLP(gpm2-0, INPUT, NONE); - PIN_SLP(gpm2-1, INPUT, NONE); - PIN_SLP(gpm2-2, INPUT, DOWN); - PIN_SLP(gpm2-3, INPUT, DOWN); - PIN_SLP(gpm2-4, INPUT, DOWN); - - PIN_SLP(gpm3-0, PREV, NONE); - PIN_SLP(gpm3-1, PREV, NONE); - PIN_SLP(gpm3-2, PREV, NONE); - PIN_SLP(gpm3-3, OUT1, NONE); - PIN_SLP(gpm3-4, INPUT, DOWN); - PIN_SLP(gpm3-5, INPUT, DOWN); - PIN_SLP(gpm3-6, INPUT, DOWN); - PIN_SLP(gpm3-7, INPUT, DOWN); - - PIN_SLP(gpm4-0, INPUT, DOWN); - PIN_SLP(gpm4-1, INPUT, DOWN); - PIN_SLP(gpm4-2, INPUT, DOWN); - PIN_SLP(gpm4-3, INPUT, DOWN); - PIN_SLP(gpm4-4, INPUT, DOWN); - PIN_SLP(gpm4-5, INPUT, DOWN); - PIN_SLP(gpm4-6, INPUT, DOWN); - PIN_SLP(gpm4-7, INPUT, DOWN); - - PIN_SLP(gpy0-0, INPUT, DOWN); - PIN_SLP(gpy0-1, INPUT, DOWN); - PIN_SLP(gpy0-2, INPUT, DOWN); - PIN_SLP(gpy0-3, INPUT, DOWN); - PIN_SLP(gpy0-4, INPUT, DOWN); - PIN_SLP(gpy0-5, INPUT, DOWN); - - PIN_SLP(gpy1-0, INPUT, DOWN); - PIN_SLP(gpy1-1, INPUT, DOWN); - PIN_SLP(gpy1-2, INPUT, DOWN); - PIN_SLP(gpy1-3, INPUT, DOWN); - - PIN_SLP(gpy2-0, PREV, NONE); - PIN_SLP(gpy2-1, INPUT, DOWN); - PIN_SLP(gpy2-2, INPUT, NONE); - PIN_SLP(gpy2-3, INPUT, NONE); - PIN_SLP(gpy2-4, INPUT, NONE); - PIN_SLP(gpy2-5, INPUT, NONE); - - PIN_SLP(gpy3-0, INPUT, DOWN); - PIN_SLP(gpy3-1, INPUT, DOWN); - PIN_SLP(gpy3-2, INPUT, DOWN); - PIN_SLP(gpy3-3, INPUT, DOWN); - PIN_SLP(gpy3-4, INPUT, DOWN); - PIN_SLP(gpy3-5, INPUT, DOWN); - PIN_SLP(gpy3-6, INPUT, DOWN); - PIN_SLP(gpy3-7, INPUT, DOWN); - - PIN_SLP(gpy4-0, INPUT, DOWN); - PIN_SLP(gpy4-1, INPUT, DOWN); - PIN_SLP(gpy4-2, INPUT, DOWN); - PIN_SLP(gpy4-3, INPUT, DOWN); - PIN_SLP(gpy4-4, INPUT, DOWN); - PIN_SLP(gpy4-5, INPUT, DOWN); - PIN_SLP(gpy4-6, INPUT, DOWN); - PIN_SLP(gpy4-7, INPUT, DOWN); - - PIN_SLP(gpy5-0, INPUT, DOWN); - PIN_SLP(gpy5-1, INPUT, DOWN); - PIN_SLP(gpy5-2, INPUT, DOWN); - PIN_SLP(gpy5-3, INPUT, DOWN); - PIN_SLP(gpy5-4, INPUT, DOWN); - PIN_SLP(gpy5-5, INPUT, DOWN); - PIN_SLP(gpy5-6, INPUT, DOWN); - PIN_SLP(gpy5-7, INPUT, DOWN); - - PIN_SLP(gpy6-0, INPUT, DOWN); - PIN_SLP(gpy6-1, INPUT, DOWN); - PIN_SLP(gpy6-2, INPUT, DOWN); - PIN_SLP(gpy6-3, INPUT, DOWN); - PIN_SLP(gpy6-4, INPUT, DOWN); - PIN_SLP(gpy6-5, INPUT, DOWN); - PIN_SLP(gpy6-6, INPUT, DOWN); - PIN_SLP(gpy6-7, INPUT, DOWN); - }; -}; - -&pinctrl_2 { - pinctrl-names = "default"; - pinctrl-0 = <&sleep2>; - - sleep2: sleep-states { - PIN_SLP(gpz-0, INPUT, DOWN); - PIN_SLP(gpz-1, INPUT, DOWN); - PIN_SLP(gpz-2, INPUT, DOWN); - PIN_SLP(gpz-3, INPUT, DOWN); - PIN_SLP(gpz-4, INPUT, DOWN); - PIN_SLP(gpz-5, INPUT, DOWN); - PIN_SLP(gpz-6, INPUT, DOWN); - }; -}; - -&pinctrl_3 { - pinctrl-names = "default"; - pinctrl-0 = <&sleep3>; - - sleep3: sleep-states { - PIN_SLP(gpv0-0, INPUT, DOWN); - PIN_SLP(gpv0-1, INPUT, DOWN); - PIN_SLP(gpv0-2, INPUT, DOWN); - PIN_SLP(gpv0-3, INPUT, DOWN); - PIN_SLP(gpv0-4, INPUT, DOWN); - PIN_SLP(gpv0-5, INPUT, DOWN); - PIN_SLP(gpv0-6, INPUT, DOWN); - PIN_SLP(gpv0-7, INPUT, DOWN); - - PIN_SLP(gpv1-0, INPUT, DOWN); - PIN_SLP(gpv1-1, INPUT, DOWN); - PIN_SLP(gpv1-2, INPUT, DOWN); - PIN_SLP(gpv1-3, INPUT, DOWN); - PIN_SLP(gpv1-4, INPUT, DOWN); - PIN_SLP(gpv1-5, INPUT, DOWN); - PIN_SLP(gpv1-6, INPUT, DOWN); - PIN_SLP(gpv1-7, INPUT, DOWN); - - PIN_SLP(gpv2-0, INPUT, DOWN); - PIN_SLP(gpv2-1, INPUT, DOWN); - PIN_SLP(gpv2-2, INPUT, DOWN); - PIN_SLP(gpv2-3, INPUT, DOWN); - PIN_SLP(gpv2-4, INPUT, DOWN); - PIN_SLP(gpv2-5, INPUT, DOWN); - PIN_SLP(gpv2-6, INPUT, DOWN); - PIN_SLP(gpv2-7, INPUT, DOWN); - - PIN_SLP(gpv3-0, INPUT, DOWN); - PIN_SLP(gpv3-1, INPUT, DOWN); - PIN_SLP(gpv3-2, INPUT, DOWN); - PIN_SLP(gpv3-3, INPUT, DOWN); - PIN_SLP(gpv3-4, INPUT, DOWN); - PIN_SLP(gpv3-5, INPUT, DOWN); - PIN_SLP(gpv3-6, INPUT, DOWN); - PIN_SLP(gpv3-7, INPUT, DOWN); - - PIN_SLP(gpv4-0, INPUT, DOWN); - }; -}; - -&pwm { - pinctrl-0 = <&pwm0_out>; - pinctrl-names = "default"; - samsung,pwm-outputs = <0>; - status = "okay"; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&sdhci_2 { - bus-width = <4>; - cd-gpios = <&gpx3 4 GPIO_ACTIVE_HIGH>; - cd-inverted; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; - pinctrl-names = "default"; - vmmc-supply = <&ldo21_reg>; - status = "okay"; -}; - -&sdhci_3 { - #address-cells = <1>; - #size-cells = <0>; - non-removable; - bus-width = <4>; - - mmc-pwrseq = <&wlan_pwrseq>; - pinctrl-names = "default"; - pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&gpx2>; - interrupts = <5 IRQ_TYPE_NONE>; - interrupt-names = "host-wake"; - }; -}; - -&serial_0 { - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; - -&serial_3 { - status = "okay"; -}; - -&spi_1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - cs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - - s5c73m3_spi: s5c73m3@0 { - compatible = "samsung,s5c73m3"; - spi-max-frequency = <50000000>; - reg = <0>; - controller-data { - samsung,spi-feedback-delay = <2>; - }; - }; -}; - -&tmu { - vtmu-supply = <&ldo10_reg>; - status = "okay"; -}; Index: sys/gnu/dts/arm/exynos4412.dtsi =================================================================== --- sys/gnu/dts/arm/exynos4412.dtsi +++ sys/gnu/dts/arm/exynos4412.dtsi @@ -15,7 +15,7 @@ */ #include "exynos4.dtsi" -#include "exynos4412-pinctrl.dtsi" + #include "exynos4-cpu-thermal.dtsi" / { @@ -42,8 +42,6 @@ clocks = <&clock CLK_ARM_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; - cooling-min-level = <13>; - cooling-max-level = <7>; #cooling-cells = <2>; /* min followed by max */ }; @@ -147,463 +145,410 @@ }; }; - sysram@2020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x40000>; - smp-sysram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; - }; + soc: soc { - smp-sysram@2f000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x2f000 0x1000>; + pinctrl_0: pinctrl@11400000 { + compatible = "samsung,exynos4x12-pinctrl"; + reg = <0x11400000 0x1000>; + interrupts = ; }; - }; - - pd_isp: isp-power-domain@10023ca0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023CA0 0x20>; - #power-domain-cells = <0>; - label = "ISP"; - }; - - l2c: l2-cache-controller@10502000 { - compatible = "arm,pl310-cache"; - reg = <0x10502000 0x1000>; - cache-unified; - cache-level = <2>; - arm,tag-latency = <2 2 1>; - arm,data-latency = <3 2 1>; - arm,double-linefill = <1>; - arm,double-linefill-incr = <0>; - arm,double-linefill-wrap = <1>; - arm,prefetch-drop = <1>; - arm,prefetch-offset = <7>; - }; - clock: clock-controller@10030000 { - compatible = "samsung,exynos4412-clock"; - reg = <0x10030000 0x18000>; - #clock-cells = <1>; - }; - - isp_clock: clock-controller@10048000 { - compatible = "samsung,exynos4412-isp-clock"; - reg = <0x10048000 0x1000>; - #clock-cells = <1>; - power-domains = <&pd_isp>; - clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>; - clock-names = "aclk200", "aclk400_mcuisp"; - }; + pinctrl_1: pinctrl@11000000 { + compatible = "samsung,exynos4x12-pinctrl"; + reg = <0x11000000 0x1000>; + interrupts = ; - mct@10050000 { - compatible = "samsung,exynos4412-mct"; - reg = <0x10050000 0x800>; - interrupt-parent = <&mct_map>; - interrupts = <0>, <1>, <2>, <3>, <4>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; - clock-names = "fin_pll", "mct"; - - mct_map: mct-map { - #interrupt-cells = <1>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>, - <1 &combiner 12 5>, - <2 &combiner 12 6>, - <3 &combiner 12 7>, - <4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>; + wakup_eint: wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = ; + }; }; - }; - - watchdog: watchdog@10060000 { - compatible = "samsung,exynos5250-wdt"; - reg = <0x10060000 0x100>; - interrupts = ; - clocks = <&clock CLK_WDT>; - clock-names = "watchdog"; - samsung,syscon-phandle = <&pmu_system_controller>; - }; - - adc: adc@126c0000 { - compatible = "samsung,exynos-adc-v1"; - reg = <0x126C0000 0x100>; - interrupt-parent = <&combiner>; - interrupts = <10 3>; - clocks = <&clock CLK_TSADC>; - clock-names = "adc"; - #io-channel-cells = <1>; - io-channel-ranges; - samsung,syscon-phandle = <&pmu_system_controller>; - status = "disabled"; - }; - - g2d: g2d@10800000 { - compatible = "samsung,exynos4212-g2d"; - reg = <0x10800000 0x1000>; - interrupts = ; - clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; - clock-names = "sclk_fimg2d", "fimg2d"; - iommus = <&sysmmu_g2d>; - }; - - camera { - clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, - <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; - clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; - /* fimc_[0-3] are configured outside, under phandles */ - fimc_lite_0: fimc-lite@12390000 { - compatible = "samsung,exynos4212-fimc-lite"; - reg = <0x12390000 0x1000>; - interrupts = ; - power-domains = <&pd_isp>; - clocks = <&isp_clock CLK_ISP_FIMC_LITE0>; - clock-names = "flite"; - iommus = <&sysmmu_fimc_lite0>; - status = "disabled"; + pinctrl_2: pinctrl@3860000 { + compatible = "samsung,exynos4x12-pinctrl"; + reg = <0x03860000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <10 0>; }; - fimc_lite_1: fimc-lite@123a0000 { - compatible = "samsung,exynos4212-fimc-lite"; - reg = <0x123A0000 0x1000>; - interrupts = ; - power-domains = <&pd_isp>; - clocks = <&isp_clock CLK_ISP_FIMC_LITE1>; - clock-names = "flite"; - iommus = <&sysmmu_fimc_lite1>; - status = "disabled"; + pinctrl_3: pinctrl@106e0000 { + compatible = "samsung,exynos4x12-pinctrl"; + reg = <0x106E0000 0x1000>; + interrupts = ; }; - fimc_is: fimc-is@12000000 { - compatible = "samsung,exynos4212-fimc-is"; - reg = <0x12000000 0x260000>; - interrupts = , - ; - power-domains = <&pd_isp>; - clocks = <&isp_clock CLK_ISP_FIMC_LITE0>, - <&isp_clock CLK_ISP_FIMC_LITE1>, - <&isp_clock CLK_ISP_PPMUISPX>, - <&isp_clock CLK_ISP_PPMUISPMX>, - <&isp_clock CLK_ISP_FIMC_ISP>, - <&isp_clock CLK_ISP_FIMC_DRC>, - <&isp_clock CLK_ISP_FIMC_FD>, - <&isp_clock CLK_ISP_MCUISP>, - <&isp_clock CLK_ISP_GICISP>, - <&isp_clock CLK_ISP_MCUCTL_ISP>, - <&isp_clock CLK_ISP_PWM_ISP>, - <&isp_clock CLK_ISP_DIV_ISP0>, - <&isp_clock CLK_ISP_DIV_ISP1>, - <&isp_clock CLK_ISP_DIV_MCUISP0>, - <&isp_clock CLK_ISP_DIV_MCUISP1>, - <&clock CLK_MOUT_MPLL_USER_T>, - <&clock CLK_ACLK200>, - <&clock CLK_ACLK400_MCUISP>, - <&clock CLK_DIV_ACLK200>, - <&clock CLK_DIV_ACLK400_MCUISP>, - <&clock CLK_UART_ISP_SCLK>; - clock-names = "lite0", "lite1", "ppmuispx", - "ppmuispmx", "isp", - "drc", "fd", "mcuisp", - "gicisp", "mcuctl_isp", "pwm_isp", - "ispdiv0", "ispdiv1", "mcuispdiv0", - "mcuispdiv1", "mpll", "aclk200", - "aclk400mcuisp", "div_aclk200", - "div_aclk400mcuisp", "uart"; - iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>, - <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>; - iommu-names = "isp", "drc", "fd", "mcuctl"; + sysram@2020000 { + compatible = "mmio-sram"; + reg = <0x02020000 0x40000>; #address-cells = <1>; #size-cells = <1>; - ranges; - status = "disabled"; + ranges = <0 0x02020000 0x40000>; - pmu@10020000 { - reg = <0x10020000 0x3000>; + smp-sysram@0 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x0 0x1000>; }; - i2c1_isp: i2c-isp@12140000 { - compatible = "samsung,exynos4212-i2c-isp"; - reg = <0x12140000 0x100>; - clocks = <&isp_clock CLK_ISP_I2C1_ISP>; - clock-names = "i2c_isp"; - #address-cells = <1>; - #size-cells = <0>; + smp-sysram@2f000 { + compatible = "samsung,exynos4210-sysram-ns"; + reg = <0x2f000 0x1000>; }; }; - }; - - mshc_0: mmc@12550000 { - compatible = "samsung,exynos4412-dw-mshc"; - reg = <0x12550000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - fifo-depth = <0x80>; - clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>; - clock-names = "biu", "ciu"; - status = "disabled"; - }; - - sysmmu_g2d: sysmmu@10A40000{ - compatible = "samsung,exynos-sysmmu"; - reg = <0x10A40000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 7>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_isp: sysmmu@12260000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12260000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 2>; - power-domains = <&pd_isp>; - clock-names = "sysmmu"; - clocks = <&isp_clock CLK_ISP_SMMU_ISP>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_drc: sysmmu@12270000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12270000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 3>; - power-domains = <&pd_isp>; - clock-names = "sysmmu"; - clocks = <&isp_clock CLK_ISP_SMMU_DRC>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_fd: sysmmu@122a0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x122A0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 4>; - power-domains = <&pd_isp>; - clock-names = "sysmmu"; - clocks = <&isp_clock CLK_ISP_SMMU_FD>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_mcuctl: sysmmu@122b0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x122B0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 5>; - power-domains = <&pd_isp>; - clock-names = "sysmmu"; - clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>; - #iommu-cells = <0>; - }; - sysmmu_fimc_lite0: sysmmu@123b0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x123B0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 0>; - power-domains = <&pd_isp>; - clock-names = "sysmmu", "master"; - clocks = <&isp_clock CLK_ISP_SMMU_LITE0>, - <&isp_clock CLK_ISP_FIMC_LITE0>; - #iommu-cells = <0>; - }; + pd_isp: isp-power-domain@10023ca0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023CA0 0x20>; + #power-domain-cells = <0>; + label = "ISP"; + }; - sysmmu_fimc_lite1: sysmmu@123c0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x123C0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 1>; - power-domains = <&pd_isp>; - clock-names = "sysmmu", "master"; - clocks = <&isp_clock CLK_ISP_SMMU_LITE1>, - <&isp_clock CLK_ISP_FIMC_LITE1>; - #iommu-cells = <0>; - }; + l2c: l2-cache-controller@10502000 { + compatible = "arm,pl310-cache"; + reg = <0x10502000 0x1000>; + cache-unified; + cache-level = <2>; + arm,tag-latency = <2 2 1>; + arm,data-latency = <3 2 1>; + arm,double-linefill = <1>; + arm,double-linefill-incr = <0>; + arm,double-linefill-wrap = <1>; + arm,prefetch-drop = <1>; + arm,prefetch-offset = <7>; + }; - bus_dmc: bus_dmc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_DMC>; - clock-names = "bus"; - operating-points-v2 = <&bus_dmc_opp_table>; - status = "disabled"; - }; + clock: clock-controller@10030000 { + compatible = "samsung,exynos4412-clock"; + reg = <0x10030000 0x18000>; + #clock-cells = <1>; + }; - bus_acp: bus_acp { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_ACP>; - clock-names = "bus"; - operating-points-v2 = <&bus_acp_opp_table>; - status = "disabled"; - }; + isp_clock: clock-controller@10048000 { + compatible = "samsung,exynos4412-isp-clock"; + reg = <0x10048000 0x1000>; + #clock-cells = <1>; + power-domains = <&pd_isp>; + clocks = <&clock CLK_ACLK200>, + <&clock CLK_ACLK400_MCUISP>; + clock-names = "aclk200", "aclk400_mcuisp"; + }; + + mct@10050000 { + compatible = "samsung,exynos4412-mct"; + reg = <0x10050000 0x800>; + interrupt-parent = <&mct_map>; + interrupts = <0>, <1>, <2>, <3>, <4>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; + clock-names = "fin_pll", "mct"; + + mct_map: mct-map { + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = + <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>, + <1 &combiner 12 5>, + <2 &combiner 12 6>, + <3 &combiner 12 7>, + <4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>; + }; + }; - bus_c2c: bus_c2c { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_C2C>; - clock-names = "bus"; - operating-points-v2 = <&bus_dmc_opp_table>; - status = "disabled"; - }; + watchdog: watchdog@10060000 { + compatible = "samsung,exynos5250-wdt"; + reg = <0x10060000 0x100>; + interrupts = ; + clocks = <&clock CLK_WDT>; + clock-names = "watchdog"; + samsung,syscon-phandle = <&pmu_system_controller>; + }; + + adc: adc@126c0000 { + compatible = "samsung,exynos-adc-v1"; + reg = <0x126C0000 0x100>; + interrupt-parent = <&combiner>; + interrupts = <10 3>; + clocks = <&clock CLK_TSADC>; + clock-names = "adc"; + #io-channel-cells = <1>; + io-channel-ranges; + samsung,syscon-phandle = <&pmu_system_controller>; + status = "disabled"; + }; - bus_dmc_opp_table: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; + g2d: g2d@10800000 { + compatible = "samsung,exynos4212-g2d"; + reg = <0x10800000 0x1000>; + interrupts = ; + clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; + clock-names = "sclk_fimg2d", "fimg2d"; + iommus = <&sysmmu_g2d>; + }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <900000>; + mshc_0: mmc@12550000 { + compatible = "samsung,exynos4412-dw-mshc"; + reg = <0x12550000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + fifo-depth = <0x80>; + clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>; + clock-names = "biu", "ciu"; + status = "disabled"; }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <900000>; + + sysmmu_g2d: sysmmu@10A40000{ + compatible = "samsung,exynos-sysmmu"; + reg = <0x10A40000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 7>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; + #iommu-cells = <0>; }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - opp-microvolt = <900000>; + + sysmmu_fimc_isp: sysmmu@12260000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x12260000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <16 2>; + power-domains = <&pd_isp>; + clock-names = "sysmmu"; + clocks = <&isp_clock CLK_ISP_SMMU_ISP>; + #iommu-cells = <0>; }; - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - opp-microvolt = <950000>; + + sysmmu_fimc_drc: sysmmu@12270000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x12270000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <16 3>; + power-domains = <&pd_isp>; + clock-names = "sysmmu"; + clocks = <&isp_clock CLK_ISP_SMMU_DRC>; + #iommu-cells = <0>; }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1050000>; + + sysmmu_fimc_fd: sysmmu@122a0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x122A0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <16 4>; + power-domains = <&pd_isp>; + clock-names = "sysmmu"; + clocks = <&isp_clock CLK_ISP_SMMU_FD>; + #iommu-cells = <0>; }; - }; - bus_acp_opp_table: opp_table2 { - compatible = "operating-points-v2"; - opp-shared; + sysmmu_fimc_mcuctl: sysmmu@122b0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x122B0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <16 5>; + power-domains = <&pd_isp>; + clock-names = "sysmmu"; + clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>; + #iommu-cells = <0>; + }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; + sysmmu_fimc_lite0: sysmmu@123b0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x123B0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <16 0>; + power-domains = <&pd_isp>; + clock-names = "sysmmu", "master"; + clocks = <&isp_clock CLK_ISP_SMMU_LITE0>, + <&isp_clock CLK_ISP_FIMC_LITE0>; + #iommu-cells = <0>; }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; + + sysmmu_fimc_lite1: sysmmu@123c0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x123C0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <16 1>; + power-domains = <&pd_isp>; + clock-names = "sysmmu", "master"; + clocks = <&isp_clock CLK_ISP_SMMU_LITE1>, + <&isp_clock CLK_ISP_FIMC_LITE1>; + #iommu-cells = <0>; }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; + + bus_dmc: bus_dmc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_DMC>; + clock-names = "bus"; + operating-points-v2 = <&bus_dmc_opp_table>; + status = "disabled"; }; - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; + + bus_acp: bus_acp { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_ACP>; + clock-names = "bus"; + operating-points-v2 = <&bus_acp_opp_table>; + status = "disabled"; }; - }; - bus_leftbus: bus_leftbus { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_GDL>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; + bus_c2c: bus_c2c { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_C2C>; + clock-names = "bus"; + operating-points-v2 = <&bus_dmc_opp_table>; + status = "disabled"; + }; - bus_rightbus: bus_rightbus { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_GDR>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; + bus_dmc_opp_table: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; - bus_display: bus_display { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK160>; - clock-names = "bus"; - operating-points-v2 = <&bus_display_opp_table>; - status = "disabled"; - }; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <900000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <900000>; + }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <900000>; + }; + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-microvolt = <950000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1050000>; + }; + }; - bus_fsys: bus_fsys { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK133>; - clock-names = "bus"; - operating-points-v2 = <&bus_fsys_opp_table>; - status = "disabled"; - }; + bus_acp_opp_table: opp_table2 { + compatible = "operating-points-v2"; + opp-shared; - bus_peri: bus_peri { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK100>; - clock-names = "bus"; - operating-points-v2 = <&bus_peri_opp_table>; - status = "disabled"; - }; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + }; + }; - bus_mfc: bus_mfc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_SCLK_MFC>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; + bus_leftbus: bus_leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; - bus_leftbus_opp_table: opp_table3 { - compatible = "operating-points-v2"; - opp-shared; + bus_rightbus: bus_rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <900000>; + bus_display: bus_display { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK160>; + clock-names = "bus"; + operating-points-v2 = <&bus_display_opp_table>; + status = "disabled"; }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <925000>; + + bus_fsys: bus_fsys { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK133>; + clock-names = "bus"; + operating-points-v2 = <&bus_fsys_opp_table>; + status = "disabled"; }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - opp-microvolt = <950000>; + + bus_peri: bus_peri { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peri_opp_table>; + status = "disabled"; }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <1000000>; + + bus_mfc: bus_mfc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; }; - }; - bus_display_opp_table: opp_table4 { - compatible = "operating-points-v2"; - opp-shared; + bus_leftbus_opp_table: opp_table3 { + compatible = "operating-points-v2"; + opp-shared; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <900000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <925000>; + }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <950000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000>; + }; }; - }; - bus_fsys_opp_table: opp_table5 { - compatible = "operating-points-v2"; - opp-shared; + bus_display_opp_table: opp_table4 { + compatible = "operating-points-v2"; + opp-shared; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + }; }; - }; - bus_peri_opp_table: opp_table6 { - compatible = "operating-points-v2"; - opp-shared; + bus_fsys_opp_table: opp_table5 { + compatible = "operating-points-v2"; + opp-shared; - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + }; }; - }; - pmu { - interrupts = <2 2>, <3 2>, <18 2>, <19 2>; + bus_peri_opp_table: opp_table6 { + compatible = "operating-points-v2"; + opp-shared; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; }; }; @@ -631,6 +576,92 @@ ; }; +&camera { + clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, + <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; + clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; + + /* fimc_[0-3] are configured outside, under phandles */ + fimc_lite_0: fimc-lite@12390000 { + compatible = "samsung,exynos4212-fimc-lite"; + reg = <0x12390000 0x1000>; + interrupts = ; + power-domains = <&pd_isp>; + clocks = <&isp_clock CLK_ISP_FIMC_LITE0>; + clock-names = "flite"; + iommus = <&sysmmu_fimc_lite0>; + status = "disabled"; + }; + + fimc_lite_1: fimc-lite@123a0000 { + compatible = "samsung,exynos4212-fimc-lite"; + reg = <0x123A0000 0x1000>; + interrupts = ; + power-domains = <&pd_isp>; + clocks = <&isp_clock CLK_ISP_FIMC_LITE1>; + clock-names = "flite"; + iommus = <&sysmmu_fimc_lite1>; + status = "disabled"; + }; + + fimc_is: fimc-is@12000000 { + compatible = "samsung,exynos4212-fimc-is"; + reg = <0x12000000 0x260000>; + interrupts = , + ; + power-domains = <&pd_isp>; + clocks = <&isp_clock CLK_ISP_FIMC_LITE0>, + <&isp_clock CLK_ISP_FIMC_LITE1>, + <&isp_clock CLK_ISP_PPMUISPX>, + <&isp_clock CLK_ISP_PPMUISPMX>, + <&isp_clock CLK_ISP_FIMC_ISP>, + <&isp_clock CLK_ISP_FIMC_DRC>, + <&isp_clock CLK_ISP_FIMC_FD>, + <&isp_clock CLK_ISP_MCUISP>, + <&isp_clock CLK_ISP_GICISP>, + <&isp_clock CLK_ISP_MCUCTL_ISP>, + <&isp_clock CLK_ISP_PWM_ISP>, + <&isp_clock CLK_ISP_DIV_ISP0>, + <&isp_clock CLK_ISP_DIV_ISP1>, + <&isp_clock CLK_ISP_DIV_MCUISP0>, + <&isp_clock CLK_ISP_DIV_MCUISP1>, + <&clock CLK_MOUT_MPLL_USER_T>, + <&clock CLK_ACLK200>, + <&clock CLK_ACLK400_MCUISP>, + <&clock CLK_DIV_ACLK200>, + <&clock CLK_DIV_ACLK400_MCUISP>, + <&clock CLK_UART_ISP_SCLK>; + clock-names = "lite0", "lite1", "ppmuispx", + "ppmuispmx", "isp", + "drc", "fd", "mcuisp", + "gicisp", "mcuctl_isp", "pwm_isp", + "ispdiv0", "ispdiv1", "mcuispdiv0", + "mcuispdiv1", "mpll", "aclk200", + "aclk400mcuisp", "div_aclk200", + "div_aclk400mcuisp", "uart"; + iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>, + <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>; + iommu-names = "isp", "drc", "fd", "mcuctl"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + pmu@10020000 { + reg = <0x10020000 0x3000>; + }; + + i2c1_isp: i2c-isp@12140000 { + compatible = "samsung,exynos4212-i2c-isp"; + reg = <0x12140000 0x100>; + clocks = <&isp_clock CLK_ISP_I2C1_ISP>; + clock-names = "i2c_isp"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + &exynos_usbphy { compatible = "samsung,exynos4x12-usb2-phy"; samsung,sysreg-phandle = <&sys_reg>; @@ -693,35 +724,8 @@ <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>; }; -&pinctrl_0 { - compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x11400000 0x1000>; - interrupts = ; -}; - -&pinctrl_1 { - compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x11000000 0x1000>; - interrupts = ; - - wakup_eint: wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = ; - }; -}; - -&pinctrl_2 { - compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x03860000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <10 0>; -}; - -&pinctrl_3 { - compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x106E0000 0x1000>; - interrupts = ; +&pmu { + interrupts = <2 2>, <3 2>, <18 2>, <19 2>; }; &pmu_system_controller { @@ -743,3 +747,5 @@ clock-names = "tmu_apbif"; status = "disabled"; }; + +#include "exynos4412-pinctrl.dtsi" Index: sys/gnu/dts/arm/exynos5250-snow-common.dtsi =================================================================== --- sys/gnu/dts/arm/exynos5250-snow-common.dtsi +++ sys/gnu/dts/arm/exynos5250-snow-common.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include "exynos5250.dtsi" / { @@ -225,6 +226,16 @@ }; }; +&clock { + assigned-clocks = <&clock CLK_FOUT_EPLL>; + assigned-clock-rates = <49152000>; +}; + +&clock_audss { + assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>; + assigned-clock-parents = <&clock CLK_FOUT_EPLL>; +}; + &cpu0 { cpu0-supply = <&buck2_reg>; }; @@ -513,6 +524,8 @@ }; &i2s0 { + assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; + assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>; status = "okay"; }; @@ -649,6 +662,11 @@ }; }; +&pmu_system_controller { + assigned-clocks = <&pmu_system_controller 0>; + assigned-clock-parents = <&clock CLK_FIN_PLL>; +}; + &rtc { status = "okay"; clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; Index: sys/gnu/dts/arm/exynos5250-snow.dts =================================================================== --- sys/gnu/dts/arm/exynos5250-snow.dts +++ sys/gnu/dts/arm/exynos5250-snow.dts @@ -18,6 +18,14 @@ samsung,model = "Snow-I2S-MAX98095"; samsung,audio-codec = <&max98095>; + + cpu { + sound-dai = <&i2s0 0>; + }; + + codec { + sound-dai = <&max98095 0>, <&hdmi>; + }; }; }; @@ -27,6 +35,9 @@ reg = <0x11>; pinctrl-names = "default"; pinctrl-0 = <&max98095_en>; + clocks = <&pmu_system_controller 0>; + clock-names = "mclk"; + #sound-dai-cells = <1>; }; }; Index: sys/gnu/dts/arm/exynos5250.dtsi =================================================================== --- sys/gnu/dts/arm/exynos5250.dtsi +++ sys/gnu/dts/arm/exynos5250.dtsi @@ -77,8 +77,6 @@ 300000 937500 200000 925000 >; - cooling-min-level = <15>; - cooling-max-level = <9>; #cooling-cells = <2>; /* min followed by max */ }; cpu@1 { @@ -500,6 +498,8 @@ pinctrl-names = "default"; pinctrl-0 = <&i2s0_bus>; power-domains = <&pd_mau>; + #clock-cells = <1>; + #sound-dai-cells = <1>; }; i2s1: i2s@12d60000 { @@ -514,6 +514,7 @@ pinctrl-names = "default"; pinctrl-0 = <&i2s1_bus>; power-domains = <&pd_mau>; + #sound-dai-cells = <1>; }; i2s2: i2s@12d70000 { @@ -528,6 +529,7 @@ pinctrl-names = "default"; pinctrl-0 = <&i2s2_bus>; power-domains = <&pd_mau>; + #sound-dai-cells = <1>; }; usb_dwc3 { @@ -655,7 +657,7 @@ power-domains = <&pd_gsc>; clocks = <&clock CLK_GSCL0>; clock-names = "gscl"; - iommu = <&sysmmu_gsc0>; + iommus = <&sysmmu_gsc0>; }; gsc_1: gsc@13e10000 { @@ -665,7 +667,7 @@ power-domains = <&pd_gsc>; clocks = <&clock CLK_GSCL1>; clock-names = "gscl"; - iommu = <&sysmmu_gsc1>; + iommus = <&sysmmu_gsc1>; }; gsc_2: gsc@13e20000 { @@ -675,7 +677,7 @@ power-domains = <&pd_gsc>; clocks = <&clock CLK_GSCL2>; clock-names = "gscl"; - iommu = <&sysmmu_gsc2>; + iommus = <&sysmmu_gsc2>; }; gsc_3: gsc@13e30000 { @@ -685,7 +687,7 @@ power-domains = <&pd_gsc>; clocks = <&clock CLK_GSCL3>; clock-names = "gscl"; - iommu = <&sysmmu_gsc3>; + iommus = <&sysmmu_gsc3>; }; hdmi: hdmi@14530000 { @@ -700,6 +702,7 @@ "sclk_hdmiphy", "mout_hdmi"; samsung,syscon-phandle = <&pmu_system_controller>; phy = <&hdmiphy>; + #sound-dai-cells = <0>; status = "disabled"; }; Index: sys/gnu/dts/arm/exynos5260-xyref5260.dts =================================================================== --- sys/gnu/dts/arm/exynos5260-xyref5260.dts +++ sys/gnu/dts/arm/exynos5260-xyref5260.dts @@ -65,7 +65,6 @@ &mmc_0 { status = "okay"; broken-cd; - bypass-smu; cap-mmc-highspeed; supports-hs200-mode; /* 200 MHz */ card-detect-delay = <200>; Index: sys/gnu/dts/arm/exynos5410.dtsi =================================================================== --- sys/gnu/dts/arm/exynos5410.dtsi +++ sys/gnu/dts/arm/exynos5410.dtsi @@ -11,7 +11,6 @@ */ #include "exynos54xx.dtsi" -#include "exynos-syscon-restart.dtsi" #include #include #include @@ -197,9 +196,9 @@ interrupt-parent = <&gic>; ranges; - pdma0: pdma@12680000 { + pdma0: pdma@121a0000 { compatible = "arm,pl330", "arm,primecell"; - reg = <0x121A0000 0x1000>; + reg = <0x121a0000 0x1000>; interrupts = ; clocks = <&clock CLK_PDMA0>; clock-names = "apb_pclk"; @@ -208,9 +207,9 @@ #dma-requests = <32>; }; - pdma1: pdma@12690000 { + pdma1: pdma@121b0000 { compatible = "arm,pl330", "arm,primecell"; - reg = <0x121B0000 0x1000>; + reg = <0x121b0000 0x1000>; interrupts = ; clocks = <&clock CLK_PDMA1>; clock-names = "apb_pclk"; Index: sys/gnu/dts/arm/exynos5420-cpus.dtsi =================================================================== --- sys/gnu/dts/arm/exynos5420-cpus.dtsi +++ sys/gnu/dts/arm/exynos5420-cpus.dtsi @@ -30,8 +30,6 @@ clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; - cooling-min-level = <0>; - cooling-max-level = <11>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <1024>; }; @@ -43,8 +41,6 @@ clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; - cooling-min-level = <0>; - cooling-max-level = <11>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <1024>; }; @@ -56,8 +52,6 @@ clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; - cooling-min-level = <0>; - cooling-max-level = <11>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <1024>; }; @@ -69,8 +63,6 @@ clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; - cooling-min-level = <0>; - cooling-max-level = <11>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <1024>; }; @@ -83,8 +75,6 @@ clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; - cooling-min-level = <0>; - cooling-max-level = <7>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <539>; }; @@ -96,8 +86,6 @@ clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; - cooling-min-level = <0>; - cooling-max-level = <7>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <539>; }; @@ -109,8 +97,6 @@ clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; - cooling-min-level = <0>; - cooling-max-level = <7>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <539>; }; @@ -122,8 +108,6 @@ clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; - cooling-min-level = <0>; - cooling-max-level = <7>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <539>; }; Index: sys/gnu/dts/arm/exynos5420-peach-pit.dts =================================================================== --- sys/gnu/dts/arm/exynos5420-peach-pit.dts +++ sys/gnu/dts/arm/exynos5420-peach-pit.dts @@ -11,6 +11,7 @@ #include #include #include +#include #include "exynos5420.dtsi" #include "exynos5420-cpus.dtsi" @@ -86,6 +87,14 @@ samsung,model = "Peach-Pit-I2S-MAX98090"; samsung,i2s-controller = <&i2s0>; samsung,audio-codec = <&max98090>; + + cpu { + sound-dai = <&i2s0 0>; + }; + + codec { + sound-dai = <&max98090>, <&hdmi>; + }; }; usb300_vbus_reg: regulator-usb300 { @@ -142,6 +151,11 @@ vdd-supply = <&ldo9_reg>; }; +&clock_audss { + assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>; + assigned-clock-parents = <&clock CLK_FOUT_EPLL>; +}; + &cpu0 { cpu-supply = <&buck2_reg>; }; @@ -606,6 +620,7 @@ pinctrl-0 = <&max98090_irq>; clocks = <&pmu_system_controller 0>; clock-names = "mclk"; + #sound-dai-cells = <0>; }; light-sensor@44 { @@ -690,6 +705,8 @@ }; &i2s0 { + assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; + assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>; status = "okay"; }; Index: sys/gnu/dts/arm/exynos5422-cpus.dtsi =================================================================== --- sys/gnu/dts/arm/exynos5422-cpus.dtsi +++ sys/gnu/dts/arm/exynos5422-cpus.dtsi @@ -29,8 +29,6 @@ clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; - cooling-min-level = <0>; - cooling-max-level = <11>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <539>; }; @@ -42,8 +40,6 @@ clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; - cooling-min-level = <0>; - cooling-max-level = <11>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <539>; }; @@ -55,8 +51,6 @@ clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; - cooling-min-level = <0>; - cooling-max-level = <11>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <539>; }; @@ -68,8 +62,6 @@ clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; - cooling-min-level = <0>; - cooling-max-level = <11>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <539>; }; @@ -82,8 +74,6 @@ clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; - cooling-min-level = <0>; - cooling-max-level = <15>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <1024>; }; @@ -95,8 +85,6 @@ clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; - cooling-min-level = <0>; - cooling-max-level = <15>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <1024>; }; @@ -108,8 +96,6 @@ clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; - cooling-min-level = <0>; - cooling-max-level = <15>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <1024>; }; @@ -121,8 +107,6 @@ clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; - cooling-min-level = <0>; - cooling-max-level = <15>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <1024>; }; Index: sys/gnu/dts/arm/exynos5440.dtsi =================================================================== --- sys/gnu/dts/arm/exynos5440.dtsi +++ sys/gnu/dts/arm/exynos5440.dtsi @@ -26,24 +26,6 @@ tmuctrl2 = &tmuctrl_2; }; - clock: clock-controller@160000 { - compatible = "samsung,exynos5440-clock"; - reg = <0x160000 0x1000>; - #clock-cells = <1>; - }; - - gic: interrupt-controller@2e0000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x2E1000 0x1000>, - <0x2E2000 0x2000>, - <0x2E4000 0x2000>, - <0x2E6000 0x2000>; - interrupts = ; - }; - cpus { #address-cells = <1>; #size-cells = <0>; @@ -70,182 +52,290 @@ }; }; - arm-pmu { - compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu"; - interrupts = , - , - , - ; - }; + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; - timer { - compatible = "arm,cortex-a15-timer", - "arm,armv7-timer"; - interrupts = , - , - , - ; - clock-frequency = <50000000>; - }; + clock: clock-controller@160000 { + compatible = "samsung,exynos5440-clock"; + reg = <0x160000 0x1000>; + #clock-cells = <1>; + }; - cpufreq@160000 { - compatible = "samsung,exynos5440-cpufreq"; - reg = <0x160000 0x1000>; - interrupts = ; - operating-points = < - /* KHz uV */ - 1500000 1100000 - 1400000 1075000 - 1300000 1050000 - 1200000 1025000 - 1100000 1000000 - 1000000 975000 - 900000 950000 - 800000 925000 - >; - }; + gic: interrupt-controller@2e0000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x2E1000 0x1000>, + <0x2E2000 0x2000>, + <0x2E4000 0x2000>, + <0x2E6000 0x2000>; + interrupts = ; + }; - serial_0: serial@b0000 { - compatible = "samsung,exynos4210-uart"; - reg = <0xB0000 0x1000>; - interrupts = ; - clocks = <&clock CLK_B_125>, <&clock CLK_B_125>; - clock-names = "uart", "clk_uart_baud0"; - }; - serial_1: serial@c0000 { - compatible = "samsung,exynos4210-uart"; - reg = <0xC0000 0x1000>; - interrupts = ; - clocks = <&clock CLK_B_125>, <&clock CLK_B_125>; - clock-names = "uart", "clk_uart_baud0"; - }; + arm-pmu { + compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu"; + interrupts = , + , + , + ; + }; - spi_0: spi@d0000 { - compatible = "samsung,exynos5440-spi"; - reg = <0xD0000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - samsung,spi-src-clk = <0>; - num-cs = <1>; - clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>; - clock-names = "spi", "spi_busclk0"; - }; + timer { + compatible = "arm,cortex-a15-timer", + "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <50000000>; + }; - pin_ctrl: pinctrl@e0000 { - compatible = "samsung,exynos5440-pinctrl"; - reg = <0xE0000 0x1000>; - interrupts = , - , - , - , - , - , - , - ; - interrupt-controller; - #interrupt-cells = <2>; - #gpio-cells = <2>; + cpufreq@160000 { + compatible = "samsung,exynos5440-cpufreq"; + reg = <0x160000 0x1000>; + interrupts = ; + operating-points = < + /* KHz uV */ + 1500000 1100000 + 1400000 1075000 + 1300000 1050000 + 1200000 1025000 + 1100000 1000000 + 1000000 975000 + 900000 950000 + 800000 925000 + >; + }; - fan: fan { - samsung,exynos5440-pin-function = <1>; + serial_0: serial@b0000 { + compatible = "samsung,exynos4210-uart"; + reg = <0xB0000 0x1000>; + interrupts = ; + clocks = <&clock CLK_B_125>, <&clock CLK_B_125>; + clock-names = "uart", "clk_uart_baud0"; }; - hdd_led0: hdd_led0 { - samsung,exynos5440-pin-function = <2>; + serial_1: serial@c0000 { + compatible = "samsung,exynos4210-uart"; + reg = <0xC0000 0x1000>; + interrupts = ; + clocks = <&clock CLK_B_125>, <&clock CLK_B_125>; + clock-names = "uart", "clk_uart_baud0"; }; - hdd_led1: hdd_led1 { - samsung,exynos5440-pin-function = <3>; + spi_0: spi@d0000 { + compatible = "samsung,exynos5440-spi"; + reg = <0xD0000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + samsung,spi-src-clk = <0>; + num-cs = <1>; + clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>; + clock-names = "spi", "spi_busclk0"; }; - uart1: uart1 { - samsung,exynos5440-pin-function = <4>; + pin_ctrl: pinctrl@e0000 { + compatible = "samsung,exynos5440-pinctrl"; + reg = <0xE0000 0x1000>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + + fan: fan { + samsung,exynos5440-pin-function = <1>; + }; + + hdd_led0: hdd_led0 { + samsung,exynos5440-pin-function = <2>; + }; + + hdd_led1: hdd_led1 { + samsung,exynos5440-pin-function = <3>; + }; + + uart1: uart1 { + samsung,exynos5440-pin-function = <4>; + }; }; - }; - i2c@f0000 { - compatible = "samsung,exynos5440-i2c"; - reg = <0xF0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_B_125>; - clock-names = "i2c"; - }; + i2c@f0000 { + compatible = "samsung,exynos5440-i2c"; + reg = <0xF0000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_B_125>; + clock-names = "i2c"; + }; - i2c@100000 { - compatible = "samsung,exynos5440-i2c"; - reg = <0x100000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_B_125>; - clock-names = "i2c"; - }; + i2c@100000 { + compatible = "samsung,exynos5440-i2c"; + reg = <0x100000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_B_125>; + clock-names = "i2c"; + }; - watchdog@110000 { - compatible = "samsung,s3c6410-wdt"; - reg = <0x110000 0x1000>; - interrupts = ; - clocks = <&clock CLK_B_125>; - clock-names = "watchdog"; - }; + watchdog@110000 { + compatible = "samsung,s3c6410-wdt"; + reg = <0x110000 0x1000>; + interrupts = ; + clocks = <&clock CLK_B_125>; + clock-names = "watchdog"; + }; - gmac: ethernet@230000 { - compatible = "snps,dwmac-3.70a", "snps,dwmac"; - reg = <0x00230000 0x8000>; - interrupt-parent = <&gic>; - interrupts = ; - interrupt-names = "macirq"; - phy-mode = "sgmii"; - clocks = <&clock CLK_GMAC0>; - clock-names = "stmmaceth"; - }; + gmac: ethernet@230000 { + compatible = "snps,dwmac-3.70a", "snps,dwmac"; + reg = <0x00230000 0x8000>; + interrupt-parent = <&gic>; + interrupts = ; + interrupt-names = "macirq"; + phy-mode = "sgmii"; + clocks = <&clock CLK_GMAC0>; + clock-names = "stmmaceth"; + }; - amba { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - }; + amba { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + }; - rtc@130000 { - compatible = "samsung,s3c6410-rtc"; - reg = <0x130000 0x1000>; - interrupts = , - ; - clocks = <&clock CLK_B_125>; - clock-names = "rtc"; - }; + rtc@130000 { + compatible = "samsung,s3c6410-rtc"; + reg = <0x130000 0x1000>; + interrupts = , + ; + clocks = <&clock CLK_B_125>; + clock-names = "rtc"; + }; - tmuctrl_0: tmuctrl@160118 { - compatible = "samsung,exynos5440-tmu"; - reg = <0x160118 0x230>, <0x160368 0x10>; - interrupts = ; - clocks = <&clock CLK_B_125>; - clock-names = "tmu_apbif"; - #include "exynos5440-tmu-sensor-conf.dtsi" - }; + tmuctrl_0: tmuctrl@160118 { + compatible = "samsung,exynos5440-tmu"; + reg = <0x160118 0x230>, <0x160368 0x10>; + interrupts = ; + clocks = <&clock CLK_B_125>; + clock-names = "tmu_apbif"; + #include "exynos5440-tmu-sensor-conf.dtsi" + }; - tmuctrl_1: tmuctrl@16011c { - compatible = "samsung,exynos5440-tmu"; - reg = <0x16011C 0x230>, <0x160368 0x10>; - interrupts = ; - clocks = <&clock CLK_B_125>; - clock-names = "tmu_apbif"; - #include "exynos5440-tmu-sensor-conf.dtsi" - }; + tmuctrl_1: tmuctrl@16011c { + compatible = "samsung,exynos5440-tmu"; + reg = <0x16011C 0x230>, <0x160368 0x10>; + interrupts = ; + clocks = <&clock CLK_B_125>; + clock-names = "tmu_apbif"; + #include "exynos5440-tmu-sensor-conf.dtsi" + }; + + tmuctrl_2: tmuctrl@160120 { + compatible = "samsung,exynos5440-tmu"; + reg = <0x160120 0x230>, <0x160368 0x10>; + interrupts = ; + clocks = <&clock CLK_B_125>; + clock-names = "tmu_apbif"; + #include "exynos5440-tmu-sensor-conf.dtsi" + }; - tmuctrl_2: tmuctrl@160120 { - compatible = "samsung,exynos5440-tmu"; - reg = <0x160120 0x230>, <0x160368 0x10>; - interrupts = ; - clocks = <&clock CLK_B_125>; - clock-names = "tmu_apbif"; - #include "exynos5440-tmu-sensor-conf.dtsi" + sata@210000 { + compatible = "snps,exynos5440-ahci"; + reg = <0x210000 0x10000>; + interrupts = ; + clocks = <&clock CLK_SATA>; + clock-names = "sata"; + }; + + ohci@220000 { + compatible = "samsung,exynos5440-ohci"; + reg = <0x220000 0x1000>; + interrupts = ; + clocks = <&clock CLK_USB>; + clock-names = "usbhost"; + }; + + ehci@221000 { + compatible = "samsung,exynos5440-ehci"; + reg = <0x221000 0x1000>; + interrupts = ; + clocks = <&clock CLK_USB>; + clock-names = "usbhost"; + }; + + pcie_phy0: pcie-phy@270000 { + #phy-cells = <0>; + compatible = "samsung,exynos5440-pcie-phy"; + reg = <0x270000 0x1000>, <0x271000 0x40>; + }; + + pcie_phy1: pcie-phy@272000 { + #phy-cells = <0>; + compatible = "samsung,exynos5440-pcie-phy"; + reg = <0x272000 0x1000>, <0x271040 0x40>; + }; + + pcie_0: pcie@290000 { + compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; + reg = <0x290000 0x1000>, <0x40000000 0x1000>; + reg-names = "elbi", "config"; + interrupts = , + , + ; + clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>; + clock-names = "pcie", "pcie_bus"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + phys = <&pcie_phy0>; + ranges = <0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */ + bus-range = <0x00 0xff>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 53>; + num-lanes = <4>; + status = "disabled"; + }; + + pcie_1: pcie@2a0000 { + compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; + reg = <0x2a0000 0x1000>, <0x60000000 0x1000>; + reg-names = "elbi", "config"; + interrupts = , + , + ; + clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>; + clock-names = "pcie", "pcie_bus"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + phys = <&pcie_phy1>; + ranges = <0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */ + bus-range = <0x00 0xff>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 56>; + num-lanes = <4>; + status = "disabled"; + }; }; thermal-zones { @@ -262,86 +352,4 @@ #include "exynos5440-trip-points.dtsi" }; }; - - sata@210000 { - compatible = "snps,exynos5440-ahci"; - reg = <0x210000 0x10000>; - interrupts = ; - clocks = <&clock CLK_SATA>; - clock-names = "sata"; - }; - - ohci@220000 { - compatible = "samsung,exynos5440-ohci"; - reg = <0x220000 0x1000>; - interrupts = ; - clocks = <&clock CLK_USB>; - clock-names = "usbhost"; - }; - - ehci@221000 { - compatible = "samsung,exynos5440-ehci"; - reg = <0x221000 0x1000>; - interrupts = ; - clocks = <&clock CLK_USB>; - clock-names = "usbhost"; - }; - - pcie_phy0: pcie-phy@270000 { - #phy-cells = <0>; - compatible = "samsung,exynos5440-pcie-phy"; - reg = <0x270000 0x1000>, <0x271000 0x40>; - }; - - pcie_phy1: pcie-phy@272000 { - #phy-cells = <0>; - compatible = "samsung,exynos5440-pcie-phy"; - reg = <0x272000 0x1000>, <0x271040 0x40>; - }; - - pcie_0: pcie@290000 { - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; - reg = <0x290000 0x1000>, <0x40000000 0x1000>; - reg-names = "elbi", "config"; - interrupts = , - , - ; - clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>; - clock-names = "pcie", "pcie_bus"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - phys = <&pcie_phy0>; - ranges = <0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */ - bus-range = <0x00 0xff>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0x0 0 &gic 53>; - num-lanes = <4>; - status = "disabled"; - }; - - pcie_1: pcie@2a0000 { - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; - reg = <0x2a0000 0x1000>, <0x60000000 0x1000>; - reg-names = "elbi", "config"; - interrupts = , - , - ; - clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>; - clock-names = "pcie", "pcie_bus"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - phys = <&pcie_phy1>; - ranges = <0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */ - bus-range = <0x00 0xff>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0x0 0 &gic 56>; - num-lanes = <4>; - status = "disabled"; - }; }; Index: sys/gnu/dts/arm/exynos5800-peach-pi.dts =================================================================== --- sys/gnu/dts/arm/exynos5800-peach-pi.dts +++ sys/gnu/dts/arm/exynos5800-peach-pi.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Google Peach Pi Rev 10+ board device tree source * * Copyright (c) 2014 Google, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ /dts-v1/; @@ -14,6 +11,7 @@ #include #include #include +#include #include "exynos5800.dtsi" #include "exynos5420-cpus.dtsi" @@ -89,6 +87,14 @@ samsung,model = "Peach-Pi-I2S-MAX98091"; samsung,i2s-controller = <&i2s0>; samsung,audio-codec = <&max98091>; + + cpu { + sound-dai = <&i2s0 0>; + }; + + codec { + sound-dai = <&max98091>, <&hdmi>; + }; }; usb300_vbus_reg: regulator-usb300 { @@ -145,6 +151,11 @@ vdd-supply = <&ldo9_reg>; }; +&clock_audss { + assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>; + assigned-clock-parents = <&clock CLK_FOUT_EPLL>; +}; + &cpu0 { cpu-supply = <&buck2_reg>; }; @@ -609,6 +620,7 @@ pinctrl-0 = <&max98091_irq>; clocks = <&pmu_system_controller 0>; clock-names = "mclk"; + #sound-dai-cells = <0>; }; light-sensor@44 { @@ -661,6 +673,8 @@ }; &i2s0 { + assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; + assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>; status = "okay"; }; Index: sys/gnu/dts/arm/exynos5800.dtsi =================================================================== --- sys/gnu/dts/arm/exynos5800.dtsi +++ sys/gnu/dts/arm/exynos5800.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * SAMSUNG EXYNOS5800 SoC device tree source * @@ -7,10 +8,6 @@ * SAMSUNG EXYNOS5800 SoC device nodes are listed in this file. * EXYNOS5800 based board files can include this file and provide * values for board specfic bindings. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include "exynos5420.dtsi" Index: sys/gnu/dts/arm/gemini-dlink-dns-313.dts =================================================================== --- sys/gnu/dts/arm/gemini-dlink-dns-313.dts +++ sys/gnu/dts/arm/gemini-dlink-dns-313.dts @@ -78,8 +78,6 @@ gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>, <&gpio0 12 GPIO_ACTIVE_HIGH>; gpio-fan,speed-map = <0 0>, <3000 1>, <6000 2>; - cooling-min-level = <0>; - cooling-max-level = <2>; #cooling-cells = <2>; }; Index: sys/gnu/dts/arm/gemini-nas4220b.dts =================================================================== --- sys/gnu/dts/arm/gemini-nas4220b.dts +++ sys/gnu/dts/arm/gemini-nas4220b.dts @@ -134,37 +134,37 @@ function = "gmii"; groups = "gmii_gmac0_grp"; }; - /* Settings come from OpenWRT */ + /* Settings come from OpenWRT, pins on SL3516 */ conf0 { - pins = "R8 GMAC0 RXDV", "U11 GMAC1 RXDV"; + pins = "V8 GMAC0 RXDV", "T10 GMAC1 RXDV"; skew-delay = <0>; }; conf1 { - pins = "T8 GMAC0 RXC", "T11 GMAC1 RXC"; + pins = "Y7 GMAC0 RXC", "Y11 GMAC1 RXC"; skew-delay = <15>; }; conf2 { - pins = "P8 GMAC0 TXEN", "V11 GMAC1 TXEN"; + pins = "T8 GMAC0 TXEN", "W11 GMAC1 TXEN"; skew-delay = <7>; }; conf3 { - pins = "V7 GMAC0 TXC"; + pins = "U8 GMAC0 TXC"; skew-delay = <11>; }; conf4 { - pins = "P10 GMAC1 TXC"; + pins = "V11 GMAC1 TXC"; skew-delay = <10>; }; conf5 { /* The data lines all have default skew */ - pins = "U8 GMAC0 RXD0", "V8 GMAC0 RXD1", - "P9 GMAC0 RXD2", "R9 GMAC0 RXD3", - "U7 GMAC0 TXD0", "T7 GMAC0 TXD1", - "R7 GMAC0 TXD2", "P7 GMAC0 TXD3", - "R11 GMAC1 RXD0", "P11 GMAC1 RXD1", - "V12 GMAC1 RXD2", "U12 GMAC1 RXD3", - "R10 GMAC1 TXD0", "T10 GMAC1 TXD1", - "U10 GMAC1 TXD2", "V10 GMAC1 TXD3"; + pins = "W8 GMAC0 RXD0", "V9 GMAC0 RXD1", + "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3", + "T7 GMAC0 TXD0", "U6 GMAC0 TXD1", + "V7 GMAC0 TXD2", "U7 GMAC0 TXD3", + "Y12 GMAC1 RXD0", "V12 GMAC1 RXD1", + "T11 GMAC1 RXD2", "W12 GMAC1 RXD3", + "U10 GMAC1 TXD0", "Y10 GMAC1 TXD1", + "W10 GMAC1 TXD2", "T9 GMAC1 TXD3"; skew-delay = <7>; }; /* Set up drive strength on GMAC0 to 16 mA */ Index: sys/gnu/dts/arm/imx1-ads.dts =================================================================== --- sys/gnu/dts/arm/imx1-ads.dts +++ sys/gnu/dts/arm/imx1-ads.dts @@ -20,7 +20,7 @@ stdout-path = &uart1; }; - memory { + memory@8000000 { reg = <0x08000000 0x04000000>; }; Index: sys/gnu/dts/arm/imx1-apf9328.dts =================================================================== --- sys/gnu/dts/arm/imx1-apf9328.dts +++ sys/gnu/dts/arm/imx1-apf9328.dts @@ -20,7 +20,7 @@ stdout-path = &uart1; }; - memory { + memory@8000000 { reg = <0x08000000 0x00800000>; }; }; Index: sys/gnu/dts/arm/imx1.dtsi =================================================================== --- sys/gnu/dts/arm/imx1.dtsi +++ sys/gnu/dts/arm/imx1.dtsi @@ -25,7 +25,7 @@ * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; reg = <0 0>; }; + memory { device_type = "memory"; }; aliases { gpio0 = &gpio1; Index: sys/gnu/dts/arm/imx23-evk.dts =================================================================== --- sys/gnu/dts/arm/imx23-evk.dts +++ sys/gnu/dts/arm/imx23-evk.dts @@ -16,7 +16,7 @@ model = "Freescale i.MX23 Evaluation Kit"; compatible = "fsl,imx23-evk", "fsl,imx23"; - memory { + memory@40000000 { reg = <0x40000000 0x08000000>; }; Index: sys/gnu/dts/arm/imx23-olinuxino.dts =================================================================== --- sys/gnu/dts/arm/imx23-olinuxino.dts +++ sys/gnu/dts/arm/imx23-olinuxino.dts @@ -19,7 +19,7 @@ model = "i.MX23 Olinuxino Low Cost Board"; compatible = "olimex,imx23-olinuxino", "fsl,imx23"; - memory { + memory@40000000 { reg = <0x40000000 0x04000000>; }; Index: sys/gnu/dts/arm/imx23-sansa.dts =================================================================== --- sys/gnu/dts/arm/imx23-sansa.dts +++ sys/gnu/dts/arm/imx23-sansa.dts @@ -49,7 +49,7 @@ model = "SanDisk Sansa Fuze+"; compatible = "sandisk,sansa_fuze_plus", "fsl,imx23"; - memory { + memory@40000000 { reg = <0x40000000 0x04000000>; }; Index: sys/gnu/dts/arm/imx23-stmp378x_devb.dts =================================================================== --- sys/gnu/dts/arm/imx23-stmp378x_devb.dts +++ sys/gnu/dts/arm/imx23-stmp378x_devb.dts @@ -16,7 +16,7 @@ model = "Freescale STMP378x Development Board"; compatible = "fsl,stmp378x-devb", "fsl,imx23"; - memory { + memory@40000000 { reg = <0x40000000 0x04000000>; }; Index: sys/gnu/dts/arm/imx23-xfi3.dts =================================================================== --- sys/gnu/dts/arm/imx23-xfi3.dts +++ sys/gnu/dts/arm/imx23-xfi3.dts @@ -48,7 +48,7 @@ model = "Creative ZEN X-Fi3"; compatible = "creative,x-fi3", "fsl,imx23"; - memory { + memory@40000000 { reg = <0x40000000 0x04000000>; }; Index: sys/gnu/dts/arm/imx23.dtsi =================================================================== --- sys/gnu/dts/arm/imx23.dtsi +++ sys/gnu/dts/arm/imx23.dtsi @@ -23,7 +23,7 @@ * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; reg = <0 0>; }; + memory { device_type = "memory"; }; aliases { gpio0 = &gpio0; @@ -222,7 +222,8 @@ fsl,pull-up = ; }; - gpmi_pins_fixup: gpmi-pins-fixup { + gpmi_pins_fixup: gpmi-pins-fixup@0 { + reg = <0>; fsl,pinmux-ids = < MX23_PAD_GPMI_WPN__GPMI_WPN MX23_PAD_GPMI_WRN__GPMI_WRN @@ -266,7 +267,8 @@ fsl,pull-up = ; }; - mmc0_pins_fixup: mmc0-pins-fixup { + mmc0_pins_fixup: mmc0-pins-fixup@0 { + reg = <0>; fsl,pinmux-ids = < MX23_PAD_SSP1_DETECT__SSP1_DETECT MX23_PAD_SSP1_SCK__SSP1_SCK Index: sys/gnu/dts/arm/imx25-eukrea-cpuimx25.dtsi =================================================================== --- sys/gnu/dts/arm/imx25-eukrea-cpuimx25.dtsi +++ sys/gnu/dts/arm/imx25-eukrea-cpuimx25.dtsi @@ -17,7 +17,7 @@ model = "Eukrea CPUIMX25"; compatible = "eukrea,cpuimx25", "fsl,imx25"; - memory { + memory@80000000 { reg = <0x80000000 0x4000000>; /* 64M */ }; }; Index: sys/gnu/dts/arm/imx25-eukrea-mbimxsd25-baseboard.dts =================================================================== --- sys/gnu/dts/arm/imx25-eukrea-mbimxsd25-baseboard.dts +++ sys/gnu/dts/arm/imx25-eukrea-mbimxsd25-baseboard.dts @@ -88,12 +88,12 @@ pinctrl_esdhc1: esdhc1grp { fsl,pins = < - MX25_PAD_SD1_CMD__SD1_CMD 0x400000c0 - MX25_PAD_SD1_CLK__SD1_CLK 0x400000c0 - MX25_PAD_SD1_DATA0__SD1_DATA0 0x400000c0 - MX25_PAD_SD1_DATA1__SD1_DATA1 0x400000c0 - MX25_PAD_SD1_DATA2__SD1_DATA2 0x400000c0 - MX25_PAD_SD1_DATA3__SD1_DATA3 0x400000c0 + MX25_PAD_SD1_CMD__ESDHC1_CMD 0x400000c0 + MX25_PAD_SD1_CLK__ESDHC1_CLK 0x400000c0 + MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x400000c0 + MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x400000c0 + MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x400000c0 + MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x400000c0 >; }; Index: sys/gnu/dts/arm/imx25-karo-tx25.dts =================================================================== --- sys/gnu/dts/arm/imx25-karo-tx25.dts +++ sys/gnu/dts/arm/imx25-karo-tx25.dts @@ -36,7 +36,7 @@ }; }; - memory { + memory@80000000 { reg = <0x80000000 0x02000000 0x90000000 0x02000000>; }; }; Index: sys/gnu/dts/arm/imx25-pdk.dts =================================================================== --- sys/gnu/dts/arm/imx25-pdk.dts +++ sys/gnu/dts/arm/imx25-pdk.dts @@ -18,7 +18,7 @@ model = "Freescale i.MX25 Product Development Kit"; compatible = "fsl,imx25-pdk", "fsl,imx25"; - memory { + memory@80000000 { reg = <0x80000000 0x4000000>; }; @@ -165,12 +165,12 @@ pinctrl_esdhc1: esdhc1grp { fsl,pins = < - MX25_PAD_SD1_CMD__SD1_CMD 0x80000000 - MX25_PAD_SD1_CLK__SD1_CLK 0x80000000 - MX25_PAD_SD1_DATA0__SD1_DATA0 0x80000000 - MX25_PAD_SD1_DATA1__SD1_DATA1 0x80000000 - MX25_PAD_SD1_DATA2__SD1_DATA2 0x80000000 - MX25_PAD_SD1_DATA3__SD1_DATA3 0x80000000 + MX25_PAD_SD1_CMD__ESDHC1_CMD 0x80000000 + MX25_PAD_SD1_CLK__ESDHC1_CLK 0x80000000 + MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000 + MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000 + MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000 + MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000 MX25_PAD_A14__GPIO_2_0 0x80000000 MX25_PAD_A15__GPIO_2_1 0x80000000 >; Index: sys/gnu/dts/arm/imx25-pinfunc.h =================================================================== --- sys/gnu/dts/arm/imx25-pinfunc.h +++ sys/gnu/dts/arm/imx25-pinfunc.h @@ -151,21 +151,21 @@ #define MX25_PAD_D15__D15 0x088 0x280 0x000 0x00 0x000 #define MX25_PAD_D15__LD16 0x088 0x280 0x000 0x01 0x000 #define MX25_PAD_D15__GPIO_4_5 0x088 0x280 0x000 0x05 0x000 -#define MX25_PAD_D15__SDHC1_DAT7 0x088 0x280 0x4d8 0x06 0x000 +#define MX25_PAD_D15__ESDHC1_DAT7 0x088 0x280 0x4d8 0x06 0x000 #define MX25_PAD_D14__D14 0x08c 0x284 0x000 0x00 0x000 #define MX25_PAD_D14__LD17 0x08c 0x284 0x000 0x01 0x000 #define MX25_PAD_D14__GPIO_4_6 0x08c 0x284 0x000 0x05 0x000 -#define MX25_PAD_D14__SDHC1_DAT6 0x08c 0x284 0x4d4 0x06 0x000 +#define MX25_PAD_D14__ESDHC1_DAT6 0x08c 0x284 0x4d4 0x06 0x000 #define MX25_PAD_D13__D13 0x090 0x288 0x000 0x00 0x000 #define MX25_PAD_D13__LD18 0x090 0x288 0x000 0x01 0x000 #define MX25_PAD_D13__GPIO_4_7 0x090 0x288 0x000 0x05 0x000 -#define MX25_PAD_D13__SDHC1_DAT5 0x090 0x288 0x4d0 0x06 0x000 +#define MX25_PAD_D13__ESDHC1_DAT5 0x090 0x288 0x4d0 0x06 0x000 #define MX25_PAD_D12__D12 0x094 0x28c 0x000 0x00 0x000 #define MX25_PAD_D12__GPIO_4_8 0x094 0x28c 0x000 0x05 0x000 -#define MX25_PAD_D12__SDHC1_DAT4 0x094 0x28c 0x4cc 0x06 0x000 +#define MX25_PAD_D12__ESDHC1_DAT4 0x094 0x28c 0x4cc 0x06 0x000 #define MX25_PAD_D11__D11 0x098 0x290 0x000 0x00 0x000 #define MX25_PAD_D11__GPIO_4_9 0x098 0x290 0x000 0x05 0x000 @@ -236,12 +236,13 @@ #define MX25_PAD_LD8__LD8 0x0e8 0x2e0 0x000 0x00 0x000 #define MX25_PAD_LD8__UART4_RXD 0x0e8 0x2e0 0x570 0x02 0x000 #define MX25_PAD_LD8__FEC_TX_ERR 0x0e8 0x2e0 0x000 0x05 0x000 -#define MX25_PAD_LD8__SDHC2_CMD 0x0e8 0x2e0 0x4e0 0x06 0x000 +/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */ +#define MX25_PAD_LD8__ESDHC2_CMD 0x0e8 0x2e0 0x4e0 0x16 0x000 #define MX25_PAD_LD9__LD9 0x0ec 0x2e4 0x000 0x00 0x000 #define MX25_PAD_LD9__UART4_TXD 0x0ec 0x2e4 0x000 0x02 0x000 #define MX25_PAD_LD9__FEC_COL 0x0ec 0x2e4 0x504 0x05 0x001 -#define MX25_PAD_LD9__SDHC2_CLK 0x0ec 0x2e4 0x4dc 0x06 0x000 +#define MX25_PAD_LD9__ESDHC2_CLK 0x0ec 0x2e4 0x4dc 0x06 0x000 #define MX25_PAD_LD10__LD10 0x0f0 0x2e8 0x000 0x00 0x000 #define MX25_PAD_LD10__UART4_RTS 0x0f0 0x2e8 0x56c 0x02 0x000 @@ -250,7 +251,7 @@ #define MX25_PAD_LD11__LD11 0x0f4 0x2ec 0x000 0x00 0x000 #define MX25_PAD_LD11__UART4_CTS 0x0f4 0x2ec 0x000 0x02 0x000 #define MX25_PAD_LD11__FEC_RDATA2 0x0f4 0x2ec 0x50c 0x05 0x001 -#define MX25_PAD_LD11__SDHC2_DAT1 0x0f4 0x2ec 0x4e8 0x06 0x000 +#define MX25_PAD_LD11__ESDHC2_DAT1 0x0f4 0x2ec 0x4e8 0x06 0x000 #define MX25_PAD_LD12__LD12 0x0f8 0x2f0 0x000 0x00 0x000 #define MX25_PAD_LD12__CSPI2_MOSI 0x0f8 0x2f0 0x4a0 0x02 0x000 @@ -316,12 +317,13 @@ #define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x07 0x000 #define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x00 0x000 -#define MX25_PAD_CSI_D6__SDHC2_CMD 0x130 0x328 0x4e0 0x02 0x001 +/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */ +#define MX25_PAD_CSI_D6__ESDHC2_CMD 0x130 0x328 0x4e0 0x12 0x001 #define MX25_PAD_CSI_D6__SIM1_PD0 0x130 0x328 0x000 0x04 0x000 #define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x05 0x000 #define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x00 0x000 -#define MX25_PAD_CSI_D7__SDHC2_DAT_CLK 0x134 0x32C 0x4dc 0x02 0x001 +#define MX25_PAD_CSI_D7__ESDHC2_CLK 0x134 0x32C 0x4dc 0x02 0x001 #define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x05 0x000 #define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x00 0x000 @@ -336,22 +338,22 @@ #define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x00 0x000 #define MX25_PAD_CSI_MCLK__AUD6_TXD 0x140 0x338 0x000 0x01 0x000 -#define MX25_PAD_CSI_MCLK__SDHC2_DAT0 0x140 0x338 0x4e4 0x02 0x001 +#define MX25_PAD_CSI_MCLK__ESDHC2_DAT0 0x140 0x338 0x4e4 0x02 0x001 #define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x05 0x000 #define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x00 0x000 #define MX25_PAD_CSI_VSYNC__AUD6_RXD 0x144 0x33c 0x000 0x01 0x000 -#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 0x144 0x33c 0x4e8 0x02 0x001 +#define MX25_PAD_CSI_VSYNC__ESDHC2_DAT1 0x144 0x33c 0x4e8 0x02 0x001 #define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x05 0x000 #define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x00 0x000 #define MX25_PAD_CSI_HSYNC__AUD6_TXC 0x148 0x340 0x000 0x01 0x000 -#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 0x148 0x340 0x4ec 0x02 0x001 +#define MX25_PAD_CSI_HSYNC__ESDHC2_DAT2 0x148 0x340 0x4ec 0x02 0x001 #define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x05 0x000 #define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x00 0x000 #define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 0x14c 0x344 0x000 0x01 0x000 -#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 0x14c 0x344 0x4f0 0x02 0x001 +#define MX25_PAD_CSI_PIXCLK__ESDHC2_DAT3 0x14c 0x344 0x4f0 0x02 0x001 #define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x05 0x000 #define MX25_PAD_I2C1_CLK__I2C1_CLK 0x150 0x348 0x000 0x00 0x000 @@ -419,37 +421,37 @@ #define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x05 0x000 /* - * Removing the SION bit from MX25_PAD_SD1_CMD__SD1_CMD breaks detecting an SD + * Removing the SION bit from MX25_PAD_*__ESDHCn_CMD breaks detecting an SD * card. According to the i.MX25 reference manual (e.g. Figure 23-2 in IMX25RM * Rev. 2 from 01/2011) this pin is bidirectional. So it seems to be a silicon - * bug that configuring the SD1_CMD function doesn't enable the input path for - * this pin. + * bug that configuring the ESDHCn_CMD function doesn't enable the input path + * for this pin. * This might have side effects for other hardware units that are connected to * that pin and use the respective function as input. */ -#define MX25_PAD_SD1_CMD__SD1_CMD 0x190 0x388 0x000 0x10 0x000 +#define MX25_PAD_SD1_CMD__ESDHC1_CMD 0x190 0x388 0x000 0x10 0x000 #define MX25_PAD_SD1_CMD__CSPI2_MOSI 0x190 0x388 0x4a0 0x01 0x001 #define MX25_PAD_SD1_CMD__FEC_RDATA2 0x190 0x388 0x50c 0x02 0x002 #define MX25_PAD_SD1_CMD__GPIO_2_23 0x190 0x388 0x000 0x05 0x000 -#define MX25_PAD_SD1_CLK__SD1_CLK 0x194 0x38c 0x000 0x00 0x000 +#define MX25_PAD_SD1_CLK__ESDHC1_CLK 0x194 0x38c 0x000 0x00 0x000 #define MX25_PAD_SD1_CLK__CSPI2_MISO 0x194 0x38c 0x49c 0x01 0x001 #define MX25_PAD_SD1_CLK__FEC_RDATA3 0x194 0x38c 0x510 0x02 0x002 #define MX25_PAD_SD1_CLK__GPIO_2_24 0x194 0x38c 0x000 0x05 0x000 -#define MX25_PAD_SD1_DATA0__SD1_DATA0 0x198 0x390 0x000 0x00 0x000 +#define MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x198 0x390 0x000 0x00 0x000 #define MX25_PAD_SD1_DATA0__CSPI2_SCLK 0x198 0x390 0x494 0x01 0x001 #define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x05 0x000 -#define MX25_PAD_SD1_DATA1__SD1_DATA1 0x19c 0x394 0x000 0x00 0x000 +#define MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x19c 0x394 0x000 0x00 0x000 #define MX25_PAD_SD1_DATA1__AUD7_RXD 0x19c 0x394 0x478 0x03 0x000 #define MX25_PAD_SD1_DATA1__GPIO_2_26 0x19c 0x394 0x000 0x05 0x000 -#define MX25_PAD_SD1_DATA2__SD1_DATA2 0x1a0 0x398 0x000 0x00 0x000 +#define MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x1a0 0x398 0x000 0x00 0x000 #define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x02 0x002 #define MX25_PAD_SD1_DATA2__GPIO_2_27 0x1a0 0x398 0x000 0x05 0x000 -#define MX25_PAD_SD1_DATA3__SD1_DATA3 0x1a4 0x39c 0x000 0x00 0x000 +#define MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x1a4 0x39c 0x000 0x00 0x000 #define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x02 0x002 #define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x05 0x000 @@ -496,6 +498,8 @@ #define MX25_PAD_KPP_COL3__GPIO_3_4 0x1c4 0x3bc 0x000 0x05 0x000 #define MX25_PAD_FEC_MDC__FEC_MDC 0x1c8 0x3c0 0x000 0x00 0x000 +/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */ +#define MX25_PAD_FEC_MDC__ESDHC2_CMD 0x1c8 0x3c0 0x4e0 0x11 0x002 #define MX25_PAD_FEC_MDC__AUD4_TXD 0x1c8 0x3c0 0x464 0x02 0x001 #define MX25_PAD_FEC_MDC__GPIO_3_5 0x1c8 0x3c0 0x000 0x05 0x000 @@ -601,4 +605,28 @@ #define MX25_PAD_BOOT_MODE1__BOOT_MODE1 0x228 0x000 0x000 0x00 0x000 #define MX25_PAD_BOOT_MODE1__GPIO_4_31 0x228 0x000 0x000 0x05 0x000 +/* + * Compatibility defines for out-of-tree users. You should update if you make + * use of one of them. + */ +#define MX25_PAD_D15__SDHC1_DAT7 MX25_PAD_D15__ESDHC1_DAT7 +#define MX25_PAD_D14__SDHC1_DAT6 MX25_PAD_D14__ESDHC1_DAT6 +#define MX25_PAD_D13__SDHC1_DAT5 MX25_PAD_D13__ESDHC1_DAT5 +#define MX25_PAD_D12__SDHC1_DAT4 MX25_PAD_D12__ESDHC1_DAT4 +#define MX25_PAD_LD8__SDHC2_CMD MX25_PAD_LD8__ESDHC2_CMD +#define MX25_PAD_LD9__SDHC2_CLK MX25_PAD_LD9__ESDHC2_CLK +#define MX25_PAD_LD11__SDHC2_DAT1 MX25_PAD_LD11__ESDHC2_DAT1 +#define MX25_PAD_CSI_D6__SDHC2_CMD MX25_PAD_CSI_D6__ESDHC2_CMD +#define MX25_PAD_CSI_D7__SDHC2_DAT_CLK MX25_PAD_CSI_D7__ESDHC2_CLK +#define MX25_PAD_CSI_MCLK__SDHC2_DAT0 MX25_PAD_CSI_MCLK__ESDHC2_DAT0 +#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 MX25_PAD_CSI_VSYNC__ESDHC2_DAT1 +#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 MX25_PAD_CSI_HSYNC__ESDHC2_DAT2 +#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 MX25_PAD_CSI_PIXCLK__ESDHC2_DAT3 +#define MX25_PAD_SD1_CMD__SD1_CMD MX25_PAD_SD1_CMD__ESDHC1_CMD +#define MX25_PAD_SD1_CLK__SD1_CLK MX25_PAD_SD1_CLK__ESDHC1_CLK +#define MX25_PAD_SD1_DATA0__SD1_DATA0 MX25_PAD_SD1_DATA0__ESDHC1_DAT0 +#define MX25_PAD_SD1_DATA1__SD1_DATA1 MX25_PAD_SD1_DATA1__ESDHC1_DAT1 +#define MX25_PAD_SD1_DATA2__SD1_DATA2 MX25_PAD_SD1_DATA2__ESDHC1_DAT2 +#define MX25_PAD_SD1_DATA3__SD1_DATA3 MX25_PAD_SD1_DATA3__ESDHC1_DAT3 + #endif /* __DTS_IMX25_PINFUNC_H */ Index: sys/gnu/dts/arm/imx25.dtsi =================================================================== --- sys/gnu/dts/arm/imx25.dtsi +++ sys/gnu/dts/arm/imx25.dtsi @@ -22,7 +22,7 @@ * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; reg = <0 0>; }; + memory { device_type = "memory"; }; aliases { ethernet0 = &fec; @@ -269,6 +269,7 @@ dmas = <&sdma 24 1 0>, <&sdma 25 1 0>; dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; status = "disabled"; }; @@ -329,6 +330,7 @@ dmas = <&sdma 28 1 0>, <&sdma 29 1 0>; dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; status = "disabled"; }; Index: sys/gnu/dts/arm/imx27-apf27.dts =================================================================== --- sys/gnu/dts/arm/imx27-apf27.dts +++ sys/gnu/dts/arm/imx27-apf27.dts @@ -19,7 +19,7 @@ model = "Armadeus Systems APF27 module"; compatible = "armadeus,imx27-apf27", "fsl,imx27"; - memory { + memory@a0000000 { reg = <0xa0000000 0x04000000>; }; Index: sys/gnu/dts/arm/imx27-eukrea-cpuimx27.dtsi =================================================================== --- sys/gnu/dts/arm/imx27-eukrea-cpuimx27.dtsi +++ sys/gnu/dts/arm/imx27-eukrea-cpuimx27.dtsi @@ -16,21 +16,14 @@ model = "Eukrea CPUIMX27"; compatible = "eukrea,cpuimx27", "fsl,imx27"; - memory { + memory@a0000000 { reg = <0xa0000000 0x04000000>; }; - clocks { - #address-cells = <1>; - #size-cells = <0>; - compatible = "simple-bus"; - - clk14745600: clock@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <14745600>; - reg = <0>; - }; + clk14745600: clk-uart { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <14745600>; }; }; Index: sys/gnu/dts/arm/imx27-eukrea-mbimxsd27-baseboard.dts =================================================================== --- sys/gnu/dts/arm/imx27-eukrea-mbimxsd27-baseboard.dts +++ sys/gnu/dts/arm/imx27-eukrea-mbimxsd27-baseboard.dts @@ -84,7 +84,7 @@ cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; status = "okay"; - ads7846 { + ads7846@0 { compatible = "ti,ads7846"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_touch>; Index: sys/gnu/dts/arm/imx27-pdk.dts =================================================================== --- sys/gnu/dts/arm/imx27-pdk.dts +++ sys/gnu/dts/arm/imx27-pdk.dts @@ -16,7 +16,7 @@ model = "Freescale i.MX27 Product Development Kit"; compatible = "fsl,imx27-pdk", "fsl,imx27"; - memory { + memory@a0000000 { reg = <0xa0000000 0x08000000>; }; Index: sys/gnu/dts/arm/imx27-phytec-phycard-s-som.dtsi =================================================================== --- sys/gnu/dts/arm/imx27-phytec-phycard-s-som.dtsi +++ sys/gnu/dts/arm/imx27-phytec-phycard-s-som.dtsi @@ -17,7 +17,7 @@ model = "Phytec pca100"; compatible = "phytec,imx27-pca100", "fsl,imx27"; - memory { + memory@a0000000 { reg = <0xa0000000 0x08000000>; /* 128MB */ }; }; Index: sys/gnu/dts/arm/imx27-phytec-phycore-som.dtsi =================================================================== --- sys/gnu/dts/arm/imx27-phytec-phycore-som.dtsi +++ sys/gnu/dts/arm/imx27-phytec-phycore-som.dtsi @@ -16,7 +16,7 @@ model = "Phytec pcm038"; compatible = "phytec,imx27-pcm038", "fsl,imx27"; - memory { + memory@a0000000 { reg = <0xa0000000 0x08000000>; }; Index: sys/gnu/dts/arm/imx27.dtsi =================================================================== --- sys/gnu/dts/arm/imx27.dtsi +++ sys/gnu/dts/arm/imx27.dtsi @@ -26,7 +26,7 @@ * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; reg = <0 0>; }; + memory { device_type = "memory"; }; aliases { ethernet0 = &fec; Index: sys/gnu/dts/arm/imx28-apf28.dts =================================================================== --- sys/gnu/dts/arm/imx28-apf28.dts +++ sys/gnu/dts/arm/imx28-apf28.dts @@ -16,7 +16,7 @@ model = "Armadeus Systems APF28 module"; compatible = "armadeus,imx28-apf28", "fsl,imx28"; - memory { + memory@40000000 { reg = <0x40000000 0x08000000>; }; Index: sys/gnu/dts/arm/imx28-apx4devkit.dts =================================================================== --- sys/gnu/dts/arm/imx28-apx4devkit.dts +++ sys/gnu/dts/arm/imx28-apx4devkit.dts @@ -6,7 +6,7 @@ model = "Bluegiga APX4 Development Kit"; compatible = "bluegiga,apx4devkit", "fsl,imx28"; - memory { + memory@40000000 { reg = <0x40000000 0x04000000>; }; @@ -82,7 +82,8 @@ fsl,pull-up = ; }; - mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4 { + mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4@0 { + reg = <0>; fsl,pinmux-ids = < MX28_PAD_SSP0_DATA7__SSP2_SCK >; @@ -146,6 +147,7 @@ sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; VDDA-supply = <®_3p3v>; VDDIO-supply = <®_3p3v>; clocks = <&saif0>; Index: sys/gnu/dts/arm/imx28-cfa10036.dts =================================================================== --- sys/gnu/dts/arm/imx28-cfa10036.dts +++ sys/gnu/dts/arm/imx28-cfa10036.dts @@ -16,7 +16,7 @@ model = "Crystalfontz CFA-10036 Board"; compatible = "crystalfontz,cfa10036", "fsl,imx28"; - memory { + memory@40000000 { reg = <0x40000000 0x08000000>; }; Index: sys/gnu/dts/arm/imx28-cfa10049.dts =================================================================== --- sys/gnu/dts/arm/imx28-cfa10049.dts +++ sys/gnu/dts/arm/imx28-cfa10049.dts @@ -19,6 +19,71 @@ model = "Crystalfontz CFA-10049 Board"; compatible = "crystalfontz,cfa10049", "crystalfontz,cfa10036", "fsl,imx28"; + i2cmux { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2cmux_pins_cfa10049>; + mux-gpios = <&gpio1 22 0 &gpio1 23 0>; + i2c-parent = <&i2c1>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + adc0: nau7802@2a { + compatible = "nuvoton,nau7802"; + reg = <0x2a>; + nuvoton,vldo = <3000>; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + adc1: nau7802@2a { + compatible = "nuvoton,nau7802"; + reg = <0x2a>; + nuvoton,vldo = <3000>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + adc2: nau7802@2a { + compatible = "nuvoton,nau7802"; + reg = <0x2a>; + nuvoton,vldo = <3000>; + }; + }; + + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + pca9555: pca9555@20 { + compatible = "nxp,pca9555"; + pinctrl-names = "default"; + pinctrl-0 = <&pca_pins_cfa10049>; + interrupt-parent = <&gpio2>; + interrupts = <19 0x2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x20>; + }; + }; + }; + apb@80000000 { apbh@80000000 { pinctrl@80018000 { @@ -219,71 +284,6 @@ status = "okay"; }; - i2cmux { - compatible = "i2c-mux-gpio"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2cmux_pins_cfa10049>; - mux-gpios = <&gpio1 22 0 &gpio1 23 0>; - i2c-parent = <&i2c1>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - adc0: nau7802@2a { - compatible = "nuvoton,nau7802"; - reg = <0x2a>; - nuvoton,vldo = <3000>; - }; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - adc1: nau7802@2a { - compatible = "nuvoton,nau7802"; - reg = <0x2a>; - nuvoton,vldo = <3000>; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - adc2: nau7802@2a { - compatible = "nuvoton,nau7802"; - reg = <0x2a>; - nuvoton,vldo = <3000>; - }; - }; - - i2c@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - - pca9555: pca9555@20 { - compatible = "nxp,pca9555"; - pinctrl-names = "default"; - pinctrl-0 = <&pca_pins_cfa10049>; - interrupt-parent = <&gpio2>; - interrupts = <19 0x2>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x20>; - }; - }; - }; - usbphy1: usbphy@8007e000 { status = "okay"; }; Index: sys/gnu/dts/arm/imx28-duckbill-2-485.dts =================================================================== --- sys/gnu/dts/arm/imx28-duckbill-2-485.dts +++ sys/gnu/dts/arm/imx28-duckbill-2-485.dts @@ -19,7 +19,7 @@ model = "I2SE Duckbill 2 485"; compatible = "i2se,duckbill-2-485", "i2se,duckbill-2", "fsl,imx28"; - memory { + memory@40000000 { reg = <0x40000000 0x08000000>; }; Index: sys/gnu/dts/arm/imx28-duckbill-2-enocean.dts =================================================================== --- sys/gnu/dts/arm/imx28-duckbill-2-enocean.dts +++ sys/gnu/dts/arm/imx28-duckbill-2-enocean.dts @@ -20,7 +20,7 @@ model = "I2SE Duckbill 2 EnOcean"; compatible = "i2se,duckbill-2-enocean", "i2se,duckbill-2", "fsl,imx28"; - memory { + memory@40000000 { reg = <0x40000000 0x08000000>; }; Index: sys/gnu/dts/arm/imx28-duckbill-2-spi.dts =================================================================== --- sys/gnu/dts/arm/imx28-duckbill-2-spi.dts +++ sys/gnu/dts/arm/imx28-duckbill-2-spi.dts @@ -23,7 +23,7 @@ ethernet1 = &qca7000; }; - memory { + memory@40000000 { reg = <0x40000000 0x08000000>; }; Index: sys/gnu/dts/arm/imx28-duckbill-2.dts =================================================================== --- sys/gnu/dts/arm/imx28-duckbill-2.dts +++ sys/gnu/dts/arm/imx28-duckbill-2.dts @@ -19,7 +19,7 @@ model = "I2SE Duckbill 2"; compatible = "i2se,duckbill-2", "fsl,imx28"; - memory { + memory@40000000 { reg = <0x40000000 0x08000000>; }; Index: sys/gnu/dts/arm/imx28-duckbill.dts =================================================================== --- sys/gnu/dts/arm/imx28-duckbill.dts +++ sys/gnu/dts/arm/imx28-duckbill.dts @@ -18,7 +18,7 @@ model = "I2SE Duckbill"; compatible = "i2se,duckbill", "fsl,imx28"; - memory { + memory@40000000 { reg = <0x40000000 0x08000000>; }; Index: sys/gnu/dts/arm/imx28-eukrea-mbmx283lc.dts =================================================================== --- sys/gnu/dts/arm/imx28-eukrea-mbmx283lc.dts +++ sys/gnu/dts/arm/imx28-eukrea-mbmx283lc.dts @@ -23,7 +23,7 @@ model = "Eukrea Electromatique MBMX283LC"; compatible = "eukrea,mbmx283lc", "eukrea,mbmx28lc", "fsl,imx28"; - memory { + memory@40000000 { reg = <0x40000000 0x04000000>; }; }; Index: sys/gnu/dts/arm/imx28-eukrea-mbmx287lc.dts =================================================================== --- sys/gnu/dts/arm/imx28-eukrea-mbmx287lc.dts +++ sys/gnu/dts/arm/imx28-eukrea-mbmx287lc.dts @@ -22,7 +22,7 @@ model = "Eukrea Electromatique MBMX287LC"; compatible = "eukrea,mbmx287lc", "eukrea,mbmx283lc", "eukrea,mbmx28lc", "fsl,imx28"; - memory { + memory@40000000 { reg = <0x40000000 0x08000000>; }; }; Index: sys/gnu/dts/arm/imx28-eukrea-mbmx28lc.dtsi =================================================================== --- sys/gnu/dts/arm/imx28-eukrea-mbmx28lc.dtsi +++ sys/gnu/dts/arm/imx28-eukrea-mbmx28lc.dtsi @@ -151,6 +151,7 @@ sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; VDDA-supply = <®_3p3v>; VDDIO-supply = <®_3p3v>; clocks = <&saif0>; Index: sys/gnu/dts/arm/imx28-evk.dts =================================================================== --- sys/gnu/dts/arm/imx28-evk.dts +++ sys/gnu/dts/arm/imx28-evk.dts @@ -16,7 +16,7 @@ model = "Freescale i.MX28 Evaluation Kit"; compatible = "fsl,imx28-evk", "fsl,imx28"; - memory { + memory@40000000 { reg = <0x40000000 0x08000000>; }; @@ -197,6 +197,7 @@ sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; VDDA-supply = <®_3p3v>; VDDIO-supply = <®_3p3v>; clocks = <&saif0>; Index: sys/gnu/dts/arm/imx28-m28.dtsi =================================================================== --- sys/gnu/dts/arm/imx28-m28.dtsi +++ sys/gnu/dts/arm/imx28-m28.dtsi @@ -15,7 +15,7 @@ model = "Aries/DENX M28"; compatible = "aries,m28", "denx,m28", "fsl,imx28"; - memory { + memory@40000000 { reg = <0x40000000 0x08000000>; }; Index: sys/gnu/dts/arm/imx28-m28cu3.dts =================================================================== --- sys/gnu/dts/arm/imx28-m28cu3.dts +++ sys/gnu/dts/arm/imx28-m28cu3.dts @@ -16,7 +16,7 @@ model = "MSR M28CU3"; compatible = "msr,m28cu3", "fsl,imx28"; - memory { + memory@40000000 { reg = <0x40000000 0x08000000>; }; Index: sys/gnu/dts/arm/imx28-m28evk.dts =================================================================== --- sys/gnu/dts/arm/imx28-m28evk.dts +++ sys/gnu/dts/arm/imx28-m28evk.dts @@ -140,6 +140,7 @@ sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; VDDA-supply = <®_3p3v>; VDDIO-supply = <®_3p3v>; clocks = <&saif0>; Index: sys/gnu/dts/arm/imx28-sps1.dts =================================================================== --- sys/gnu/dts/arm/imx28-sps1.dts +++ sys/gnu/dts/arm/imx28-sps1.dts @@ -16,7 +16,7 @@ model = "SchulerControl GmbH, SC SPS 1"; compatible = "schulercontrol,imx28-sps1", "fsl,imx28"; - memory { + memory@40000000 { reg = <0x40000000 0x08000000>; }; Index: sys/gnu/dts/arm/imx28-ts4600.dts =================================================================== --- sys/gnu/dts/arm/imx28-ts4600.dts +++ sys/gnu/dts/arm/imx28-ts4600.dts @@ -19,7 +19,7 @@ model = "Technologic Systems i.MX28 TS-4600"; compatible = "technologic,imx28-ts4600", "fsl,imx28"; - memory { + memory@40000000 { reg = <0x40000000 0x10000000>; /* 256MB */ }; Index: sys/gnu/dts/arm/imx28-tx28.dts =================================================================== --- sys/gnu/dts/arm/imx28-tx28.dts +++ sys/gnu/dts/arm/imx28-tx28.dts @@ -65,8 +65,8 @@ usbotg = &usb0; }; - memory { - reg = <0 0>; /* will be filled in by U-Boot */ + memory@40000000 { + reg = <0x40000000 0>; /* will be filled in by U-Boot */ }; onewire { @@ -531,7 +531,8 @@ fsl,pull-up = ; }; - tx28_edt_ft5x06_pins: tx28-edt-ft5x06-pins { + tx28_edt_ft5x06_pins: tx28-edt-ft5x06-pins@0 { + reg = <0>; fsl,pinmux-ids = < MX28_PAD_SSP0_DATA6__GPIO_2_6 /* RESET */ MX28_PAD_SSP0_DATA5__GPIO_2_5 /* IRQ */ @@ -542,7 +543,8 @@ fsl,pull-up = ; }; - tx28_flexcan_xcvr_pins: tx28-flexcan-xcvr-pins { + tx28_flexcan_xcvr_pins: tx28-flexcan-xcvr-pins@0 { + reg = <0>; fsl,pinmux-ids = < MX28_PAD_LCD_D00__GPIO_1_0 >; @@ -551,7 +553,8 @@ fsl,pull-up = ; }; - tx28_lcdif_23bit_pins: tx28-lcdif-23bit { + tx28_lcdif_23bit_pins: tx28-lcdif-23bit@0 { + reg = <0>; fsl,pinmux-ids = < /* LCD_D00 may be used as Flexcan Transceiver Enable on STK5-V5 */ MX28_PAD_LCD_D01__LCD_D1 @@ -583,7 +586,8 @@ fsl,pull-up = ; }; - tx28_lcdif_ctrl_pins: tx28-lcdif-ctrl { + tx28_lcdif_ctrl_pins: tx28-lcdif-ctrl@0 { + reg = <0>; fsl,pinmux-ids = < MX28_PAD_LCD_ENABLE__GPIO_1_31 /* Enable */ MX28_PAD_LCD_RESET__GPIO_3_30 /* Reset */ @@ -593,7 +597,8 @@ fsl,pull-up = ; }; - tx28_mac0_pins_gpio: tx28-mac0-gpio-pins { + tx28_mac0_pins_gpio: tx28-mac0-gpio-pins@0 { + reg = <0>; fsl,pinmux-ids = < MX28_PAD_ENET0_MDC__GPIO_4_0 MX28_PAD_ENET0_MDIO__GPIO_4_1 @@ -610,7 +615,8 @@ fsl,pull-up = ; }; - tx28_pca9554_pins: tx28-pca9554-pins { + tx28_pca9554_pins: tx28-pca9554-pins@0 { + reg = <0>; fsl,pinmux-ids = < MX28_PAD_PWM3__GPIO_3_28 >; @@ -619,7 +625,8 @@ fsl,pull-up = ; }; - tx28_spi_gpio_pins: spi-gpiogrp { + tx28_spi_gpio_pins: spi-gpiogrp@0 { + reg = <0>; fsl,pinmux-ids = < MX28_PAD_AUART2_RX__GPIO_3_8 MX28_PAD_AUART2_TX__GPIO_3_9 @@ -633,7 +640,8 @@ fsl,pull-up = ; }; - tx28_tsc2007_pins: tx28-tsc2007-pins { + tx28_tsc2007_pins: tx28-tsc2007-pins@0 { + reg = <0>; fsl,pinmux-ids = < MX28_PAD_SAIF0_MCLK__GPIO_3_20 /* TSC2007 IRQ */ >; @@ -643,7 +651,8 @@ }; - tx28_usbphy0_pins: tx28-usbphy0-pins { + tx28_usbphy0_pins: tx28-usbphy0-pins@0 { + reg = <0>; fsl,pinmux-ids = < MX28_PAD_GPMI_CE2N__GPIO_0_18 /* USBOTG_VBUSEN */ MX28_PAD_GPMI_CE3N__GPIO_0_19 /* USBOTH_OC */ @@ -653,7 +662,8 @@ fsl,pull-up = ; }; - tx28_usbphy1_pins: tx28-usbphy1-pins { + tx28_usbphy1_pins: tx28-usbphy1-pins@0 { + reg = <0>; fsl,pinmux-ids = < MX28_PAD_SPDIF__GPIO_3_27 /* USBH_VBUSEN */ MX28_PAD_JTAG_RTCK__GPIO_4_20 /* USBH_OC */ Index: sys/gnu/dts/arm/imx28.dtsi =================================================================== --- sys/gnu/dts/arm/imx28.dtsi +++ sys/gnu/dts/arm/imx28.dtsi @@ -24,7 +24,7 @@ * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; reg = <0 0>; }; + memory { device_type = "memory"; }; aliases { ethernet0 = &mac0; @@ -283,7 +283,8 @@ fsl,pull-up = ; }; - gpmi_status_cfg: gpmi-status-cfg { + gpmi_status_cfg: gpmi-status-cfg@0 { + reg = <0>; fsl,pinmux-ids = < MX28_PAD_GPMI_RDN__GPMI_RDN MX28_PAD_GPMI_WRN__GPMI_WRN @@ -527,14 +528,16 @@ fsl,pull-up = ; }; - mmc0_cd_cfg: mmc0-cd-cfg { + mmc0_cd_cfg: mmc0-cd-cfg@0 { + reg = <0>; fsl,pinmux-ids = < MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT >; fsl,pull-up = ; }; - mmc0_sck_cfg: mmc0-sck-cfg { + mmc0_sck_cfg: mmc0-sck-cfg@0 { + reg = <0>; fsl,pinmux-ids = < MX28_PAD_SSP0_SCK__SSP0_SCK >; @@ -558,14 +561,16 @@ fsl,pull-up = ; }; - mmc1_cd_cfg: mmc1-cd-cfg { + mmc1_cd_cfg: mmc1-cd-cfg@0 { + reg = <0>; fsl,pinmux-ids = < MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT >; fsl,pull-up = ; }; - mmc1_sck_cfg: mmc1-sck-cfg { + mmc1_sck_cfg: mmc1-sck-cfg@0 { + reg = <0>; fsl,pinmux-ids = < MX28_PAD_GPMI_WRN__SSP1_SCK >; @@ -606,7 +611,8 @@ fsl,pull-up = ; }; - mmc2_cd_cfg: mmc2-cd-cfg { + mmc2_cd_cfg: mmc2-cd-cfg@0 { + reg = <0>; fsl,pinmux-ids = < MX28_PAD_AUART1_RX__SSP2_CARD_DETECT >; Index: sys/gnu/dts/arm/imx31-bug.dts =================================================================== --- sys/gnu/dts/arm/imx31-bug.dts +++ sys/gnu/dts/arm/imx31-bug.dts @@ -16,7 +16,7 @@ model = "Buglabs i.MX31 Bug 1.x"; compatible = "buglabs,imx31-bug", "fsl,imx31"; - memory { + memory@80000000 { reg = <0x80000000 0x8000000>; /* 128M */ }; }; Index: sys/gnu/dts/arm/imx31.dtsi =================================================================== --- sys/gnu/dts/arm/imx31.dtsi +++ sys/gnu/dts/arm/imx31.dtsi @@ -19,7 +19,7 @@ * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; reg = <0 0>; }; + memory { device_type = "memory"; }; aliases { serial0 = &uart1; Index: sys/gnu/dts/arm/imx35-eukrea-cpuimx35.dtsi =================================================================== --- sys/gnu/dts/arm/imx35-eukrea-cpuimx35.dtsi +++ sys/gnu/dts/arm/imx35-eukrea-cpuimx35.dtsi @@ -17,7 +17,7 @@ model = "Eukrea CPUIMX35"; compatible = "eukrea,cpuimx35", "fsl,imx35"; - memory { + memory@80000000 { reg = <0x80000000 0x8000000>; /* 128M */ }; }; Index: sys/gnu/dts/arm/imx35-pdk.dts =================================================================== --- sys/gnu/dts/arm/imx35-pdk.dts +++ sys/gnu/dts/arm/imx35-pdk.dts @@ -17,7 +17,7 @@ model = "Freescale i.MX35 Product Development Kit"; compatible = "fsl,imx35-pdk", "fsl,imx35"; - memory { + memory@80000000 { reg = <0x80000000 0x8000000>, <0x90000000 0x8000000>; }; Index: sys/gnu/dts/arm/imx35.dtsi =================================================================== --- sys/gnu/dts/arm/imx35.dtsi +++ sys/gnu/dts/arm/imx35.dtsi @@ -20,7 +20,7 @@ * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; reg = <0 0>; }; + memory { device_type = "memory"; }; aliases { ethernet0 = &fec; @@ -303,7 +303,7 @@ }; can1: can@53fe4000 { - compatible = "fsl,imx35-flexcan"; + compatible = "fsl,imx35-flexcan", "fsl,imx25-flexcan"; reg = <0x53fe4000 0x1000>; clocks = <&clks 33>, <&clks 33>; clock-names = "ipg", "per"; @@ -312,7 +312,7 @@ }; can2: can@53fe8000 { - compatible = "fsl,imx35-flexcan"; + compatible = "fsl,imx35-flexcan", "fsl,imx25-flexcan"; reg = <0x53fe8000 0x1000>; clocks = <&clks 34>, <&clks 34>; clock-names = "ipg", "per"; Index: sys/gnu/dts/arm/imx50-evk.dts =================================================================== --- sys/gnu/dts/arm/imx50-evk.dts +++ sys/gnu/dts/arm/imx50-evk.dts @@ -18,7 +18,7 @@ model = "Freescale i.MX50 Evaluation Kit"; compatible = "fsl,imx50-evk", "fsl,imx50"; - memory { + memory@70000000 { reg = <0x70000000 0x80000000>; }; }; Index: sys/gnu/dts/arm/imx50.dtsi =================================================================== --- sys/gnu/dts/arm/imx50.dtsi +++ sys/gnu/dts/arm/imx50.dtsi @@ -25,7 +25,7 @@ * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; reg = <0 0>; }; + memory { device_type = "memory"; }; aliases { ethernet0 = &fec; Index: sys/gnu/dts/arm/imx51-apf51.dts =================================================================== --- sys/gnu/dts/arm/imx51-apf51.dts +++ sys/gnu/dts/arm/imx51-apf51.dts @@ -21,7 +21,7 @@ model = "Armadeus Systems APF51 module"; compatible = "armadeus,imx51-apf51", "fsl,imx51"; - memory { + memory@90000000 { reg = <0x90000000 0x20000000>; }; Index: sys/gnu/dts/arm/imx51-babbage.dts =================================================================== --- sys/gnu/dts/arm/imx51-babbage.dts +++ sys/gnu/dts/arm/imx51-babbage.dts @@ -21,7 +21,7 @@ stdout-path = &uart1; }; - memory { + memory@90000000 { reg = <0x90000000 0x20000000>; }; @@ -369,6 +369,7 @@ sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; clocks = <&clk_audio>; VDDA-supply = <&vdig_reg>; VDDIO-supply = <&vvideo_reg>; Index: sys/gnu/dts/arm/imx51-digi-connectcore-jsk.dts =================================================================== --- sys/gnu/dts/arm/imx51-digi-connectcore-jsk.dts +++ sys/gnu/dts/arm/imx51-digi-connectcore-jsk.dts @@ -17,7 +17,7 @@ "digi,connectcore-ccxmx51-som", "fsl,imx51"; chosen { - linux,stdout-path = &uart1; + stdout-path = &uart1; }; }; Index: sys/gnu/dts/arm/imx51-digi-connectcore-som.dtsi =================================================================== --- sys/gnu/dts/arm/imx51-digi-connectcore-som.dtsi +++ sys/gnu/dts/arm/imx51-digi-connectcore-som.dtsi @@ -16,7 +16,7 @@ model = "Digi ConnectCore CC(W)-MX51"; compatible = "digi,connectcore-ccxmx51-som", "fsl,imx51"; - memory { + memory@90000000 { reg = <0x90000000 0x08000000>; }; }; Index: sys/gnu/dts/arm/imx51-eukrea-cpuimx51.dtsi =================================================================== --- sys/gnu/dts/arm/imx51-eukrea-cpuimx51.dtsi +++ sys/gnu/dts/arm/imx51-eukrea-cpuimx51.dtsi @@ -22,7 +22,7 @@ model = "Eukrea CPUIMX51"; compatible = "eukrea,cpuimx51", "fsl,imx51"; - memory { + memory@90000000 { reg = <0x90000000 0x10000000>; /* 256M */ }; }; Index: sys/gnu/dts/arm/imx51-ts4800.dts =================================================================== --- sys/gnu/dts/arm/imx51-ts4800.dts +++ sys/gnu/dts/arm/imx51-ts4800.dts @@ -17,7 +17,7 @@ stdout-path = &uart1; }; - memory { + memory@90000000 { reg = <0x90000000 0x10000000>; }; Index: sys/gnu/dts/arm/imx51-zii-rdu1.dts =================================================================== --- sys/gnu/dts/arm/imx51-zii-rdu1.dts +++ sys/gnu/dts/arm/imx51-zii-rdu1.dts @@ -51,6 +51,11 @@ stdout-path = &uart1; }; + /* Will be filled by the bootloader */ + memory@90000000 { + reg = <0x90000000 0>; + }; + aliases { mdio-gpio0 = &mdio_gpio; rtc0 = &ds1341; @@ -518,7 +523,7 @@ }; touchscreen@20 { - compatible = "syna,rmi4_i2c"; + compatible = "syna,rmi4-i2c"; reg = <0x20>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ts>; @@ -536,8 +541,8 @@ rmi4-f11@11 { reg = <0x11>; - touch-inverted-y; - touch-swapped-x-y; + touchscreen-inverted-y; + touchscreen-swapped-x-y; syna,sensor-type = <1>; }; }; @@ -568,6 +573,15 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; status = "okay"; + + rave-sp { + compatible = "zii,rave-sp-rdu1"; + current-speed = <38400>; + + watchdog { + compatible = "zii,rave-sp-watchdog"; + }; + }; }; &usbh1 { Index: sys/gnu/dts/arm/imx51.dtsi =================================================================== --- sys/gnu/dts/arm/imx51.dtsi +++ sys/gnu/dts/arm/imx51.dtsi @@ -26,7 +26,7 @@ * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; reg = <0 0>; }; + memory { device_type = "memory"; }; aliases { ethernet0 = &fec; Index: sys/gnu/dts/arm/imx53-ard.dts =================================================================== --- sys/gnu/dts/arm/imx53-ard.dts +++ sys/gnu/dts/arm/imx53-ard.dts @@ -17,7 +17,7 @@ model = "Freescale i.MX53 Automotive Reference Design Board"; compatible = "fsl,imx53-ard", "fsl,imx53"; - memory { + memory@70000000 { reg = <0x70000000 0x40000000>; }; Index: sys/gnu/dts/arm/imx53-cx9020.dts =================================================================== --- sys/gnu/dts/arm/imx53-cx9020.dts +++ sys/gnu/dts/arm/imx53-cx9020.dts @@ -21,7 +21,7 @@ stdout-path = &uart2; }; - memory { + memory@70000000 { reg = <0x70000000 0x20000000>, <0xb0000000 0x20000000>; }; Index: sys/gnu/dts/arm/imx53-m53.dtsi =================================================================== --- sys/gnu/dts/arm/imx53-m53.dtsi +++ sys/gnu/dts/arm/imx53-m53.dtsi @@ -15,7 +15,7 @@ model = "Aries/DENX M53"; compatible = "aries,imx53-m53", "denx,imx53-m53", "fsl,imx53"; - memory { + memory@70000000 { reg = <0x70000000 0x20000000>, <0xb0000000 0x20000000>; }; Index: sys/gnu/dts/arm/imx53-m53evk.dts =================================================================== --- sys/gnu/dts/arm/imx53-m53evk.dts +++ sys/gnu/dts/arm/imx53-m53evk.dts @@ -153,6 +153,7 @@ sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; VDDA-supply = <®_3p2v>; VDDIO-supply = <®_3p2v>; clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; Index: sys/gnu/dts/arm/imx53-ppd.dts =================================================================== --- sys/gnu/dts/arm/imx53-ppd.dts +++ sys/gnu/dts/arm/imx53-ppd.dts @@ -132,6 +132,14 @@ enable-active-high; }; + reg_tsiref: regulator-tsiref { + compatible = "regulator-fixed"; + regulator-name = "tsiref"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + pwm_bl: backlight { compatible = "pwm-backlight"; pwms = <&pwm2 0 50000>; @@ -294,6 +302,8 @@ interrupt-parent = <&gpio3>; interrupts = <12 0x8>; spi-max-frequency = <1000000>; + dlg,tsi-as-adc; + tsiref-supply = <®_tsiref>; regulators { buck1_reg: buck1 { @@ -436,6 +446,7 @@ sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0xa>; + #sound-dai-cells = <0>; VDDA-supply = <®_sgtl5k>; VDDIO-supply = <®_sgtl5k>; clocks = <&cko2_11M>; @@ -525,6 +536,7 @@ touchscreen@4b { compatible = "atmel,maxtouch"; + reset-gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>; reg = <0x4b>; interrupt-parent = <&gpio5>; interrupts = <4 0x8>; Index: sys/gnu/dts/arm/imx53-qsb-common.dtsi =================================================================== --- sys/gnu/dts/arm/imx53-qsb-common.dtsi +++ sys/gnu/dts/arm/imx53-qsb-common.dtsi @@ -17,7 +17,7 @@ stdout-path = &uart1; }; - memory { + memory@70000000 { reg = <0x70000000 0x20000000>, <0xb0000000 0x20000000>; }; @@ -317,6 +317,7 @@ sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; VDDA-supply = <®_3p2v>; VDDIO-supply = <®_3p2v>; clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; Index: sys/gnu/dts/arm/imx53-smd.dts =================================================================== --- sys/gnu/dts/arm/imx53-smd.dts +++ sys/gnu/dts/arm/imx53-smd.dts @@ -17,7 +17,7 @@ model = "Freescale i.MX53 Smart Mobile Reference Design Board"; compatible = "fsl,imx53-smd", "fsl,imx53"; - memory { + memory@70000000 { reg = <0x70000000 0x40000000>; }; Index: sys/gnu/dts/arm/imx53-tqma53.dtsi =================================================================== --- sys/gnu/dts/arm/imx53-tqma53.dtsi +++ sys/gnu/dts/arm/imx53-tqma53.dtsi @@ -16,7 +16,7 @@ model = "TQ TQMa53"; compatible = "tq,tqma53", "fsl,imx53"; - memory { + memory@70000000 { reg = <0x70000000 0x40000000>; /* Up to 1GiB */ }; Index: sys/gnu/dts/arm/imx53-tx53-x03x.dts =================================================================== --- sys/gnu/dts/arm/imx53-tx53-x03x.dts +++ sys/gnu/dts/arm/imx53-tx53-x03x.dts @@ -230,6 +230,7 @@ sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; VDDA-supply = <®_2v5>; VDDIO-supply = <®_3v3>; clocks = <&mclk>; Index: sys/gnu/dts/arm/imx53-tx53-x13x.dts =================================================================== --- sys/gnu/dts/arm/imx53-tx53-x13x.dts +++ sys/gnu/dts/arm/imx53-tx53-x13x.dts @@ -131,6 +131,7 @@ sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; VDDA-supply = <®_2v5>; VDDIO-supply = <®_3v3>; clocks = <&mclk>; Index: sys/gnu/dts/arm/imx53-tx53.dtsi =================================================================== --- sys/gnu/dts/arm/imx53-tx53.dtsi +++ sys/gnu/dts/arm/imx53-tx53.dtsi @@ -49,6 +49,11 @@ model = "Ka-Ro electronics TX53 module"; compatible = "karo,tx53", "fsl,imx53"; + /* Will be filled by the bootloader */ + memory@70000000 { + reg = <0x70000000 0>; + }; + aliases { can0 = &can2; /* Make the can interface indices consistent with TX28/TX48 modules */ can1 = &can1; Index: sys/gnu/dts/arm/imx53-usbarmory.dts =================================================================== --- sys/gnu/dts/arm/imx53-usbarmory.dts +++ sys/gnu/dts/arm/imx53-usbarmory.dts @@ -57,7 +57,7 @@ stdout-path = &uart1; }; - memory { + memory@70000000 { reg = <0x70000000 0x20000000>; }; Index: sys/gnu/dts/arm/imx53-voipac-bsb.dts =================================================================== --- sys/gnu/dts/arm/imx53-voipac-bsb.dts +++ sys/gnu/dts/arm/imx53-voipac-bsb.dts @@ -133,6 +133,7 @@ sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; VDDA-supply = <®_3p3v>; VDDIO-supply = <®_3p3v>; clocks = <&clks 150>; Index: sys/gnu/dts/arm/imx53.dtsi =================================================================== --- sys/gnu/dts/arm/imx53.dtsi +++ sys/gnu/dts/arm/imx53.dtsi @@ -26,7 +26,7 @@ * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; reg = <0 0>; }; + memory { device_type = "memory"; }; aliases { ethernet0 = &fec; @@ -551,7 +551,7 @@ }; can1: can@53fc8000 { - compatible = "fsl,imx53-flexcan"; + compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan"; reg = <0x53fc8000 0x4000>; interrupts = <82>; clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, @@ -561,7 +561,7 @@ }; can2: can@53fcc000 { - compatible = "fsl,imx53-flexcan"; + compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan"; reg = <0x53fcc000 0x4000>; interrupts = <83>; clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>, Index: sys/gnu/dts/arm/imx6dl-apf6dev.dts =================================================================== --- sys/gnu/dts/arm/imx6dl-apf6dev.dts +++ sys/gnu/dts/arm/imx6dl-apf6dev.dts @@ -54,7 +54,7 @@ model = "Armadeus APF6 Solo Module on APF6Dev Board"; compatible = "armadeus,imx6dl-apf6dev", "armadeus,imx6dl-apf6", "fsl,imx6dl"; - memory { + memory@10000000 { reg = <0x10000000 0x20000000>; }; }; Index: sys/gnu/dts/arm/imx6dl-aristainetos2_4.dts =================================================================== --- sys/gnu/dts/arm/imx6dl-aristainetos2_4.dts +++ sys/gnu/dts/arm/imx6dl-aristainetos2_4.dts @@ -48,7 +48,7 @@ model = "aristainetos2 i.MX6 Dual Lite Board 4"; compatible = "fsl,imx6dl"; - memory { + memory@10000000 { reg = <0x10000000 0x40000000>; }; Index: sys/gnu/dts/arm/imx6dl-aristainetos2_7.dts =================================================================== --- sys/gnu/dts/arm/imx6dl-aristainetos2_7.dts +++ sys/gnu/dts/arm/imx6dl-aristainetos2_7.dts @@ -48,7 +48,7 @@ model = "aristainetos2 i.MX6 Dual Lite Board 7"; compatible = "fsl,imx6dl"; - memory { + memory@10000000 { reg = <0x10000000 0x40000000>; }; Index: sys/gnu/dts/arm/imx6dl-aristainetos_4.dts =================================================================== --- sys/gnu/dts/arm/imx6dl-aristainetos_4.dts +++ sys/gnu/dts/arm/imx6dl-aristainetos_4.dts @@ -27,7 +27,7 @@ status = "okay"; }; - memory { + memory@10000000 { reg = <0x10000000 0x40000000>; }; Index: sys/gnu/dts/arm/imx6dl-aristainetos_7.dts =================================================================== --- sys/gnu/dts/arm/imx6dl-aristainetos_7.dts +++ sys/gnu/dts/arm/imx6dl-aristainetos_7.dts @@ -16,7 +16,7 @@ model = "aristainetos i.MX6 Dual Lite Board 7"; compatible = "fsl,imx6dl"; - memory { + memory@10000000 { reg = <0x10000000 0x40000000>; }; Index: sys/gnu/dts/arm/imx6dl-colibri-eval-v3.dts =================================================================== --- sys/gnu/dts/arm/imx6dl-colibri-eval-v3.dts +++ sys/gnu/dts/arm/imx6dl-colibri-eval-v3.dts @@ -53,6 +53,11 @@ compatible = "toradex,colibri_imx6dl-eval-v3", "toradex,colibri_imx6dl", "fsl,imx6dl"; + /* Will be filled by the bootloader */ + memory@10000000 { + reg = <0x10000000 0>; + }; + aliases { i2c0 = &i2c2; i2c1 = &i2c3; @@ -63,6 +68,10 @@ rtc1 = &snvs_rtc; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + clocks { /* Fixed crystal dedicated to mcp251x */ clk16m: clk@1 { Index: sys/gnu/dts/arm/imx6dl-dfi-fs700-m60.dts =================================================================== --- sys/gnu/dts/arm/imx6dl-dfi-fs700-m60.dts +++ sys/gnu/dts/arm/imx6dl-dfi-fs700-m60.dts @@ -20,4 +20,9 @@ / { model = "DFI FS700-M60-6DL i.MX6dl Q7 Board"; compatible = "dfi,fs700-m60-6dl", "dfi,fs700e-m60", "fsl,imx6dl"; + + /* Will be filled by the bootloader */ + memory@10000000 { + reg = <0x10000000 0>; + }; }; Index: sys/gnu/dts/arm/imx6dl-phytec-mira-rdk-nand.dts =================================================================== --- /dev/null +++ sys/gnu/dts/arm/imx6dl-phytec-mira-rdk-nand.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 PHYTEC Messtechnik GmbH + * Author: Christian Hemp + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-phytec-phycore-som.dtsi" +#include "imx6qdl-phytec-mira.dtsi" + +/ { + model = "PHYTEC phyBOARD-Mira DualLite/Solo Carrier-Board with NAND"; + compatible = "phytec,imx6dl-pbac06-nand", "phytec,imx6dl-pbac06", + "phytec,imx6qdl-pcm058", "fsl,imx6dl"; + + chosen { + stdout-path = &uart2; + }; +}; + +ðphy { + max-speed = <100>; +}; + +&fec { + status = "okay"; +}; + +&gpmi { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c_rtc { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; Index: sys/gnu/dts/arm/imx6dl-phytec-pfla02.dtsi =================================================================== --- sys/gnu/dts/arm/imx6dl-phytec-pfla02.dtsi +++ sys/gnu/dts/arm/imx6dl-phytec-pfla02.dtsi @@ -16,7 +16,7 @@ model = "Phytec phyFLEX-i.MX6 DualLite/Solo"; compatible = "phytec,imx6dl-pfla02", "fsl,imx6dl"; - memory { + memory@10000000 { reg = <0x10000000 0x20000000>; }; }; Index: sys/gnu/dts/arm/imx6dl-rex-basic.dts =================================================================== --- sys/gnu/dts/arm/imx6dl-rex-basic.dts +++ sys/gnu/dts/arm/imx6dl-rex-basic.dts @@ -16,7 +16,7 @@ model = "Rex Basic i.MX6 Dual Lite Board"; compatible = "rex,imx6dl-rex-basic", "fsl,imx6dl"; - memory { + memory@10000000 { reg = <0x10000000 0x20000000>; }; }; Index: sys/gnu/dts/arm/imx6dl-riotboard.dts =================================================================== --- sys/gnu/dts/arm/imx6dl-riotboard.dts +++ sys/gnu/dts/arm/imx6dl-riotboard.dts @@ -15,7 +15,7 @@ model = "RIoTboard i.MX6S"; compatible = "riot,imx6s-riotboard", "fsl,imx6dl"; - memory { + memory@10000000 { reg = <0x10000000 0x40000000>; }; Index: sys/gnu/dts/arm/imx6dl-ts4900.dts =================================================================== --- sys/gnu/dts/arm/imx6dl-ts4900.dts +++ sys/gnu/dts/arm/imx6dl-ts4900.dts @@ -46,4 +46,9 @@ / { model = "Technologic Systems i.MX6 Solo/DualLite TS-4900 (Default Device Tree)"; compatible = "technologic,imx6dl-ts4900", "fsl,imx6dl"; + + /* Will be filled by the bootloader */ + memory@10000000 { + reg = <0x10000000 0>; + }; }; Index: sys/gnu/dts/arm/imx6dl-ts7970.dts =================================================================== --- sys/gnu/dts/arm/imx6dl-ts7970.dts +++ sys/gnu/dts/arm/imx6dl-ts7970.dts @@ -47,4 +47,9 @@ / { model = "Technologic Systems i.MX6 Solo/DualLite TS-7970 (Default Device Tree)"; compatible = "technologic,imx6dl-ts7970", "fsl,imx6dl"; + + /* Will be filled by the bootloader */ + memory@10000000 { + reg = <0x10000000 0>; + }; }; Index: sys/gnu/dts/arm/imx6dl-wandboard-revb1.dts =================================================================== --- sys/gnu/dts/arm/imx6dl-wandboard-revb1.dts +++ sys/gnu/dts/arm/imx6dl-wandboard-revb1.dts @@ -16,7 +16,7 @@ model = "Wandboard i.MX6 Dual Lite Board rev B1"; compatible = "wand,imx6dl-wandboard", "fsl,imx6dl"; - memory { + memory@10000000 { reg = <0x10000000 0x40000000>; }; }; Index: sys/gnu/dts/arm/imx6dl-wandboard-revd1.dts =================================================================== --- sys/gnu/dts/arm/imx6dl-wandboard-revd1.dts +++ sys/gnu/dts/arm/imx6dl-wandboard-revd1.dts @@ -16,7 +16,7 @@ model = "Wandboard i.MX6 Dual Lite Board revD1"; compatible = "wand,imx6dl-wandboard", "fsl,imx6dl"; - memory { + memory@10000000 { reg = <0x10000000 0x40000000>; }; }; Index: sys/gnu/dts/arm/imx6dl-wandboard.dts =================================================================== --- sys/gnu/dts/arm/imx6dl-wandboard.dts +++ sys/gnu/dts/arm/imx6dl-wandboard.dts @@ -16,7 +16,7 @@ model = "Wandboard i.MX6 Dual Lite Board"; compatible = "wand,imx6dl-wandboard", "fsl,imx6dl"; - memory { + memory@10000000 { reg = <0x10000000 0x40000000>; }; }; Index: sys/gnu/dts/arm/imx6dl.dtsi =================================================================== --- sys/gnu/dts/arm/imx6dl.dtsi +++ sys/gnu/dts/arm/imx6dl.dtsi @@ -80,11 +80,6 @@ reg = <0x020f4000 0x4000>; interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; }; - - lcdif: lcdif@20f8000 { - reg = <0x020f8000 0x4000>; - interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; - }; }; aips2: aips-bus@2100000 { @@ -109,11 +104,6 @@ compatible = "fsl,imx-display-subsystem"; ports = <&ipu1_di0>, <&ipu1_di1>; }; - - gpu-subsystem { - compatible = "fsl,imx-gpu-subsystem"; - cores = <&gpu_2d>, <&gpu_3d>; - }; }; &gpio1 { Index: sys/gnu/dts/arm/imx6q-apf6dev.dts =================================================================== --- sys/gnu/dts/arm/imx6q-apf6dev.dts +++ sys/gnu/dts/arm/imx6q-apf6dev.dts @@ -54,7 +54,7 @@ model = "Armadeus APF6 Quad / Dual Module on APF6Dev Board"; compatible = "armadeus,imx6q-apf6dev", "armadeus,imx6q-apf6", "fsl,imx6q"; - memory { + memory@10000000 { reg = <0x10000000 0x40000000>; }; }; Index: sys/gnu/dts/arm/imx6q-arm2.dts =================================================================== --- sys/gnu/dts/arm/imx6q-arm2.dts +++ sys/gnu/dts/arm/imx6q-arm2.dts @@ -18,7 +18,7 @@ model = "Freescale i.MX6 Quad Armadillo2 Board"; compatible = "fsl,imx6q-arm2", "fsl,imx6q"; - memory { + memory@10000000 { reg = <0x10000000 0x80000000>; }; Index: sys/gnu/dts/arm/imx6q-ba16.dtsi =================================================================== --- sys/gnu/dts/arm/imx6q-ba16.dtsi +++ sys/gnu/dts/arm/imx6q-ba16.dtsi @@ -46,7 +46,7 @@ #include / { - memory { + memory@10000000 { reg = <0x10000000 0x40000000>; }; Index: sys/gnu/dts/arm/imx6q-bx50v3.dtsi =================================================================== --- sys/gnu/dts/arm/imx6q-bx50v3.dtsi +++ sys/gnu/dts/arm/imx6q-bx50v3.dtsi @@ -353,6 +353,14 @@ }; }; +&pmu { + secure-reg-access; +}; + +&usdhc2 { + status = "disabled"; +}; + &usdhc4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc4>; Index: sys/gnu/dts/arm/imx6q-cm-fx6.dts =================================================================== --- sys/gnu/dts/arm/imx6q-cm-fx6.dts +++ sys/gnu/dts/arm/imx6q-cm-fx6.dts @@ -50,7 +50,7 @@ model = "CompuLab CM-FX6"; compatible = "compulab,cm-fx6", "fsl,imx6q"; - memory { + memory@10000000 { reg = <0x10000000 0x80000000>; }; Index: sys/gnu/dts/arm/imx6q-dfi-fs700-m60.dts =================================================================== --- sys/gnu/dts/arm/imx6q-dfi-fs700-m60.dts +++ sys/gnu/dts/arm/imx6q-dfi-fs700-m60.dts @@ -20,4 +20,9 @@ / { model = "DFI FS700-M60-6QD i.MX6qd Q7 Board"; compatible = "dfi,fs700-m60-6qd", "dfi,fs700e-m60", "fsl,imx6q"; + + /* Will be filled by the bootloader */ + memory@10000000 { + reg = <0x10000000 0>; + }; }; Index: sys/gnu/dts/arm/imx6q-display5.dtsi =================================================================== --- sys/gnu/dts/arm/imx6q-display5.dtsi +++ sys/gnu/dts/arm/imx6q-display5.dtsi @@ -47,7 +47,7 @@ model = "Liebherr (LWN) display5 i.MX6 Quad Board"; compatible = "lwn,display5", "fsl,imx6q"; - memory { + memory@10000000 { reg = <0x10000000 0x40000000>; }; Index: sys/gnu/dts/arm/imx6q-dmo-edmqmx6.dts =================================================================== --- sys/gnu/dts/arm/imx6q-dmo-edmqmx6.dts +++ sys/gnu/dts/arm/imx6q-dmo-edmqmx6.dts @@ -29,7 +29,7 @@ stmpe-i2c1 = &stmpe2; }; - memory { + memory@10000000 { reg = <0x10000000 0x80000000>; }; Index: sys/gnu/dts/arm/imx6q-dms-ba16.dts =================================================================== --- /dev/null +++ sys/gnu/dts/arm/imx6q-dms-ba16.dts @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include "imx6q-ba16.dtsi" + +/ { + model = "Advantech DMS-BA16"; + compatible = "advantech,imx6q-dms-ba16", "advantech,imx6q-ba16", "fsl,imx6q"; + + reg_usb_otg_vbus: regulator-usbotgvbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotgvbus>; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sys_mclk: clock-sys-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <22000000>; + }; + + sound { + compatible = "fsl,imx6q-ba16-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6q-ba16-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + }; +}; + +&ecspi5 { + cs-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi5>; + status = "okay"; + + m25_eeprom: m25p80@0 { + compatible = "atmel,at25256B", "atmel,at25"; + spi-max-frequency = <20000000>; + size = <0x8000>; + pagesize = <64>; + reg = <0>; + address-width = <16>; + }; +}; + +&iomuxc { + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x1b0b0 + MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x1b0b0 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 + >; + }; + + pinctrl_usbotgvbus: usbotgvbusgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0 + >; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&sys_mclk>; + lrclk-strength = <0x3>; + VDDA-supply = <®_1p8v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&sata { + fsl,no-spread-spectrum; + fsl,transmit-atten-16ths = <12>; + fsl,transmit-boost-mdB = <3330>; + fsl,transmit-level-mV = <1133>; + fsl,receive-dpll-mode = <1>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + dr_mode = "otg"; + disable-over-current; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; Index: sys/gnu/dts/arm/imx6q-evi.dts =================================================================== --- sys/gnu/dts/arm/imx6q-evi.dts +++ sys/gnu/dts/arm/imx6q-evi.dts @@ -50,7 +50,7 @@ model = "Uniwest Evi"; compatible = "uniwest,imx6q-evi", "fsl,imx6q"; - memory { + memory@10000000 { reg = <0x10000000 0x40000000>; }; Index: sys/gnu/dts/arm/imx6q-gk802.dts =================================================================== --- sys/gnu/dts/arm/imx6q-gk802.dts +++ sys/gnu/dts/arm/imx6q-gk802.dts @@ -18,7 +18,7 @@ stdout-path = &uart4; }; - memory { + memory@10000000 { reg = <0x10000000 0x40000000>; }; Index: sys/gnu/dts/arm/imx6q-gw5400-a.dts =================================================================== --- sys/gnu/dts/arm/imx6q-gw5400-a.dts +++ sys/gnu/dts/arm/imx6q-gw5400-a.dts @@ -60,7 +60,7 @@ }; }; - memory { + memory@10000000 { reg = <0x10000000 0x40000000>; }; Index: sys/gnu/dts/arm/imx6q-h100.dts =================================================================== --- sys/gnu/dts/arm/imx6q-h100.dts +++ sys/gnu/dts/arm/imx6q-h100.dts @@ -49,6 +49,11 @@ model = "Auvidea H100"; compatible = "auvidea,h100", "fsl,imx6q"; + /* Will be filled by the bootloader */ + memory@10000000 { + reg = <0x10000000 0>; + }; + aliases { rtc0 = &rtc; rtc1 = &snvs_rtc; @@ -161,7 +166,7 @@ status = "okay"; eeprom: 24c02@51 { - compatible = "microchip,24c02", "at24"; + compatible = "microchip,24c02", "atmel,24c02"; reg = <0x51>; }; Index: sys/gnu/dts/arm/imx6q-marsboard.dts =================================================================== --- sys/gnu/dts/arm/imx6q-marsboard.dts +++ sys/gnu/dts/arm/imx6q-marsboard.dts @@ -47,7 +47,7 @@ model = "Embest MarS Board i.MX6Dual"; compatible = "embest,imx6q-marsboard", "fsl,imx6q"; - memory { + memory@10000000 { reg = <0x10000000 0x40000000>; }; Index: sys/gnu/dts/arm/imx6q-mccmon6.dts =================================================================== --- sys/gnu/dts/arm/imx6q-mccmon6.dts +++ sys/gnu/dts/arm/imx6q-mccmon6.dts @@ -19,7 +19,7 @@ model = "Liebherr (LWN) monitor6 i.MX6 Quad Board"; compatible = "lwn,mccmon6", "fsl,imx6q"; - memory { + memory@10000000 { reg = <0x10000000 0x80000000>; }; Index: sys/gnu/dts/arm/imx6q-novena.dts =================================================================== --- sys/gnu/dts/arm/imx6q-novena.dts +++ sys/gnu/dts/arm/imx6q-novena.dts @@ -55,6 +55,11 @@ model = "Kosagi Novena Dual/Quad"; compatible = "kosagi,imx6q-novena", "fsl,imx6q"; + /* Will be filled by the bootloader */ + memory@10000000 { + reg = <0x10000000 0>; + }; + chosen { stdout-path = &uart2; }; Index: sys/gnu/dts/arm/imx6q-phytec-mira-rdk-emmc.dts =================================================================== --- /dev/null +++ sys/gnu/dts/arm/imx6q-phytec-mira-rdk-emmc.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 PHYTEC Messtechnik GmbH + * Author: Christian Hemp + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-phytec-phycore-som.dtsi" +#include "imx6qdl-phytec-mira.dtsi" + +/ { + model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with eMMC"; + compatible = "phytec,imx6q-pbac06-emmc", "phytec,imx6q-pbac06", + "phytec,imx6qdl-pcm058", "fsl,imx6q"; + + chosen { + stdout-path = &uart2; + }; +}; + +&can1 { + status = "okay"; +}; + +&fec { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c_rtc { + status = "okay"; +}; + +&m25p80 { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; + +&usdhc4 { + status = "okay"; +}; Index: sys/gnu/dts/arm/imx6q-phytec-mira-rdk-nand.dts =================================================================== --- /dev/null +++ sys/gnu/dts/arm/imx6q-phytec-mira-rdk-nand.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 PHYTEC Messtechnik GmbH + * Author: Christian Hemp + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-phytec-phycore-som.dtsi" +#include "imx6qdl-phytec-mira.dtsi" + +/ { + model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with NAND"; + compatible = "phytec,imx6q-pbac06-nand", "phytec,imx6q-pbac06", + "phytec,imx6qdl-pcm058", "fsl,imx6q"; + + chosen { + stdout-path = &uart2; + }; +}; + +&can1 { + status = "okay"; +}; + +&fec { + status = "okay"; +}; + +&gpmi { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c_rtc { + status = "okay"; +}; + +&m25p80 { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; Index: sys/gnu/dts/arm/imx6q-phytec-pfla02.dtsi =================================================================== --- sys/gnu/dts/arm/imx6q-phytec-pfla02.dtsi +++ sys/gnu/dts/arm/imx6q-phytec-pfla02.dtsi @@ -16,7 +16,7 @@ model = "Phytec phyFLEX-i.MX6 Quad"; compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; - memory { + memory@10000000 { reg = <0x10000000 0x80000000>; }; }; Index: sys/gnu/dts/arm/imx6q-pistachio.dts =================================================================== --- sys/gnu/dts/arm/imx6q-pistachio.dts +++ sys/gnu/dts/arm/imx6q-pistachio.dts @@ -56,7 +56,7 @@ stdout-path = &uart4; }; - memory: memory { + memory@10000000 { reg = <0x10000000 0x80000000>; }; Index: sys/gnu/dts/arm/imx6q-rex-pro.dts =================================================================== --- sys/gnu/dts/arm/imx6q-rex-pro.dts +++ sys/gnu/dts/arm/imx6q-rex-pro.dts @@ -16,7 +16,7 @@ model = "Rex Pro i.MX6 Quad Board"; compatible = "rex,imx6q-rex-pro", "fsl,imx6q"; - memory { + memory@10000000 { reg = <0x10000000 0x80000000>; }; }; Index: sys/gnu/dts/arm/imx6q-sbc6x.dts =================================================================== --- sys/gnu/dts/arm/imx6q-sbc6x.dts +++ sys/gnu/dts/arm/imx6q-sbc6x.dts @@ -12,7 +12,7 @@ model = "MicroSys sbc6x board"; compatible = "microsys,sbc6x", "fsl,imx6q"; - memory { + memory@10000000 { reg = <0x10000000 0x80000000>; }; }; Index: sys/gnu/dts/arm/imx6q-tbs2910.dts =================================================================== --- sys/gnu/dts/arm/imx6q-tbs2910.dts +++ sys/gnu/dts/arm/imx6q-tbs2910.dts @@ -59,7 +59,7 @@ stdout-path = &uart1; }; - memory { + memory@10000000 { reg = <0x10000000 0x80000000>; }; Index: sys/gnu/dts/arm/imx6q-ts4900.dts =================================================================== --- sys/gnu/dts/arm/imx6q-ts4900.dts +++ sys/gnu/dts/arm/imx6q-ts4900.dts @@ -46,6 +46,11 @@ / { model = "Technologic Systems i.MX6 Quad TS-4900 (Default Device Tree)"; compatible = "technologic,imx6q-ts4900", "fsl,imx6q"; + + /* Will be filled by the bootloader */ + memory@10000000 { + reg = <0x10000000 0>; + }; }; &sata { Index: sys/gnu/dts/arm/imx6q-ts7970.dts =================================================================== --- sys/gnu/dts/arm/imx6q-ts7970.dts +++ sys/gnu/dts/arm/imx6q-ts7970.dts @@ -47,6 +47,11 @@ / { model = "Technologic Systems i.MX6 Quad TS-7970 (Default Device Tree)"; compatible = "technologic,imx6q-ts7970", "fsl,imx6q"; + + /* Will be filled by the bootloader */ + memory@10000000 { + reg = <0x10000000 0>; + }; }; &sata { Index: sys/gnu/dts/arm/imx6q-wandboard-revb1.dts =================================================================== --- sys/gnu/dts/arm/imx6q-wandboard-revb1.dts +++ sys/gnu/dts/arm/imx6q-wandboard-revb1.dts @@ -16,7 +16,7 @@ model = "Wandboard i.MX6 Quad Board rev B1"; compatible = "wand,imx6q-wandboard", "fsl,imx6q"; - memory { + memory@10000000 { reg = <0x10000000 0x80000000>; }; }; Index: sys/gnu/dts/arm/imx6q-wandboard-revd1.dts =================================================================== --- sys/gnu/dts/arm/imx6q-wandboard-revd1.dts +++ sys/gnu/dts/arm/imx6q-wandboard-revd1.dts @@ -16,7 +16,7 @@ model = "Wandboard i.MX6 Quad Board revD1"; compatible = "wand,imx6q-wandboard", "fsl,imx6q"; - memory { + memory@10000000 { reg = <0x10000000 0x80000000>; }; }; Index: sys/gnu/dts/arm/imx6q-wandboard.dts =================================================================== --- sys/gnu/dts/arm/imx6q-wandboard.dts +++ sys/gnu/dts/arm/imx6q-wandboard.dts @@ -16,7 +16,7 @@ model = "Wandboard i.MX6 Quad Board"; compatible = "wand,imx6q-wandboard", "fsl,imx6q"; - memory { + memory@10000000 { reg = <0x10000000 0x80000000>; }; }; Index: sys/gnu/dts/arm/imx6q-zii-rdu2.dts =================================================================== --- sys/gnu/dts/arm/imx6q-zii-rdu2.dts +++ sys/gnu/dts/arm/imx6q-zii-rdu2.dts @@ -47,4 +47,9 @@ / { model = "ZII RDU2 Board"; compatible = "zii,imx6q-zii-rdu2", "fsl,imx6q"; + + /* Will be filled by the bootloader */ + memory@10000000 { + reg = <0x10000000 0>; + }; }; Index: sys/gnu/dts/arm/imx6q.dtsi =================================================================== --- sys/gnu/dts/arm/imx6q.dtsi +++ sys/gnu/dts/arm/imx6q.dtsi @@ -215,11 +215,6 @@ compatible = "fsl,imx-display-subsystem"; ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>; }; - - gpu-subsystem { - compatible = "fsl,imx-gpu-subsystem"; - cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>; - }; }; &gpio1 { Index: sys/gnu/dts/arm/imx6qdl-apalis.dtsi =================================================================== --- sys/gnu/dts/arm/imx6qdl-apalis.dtsi +++ sys/gnu/dts/arm/imx6qdl-apalis.dtsi @@ -47,6 +47,11 @@ model = "Toradex Apalis iMX6Q/D Module"; compatible = "toradex,apalis_imx6q", "fsl,imx6q"; + /* Will be filled by the bootloader */ + memory@10000000 { + reg = <0x10000000 0>; + }; + backlight: backlight { compatible = "pwm-backlight"; pinctrl-names = "default"; Index: sys/gnu/dts/arm/imx6qdl-cubox-i.dtsi =================================================================== --- sys/gnu/dts/arm/imx6qdl-cubox-i.dtsi +++ sys/gnu/dts/arm/imx6qdl-cubox-i.dtsi @@ -42,6 +42,11 @@ #include / { + /* Will be filled by the bootloader */ + memory@10000000 { + reg = <0x10000000 0>; + }; + ir_recv: ir-receiver { compatible = "gpio-ir-receiver"; gpios = <&gpio3 9 1>; Index: sys/gnu/dts/arm/imx6qdl-gw51xx.dtsi =================================================================== --- sys/gnu/dts/arm/imx6qdl-gw51xx.dtsi +++ sys/gnu/dts/arm/imx6qdl-gw51xx.dtsi @@ -44,7 +44,7 @@ }; }; - memory { + memory@10000000 { reg = <0x10000000 0x20000000>; }; Index: sys/gnu/dts/arm/imx6qdl-gw52xx.dtsi =================================================================== --- sys/gnu/dts/arm/imx6qdl-gw52xx.dtsi +++ sys/gnu/dts/arm/imx6qdl-gw52xx.dtsi @@ -59,7 +59,7 @@ }; }; - memory { + memory@10000000 { reg = <0x10000000 0x20000000>; }; Index: sys/gnu/dts/arm/imx6qdl-gw53xx.dtsi =================================================================== --- sys/gnu/dts/arm/imx6qdl-gw53xx.dtsi +++ sys/gnu/dts/arm/imx6qdl-gw53xx.dtsi @@ -59,7 +59,7 @@ }; }; - memory { + memory@10000000 { reg = <0x10000000 0x40000000>; }; Index: sys/gnu/dts/arm/imx6qdl-gw54xx.dtsi =================================================================== --- sys/gnu/dts/arm/imx6qdl-gw54xx.dtsi +++ sys/gnu/dts/arm/imx6qdl-gw54xx.dtsi @@ -59,7 +59,7 @@ }; }; - memory { + memory@10000000 { reg = <0x10000000 0x40000000>; }; Index: sys/gnu/dts/arm/imx6qdl-gw551x.dtsi =================================================================== --- sys/gnu/dts/arm/imx6qdl-gw551x.dtsi +++ sys/gnu/dts/arm/imx6qdl-gw551x.dtsi @@ -74,7 +74,7 @@ }; }; - memory { + memory@10000000 { reg = <0x10000000 0x20000000>; }; Index: sys/gnu/dts/arm/imx6qdl-gw552x.dtsi =================================================================== --- sys/gnu/dts/arm/imx6qdl-gw552x.dtsi +++ sys/gnu/dts/arm/imx6qdl-gw552x.dtsi @@ -51,7 +51,7 @@ }; }; - memory { + memory@10000000 { reg = <0x10000000 0x20000000>; }; Index: sys/gnu/dts/arm/imx6qdl-gw553x.dtsi =================================================================== --- sys/gnu/dts/arm/imx6qdl-gw553x.dtsi +++ sys/gnu/dts/arm/imx6qdl-gw553x.dtsi @@ -80,7 +80,7 @@ }; }; - memory { + memory@10000000 { reg = <0x10000000 0x20000000>; }; Index: sys/gnu/dts/arm/imx6qdl-gw560x.dtsi =================================================================== --- sys/gnu/dts/arm/imx6qdl-gw560x.dtsi +++ sys/gnu/dts/arm/imx6qdl-gw560x.dtsi @@ -288,6 +288,7 @@ sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_1p8v>; VDDIO-supply = <®_3p3v>; Index: sys/gnu/dts/arm/imx6qdl-gw5903.dtsi =================================================================== --- sys/gnu/dts/arm/imx6qdl-gw5903.dtsi +++ sys/gnu/dts/arm/imx6qdl-gw5903.dtsi @@ -83,7 +83,7 @@ }; }; - memory { + memory@10000000 { reg = <0x10000000 0x40000000>; }; Index: sys/gnu/dts/arm/imx6qdl-gw5904.dtsi =================================================================== --- sys/gnu/dts/arm/imx6qdl-gw5904.dtsi +++ sys/gnu/dts/arm/imx6qdl-gw5904.dtsi @@ -93,7 +93,7 @@ }; }; - memory { + memory@10000000 { reg = <0x10000000 0x40000000>; }; Index: sys/gnu/dts/arm/imx6qdl-hummingboard.dtsi =================================================================== --- sys/gnu/dts/arm/imx6qdl-hummingboard.dtsi +++ sys/gnu/dts/arm/imx6qdl-hummingboard.dtsi @@ -40,6 +40,11 @@ */ / { + /* Will be filled by the bootloader */ + memory@10000000 { + reg = <0x10000000 0>; + }; + chosen { stdout-path = &uart1; }; @@ -239,10 +244,9 @@ pinctrl_hummingboard_usbotg_id: hummingboard-usbotg-id { /* - * Similar to pinctrl_usbotg_2, but we want it - * pulled down for a fixed host connection. + * We want it pulled down for a fixed host connection. */ - fsl,pins = ; + fsl,pins = ; }; pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus { Index: sys/gnu/dts/arm/imx6qdl-hummingboard2.dtsi =================================================================== --- sys/gnu/dts/arm/imx6qdl-hummingboard2.dtsi +++ sys/gnu/dts/arm/imx6qdl-hummingboard2.dtsi @@ -40,6 +40,11 @@ */ / { + /* Will be filled by the bootloader */ + memory@10000000 { + reg = <0x10000000 0>; + }; + chosen { stdout-path = &uart1; }; @@ -191,6 +196,7 @@ sgtl5000: codec@a { clocks = <&clks IMX6QDL_CLK_CKO>; compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hummingboard2_sgtl5000>; reg = <0x0a>; @@ -409,8 +415,7 @@ pinctrl_hummingboard2_usbotg_id: hummingboard2-usbotg-id { /* - * Similar to pinctrl_usbotg_2, but we want it - * pulled down for a fixed host connection. + * We want it pulled down for a fixed host connection. */ fsl,pins = ; }; Index: sys/gnu/dts/arm/imx6qdl-icore-rqs.dtsi =================================================================== --- sys/gnu/dts/arm/imx6qdl-icore-rqs.dtsi +++ sys/gnu/dts/arm/imx6qdl-icore-rqs.dtsi @@ -44,7 +44,7 @@ #include / { - memory { + memory@10000000 { reg = <0x10000000 0x80000000>; }; @@ -200,7 +200,11 @@ status = "okay"; mdio { - eth_phy: ethernet-phy { + #address-cells = <1>; + #size-cells = <0>; + + eth_phy: ethernet-phy@0 { + reg = <0x0>; rxc-skew-ps = <1140>; txc-skew-ps = <1140>; txen-skew-ps = <600>; Index: sys/gnu/dts/arm/imx6qdl-icore.dtsi =================================================================== --- sys/gnu/dts/arm/imx6qdl-icore.dtsi +++ sys/gnu/dts/arm/imx6qdl-icore.dtsi @@ -45,7 +45,7 @@ #include / { - memory { + memory@10000000 { reg = <0x10000000 0x80000000>; }; Index: sys/gnu/dts/arm/imx6qdl-nit6xlite.dtsi =================================================================== --- sys/gnu/dts/arm/imx6qdl-nit6xlite.dtsi +++ sys/gnu/dts/arm/imx6qdl-nit6xlite.dtsi @@ -46,7 +46,7 @@ stdout-path = &uart2; }; - memory { + memory@10000000 { reg = <0x10000000 0x20000000>; }; Index: sys/gnu/dts/arm/imx6qdl-nitrogen6_max.dtsi =================================================================== --- sys/gnu/dts/arm/imx6qdl-nitrogen6_max.dtsi +++ sys/gnu/dts/arm/imx6qdl-nitrogen6_max.dtsi @@ -46,7 +46,7 @@ stdout-path = &uart2; }; - memory { + memory@10000000 { reg = <0x10000000 0xF0000000>; }; Index: sys/gnu/dts/arm/imx6qdl-nitrogen6_som2.dtsi =================================================================== --- sys/gnu/dts/arm/imx6qdl-nitrogen6_som2.dtsi +++ sys/gnu/dts/arm/imx6qdl-nitrogen6_som2.dtsi @@ -46,7 +46,7 @@ stdout-path = &uart2; }; - memory { + memory@10000000 { reg = <0x10000000 0x40000000>; }; Index: sys/gnu/dts/arm/imx6qdl-nitrogen6x.dtsi =================================================================== --- sys/gnu/dts/arm/imx6qdl-nitrogen6x.dtsi +++ sys/gnu/dts/arm/imx6qdl-nitrogen6x.dtsi @@ -48,7 +48,7 @@ stdout-path = &uart2; }; - memory { + memory@10000000 { reg = <0x10000000 0x40000000>; }; Index: sys/gnu/dts/arm/imx6qdl-phytec-mira.dtsi =================================================================== --- /dev/null +++ sys/gnu/dts/arm/imx6qdl-phytec-mira.dtsi @@ -0,0 +1,390 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 PHYTEC Messtechnik GmbH + * Author: Christian Hemp + */ + + +/ { + aliases { + rtc0 = &i2c_rtc; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_backlight>; + pwms = <&pwm1 0 5000000>; + status = "okay"; + }; + + gpio_leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpioleds>; + status = "disabled"; + + red { + label = "phyboard-mira:red"; + gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; + }; + + green { + label = "phyboard-mira:green"; + gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; + }; + + blue { + label = "phyboard-mira:blue"; + gpios = <&gpio5 24 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + }; + + reg_backlight: regulator-backlight { + compatible = "regulator-fixed"; + regulator-name = "backlight_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_en_switch: regulator-en-switch { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_en_switch>; + regulator-name = "Enable Switch"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio3 4 GPIO_ACTIVE_HIGH>; + regulator-always-on; + }; + + reg_flexcan1: regulator-flexcan1 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_en>; + regulator-name = "flexcan1-reg"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_panel: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "panel-power-supply"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + reg_pcie: regulator-pcie { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_reg>; + regulator-name = "mPCIe_1V5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&gpio3 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_h1_vbus: usb-h1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_vbus>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usbotg_vbus: usbotg-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + panel { + compatible = "auo,g104sn02"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel_en>; + power-supply = <®_panel>; + enable-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_flexcan1>; + status = "disabled"; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmicec>; + ddc-i2c-bus = <&i2c2>; + status = "disabled"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <400000>; + status = "disabled"; + + stmpe: touchctrl@44 { + compatible = "st,stmpe811"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_stmpe>; + reg = <0x44>; + interrupt-parent = <&gpio7>; + interrupts = <12 IRQ_TYPE_NONE>; + status = "disabled"; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + st,sample-time = <4>; + st,mod-12b = <1>; + st,ref-sel = <0>; + st,adc-freq = <1>; + st,ave-ctrl = <1>; + st,touch-det-delay = <2>; + st,settling = <2>; + st,fraction-z = <7>; + st,i-drive = <1>; + }; + }; + + i2c_rtc: rtc@68 { + compatible = "microcrystal,rv4162"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc_int>; + reg = <0x68>; + interrupt-parent = <&gpio7>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "disabled"; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "disabled"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio2 25 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie>; + status = "disabled"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "disabled"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + disable-over-current; + status = "disabled"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + vbus-supply = <®_usbotg_vbus>; + disable-over-current; + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio6 31 GPIO_ACTIVE_LOW>; + no-1-8-v; + status = "disabled"; +}; + +&iomuxc { + pinctrl_panel_en: panelen1grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0xb0b1 + >; + }; + + pinctrl_en_switch: enswitchgrp { + fsl,pins = < + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0xb0b1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 + >; + }; + + pinctrl_flexcan1_en: flexcan1engrp { + fsl,pins = < + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0xb0b1 + >; + }; + + pinctrl_gpioleds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x1b0b0 + >; + }; + + pinctrl_hdmicec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0xb0b1 + >; + }; + + pinctrl_pcie_reg: pciereggrp { + fsl,pins = < + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0xb0b1 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_rtc_int: rtcintgrp { + fsl,pins = < + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 + >; + }; + + pinctrl_stmpe: stmpegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1_vbus: usbh1vbusgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0xb0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usbotg_vbus: usbotgvbusgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0xb0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb0b1 /* CD */ + >; + }; +}; Index: sys/gnu/dts/arm/imx6qdl-phytec-pbab01.dtsi =================================================================== --- sys/gnu/dts/arm/imx6qdl-phytec-pbab01.dtsi +++ sys/gnu/dts/arm/imx6qdl-phytec-pbab01.dtsi @@ -13,7 +13,7 @@ / { chosen { - linux,stdout-path = &uart4; + stdout-path = &uart4; }; regulators { Index: sys/gnu/dts/arm/imx6qdl-phytec-pfla02.dtsi =================================================================== --- sys/gnu/dts/arm/imx6qdl-phytec-pfla02.dtsi +++ sys/gnu/dts/arm/imx6qdl-phytec-pfla02.dtsi @@ -15,7 +15,7 @@ model = "Phytec phyFLEX-i.MX6 Quad"; compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; - memory { + memory@10000000 { reg = <0x10000000 0x80000000>; }; Index: sys/gnu/dts/arm/imx6qdl-phytec-phycore-som.dtsi =================================================================== --- /dev/null +++ sys/gnu/dts/arm/imx6qdl-phytec-phycore-som.dtsi @@ -0,0 +1,279 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 PHYTEC Messtechnik GmbH + * Author: Christian Hemp + */ + +#include + +/ { + aliases { + rtc1 = &da9062_rtc; + rtc2 = &snvs_rtc; + }; + + /* + * Set the minimum memory size here and + * let the bootloader set the real size. + */ + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x8000000>; + }; + + gpio_leds_som: somleds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpioleds_som>; + + som-led-green { + label = "phycore:green"; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + status = "okay"; + + m25p80: flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + status = "disabled"; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; + phy-supply = <&vdd_eth_io>; + phy-reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + status = "disabled"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@3 { + reg = <3>; + txc-skew-ps = <1680>; + rxc-skew-ps = <1860>; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "disabled"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <400000>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + + pmic@58 { + compatible = "dlg,da9062"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + reg = <0x58>; + interrupt-parent = <&gpio1>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + + da9062_rtc: rtc { + compatible = "dlg,da9062-rtc"; + }; + + watchdog { + compatible = "dlg,da9062-watchdog"; + }; + + regulators { + vdd_arm: buck1 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <730000>; + regulator-max-microvolt = <1380000>; + regulator-always-on; + }; + + vdd_soc: buck2 { + regulator-name = "vdd_soc"; + regulator-min-microvolt = <730000>; + regulator-max-microvolt = <1380000>; + regulator-always-on; + }; + + vdd_ddr3_1p5: buck3 { + regulator-name = "vdd_ddr3"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + vdd_eth_1p2: buck4 { + regulator-name = "vdd_eth"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd_snvs: ldo1 { + regulator-name = "vdd_snvs"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vdd_high: ldo2 { + regulator-name = "vdd_high"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vdd_eth_io: ldo3 { + regulator-name = "vdd_eth_io"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + vdd_emmc_1p8: ldo4 { + regulator-name = "vdd_emmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; +}; + +®_arm { + vin-supply = <&vdd_arm>; +}; + +®_pu { + vin-supply = <&vdd_soc>; +}; + +®_soc { + vin-supply = <&vdd_soc>; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + vmmc-supply = <&vdd_emmc_1p8>; + status = "disabled"; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0 + >; + }; + + pinctrl_gpioleds_som: gpioledssomgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1 + MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; +}; Index: sys/gnu/dts/arm/imx6qdl-rex.dtsi =================================================================== --- sys/gnu/dts/arm/imx6qdl-rex.dtsi +++ sys/gnu/dts/arm/imx6qdl-rex.dtsi @@ -137,7 +137,7 @@ status = "okay"; eeprom@57 { - compatible = "at,24c02"; + compatible = "atmel,24c02"; reg = <0x57>; }; }; Index: sys/gnu/dts/arm/imx6qdl-sabreauto.dtsi =================================================================== --- sys/gnu/dts/arm/imx6qdl-sabreauto.dtsi +++ sys/gnu/dts/arm/imx6qdl-sabreauto.dtsi @@ -13,7 +13,7 @@ #include / { - memory { + memory@10000000 { reg = <0x10000000 0x80000000>; }; Index: sys/gnu/dts/arm/imx6qdl-sabrelite.dtsi =================================================================== --- sys/gnu/dts/arm/imx6qdl-sabrelite.dtsi +++ sys/gnu/dts/arm/imx6qdl-sabrelite.dtsi @@ -49,7 +49,7 @@ stdout-path = &uart2; }; - memory { + memory@10000000 { reg = <0x10000000 0x40000000>; }; Index: sys/gnu/dts/arm/imx6qdl-sabresd.dtsi =================================================================== --- sys/gnu/dts/arm/imx6qdl-sabresd.dtsi +++ sys/gnu/dts/arm/imx6qdl-sabresd.dtsi @@ -19,7 +19,7 @@ stdout-path = &uart1; }; - memory { + memory@10000000 { reg = <0x10000000 0x40000000>; }; Index: sys/gnu/dts/arm/imx6qdl-tx6.dtsi =================================================================== --- sys/gnu/dts/arm/imx6qdl-tx6.dtsi +++ sys/gnu/dts/arm/imx6qdl-tx6.dtsi @@ -61,8 +61,8 @@ sdhc1 = &usdhc2; }; - memory { - reg = <0 0>; /* will be filled by U-Boot */ + memory@10000000 { + reg = <0x10000000 0>; /* will be filled by U-Boot */ }; clocks { Index: sys/gnu/dts/arm/imx6qdl-udoo.dtsi =================================================================== --- sys/gnu/dts/arm/imx6qdl-udoo.dtsi +++ sys/gnu/dts/arm/imx6qdl-udoo.dtsi @@ -35,7 +35,7 @@ pinctrl-names = "default"; }; - memory { + memory@10000000 { reg = <0x10000000 0x40000000>; }; Index: sys/gnu/dts/arm/imx6qdl-var-dart.dtsi =================================================================== --- sys/gnu/dts/arm/imx6qdl-var-dart.dtsi +++ sys/gnu/dts/arm/imx6qdl-var-dart.dtsi @@ -10,7 +10,7 @@ #include / { - memory { + memory@10000000 { reg = <0x10000000 0x40000000>; }; Index: sys/gnu/dts/arm/imx6qdl-zii-rdu2.dtsi =================================================================== --- sys/gnu/dts/arm/imx6qdl-zii-rdu2.dtsi +++ sys/gnu/dts/arm/imx6qdl-zii-rdu2.dtsi @@ -305,6 +305,15 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4>; status = "okay"; + + rave-sp { + compatible = "zii,rave-sp-rdu2"; + current-speed = <1000000>; + + watchdog { + compatible = "zii,rave-sp-watchdog"; + }; + }; }; &ecspi1 { @@ -498,7 +507,7 @@ }; eeprom@54 { - compatible = "at,24c128"; + compatible = "atmel,24c128"; reg = <0x54>; }; @@ -602,6 +611,8 @@ wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; vmmc-supply = <®_3p3v_sd>; vqmmc-supply = <®_3p3v>; + no-1-8-v; + no-sdio; status = "okay"; }; @@ -613,6 +624,8 @@ wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; vmmc-supply = <®_3p3v_sd>; vqmmc-supply = <®_3p3v>; + no-1-8-v; + no-sdio; status = "okay"; }; @@ -622,7 +635,10 @@ bus-width = <8>; vmmc-supply = <®_3p3v>; vqmmc-supply = <®_3p3v>; + no-1-8-v; non-removable; + no-sdio; + no-sd; status = "okay"; }; @@ -805,6 +821,10 @@ }; }; +&wdog1 { + status = "disabled"; +}; + &iomuxc { pinctrl_accel: accelgrp { fsl,pins = < Index: sys/gnu/dts/arm/imx6qdl.dtsi =================================================================== --- sys/gnu/dts/arm/imx6qdl.dtsi +++ sys/gnu/dts/arm/imx6qdl.dtsi @@ -23,7 +23,7 @@ * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; reg = <0 0>; }; + memory { device_type = "memory"; }; aliases { ethernet0 = &fec; @@ -143,7 +143,7 @@ }; }; - pmu { + pmu: pmu { compatible = "arm,cortex-a9-pmu"; interrupt-parent = <&gpc>; interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; Index: sys/gnu/dts/arm/imx6qp-phytec-mira-rdk-nand.dts =================================================================== --- /dev/null +++ sys/gnu/dts/arm/imx6qp-phytec-mira-rdk-nand.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 PHYTEC Messtechnik GmbH + * Author: Enrico Scholz + */ + +/dts-v1/; +#include "imx6qp.dtsi" +#include "imx6qdl-phytec-phycore-som.dtsi" +#include "imx6qdl-phytec-mira.dtsi" + +/ { + model = "PHYTEC phyBOARD-Mira QuadPlus Carrier-Board with NAND"; + compatible = "phytec,imx6qp-pbac06-nand", "phytec,imx6qp-pbac06", + "phytec,imx6qdl-pcm058", "fsl,imx6qp"; + + chosen { + stdout-path = &uart2; + }; +}; + +&can1 { + status = "okay"; +}; + +&fec { + status = "okay"; +}; + +&gpmi { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c_rtc { + status = "okay"; +}; + +&m25p80 { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; Index: sys/gnu/dts/arm/imx6qp-wandboard-revd1.dts =================================================================== --- sys/gnu/dts/arm/imx6qp-wandboard-revd1.dts +++ sys/gnu/dts/arm/imx6qp-wandboard-revd1.dts @@ -16,7 +16,7 @@ model = "Wandboard i.MX6 QuadPlus Board revD1"; compatible = "wand,imx6qp-wandboard", "fsl,imx6qp"; - memory { + memory@10000000 { reg = <0x10000000 0x80000000>; }; }; Index: sys/gnu/dts/arm/imx6qp-zii-rdu2.dts =================================================================== --- sys/gnu/dts/arm/imx6qp-zii-rdu2.dts +++ sys/gnu/dts/arm/imx6qp-zii-rdu2.dts @@ -47,4 +47,9 @@ / { model = "ZII RDU2+ Board"; compatible = "zii,imx6qp-zii-rdu2", "fsl,imx6qp"; + + /* Will be filled by the bootloader */ + memory@10000000 { + reg = <0x10000000 0>; + }; }; Index: sys/gnu/dts/arm/imx6sl-evk.dts =================================================================== --- sys/gnu/dts/arm/imx6sl-evk.dts +++ sys/gnu/dts/arm/imx6sl-evk.dts @@ -16,7 +16,7 @@ model = "Freescale i.MX6 SoloLite EVK Board"; compatible = "fsl,imx6sl-evk", "fsl,imx6sl"; - memory { + memory@80000000 { reg = <0x80000000 0x40000000>; }; Index: sys/gnu/dts/arm/imx6sl-warp.dts =================================================================== --- sys/gnu/dts/arm/imx6sl-warp.dts +++ sys/gnu/dts/arm/imx6sl-warp.dts @@ -54,7 +54,7 @@ model = "WaRP Board"; compatible = "warp,imx6sl-warp", "fsl,imx6sl"; - memory { + memory@80000000 { reg = <0x80000000 0x20000000>; }; Index: sys/gnu/dts/arm/imx6sl.dtsi =================================================================== --- sys/gnu/dts/arm/imx6sl.dtsi +++ sys/gnu/dts/arm/imx6sl.dtsi @@ -21,7 +21,7 @@ * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; reg = <0 0>; }; + memory { device_type = "memory"; }; aliases { ethernet0 = &fec; Index: sys/gnu/dts/arm/imx6sx-nitrogen6sx.dts =================================================================== --- sys/gnu/dts/arm/imx6sx-nitrogen6sx.dts +++ sys/gnu/dts/arm/imx6sx-nitrogen6sx.dts @@ -52,7 +52,7 @@ t_lcd = &t_lcd; }; - memory { + memory@80000000 { reg = <0x80000000 0x40000000>; }; Index: sys/gnu/dts/arm/imx6sx-sabreauto.dts =================================================================== --- sys/gnu/dts/arm/imx6sx-sabreauto.dts +++ sys/gnu/dts/arm/imx6sx-sabreauto.dts @@ -14,7 +14,7 @@ model = "Freescale i.MX6 SoloX Sabre Auto Board"; compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx"; - memory { + memory@80000000 { reg = <0x80000000 0x80000000>; }; Index: sys/gnu/dts/arm/imx6sx-sdb.dtsi =================================================================== --- sys/gnu/dts/arm/imx6sx-sdb.dtsi +++ sys/gnu/dts/arm/imx6sx-sdb.dtsi @@ -20,7 +20,7 @@ stdout-path = &uart1; }; - memory { + memory@80000000 { reg = <0x80000000 0x40000000>; }; Index: sys/gnu/dts/arm/imx6sx-softing-vining-2000.dts =================================================================== --- sys/gnu/dts/arm/imx6sx-softing-vining-2000.dts +++ sys/gnu/dts/arm/imx6sx-softing-vining-2000.dts @@ -20,7 +20,7 @@ stdout-path = &uart1; }; - memory { + memory@80000000 { reg = <0x80000000 0x40000000>; }; Index: sys/gnu/dts/arm/imx6sx-udoo-neo-basic.dts =================================================================== --- sys/gnu/dts/arm/imx6sx-udoo-neo-basic.dts +++ sys/gnu/dts/arm/imx6sx-udoo-neo-basic.dts @@ -48,7 +48,7 @@ model = "UDOO Neo Basic"; compatible = "udoo,neobasic", "fsl,imx6sx"; - memory { + memory@80000000 { reg = <0x80000000 0x20000000>; }; }; Index: sys/gnu/dts/arm/imx6sx-udoo-neo-extended.dts =================================================================== --- sys/gnu/dts/arm/imx6sx-udoo-neo-extended.dts +++ sys/gnu/dts/arm/imx6sx-udoo-neo-extended.dts @@ -48,7 +48,7 @@ model = "UDOO Neo Extended"; compatible = "udoo,neoextended", "fsl,imx6sx"; - memory { + memory@80000000 { reg = <0x80000000 0x40000000>; }; }; Index: sys/gnu/dts/arm/imx6sx-udoo-neo-full.dts =================================================================== --- sys/gnu/dts/arm/imx6sx-udoo-neo-full.dts +++ sys/gnu/dts/arm/imx6sx-udoo-neo-full.dts @@ -48,7 +48,7 @@ model = "UDOO Neo Full"; compatible = "udoo,neofull", "fsl,imx6sx"; - memory { + memory@80000000 { reg = <0x80000000 0x40000000>; }; }; Index: sys/gnu/dts/arm/imx6sx.dtsi =================================================================== --- sys/gnu/dts/arm/imx6sx.dtsi +++ sys/gnu/dts/arm/imx6sx.dtsi @@ -22,7 +22,7 @@ * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; reg = <0 0>; }; + memory { device_type = "memory"; }; aliases { can0 = &flexcan1; @@ -188,6 +188,7 @@ <&clks IMX6SX_CLK_GPU>, <&clks IMX6SX_CLK_GPU>; clock-names = "bus", "core", "shader"; + power-domains = <&pd_pu>; }; dma_apbh: dma-apbh@1804000 { @@ -767,6 +768,18 @@ #address-cells = <1>; #size-cells = <0>; + power-domain@0 { + reg = <0>; + #power-domain-cells = <0>; + }; + + pd_pu: power-domain@1 { + reg = <1>; + #power-domain-cells = <0>; + power-supply = <®_soc>; + clocks = <&clks IMX6SX_CLK_GPU>; + }; + pd_pci: power-domain@3 { reg = <3>; #power-domain-cells = <0>; @@ -1355,9 +1368,4 @@ status = "disabled"; }; }; - - gpu-subsystem { - compatible = "fsl,imx-gpu-subsystem"; - cores = <&gpu>; - }; }; Index: sys/gnu/dts/arm/imx6ul-14x14-evk.dts =================================================================== --- sys/gnu/dts/arm/imx6ul-14x14-evk.dts +++ sys/gnu/dts/arm/imx6ul-14x14-evk.dts @@ -9,487 +9,9 @@ /dts-v1/; #include "imx6ul.dtsi" +#include "imx6ul-14x14-evk.dtsi" / { model = "Freescale i.MX6 UltraLite 14x14 EVK Board"; compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul"; - - chosen { - stdout-path = &uart1; - }; - - memory { - reg = <0x80000000 0x20000000>; - }; - - backlight_display: backlight-display { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "okay"; - }; - - - reg_sd1_vmmc: regulator-sd1-vmmc { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "mx6ul-wm8960"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Line", "Line In", - "Line", "Line Out", - "Speaker", "Speaker", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Headphone Jack", "HP_L", - "Headphone Jack", "HP_R", - "Speaker", "SPK_LP", - "Speaker", "SPK_LN", - "Speaker", "SPK_RP", - "Speaker", "SPK_RN", - "LINPUT1", "Mic Jack", - "LINPUT3", "Mic Jack", - "RINPUT1", "Mic Jack", - "RINPUT2", "Mic Jack"; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - }; - - dailink_master: simple-audio-card,codec { - sound-dai = <&codec>; - clocks = <&clks IMX6UL_CLK_SAI2>; - }; - }; - - panel { - compatible = "innolux,at043tn24"; - backlight = <&backlight_display>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; -}; - -&clks { - assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <786432000>; -}; - -&i2c2 { - clock_frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - codec: wm8960@1a { - #sound-dai-cells = <0>; - compatible = "wlf,wm8960"; - reg = <0x1a>; - wlf,shared-lrclk; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - status = "okay"; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@2 { - reg = <2>; - micrel,led-mode = <1>; - clocks = <&clks IMX6UL_CLK_ENET_REF>; - clock-names = "rmii-ref"; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - micrel,led-mode = <1>; - clocks = <&clks IMX6UL_CLK_ENET2_REF>; - clock-names = "rmii-ref"; - }; - }; -}; - - -&lcdif { - assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>; - assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat - &pinctrl_lcdif_ctrl>; - status = "okay"; - - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&qspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi>; - status = "okay"; - - flash0: n25q256a@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q256a"; - spi-max-frequency = <29000000>; - reg = <0>; - }; -}; - -&sai2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, - <&clks IMX6UL_CLK_SAI2>; - assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <0>, <12288000>; - fsl,sai-mclk-direction-output; - status = "okay"; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&tsc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tsc>; - xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; - measure-delay-time = <0xffff>; - pre-charge-time = <0xfff>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "otg"; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usbphy1 { - fsl,tx-d-cal = <106>; -}; - -&usbphy2 { - fsl,tx-d-cal = <106>; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_sd1_vmmc>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl-names = "default"; - - pinctrl_csi1: csi1grp { - fsl,pins = < - MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 - MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 - MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 - MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 - MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 - MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 - MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 - MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 - MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 - MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 - MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 - MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 - >; - }; - - pinctrl_flexcan1: flexcan1grp{ - fsl,pins = < - MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 - MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 - >; - }; - - pinctrl_flexcan2: flexcan2grp{ - fsl,pins = < - MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 - MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 - MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 - >; - }; - - pinctrl_lcdif_dat: lcdifdatgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 - MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 - MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 - MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 - MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 - MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 - MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 - >; - }; - - pinctrl_lcdif_ctrl: lcdifctrlgrp { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 - /* used for lcd reset */ - MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 - >; - }; - - pinctrl_qspi: qspigrp { - fsl,pins = < - MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 - MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 - MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 - MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 - MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 - MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 - MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 - MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 - MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 - MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 - MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 - >; - }; - - pinctrl_sim2: sim2grp { - fsl,pins = < - MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808 - MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31 - MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808 - MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808 - MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809 - MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008 - >; - }; - - pinctrl_tsc: tscgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 - MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 - MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 - MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 - MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ - MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ - MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 - - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 - >; - }; }; Index: sys/gnu/dts/arm/imx6ul-14x14-evk.dtsi =================================================================== --- sys/gnu/dts/arm/imx6ul-14x14-evk.dtsi +++ sys/gnu/dts/arm/imx6ul-14x14-evk.dtsi @@ -6,19 +6,12 @@ * published by the Free Software Foundation. */ -/dts-v1/; - -#include "imx6ul.dtsi" - / { - model = "Freescale i.MX6 UltraLite 14x14 EVK Board"; - compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul"; - chosen { stdout-path = &uart1; }; - memory { + memory@80000000 { reg = <0x80000000 0x20000000>; }; @@ -140,6 +133,17 @@ }; }; +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + mag3110@e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + }; +}; &lcdif { assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>; Index: sys/gnu/dts/arm/imx6ul-geam.dts =================================================================== --- sys/gnu/dts/arm/imx6ul-geam.dts +++ sys/gnu/dts/arm/imx6ul-geam.dts @@ -50,7 +50,7 @@ model = "Engicam GEAM6UL Starter Kit"; compatible = "engicam,imx6ul-geam", "fsl,imx6ul"; - memory { + memory@80000000 { reg = <0x80000000 0x08000000>; }; @@ -181,6 +181,7 @@ sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; clocks = <&clks IMX6UL_CLK_OSC>; clock-names = "mclk"; VDDA-supply = <®_3p3v>; Index: sys/gnu/dts/arm/imx6ul-isiot.dtsi =================================================================== --- sys/gnu/dts/arm/imx6ul-isiot.dtsi +++ sys/gnu/dts/arm/imx6ul-isiot.dtsi @@ -45,7 +45,7 @@ #include "imx6ul.dtsi" / { - memory { + memory@80000000 { reg = <0x80000000 0x20000000>; }; @@ -142,6 +142,7 @@ sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; clocks = <&clks IMX6UL_CLK_OSC>; clock-names = "mclk"; VDDA-supply = <®_3p3v>; Index: sys/gnu/dts/arm/imx6ul-litesom.dtsi =================================================================== --- sys/gnu/dts/arm/imx6ul-litesom.dtsi +++ sys/gnu/dts/arm/imx6ul-litesom.dtsi @@ -47,7 +47,7 @@ model = "Grinn i.MX6UL liteSOM"; compatible = "grinn,imx6ul-litesom", "fsl,imx6ul"; - memory { + memory@80000000 { reg = <0x80000000 0x20000000>; }; }; Index: sys/gnu/dts/arm/imx6ul-opos6ul.dtsi =================================================================== --- sys/gnu/dts/arm/imx6ul-opos6ul.dtsi +++ sys/gnu/dts/arm/imx6ul-opos6ul.dtsi @@ -48,7 +48,7 @@ #include "imx6ul.dtsi" / { - memory { + memory@80000000 { reg = <0x80000000 0>; /* will be filled by U-Boot */ }; Index: sys/gnu/dts/arm/imx6ul-pico-hobbit.dts =================================================================== --- sys/gnu/dts/arm/imx6ul-pico-hobbit.dts +++ sys/gnu/dts/arm/imx6ul-pico-hobbit.dts @@ -51,7 +51,7 @@ model = "Technexion Pico i.MX6UL Board"; compatible = "technexion,imx6ul-pico-hobbit", "fsl,imx6ul"; - memory { + memory@80000000 { reg = <0x80000000 0x10000000>; }; Index: sys/gnu/dts/arm/imx6ul-pinfunc.h =================================================================== --- sys/gnu/dts/arm/imx6ul-pinfunc.h +++ sys/gnu/dts/arm/imx6ul-pinfunc.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2014 - 2015 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -34,14 +34,14 @@ #define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M 0x0044 0x02d0 0x0000 3 0 #define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY 0x0044 0x02d0 0x04c0 4 0 #define MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0044 0x02d0 0x0000 5 0 -#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00 0x0044 0x02d0 0x0000 6 0 +#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00 0x0044 0x02d0 0x0610 6 0 #define MX6UL_PAD_JTAG_TMS__SJC_TMS 0x0048 0x02d4 0x0000 0 0 #define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1 0x0048 0x02d4 0x0598 1 0 -#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x0048 0x02d4 0x0000 2 0 +#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x0048 0x02d4 0x05f0 2 0 #define MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x0048 0x02d4 0x0000 3 0 #define MX6UL_PAD_JTAG_TMS__CCM_WAIT 0x0048 0x02d4 0x0000 4 0 #define MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x0048 0x02d4 0x0000 5 0 -#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01 0x0048 0x02d4 0x0000 6 0 +#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01 0x0048 0x02d4 0x0614 6 0 #define MX6UL_PAD_JTAG_TMS__EPIT1_OUT 0x0048 0x02d4 0x0000 8 0 #define MX6UL_PAD_JTAG_TDO__SJC_TDO 0x004c 0x02d8 0x0000 0 0 #define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2 0x004c 0x02d8 0x059c 1 0 @@ -63,12 +63,14 @@ #define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0054 0x02e0 0x05f4 2 0 #define MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0054 0x02e0 0x0000 4 0 #define MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x0054 0x02e0 0x0000 5 0 +#define MX6UL_PAD_JTAG_TCK__OSC32K_32K_OUT 0x0054 0x02e0 0x0000 6 0 #define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL 0x0054 0x02e0 0x0000 8 0 #define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB 0x0058 0x02e4 0x0000 0 0 #define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3 0x0058 0x02e4 0x0000 1 0 #define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0058 0x02e4 0x0000 2 0 #define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0058 0x02e4 0x0000 4 0 #define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x0058 0x02e4 0x0000 5 0 +#define MX6UL_PAD_JTAG_TRST_B__REF_CLK_24M 0x0058 0x02e4 0x0000 6 0 #define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS 0x0058 0x02e4 0x0000 8 0 #define MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x005c 0x02e8 0x05ac 0 1 #define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1 0x005c 0x02e8 0x058c 1 0 @@ -94,22 +96,24 @@ #define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25M 0x0064 0x02f0 0x0000 3 0 #define MX6UL_PAD_GPIO1_IO02__USDHC1_WP 0x0064 0x02f0 0x066c 4 0 #define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0064 0x02f0 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 0x0064 0x02f0 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 0x0064 0x02f0 0x0610 6 1 #define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET 0x0064 0x02f0 0x0000 7 0 #define MX6UL_PAD_GPIO1_IO02__UART1_DCE_TX 0x0064 0x02f0 0x0000 8 0 #define MX6UL_PAD_GPIO1_IO02__UART1_DTE_RX 0x0064 0x02f0 0x0624 8 0 #define MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x0068 0x02f4 0x05a8 0 1 #define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3 0x0068 0x02f4 0x0000 1 0 #define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC 0x0068 0x02f4 0x0660 2 0 +#define MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x0068 0x02f4 0x0000 3 0 #define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B 0x0068 0x02f4 0x0668 4 0 #define MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x0068 0x02f4 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_eXT_CLK 0x0068 0x02f4 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK 0x0068 0x02f4 0x0000 6 0 #define MX6UL_PAD_GPIO1_IO03__SRC_TESTER_ACK 0x0068 0x02f4 0x0000 7 0 -#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX 0x0068 0x02f4 0x0000 8 0 #define MX6UL_PAD_GPIO1_IO03__UART1_DCE_RX 0x0068 0x02f4 0x0624 8 1 +#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX 0x0068 0x02f4 0x0000 8 0 #define MX6UL_PAD_GPIO1_IO04__ENET1_REF_CLK1 0x006c 0x02f8 0x0574 0 1 #define MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x006c 0x02f8 0x0000 1 0 #define MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x006c 0x02f8 0x0000 2 0 +#define MX6UL_PAD_GPIO1_IO04__REF_CLK_24M 0x006c 0x02f8 0x0000 3 0 #define MX6UL_PAD_GPIO1_IO04__USDHC1_RESET_B 0x006c 0x02f8 0x0000 4 0 #define MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x006c 0x02f8 0x0000 5 0 #define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN 0x006c 0x02f8 0x0000 6 0 @@ -200,7 +204,7 @@ #define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06 0x0094 0x0320 0x04dc 3 0 #define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1 0x0094 0x0320 0x058c 4 1 #define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x0094 0x0320 0x0000 5 0 -#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x0094 0x0320 0x0000 8 0 +#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x0094 0x0320 0x0560 8 0 #define MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0098 0x0324 0x062c 0 1 #define MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0098 0x0324 0x0000 0 0 #define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03 0x0098 0x0324 0x0000 1 0 @@ -232,7 +236,7 @@ #define MX6UL_PAD_UART3_TX_DATA__UART3_DTE_RX 0x00a4 0x0330 0x0634 0 0 #define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x00a4 0x0330 0x0000 1 0 #define MX6UL_PAD_UART3_TX_DATA__SIM1_PORT0_PD 0x00a4 0x0330 0x0000 2 0 -#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01 0x00a4 0x0330 0x0000 3 0 +#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01 0x00a4 0x0330 0x04d4 3 0 #define MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x00a4 0x0330 0x0000 4 0 #define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x00a4 0x0330 0x0628 4 2 #define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x00a4 0x0330 0x0000 5 0 @@ -242,7 +246,7 @@ #define MX6UL_PAD_UART3_RX_DATA__UART3_DTE_TX 0x00a8 0x0334 0x0000 0 0 #define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x00a8 0x0334 0x0000 1 0 #define MX6UL_PAD_UART3_RX_DATA__SIM2_PORT0_PD 0x00a8 0x0334 0x0000 2 0 -#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00 0x00a8 0x0334 0x0000 3 0 +#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00 0x00a8 0x0334 0x04d0 3 0 #define MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x00a8 0x0334 0x0628 4 3 #define MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x00a8 0x0334 0x0000 4 0 #define MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x00a8 0x0334 0x0000 5 0 @@ -251,7 +255,7 @@ #define MX6UL_PAD_UART3_CTS_B__UART3_DTE_RTS 0x00ac 0x0338 0x0630 0 0 #define MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x00ac 0x0338 0x0000 1 0 #define MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x00ac 0x0338 0x0000 2 0 -#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10 0x00ac 0x0338 0x0000 3 0 +#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10 0x00ac 0x0338 0x04ec 3 0 #define MX6UL_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN 0x00ac 0x0338 0x0000 4 0 #define MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x00ac 0x0338 0x0000 5 0 #define MX6UL_PAD_UART3_CTS_B__EPIT2_OUT 0x00ac 0x0338 0x0000 8 0 @@ -259,7 +263,7 @@ #define MX6UL_PAD_UART3_RTS_B__UART3_DTE_CTS 0x00b0 0x033c 0x0000 0 0 #define MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER 0x00b0 0x033c 0x0000 1 0 #define MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x00b0 0x033c 0x0584 2 0 -#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11 0x00b0 0x033c 0x0000 3 0 +#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11 0x00b0 0x033c 0x04f0 3 0 #define MX6UL_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT 0x00b0 0x033c 0x0000 4 0 #define MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x00b0 0x033c 0x0000 5 0 #define MX6UL_PAD_UART3_RTS_B__WDOG1_WDOG_B 0x00b0 0x033c 0x0000 8 0 @@ -267,7 +271,7 @@ #define MX6UL_PAD_UART4_TX_DATA__UART4_DTE_RX 0x00b4 0x0340 0x063c 0 0 #define MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x00b4 0x0340 0x0000 1 0 #define MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x00b4 0x0340 0x05a4 2 1 -#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12 0x00b4 0x0340 0x0000 3 0 +#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12 0x00b4 0x0340 0x04f4 3 0 #define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02 0x00b4 0x0340 0x0000 4 0 #define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x00b4 0x0340 0x0000 5 0 #define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x00b4 0x0340 0x0544 8 1 @@ -275,23 +279,23 @@ #define MX6UL_PAD_UART4_RX_DATA__UART4_DTE_TX 0x00b8 0x0344 0x0000 0 0 #define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x00b8 0x0344 0x0000 1 0 #define MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x00b8 0x0344 0x05a8 2 2 -#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13 0x00b8 0x0344 0x0000 3 0 +#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13 0x00b8 0x0344 0x04f8 3 0 #define MX6UL_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01 0x00b8 0x0344 0x0000 4 0 #define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x00b8 0x0344 0x0000 5 0 -#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x00b8 0x0344 0x0000 8 0 +#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x00b8 0x0344 0x0550 8 1 #define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x00bc 0x0348 0x0000 5 0 #define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x00bc 0x0348 0x054c 8 0 #define MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x00bc 0x0348 0x0000 0 0 #define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00bc 0x0348 0x0644 0 4 #define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x00bc 0x0348 0x0000 1 0 #define MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x00bc 0x0348 0x05ac 2 2 -#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14 0x00bc 0x0348 0x0000 3 0 +#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14 0x00bc 0x0348 0x04fc 3 0 #define MX6UL_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00 0x00bc 0x0348 0x0000 4 0 #define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00c0 0x034c 0x0644 0 5 #define MX6UL_PAD_UART5_RX_DATA__UART5_DTE_TX 0x00c0 0x034c 0x0000 0 0 #define MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x00c0 0x034c 0x0000 1 0 #define MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x00c0 0x034c 0x05b0 2 2 -#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15 0x00c0 0x034c 0x0000 3 0 +#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15 0x00c0 0x034c 0x0500 3 0 #define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB 0x00c0 0x034c 0x0000 4 0 #define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x00c0 0x034c 0x0000 5 0 #define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x00c0 0x034c 0x0548 8 1 @@ -299,59 +303,61 @@ #define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS 0x00c4 0x0350 0x0638 1 0 #define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CTS 0x00c4 0x0350 0x0000 1 0 #define MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x00c4 0x0350 0x0000 2 0 -#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16 0x00c4 0x0350 0x0000 3 0 +#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16 0x00c4 0x0350 0x0504 3 0 #define MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x00c4 0x0350 0x0000 4 0 #define MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x00c4 0x0350 0x0000 5 0 -#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00 0x00c4 0x0350 0x0000 6 0 +#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00 0x00c4 0x0350 0x05d0 6 0 #define MX6UL_PAD_ENET1_RX_DATA0__USDHC1_LCTL 0x00c4 0x0350 0x0000 8 0 #define MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x00c8 0x0354 0x0000 0 0 #define MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS 0x00c8 0x0354 0x0000 1 0 #define MX6UL_PAD_ENET1_RX_DATA1__UART4_DTE_RTS 0x00c8 0x0354 0x0638 1 1 #define MX6UL_PAD_ENET1_RX_DATA1__PWM2_OUT 0x00c8 0x0354 0x0000 2 0 -#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17 0x00c8 0x0354 0x0000 3 0 +#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17 0x00c8 0x0354 0x0508 3 0 #define MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x00c8 0x0354 0x0584 4 1 #define MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x00c8 0x0354 0x0000 5 0 -#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00 0x00c8 0x0354 0x0000 6 0 +#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00 0x00c8 0x0354 0x05c4 6 0 #define MX6UL_PAD_ENET1_RX_DATA1__USDHC2_LCTL 0x00c8 0x0354 0x0000 8 0 #define MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x00cc 0x0358 0x0000 0 0 #define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00cc 0x0358 0x0640 1 3 #define MX6UL_PAD_ENET1_RX_EN__UART5_DTE_CTS 0x00cc 0x0358 0x0000 1 0 -#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18 0x00cc 0x0358 0x0000 3 0 +#define MX6UL_PAD_ENET1_RX_EN__OSC32K_32K_OUT 0x00cc 0x0358 0x0000 2 0 +#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18 0x00cc 0x0358 0x050c 3 0 #define MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x00cc 0x0358 0x0000 4 0 #define MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x00cc 0x0358 0x0000 5 0 -#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01 0x00cc 0x0358 0x0000 6 0 +#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01 0x00cc 0x0358 0x05d4 6 0 #define MX6UL_PAD_ENET1_RX_EN__USDHC1_VSELECT 0x00cc 0x0358 0x0000 8 0 #define MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x00d0 0x035c 0x0000 0 0 #define MX6UL_PAD_ENET1_TX_DATA0__UART5_DCE_CTS 0x00d0 0x035c 0x0000 1 0 #define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00d0 0x035c 0x0640 1 4 -#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19 0x00d0 0x035c 0x0000 3 0 +#define MX6UL_PAD_ENET1_TX_DATA0__REF_CLK_24M 0x00d0 0x035c 0x0000 2 0 +#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19 0x00d0 0x035c 0x0510 3 0 #define MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x00d0 0x035c 0x0588 4 1 #define MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x00d0 0x035c 0x0000 5 0 -#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01 0x00d0 0x035c 0x0000 6 0 +#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01 0x00d0 0x035c 0x05c8 6 0 #define MX6UL_PAD_ENET1_TX_DATA0__USDHC2_VSELECT 0x00d0 0x035c 0x0000 8 0 #define MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x00d4 0x0360 0x0000 0 0 #define MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CTS 0x00d4 0x0360 0x0000 1 0 #define MX6UL_PAD_ENET1_TX_DATA1__UART6_DTE_RTS 0x00d4 0x0360 0x0648 1 2 #define MX6UL_PAD_ENET1_TX_DATA1__PWM5_OUT 0x00d4 0x0360 0x0000 2 0 -#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20 0x00d4 0x0360 0x0000 3 0 +#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20 0x00d4 0x0360 0x0514 3 0 #define MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x00d4 0x0360 0x0580 4 1 #define MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x00d4 0x0360 0x0000 5 0 -#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02 0x00d4 0x0360 0x0000 6 0 +#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02 0x00d4 0x0360 0x05d8 6 0 #define MX6UL_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB 0x00d4 0x0360 0x0000 8 0 #define MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x00d8 0x0364 0x0000 0 0 #define MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS 0x00d8 0x0364 0x0648 1 3 #define MX6UL_PAD_ENET1_TX_EN__UART6_DTE_CTS 0x00d8 0x0364 0x0000 1 0 #define MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00d8 0x0364 0x0000 2 0 -#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21 0x00d8 0x0364 0x0000 3 0 +#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21 0x00d8 0x0364 0x0518 3 0 #define MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x00d8 0x0364 0x0000 4 0 #define MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0x00d8 0x0364 0x0000 5 0 -#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02 0x00d8 0x0364 0x0000 6 0 +#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02 0x00d8 0x0364 0x05cc 6 0 #define MX6UL_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB 0x00d8 0x0364 0x0000 8 0 #define MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x00dc 0x0368 0x0000 0 0 #define MX6UL_PAD_ENET1_TX_CLK__UART7_DCE_CTS 0x00dc 0x0368 0x0000 1 0 #define MX6UL_PAD_ENET1_TX_CLK__UART7_DTE_RTS 0x00dc 0x0368 0x0650 1 0 #define MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00dc 0x0368 0x0000 2 0 -#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22 0x00dc 0x0368 0x0000 3 0 +#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22 0x00dc 0x0368 0x051c 3 0 #define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x00dc 0x0368 0x0574 4 2 #define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06 0x00dc 0x0368 0x0000 5 0 #define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03 0x00dc 0x0368 0x0000 6 0 @@ -360,7 +366,7 @@ #define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS 0x00e0 0x036c 0x0650 1 1 #define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS 0x00e0 0x036c 0x0000 1 0 #define MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x00e0 0x036c 0x0000 2 0 -#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23 0x00e0 0x036c 0x0000 3 0 +#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23 0x00e0 0x036c 0x0520 3 0 #define MX6UL_PAD_ENET1_RX_ER__EIM_CRE 0x00e0 0x036c 0x0000 4 0 #define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x00e0 0x036c 0x0000 5 0 #define MX6UL_PAD_ENET1_RX_ER__KPP_COL03 0x00e0 0x036c 0x0000 6 0 @@ -377,7 +383,7 @@ #define MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x00e8 0x0374 0x0000 0 0 #define MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX 0x00e8 0x0374 0x064c 1 2 #define MX6UL_PAD_ENET2_RX_DATA1__UART6_DTE_TX 0x00e8 0x0374 0x0000 1 0 -#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_cLK 0x00e8 0x0374 0x0000 2 0 +#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK 0x00e8 0x0374 0x0000 2 0 #define MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA 0x00e8 0x0374 0x05b8 3 1 #define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x00e8 0x0374 0x0000 4 0 #define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x00e8 0x0374 0x0000 5 0 @@ -400,6 +406,7 @@ #define MX6UL_PAD_ENET2_TX_DATA0__EIM_EB_B02 0x00f0 0x037c 0x0000 4 0 #define MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x00f0 0x037c 0x0000 5 0 #define MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x00f0 0x037c 0x0000 6 0 +#define MX6UL_PAD_ENET2_TX_DATA0__REF_CLK_24M 0x00f0 0x037c 0x0000 8 0 #define MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x00f4 0x0380 0x0000 0 0 #define MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x00f4 0x0380 0x0000 1 0 #define MX6UL_PAD_ENET2_TX_DATA1__UART8_DTE_RX 0x00f4 0x0380 0x065c 1 0 @@ -412,7 +419,7 @@ #define MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x00f8 0x0384 0x0000 0 0 #define MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x00f8 0x0384 0x065c 1 1 #define MX6UL_PAD_ENET2_TX_EN__UART8_DTE_TX 0x00f8 0x0384 0x0000 1 0 -#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_cLK 0x00f8 0x0384 0x0000 2 0 +#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_CLK 0x00f8 0x0384 0x0000 2 0 #define MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x00f8 0x0384 0x056c 3 0 #define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN 0x00f8 0x0384 0x0000 4 0 #define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x00f8 0x0384 0x0000 5 0 @@ -431,7 +438,7 @@ #define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x0100 0x038c 0x0658 1 1 #define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS 0x0100 0x038c 0x0000 1 0 #define MX6UL_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN 0x0100 0x038c 0x0000 2 0 -#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0 0x0100 0x038c 0x0000 3 0 +#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0 0x0100 0x038c 0x0570 3 0 #define MX6UL_PAD_ENET2_RX_ER__EIM_ADDR25 0x0100 0x038c 0x0000 4 0 #define MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0100 0x038c 0x0000 5 0 #define MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x0100 0x038c 0x0000 6 0 @@ -440,7 +447,7 @@ #define MX6UL_PAD_LCD_CLK__LCDIF_WR_RWN 0x0104 0x0390 0x0000 1 0 #define MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x0104 0x0390 0x0000 2 0 #define MX6UL_PAD_LCD_CLK__UART4_DTE_RX 0x0104 0x0390 0x063c 2 2 -#define MX6UL_PAD_LCD_CLK__SAI3_MCLK 0x0104 0x0390 0x0000 3 0 +#define MX6UL_PAD_LCD_CLK__SAI3_MCLK 0x0104 0x0390 0x0600 3 0 #define MX6UL_PAD_LCD_CLK__EIM_CS2_B 0x0104 0x0390 0x0000 4 0 #define MX6UL_PAD_LCD_CLK__GPIO3_IO00 0x0104 0x0390 0x0000 5 0 #define MX6UL_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB 0x0104 0x0390 0x0000 8 0 @@ -464,7 +471,7 @@ #define MX6UL_PAD_LCD_VSYNC__LCDIF_BUSY 0x0110 0x039c 0x05dc 1 1 #define MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x0110 0x039c 0x0638 2 3 #define MX6UL_PAD_LCD_VSYNC__UART4_DTE_CTS 0x0110 0x039c 0x0000 2 0 -#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA 0x0110 0x039c 0x0000 3 0 +#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA 0x0110 0x039c 0x0604 3 0 #define MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B 0x0110 0x039c 0x0000 4 0 #define MX6UL_PAD_LCD_VSYNC__GPIO3_IO03 0x0110 0x039c 0x0000 5 0 #define MX6UL_PAD_LCD_VSYNC__ECSPI2_SS2 0x0110 0x039c 0x0000 8 0 @@ -477,13 +484,15 @@ #define MX6UL_PAD_LCD_RESET__ECSPI2_SS3 0x0114 0x03a0 0x0000 8 0 #define MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x0118 0x03a4 0x0000 0 0 #define MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x0118 0x03a4 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA00__CA7_MX6UL_TRACE0 0x0118 0x03a4 0x0000 2 0 #define MX6UL_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN 0x0118 0x03a4 0x0000 3 0 #define MX6UL_PAD_LCD_DATA00__I2C3_SDA 0x0118 0x03a4 0x05b8 4 2 #define MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0118 0x03a4 0x0000 5 0 #define MX6UL_PAD_LCD_DATA00__SRC_BT_CFG00 0x0118 0x03a4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK 0x0118 0x03a4 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK 0x0118 0x03a4 0x05e0 8 1 #define MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x011c 0x03a8 0x0000 0 0 #define MX6UL_PAD_LCD_DATA01__PWM2_OUT 0x011c 0x03a8 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA01__CA7_MX6UL_TRACE1 0x011c 0x03a8 0x0000 2 0 #define MX6UL_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT 0x011c 0x03a8 0x0000 3 0 #define MX6UL_PAD_LCD_DATA01__I2C3_SCL 0x011c 0x03a8 0x05b4 4 2 #define MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0x011c 0x03a8 0x0000 5 0 @@ -491,6 +500,7 @@ #define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC 0x011c 0x03a8 0x05ec 8 0 #define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x0120 0x03ac 0x0000 0 0 #define MX6UL_PAD_LCD_DATA02__PWM3_OUT 0x0120 0x03ac 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA02__CA7_MX6UL_TRACE2 0x0120 0x03ac 0x0000 2 0 #define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN 0x0120 0x03ac 0x0000 3 0 #define MX6UL_PAD_LCD_DATA02__I2C4_SDA 0x0120 0x03ac 0x05c0 4 2 #define MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x0120 0x03ac 0x0000 5 0 @@ -498,14 +508,16 @@ #define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK 0x0120 0x03ac 0x05e8 8 0 #define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x0124 0x03b0 0x0000 0 0 #define MX6UL_PAD_LCD_DATA03__PWM4_OUT 0x0124 0x03b0 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA03__CA7_MX6UL_TRACE3 0x0124 0x03b0 0x0000 2 0 #define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT 0x0124 0x03b0 0x0000 3 0 #define MX6UL_PAD_LCD_DATA03__I2C4_SCL 0x0124 0x03b0 0x05bc 4 2 #define MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x0124 0x03b0 0x0000 5 0 #define MX6UL_PAD_LCD_DATA03__SRC_BT_CFG03 0x0124 0x03b0 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA 0x0124 0x03b0 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA 0x0124 0x03b0 0x05e4 8 0 #define MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x0128 0x03b4 0x0000 0 0 #define MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS 0x0128 0x03b4 0x0000 1 0 #define MX6UL_PAD_LCD_DATA04__UART8_DTE_RTS 0x0128 0x03b4 0x0658 1 2 +#define MX6UL_PAD_LCD_DATA04__CA7_MX6UL_TRACE4 0x0128 0x03b4 0x0000 2 0 #define MX6UL_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN 0x0128 0x03b4 0x0000 3 0 #define MX6UL_PAD_LCD_DATA04__SPDIF_SR_CLK 0x0128 0x03b4 0x0000 4 0 #define MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x0128 0x03b4 0x0000 5 0 @@ -514,6 +526,7 @@ #define MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x012c 0x03b8 0x0000 0 0 #define MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS 0x012c 0x03b8 0x0658 1 3 #define MX6UL_PAD_LCD_DATA05__UART8_DTE_CTS 0x012c 0x03b8 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA05__CA7_MX6UL_TRACE5 0x012c 0x03b8 0x0000 2 0 #define MX6UL_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT 0x012c 0x03b8 0x0000 3 0 #define MX6UL_PAD_LCD_DATA05__SPDIF_OUT 0x012c 0x03b8 0x0000 4 0 #define MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x012c 0x03b8 0x0000 5 0 @@ -522,6 +535,7 @@ #define MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x0130 0x03bc 0x0000 0 0 #define MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS 0x0130 0x03bc 0x0000 1 0 #define MX6UL_PAD_LCD_DATA06__UART7_DTE_RTS 0x0130 0x03bc 0x0650 1 2 +#define MX6UL_PAD_LCD_DATA06__CA7_MX6UL_TRACE6 0x0130 0x03bc 0x0000 2 0 #define MX6UL_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN 0x0130 0x03bc 0x0000 3 0 #define MX6UL_PAD_LCD_DATA06__SPDIF_LOCK 0x0130 0x03bc 0x0000 4 0 #define MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x0130 0x03bc 0x0000 5 0 @@ -530,6 +544,7 @@ #define MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x0134 0x03c0 0x0000 0 0 #define MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS 0x0134 0x03c0 0x0650 1 3 #define MX6UL_PAD_LCD_DATA07__UART7_DTE_CTS 0x0134 0x03c0 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA07__CA7_MX6UL_TRACE7 0x0134 0x03c0 0x0000 2 0 #define MX6UL_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT 0x0134 0x03c0 0x0000 3 0 #define MX6UL_PAD_LCD_DATA07__SPDIF_EXT_CLK 0x0134 0x03c0 0x061c 4 0 #define MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x0134 0x03c0 0x0000 5 0 @@ -537,56 +552,64 @@ #define MX6UL_PAD_LCD_DATA07__ECSPI1_SS3 0x0134 0x03c0 0x0000 8 0 #define MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x0138 0x03c4 0x0000 0 0 #define MX6UL_PAD_LCD_DATA08__SPDIF_IN 0x0138 0x03c4 0x0618 1 2 -#define MX6UL_PAD_LCD_DATA08__CSI_DATA16 0x0138 0x03c4 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA08__CA7_MX6UL_TRACE8 0x0138 0x03c4 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA08__CSI_DATA16 0x0138 0x03c4 0x0504 3 1 #define MX6UL_PAD_LCD_DATA08__EIM_DATA00 0x0138 0x03c4 0x0000 4 0 #define MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x0138 0x03c4 0x0000 5 0 #define MX6UL_PAD_LCD_DATA08__SRC_BT_CFG08 0x0138 0x03c4 0x0000 6 0 #define MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x0138 0x03c4 0x0000 8 0 #define MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x013c 0x03c8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK 0x013c 0x03c8 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA09__CSI_DATA17 0x013c 0x03c8 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK 0x013c 0x03c8 0x0600 1 1 +#define MX6UL_PAD_LCD_DATA09__CA7_MX6UL_TRACE9 0x013c 0x03c8 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA09__CSI_DATA17 0x013c 0x03c8 0x0508 3 1 #define MX6UL_PAD_LCD_DATA09__EIM_DATA01 0x013c 0x03c8 0x0000 4 0 #define MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x013c 0x03c8 0x0000 5 0 #define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09 0x013c 0x03c8 0x0000 6 0 #define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x013c 0x03c8 0x0584 8 2 #define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x0140 0x03cc 0x0000 0 0 #define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC 0x0140 0x03cc 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA10__CSI_DATA18 0x0140 0x03cc 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA10__CA7_MX6UL_TRACE10 0x0140 0x03cc 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA10__CSI_DATA18 0x0140 0x03cc 0x050c 3 1 #define MX6UL_PAD_LCD_DATA10__EIM_DATA02 0x0140 0x03cc 0x0000 4 0 #define MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0x0140 0x03cc 0x0000 5 0 #define MX6UL_PAD_LCD_DATA10__SRC_BT_CFG10 0x0140 0x03cc 0x0000 6 0 #define MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0140 0x03cc 0x0000 8 0 #define MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x0144 0x03d0 0x0000 0 0 #define MX6UL_PAD_LCD_DATA11__SAI3_RX_BCLK 0x0144 0x03d0 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA11__CSI_DATA19 0x0144 0x03d0 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA11__CA7_MX6UL_TRACE11 0x0144 0x03d0 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA11__CSI_DATA19 0x0144 0x03d0 0x0510 3 1 #define MX6UL_PAD_LCD_DATA11__EIM_DATA03 0x0144 0x03d0 0x0000 4 0 #define MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x0144 0x03d0 0x0000 5 0 #define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11 0x0144 0x03d0 0x0000 6 0 #define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0144 0x03d0 0x0588 8 2 #define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x0148 0x03d4 0x0000 0 0 #define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC 0x0148 0x03d4 0x060c 1 1 -#define MX6UL_PAD_LCD_DATA12__CSI_DATA20 0x0148 0x03d4 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA12__CA7_MX6UL_TRACE12 0x0148 0x03d4 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA12__CSI_DATA20 0x0148 0x03d4 0x0514 3 1 #define MX6UL_PAD_LCD_DATA12__EIM_DATA04 0x0148 0x03d4 0x0000 4 0 #define MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x0148 0x03d4 0x0000 5 0 #define MX6UL_PAD_LCD_DATA12__SRC_BT_CFG12 0x0148 0x03d4 0x0000 6 0 #define MX6UL_PAD_LCD_DATA12__ECSPI1_RDY 0x0148 0x03d4 0x0000 8 0 #define MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x014c 0x03d8 0x0000 0 0 #define MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK 0x014c 0x03d8 0x0608 1 1 -#define MX6UL_PAD_LCD_DATA13__CSI_DATA21 0x014c 0x03d8 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA13__CA7_MX6UL_TRACE13 0x014c 0x03d8 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA13__CSI_DATA21 0x014c 0x03d8 0x0518 3 1 #define MX6UL_PAD_LCD_DATA13__EIM_DATA05 0x014c 0x03d8 0x0000 4 0 #define MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x014c 0x03d8 0x0000 5 0 #define MX6UL_PAD_LCD_DATA13__SRC_BT_CFG13 0x014c 0x03d8 0x0000 6 0 #define MX6UL_PAD_LCD_DATA13__USDHC2_RESET_B 0x014c 0x03d8 0x0000 8 0 #define MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x0150 0x03dc 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA 0x0150 0x03dc 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA14__CSI_DATA22 0x0150 0x03dc 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA 0x0150 0x03dc 0x0604 1 1 +#define MX6UL_PAD_LCD_DATA14__CA7_MX6UL_TRACE14 0x0150 0x03dc 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA14__CSI_DATA22 0x0150 0x03dc 0x051c 3 1 #define MX6UL_PAD_LCD_DATA14__EIM_DATA06 0x0150 0x03dc 0x0000 4 0 #define MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x0150 0x03dc 0x0000 5 0 #define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14 0x0150 0x03dc 0x0000 6 0 #define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4 0x0150 0x03dc 0x068c 8 0 #define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x0154 0x03e0 0x0000 0 0 #define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA 0x0154 0x03e0 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA15__CSI_DATA23 0x0154 0x03e0 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA15__CA7_MX6UL_TRACE15 0x0154 0x03e0 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA15__CSI_DATA23 0x0154 0x03e0 0x0520 3 1 #define MX6UL_PAD_LCD_DATA15__EIM_DATA07 0x0154 0x03e0 0x0000 4 0 #define MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x0154 0x03e0 0x0000 5 0 #define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15 0x0154 0x03e0 0x0000 6 0 @@ -594,7 +617,8 @@ #define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x0158 0x03e4 0x0000 0 0 #define MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x0158 0x03e4 0x0000 1 0 #define MX6UL_PAD_LCD_DATA16__UART7_DTE_RX 0x0158 0x03e4 0x0654 1 2 -#define MX6UL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x03e4 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA16__CA7_MX6UL_TRACE_CLK 0x0158 0x03e4 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x03e4 0x04d4 3 1 #define MX6UL_PAD_LCD_DATA16__EIM_DATA08 0x0158 0x03e4 0x0000 4 0 #define MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x0158 0x03e4 0x0000 5 0 #define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24 0x0158 0x03e4 0x0000 6 0 @@ -602,7 +626,8 @@ #define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x015c 0x03e8 0x0000 0 0 #define MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x015c 0x03e8 0x0654 1 3 #define MX6UL_PAD_LCD_DATA17__UART7_DTE_TX 0x015c 0x03e8 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA17__CSI_DATA00 0x015c 0x03e8 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA17__CA7_MX6UL_TRACE_CTL 0x015c 0x03e8 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA17__CSI_DATA00 0x015c 0x03e8 0x04d0 3 1 #define MX6UL_PAD_LCD_DATA17__EIM_DATA09 0x015c 0x03e8 0x0000 4 0 #define MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x015c 0x03e8 0x0000 5 0 #define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25 0x015c 0x03e8 0x0000 6 0 @@ -610,7 +635,7 @@ #define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x0160 0x03ec 0x0000 0 0 #define MX6UL_PAD_LCD_DATA18__PWM5_OUT 0x0160 0x03ec 0x0000 1 0 #define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO 0x0160 0x03ec 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA18__CSI_DATA10 0x0160 0x03ec 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA18__CSI_DATA10 0x0160 0x03ec 0x04ec 3 1 #define MX6UL_PAD_LCD_DATA18__EIM_DATA10 0x0160 0x03ec 0x0000 4 0 #define MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x0160 0x03ec 0x0000 5 0 #define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26 0x0160 0x03ec 0x0000 6 0 @@ -622,7 +647,7 @@ #define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x0164 0x03f0 0x0000 0 0 #define MX6UL_PAD_LCD_DATA19__PWM6_OUT 0x0164 0x03f0 0x0000 1 0 #define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY 0x0164 0x03f0 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA19__CSI_DATA11 0x0164 0x03f0 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA19__CSI_DATA11 0x0164 0x03f0 0x04f0 3 1 #define MX6UL_PAD_LCD_DATA20__EIM_DATA12 0x0168 0x03f4 0x0000 4 0 #define MX6UL_PAD_LCD_DATA20__GPIO3_IO25 0x0168 0x03f4 0x0000 5 0 #define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28 0x0168 0x03f4 0x0000 6 0 @@ -631,12 +656,12 @@ #define MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x0168 0x03f4 0x0000 1 0 #define MX6UL_PAD_LCD_DATA20__UART8_DTE_RX 0x0168 0x03f4 0x065c 1 2 #define MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x0168 0x03f4 0x0534 2 0 -#define MX6UL_PAD_LCD_DATA20__CSI_DATA12 0x0168 0x03f4 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA20__CSI_DATA12 0x0168 0x03f4 0x04f4 3 1 #define MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x016c 0x03f8 0x0000 0 0 #define MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x016c 0x03f8 0x065c 1 3 #define MX6UL_PAD_LCD_DATA21__UART8_DTE_TX 0x016c 0x03f8 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0 0x016c 0x03f8 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA21__CSI_DATA13 0x016c 0x03f8 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0 0x016c 0x03f8 0x0540 2 0 +#define MX6UL_PAD_LCD_DATA21__CSI_DATA13 0x016c 0x03f8 0x04f8 3 1 #define MX6UL_PAD_LCD_DATA21__EIM_DATA13 0x016c 0x03f8 0x0000 4 0 #define MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x016c 0x03f8 0x0000 5 0 #define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29 0x016c 0x03f8 0x0000 6 0 @@ -644,7 +669,7 @@ #define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x0170 0x03fc 0x0000 0 0 #define MX6UL_PAD_LCD_DATA22__MQS_RIGHT 0x0170 0x03fc 0x0000 1 0 #define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x0170 0x03fc 0x053c 2 0 -#define MX6UL_PAD_LCD_DATA22__CSI_DATA14 0x0170 0x03fc 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA22__CSI_DATA14 0x0170 0x03fc 0x04fc 3 1 #define MX6UL_PAD_LCD_DATA22__EIM_DATA14 0x0170 0x03fc 0x0000 4 0 #define MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0x0170 0x03fc 0x0000 5 0 #define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30 0x0170 0x03fc 0x0000 6 0 @@ -652,7 +677,7 @@ #define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x0174 0x0400 0x0000 0 0 #define MX6UL_PAD_LCD_DATA23__MQS_LEFT 0x0174 0x0400 0x0000 1 0 #define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x0174 0x0400 0x0538 2 0 -#define MX6UL_PAD_LCD_DATA23__CSI_DATA15 0x0174 0x0400 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA23__CSI_DATA15 0x0174 0x0400 0x0500 3 1 #define MX6UL_PAD_LCD_DATA23__EIM_DATA15 0x0174 0x0400 0x0000 4 0 #define MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0x0174 0x0400 0x0000 5 0 #define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31 0x0174 0x0400 0x0000 6 0 @@ -660,42 +685,42 @@ #define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0178 0x0404 0x0000 0 0 #define MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x0178 0x0404 0x0670 1 2 #define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x0178 0x0404 0x0000 2 0 -#define MX6UL_PAD_NAND_RE_B__KPP_ROW00 0x0178 0x0404 0x0000 3 0 +#define MX6UL_PAD_NAND_RE_B__KPP_ROW00 0x0178 0x0404 0x05d0 3 1 #define MX6UL_PAD_NAND_RE_B__EIM_EB_B00 0x0178 0x0404 0x0000 4 0 #define MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0178 0x0404 0x0000 5 0 #define MX6UL_PAD_NAND_RE_B__ECSPI3_SS2 0x0178 0x0404 0x0000 8 0 #define MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x017c 0x0408 0x0000 0 0 #define MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x017c 0x0408 0x0678 1 2 #define MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x017c 0x0408 0x0000 2 0 -#define MX6UL_PAD_NAND_WE_B__KPP_COL00 0x017c 0x0408 0x0000 3 0 +#define MX6UL_PAD_NAND_WE_B__KPP_COL00 0x017c 0x0408 0x05c4 3 1 #define MX6UL_PAD_NAND_WE_B__EIM_EB_B01 0x017c 0x0408 0x0000 4 0 #define MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x017c 0x0408 0x0000 5 0 #define MX6UL_PAD_NAND_WE_B__ECSPI3_SS3 0x017c 0x0408 0x0000 8 0 #define MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0180 0x040c 0x0000 0 0 #define MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x0180 0x040c 0x067c 1 2 #define MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x0180 0x040c 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA00__KPP_ROW01 0x0180 0x040c 0x0000 3 0 +#define MX6UL_PAD_NAND_DATA00__KPP_ROW01 0x0180 0x040c 0x05d4 3 1 #define MX6UL_PAD_NAND_DATA00__EIM_AD08 0x0180 0x040c 0x0000 4 0 #define MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x0180 0x040c 0x0000 5 0 #define MX6UL_PAD_NAND_DATA00__ECSPI4_RDY 0x0180 0x040c 0x0000 8 0 #define MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0184 0x0410 0x0000 0 0 #define MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x0184 0x0410 0x0680 1 2 #define MX6UL_PAD_NAND_DATA01__QSPI_B_DQS 0x0184 0x0410 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA01__KPP_COL01 0x0184 0x0410 0x0000 3 0 +#define MX6UL_PAD_NAND_DATA01__KPP_COL01 0x0184 0x0410 0x05c8 3 1 #define MX6UL_PAD_NAND_DATA01__EIM_AD09 0x0184 0x0410 0x0000 4 0 #define MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x0184 0x0410 0x0000 5 0 #define MX6UL_PAD_NAND_DATA01__ECSPI4_SS1 0x0184 0x0410 0x0000 8 0 #define MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0188 0x0414 0x0000 0 0 #define MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x0188 0x0414 0x0684 1 1 #define MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x0188 0x0414 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA02__KPP_ROW02 0x0188 0x0414 0x0000 3 0 +#define MX6UL_PAD_NAND_DATA02__KPP_ROW02 0x0188 0x0414 0x05d8 3 1 #define MX6UL_PAD_NAND_DATA02__EIM_AD10 0x0188 0x0414 0x0000 4 0 #define MX6UL_PAD_NAND_DATA02__GPIO4_IO04 0x0188 0x0414 0x0000 5 0 #define MX6UL_PAD_NAND_DATA02__ECSPI4_SS2 0x0188 0x0414 0x0000 8 0 #define MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x018c 0x0418 0x0000 0 0 #define MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x018c 0x0418 0x0688 1 2 #define MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x018c 0x0418 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA03__KPP_COL02 0x018c 0x0418 0x0000 3 0 +#define MX6UL_PAD_NAND_DATA03__KPP_COL02 0x018c 0x0418 0x05cc 3 1 #define MX6UL_PAD_NAND_DATA03__EIM_AD11 0x018c 0x0418 0x0000 4 0 #define MX6UL_PAD_NAND_DATA03__GPIO4_IO05 0x018c 0x0418 0x0000 5 0 #define MX6UL_PAD_NAND_DATA03__ECSPI4_SS3 0x018c 0x0418 0x0000 8 0 @@ -726,7 +751,7 @@ #define MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x019c 0x0428 0x0000 0 0 #define MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x019c 0x0428 0x0698 1 1 #define MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x019c 0x0428 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0 0x019c 0x0428 0x0000 3 0 +#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0 0x019c 0x0428 0x0570 3 1 #define MX6UL_PAD_NAND_DATA07__EIM_AD15 0x019c 0x0428 0x0000 4 0 #define MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x019c 0x0428 0x0000 5 0 #define MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x019c 0x0428 0x0628 8 5 @@ -748,7 +773,7 @@ #define MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x01a8 0x0434 0x0000 0 0 #define MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x01a8 0x0434 0x0000 1 0 #define MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x01a8 0x0434 0x0000 2 0 -#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0 0x01a8 0x0434 0x0000 3 0 +#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0 0x01a8 0x0434 0x0560 3 1 #define MX6UL_PAD_NAND_READY_B__EIM_CS1_B 0x01a8 0x0434 0x0000 4 0 #define MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x01a8 0x0434 0x0000 5 0 #define MX6UL_PAD_NAND_READY_B__UART3_DCE_TX 0x01a8 0x0434 0x0000 8 0 @@ -783,7 +808,7 @@ #define MX6UL_PAD_NAND_DQS__PWM5_OUT 0x01b8 0x0444 0x0000 3 0 #define MX6UL_PAD_NAND_DQS__EIM_WAIT 0x01b8 0x0444 0x0000 4 0 #define MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x01b8 0x0444 0x0000 5 0 -#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01 0x01b8 0x0444 0x0000 6 0 +#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01 0x01b8 0x0444 0x0614 6 1 #define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK 0x01b8 0x0444 0x061c 8 1 #define MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x01bc 0x0448 0x0000 0 0 #define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1 0x01bc 0x0448 0x0000 1 0 @@ -791,11 +816,11 @@ #define MX6UL_PAD_SD1_CMD__SPDIF_OUT 0x01bc 0x0448 0x0000 3 0 #define MX6UL_PAD_SD1_CMD__EIM_ADDR19 0x01bc 0x0448 0x0000 4 0 #define MX6UL_PAD_SD1_CMD__GPIO2_IO16 0x01bc 0x0448 0x0000 5 0 -#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00 0x01bc 0x0448 0x0000 6 0 +#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00 0x01bc 0x0448 0x0610 6 2 #define MX6UL_PAD_SD1_CMD__USB_OTG1_PWR 0x01bc 0x0448 0x0000 8 0 #define MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x01c0 0x044c 0x0000 0 0 #define MX6UL_PAD_SD1_CLK__GPT2_COMPARE2 0x01c0 0x044c 0x0000 1 0 -#define MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x01c0 0x044c 0x0000 2 0 +#define MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x01c0 0x044c 0x05f0 2 1 #define MX6UL_PAD_SD1_CLK__SPDIF_IN 0x01c0 0x044c 0x0618 3 3 #define MX6UL_PAD_SD1_CLK__EIM_ADDR20 0x01c0 0x044c 0x0000 4 0 #define MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x01c0 0x044c 0x0000 5 0 @@ -878,10 +903,10 @@ #define MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x01e8 0x0474 0x04c8 0 0 #define MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x01e8 0x0474 0x0680 1 0 #define MX6UL_PAD_CSI_DATA01__SIM1_PORT1_SVEN 0x01e8 0x0474 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0 0x01e8 0x0474 0x0000 3 0 +#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0 0x01e8 0x0474 0x0550 3 0 #define MX6UL_PAD_CSI_DATA01__EIM_AD01 0x01e8 0x0474 0x0000 4 0 #define MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x01e8 0x0474 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x01e8 0x0474 0x0000 6 0 +#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x01e8 0x0474 0x05e0 6 0 #define MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x01e8 0x0474 0x0644 8 1 #define MX6UL_PAD_CSI_DATA01__UART5_DTE_TX 0x01e8 0x0474 0x0000 8 0 #define MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x01ec 0x0478 0x04d8 0 1 @@ -913,7 +938,7 @@ #define MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x01f8 0x0484 0x04e0 0 1 #define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5 0x01f8 0x0484 0x0690 1 2 #define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0x01f8 0x0484 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0 0x01f8 0x0484 0x0000 3 0 +#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0 0x01f8 0x0484 0x0540 3 1 #define MX6UL_PAD_CSI_DATA05__EIM_AD05 0x01f8 0x0484 0x0000 4 0 #define MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x01f8 0x0484 0x0000 5 0 #define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x01f8 0x0484 0x05e8 6 1 @@ -924,7 +949,7 @@ #define MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x01fc 0x0488 0x053c 3 1 #define MX6UL_PAD_CSI_DATA06__EIM_AD06 0x01fc 0x0488 0x0000 4 0 #define MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x01fc 0x0488 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x01fc 0x0488 0x0000 6 0 +#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x01fc 0x0488 0x05e4 6 1 #define MX6UL_PAD_CSI_DATA06__USDHC1_RESET_B 0x01fc 0x0488 0x0000 8 0 #define MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x0200 0x048c 0x04e8 0 1 #define MX6UL_PAD_CSI_DATA07__USDHC2_DATA7 0x0200 0x048c 0x0698 1 2 Index: sys/gnu/dts/arm/imx6ul-tx6ul.dtsi =================================================================== --- sys/gnu/dts/arm/imx6ul-tx6ul.dtsi +++ sys/gnu/dts/arm/imx6ul-tx6ul.dtsi @@ -70,8 +70,8 @@ stdout-path = &uart1; }; - memory { - reg = <0 0>; /* will be filled by U-Boot */ + memory@80000000 { + reg = <0x80000000 0>; /* will be filled by U-Boot */ }; clocks { Index: sys/gnu/dts/arm/imx6ul.dtsi =================================================================== --- sys/gnu/dts/arm/imx6ul.dtsi +++ sys/gnu/dts/arm/imx6ul.dtsi @@ -22,7 +22,7 @@ * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; reg = <0 0>; }; + memory { device_type = "memory"; }; aliases { ethernet0 = &fec1; @@ -86,15 +86,10 @@ <&clks IMX6UL_CA7_SECONDARY_SEL>, <&clks IMX6UL_CLK_STEP>, <&clks IMX6UL_CLK_PLL1_SW>, - <&clks IMX6UL_CLK_PLL1_SYS>, - <&clks IMX6UL_PLL1_BYPASS>, - <&clks IMX6UL_CLK_PLL1>, - <&clks IMX6UL_PLL1_BYPASS_SRC>, - <&clks IMX6UL_CLK_OSC>; + <&clks IMX6UL_CLK_PLL1_SYS>; clock-names = "arm", "pll2_bus", "pll2_pfd2_396m", "secondary_sel", "step", "pll1_sw", - "pll1_sys", "pll1_bypass", "pll1", - "pll1_bypass_src", "osc"; + "pll1_sys"; arm-supply = <®_arm>; soc-supply = <®_soc>; }; @@ -102,14 +97,26 @@ intc: interrupt-controller@a01000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; + interrupts = ; #interrupt-cells = <3>; interrupt-controller; + interrupt-parent = <&intc>; reg = <0x00a01000 0x1000>, <0x00a02000 0x2000>, <0x00a04000 0x2000>, <0x00a06000 0x2000>; }; + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + interrupt-parent = <&intc>; + status = "disabled"; + }; + ckil: clock-cli { compatible = "fixed-clock"; #clock-cells = <0>; @@ -924,6 +931,14 @@ status = "disabled"; }; + wdog3: wdog@21e4000 { + compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; + reg = <0x021e4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_WDOG3>; + status = "disabled"; + }; + uart2: serial@21e8000 { compatible = "fsl,imx6ul-uart", "fsl,imx6q-uart"; Index: sys/gnu/dts/arm/imx6ull-14x14-evk.dts =================================================================== --- sys/gnu/dts/arm/imx6ull-14x14-evk.dts +++ sys/gnu/dts/arm/imx6ull-14x14-evk.dts @@ -39,7 +39,10 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "imx6ul-14x14-evk.dts" +/dts-v1/; + +#include "imx6ull.dtsi" +#include "imx6ul-14x14-evk.dtsi" / { model = "Freescale i.MX6 UlltraLite 14x14 EVK Board"; Index: sys/gnu/dts/arm/imx6ull-colibri-eval-v3.dts =================================================================== --- /dev/null +++ sys/gnu/dts/arm/imx6ull-colibri-eval-v3.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2018 Toradex AG + */ + +/dts-v1/; + +#include "imx6ull-colibri-nonwifi.dtsi" +#include "imx6ull-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 256MB on Colibri Evaluation Board V3"; + compatible = "toradex,colibri-imx6ull-eval", "fsl,imx6ull"; +}; Index: sys/gnu/dts/arm/imx6ull-colibri-eval-v3.dtsi =================================================================== --- /dev/null +++ sys/gnu/dts/arm/imx6ull-colibri-eval-v3.dtsi @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 Toradex AG + */ + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; + + /* fixed crystal dedicated to mcp2515 */ + clk16m: clk16m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + }; + + panel: panel { + compatible = "edt,et057090dhu"; + backlight = <&bl>; + power-supply = <®_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&lcdif_out>; + }; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_reg>; + regulator-name = "VCC_USB[1-4]"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + vin-supply = <®_5v0>; + }; +}; + +&adc1 { + status = "okay"; +}; + +&bl { + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + power-supply = <®_3v3>; + pwms = <&pwm4 0 5000000 1>; + status = "okay"; +}; + +&ecspi1 { + status = "okay"; + + mcp2515: can@0 { + compatible = "microchip,mcp2515"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_int>; + reg = <0>; + clocks = <&clk16m>; + interrupt-parent = <&gpio2>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <10000000>; + vdd-supply = <®_3v3>; + xceiver-supply = <®_5v0>; + status = "okay"; + }; +}; + +&i2c1 { + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + m41t0m6: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +&lcdif { + status = "okay"; + + port { + lcdif_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; + +/* PWM */ +&pwm4 { + status = "okay"; +}; + +/* PWM */ +&pwm5 { + status = "okay"; +}; + +/* PWM */ +&pwm6 { + status = "okay"; +}; + +/* PWM */ +&pwm7 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbotg1 { + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; + no-1-8-v; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + disable-wp; + wakeup-source; + keep-power-in-suspend; + vmmc-supply = <®_3v3>; + status = "okay"; +}; Index: sys/gnu/dts/arm/imx6ull-colibri-nonwifi.dtsi =================================================================== --- /dev/null +++ sys/gnu/dts/arm/imx6ull-colibri-nonwifi.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2018 Toradex AG + */ + +#include "imx6ull-colibri.dtsi" + +/ { + memory@80000000 { + reg = <0x80000000 0x10000000>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 + &pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio6>; +}; + +&iomuxc_snvs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio2 &pinctrl_snvs_gpio3>; +}; Index: sys/gnu/dts/arm/imx6ull-colibri-wifi-eval-v3.dts =================================================================== --- /dev/null +++ sys/gnu/dts/arm/imx6ull-colibri-wifi-eval-v3.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2018 Toradex AG + */ + +/dts-v1/; + +#include "imx6ull-colibri-wifi.dtsi" +#include "imx6ull-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 512MB on Colibri Evaluation Board V3"; + compatible = "toradex,colibri-imx6ull-wifi-eval", "fsl,imx6ull"; +}; Index: sys/gnu/dts/arm/imx6ull-colibri-wifi.dtsi =================================================================== --- /dev/null +++ sys/gnu/dts/arm/imx6ull-colibri-wifi.dtsi @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2018 Toradex AG + */ + +#include "imx6ull-colibri.dtsi" + +/ { + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + wifi_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_wifi_pdn>; + reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + }; +}; + +&cpu0 { + clock-frequency = <792000000>; + operating-points = < + /* kHz uV */ + 792000 1225000 + 528000 1175000 + 396000 1025000 + 198000 950000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 792000 1175000 + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 + &pinctrl_gpio4 &pinctrl_gpio5>; + +}; + +&iomuxc_snvs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio2>; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <198000000>; + cap-power-off-card; + keep-power-in-suspend; + mmc-pwrseq = <&wifi_pwrseq>; + no-1-8-v; + non-removable; + vmmc-supply = <®_module_3v3>; + wakeup-source; + status = "okay"; +}; Index: sys/gnu/dts/arm/imx6ull-colibri.dtsi =================================================================== --- /dev/null +++ sys/gnu/dts/arm/imx6ull-colibri.dtsi @@ -0,0 +1,553 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2018 Toradex AG + */ + +#include "imx6ull.dtsi" + +/ { + aliases { + ethernet0 = &fec2; + ethernet1 = &fec1; + }; + + bl: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bl_on>; + enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_module_3v3_avdd: regulator-module-3v3-avdd { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-name = "+V3.3_AVDD_AUDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_sd1_vmmc: regulator-sd1-vmmc { + compatible = "regulator-gpio"; + gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_reg_sd>; + regulator-always-on; + regulator-name = "+V3.3_1.8_SD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <1800000 0x1 3300000 0x0>; + vin-supply = <®_module_3v3>; + }; +}; + +&adc1 { + num-channels = <10>; + vref-supply = <®_module_3v3_avdd>; +}; + +/* Colibri SPI */ +&ecspi1 { + cs-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + max-speed = <100>; + reg = <2>; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + sda-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; + scl-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; +}; + +&i2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + sda-gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; + scl-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + status = "okay"; + + ad7879@2c { + compatible = "adi,ad7879-1"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_ad7879_int>; + reg = <0x2c>; + interrupt-parent = <&gpio5>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + touchscreen-max-pressure = <4096>; + adi,resistance-plate-x = <120>; + adi,first-conversion-delay = /bits/ 8 <3>; + adi,acquisition-time = /bits/ 8 <1>; + adi,median-filter-size = /bits/ 8 <2>; + adi,averaging = /bits/ 8 <1>; + adi,conversion-interval = /bits/ 8 <255>; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + #pwm-cells = <3>; +}; + +&pwm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm5>; + #pwm-cells = <3>; +}; + +&pwm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm6>; + #pwm-cells = <3>; +}; + +&pwm7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm7>; + #pwm-cells = <3>; +}; + +&sdma { + status = "okay"; +}; + +&snvs_pwrkey { + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>; + uart-has-rtscts; + fsl,dte-mode; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + fsl,dte-mode; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + fsl,dte-mode; +}; + +&usbotg1 { + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; +}; + +&usbotg2 { + dr_mode = "host"; +}; + +&usdhc1 { + assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <198000000>; +}; + +&iomuxc { + pinctrl_can_int: canint-grp { + fsl,pins = < + MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0X14 /* SODIMM 73 */ + >; + }; + + pinctrl_enet2: enet2-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + >; + }; + + pinctrl_ecspi1_cs: ecspi1-cs-grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x000a0 + >; + }; + + pinctrl_ecspi1: ecspi1-grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0 + MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0 + MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0 + >; + }; + + pinctrl_flexcan2: flexcan2-grp { + fsl,pins = < + MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_gpio_bl_on: gpio-bl-on-grp { + fsl,pins = < + MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x000a0 + >; + }; + + pinctrl_gpio1: gpio1-grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x74 /* SODIMM 55 */ + MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x74 /* SODIMM 63 */ + MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0X14 /* SODIMM 77 */ + MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x14 /* SODIMM 99 */ + MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x14 /* SODIMM 133 */ + MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x14 /* SODIMM 135 */ + MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x14 /* SODIMM 100 */ + MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x14 /* SODIMM 102 */ + MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x14 /* SODIMM 104 */ + MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x14 /* SODIMM 186 */ + >; + }; + + pinctrl_gpio2: gpio2-grp { /* Camera */ + fsl,pins = < + MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x74 /* SODIMM 69 */ + MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x14 /* SODIMM 75 */ + MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x14 /* SODIMM 85 */ + MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x14 /* SODIMM 96 */ + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x14 /* SODIMM 98 */ + >; + }; + + pinctrl_gpio3: gpio3-grp { /* CAN2 */ + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x14 /* SODIMM 178 */ + MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x14 /* SODIMM 188 */ + >; + }; + + pinctrl_gpio4: gpio4-grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x74 /* SODIMM 65 */ + >; + }; + + pinctrl_gpio5: gpio5-grp { /* ATMEL MXT TOUCH */ + fsl,pins = < + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x74 /* SODIMM 106 */ + >; + }; + + pinctrl_gpio6: gpio6-grp { /* Wifi pins */ + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x14 /* SODIMM 89 */ + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x14 /* SODIMM 79 */ + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x14 /* SODIMM 81 */ + MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x14 /* SODIMM 97 */ + MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x14 /* SODIMM 101 */ + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x14 /* SODIMM 103 */ + MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x14 /* SODIMM 94 */ + >; + }; + + pinctrl_gpmi_nand: gpmi-nand-grp { + fsl,pins = < + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x100a9 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x100a9 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x100a9 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x100a9 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x100a9 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x100a9 + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x100a9 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x100a9 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x100a9 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x100a9 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x100a9 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9 + >; + }; + + pinctrl_i2c1: i2c1-grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2-grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpio-grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0 + >; + }; + + pinctrl_lcdif_dat: lcdif-dat-grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079 + >; + }; + + pinctrl_lcdif_ctrl: lcdif-ctrl-grp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x00079 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079 + >; + }; + + pinctrl_pwm4: pwm4-grp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079 + >; + }; + + pinctrl_pwm5: pwm5-grp { + fsl,pins = < + MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079 + >; + }; + + pinctrl_pwm6: pwm6-grp { + fsl,pins = < + MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079 + >; + }; + + pinctrl_pwm7: pwm7-grp { + fsl,pins = < + MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079 + >; + }; + + pinctrl_uart1: uart1-grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1 + MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x1b0b1 + MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */ + fsl,pins = < + MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x1b0b1 /* DCD */ + MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x1b0b1 /* DSR */ + MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x1b0b1 /* DTR */ + MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x1b0b1 /* RI */ + >; + }; + + pinctrl_uart2: uart2-grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 + >; + }; + pinctrl_uart5: uart5-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1 + MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1 + >; + }; + + pinctrl_usbh_reg: gpio-usbh-reg { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x1b0b1 /* SODIMM 129 USBH PEN */ + >; + }; + + pinctrl_usdhc1: usdhc1-grp { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170b9 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170f9 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2: usdhc2-grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17059 + + MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x14 + >; + }; +}; + +&iomuxc_snvs { + pinctrl_snvs_gpio1: snvs-gpio1-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x14 /* SODIMM 93 */ + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x14 /* SODIMM 95 */ + MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x74 /* SODIMM 105 */ + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x14 /* SODIMM 131 USBH OC */ + MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x74 /* SODIMM 138 */ + >; + }; + + pinctrl_snvs_gpio2: snvs-gpio2-grp { /* ATMEL MXT TOUCH */ + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x74 /* SODIMM 107 */ + >; + }; + + pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */ + fsl,pins = < + MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14 /* SODIMM 127 */ + >; + }; + + pinctrl_snvs_ad7879_int: snvs-ad7879-int-grp { /* TOUCH Interrupt */ + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 + >; + }; + + pinctrl_snvs_reg_sd: snvs-reg-sd-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x4001b8b0 + >; + }; + + pinctrl_snvs_usbc_det: snvs-usbc-det-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 + >; + }; + + pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130b0 + >; + }; + + pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* CD */ + >; + }; + + pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp { + fsl,pins = < + MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14 + >; + }; +}; Index: sys/gnu/dts/arm/imx6ull-pinfunc-snvs.h =================================================================== --- /dev/null +++ sys/gnu/dts/arm/imx6ull-pinfunc-snvs.h @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright (C) 2017 NXP + */ + +#ifndef __DTS_IMX6ULL_PINFUNC_SNVS_H +#define __DTS_IMX6ULL_PINFUNC_SNVS_H +/* + * The pin function ID is a tuple of + * + */ +#define MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x0000 0x0044 0x0000 0x5 0x0 +#define MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x0004 0x0048 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0008 0x004C 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x000C 0x0050 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0010 0x0054 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0014 0x0058 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0018 0x005C 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x001C 0x0060 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0020 0x0064 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0024 0x0068 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0028 0x006C 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x002C 0x0070 0x0000 0x5 0x0 + +#endif /* __DTS_IMX6ULL_PINFUNC_SNVS_H */ Index: sys/gnu/dts/arm/imx6ull.dtsi =================================================================== --- sys/gnu/dts/arm/imx6ull.dtsi +++ sys/gnu/dts/arm/imx6ull.dtsi @@ -41,3 +41,35 @@ #include "imx6ul.dtsi" #include "imx6ull-pinfunc.h" +#include "imx6ull-pinfunc-snvs.h" + +/* Delete UART8 in AIPS-1 (i.MX6UL specific) */ +/delete-node/ &uart8; + +/ { + soc { + aips3: aips-bus@2200000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02200000 0x100000>; + ranges; + + iomuxc_snvs: iomuxc-snvs@2290000 { + compatible = "fsl,imx6ull-iomuxc-snvs"; + reg = <0x02290000 0x4000>; + }; + + uart8: serial@2288000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart"; + reg = <0x02288000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_UART8_IPG>, + <&clks IMX6UL_CLK_UART8_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; + }; +}; Index: sys/gnu/dts/arm/imx7d-cl-som-imx7.dts =================================================================== --- sys/gnu/dts/arm/imx7d-cl-som-imx7.dts +++ sys/gnu/dts/arm/imx7d-cl-som-imx7.dts @@ -18,7 +18,7 @@ model = "CompuLab CL-SOM-iMX7"; compatible = "compulab,cl-som-imx7", "fsl,imx7d"; - memory { + memory@80000000 { reg = <0x80000000 0x10000000>; /* 256 MB - minimal configuration */ }; @@ -213,37 +213,37 @@ &iomuxc { pinctrl_enet1: enet1grp { fsl,pins = < - MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 - MX7D_PAD_SD2_WP__ENET1_MDC 0x3 - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 + MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x30 + MX7D_PAD_SD2_WP__ENET1_MDC 0x30 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x11 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x11 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x11 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x11 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x11 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x11 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x11 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x11 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x11 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x11 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x11 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11 >; }; pinctrl_enet2: enet2grp { fsl,pins = < - MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 - MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 - MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 - MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 - MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 - MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 - MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 - MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 - MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 - MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 - MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 - MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x11 + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x11 + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x11 + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x11 + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x11 + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x11 + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x11 + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x11 + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x11 + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x11 + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x11 + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x11 >; }; Index: sys/gnu/dts/arm/imx7d-colibri-emmc.dtsi =================================================================== --- sys/gnu/dts/arm/imx7d-colibri-emmc.dtsi +++ sys/gnu/dts/arm/imx7d-colibri-emmc.dtsi @@ -7,7 +7,7 @@ #include "imx7-colibri.dtsi" / { - memory { + memory@80000000 { reg = <0x80000000 0x40000000>; }; }; Index: sys/gnu/dts/arm/imx7d-colibri.dtsi =================================================================== --- sys/gnu/dts/arm/imx7d-colibri.dtsi +++ sys/gnu/dts/arm/imx7d-colibri.dtsi @@ -44,7 +44,7 @@ #include "imx7-colibri.dtsi" / { - memory { + memory@80000000 { reg = <0x80000000 0x20000000>; }; }; Index: sys/gnu/dts/arm/imx7d-nitrogen7.dts =================================================================== --- sys/gnu/dts/arm/imx7d-nitrogen7.dts +++ sys/gnu/dts/arm/imx7d-nitrogen7.dts @@ -53,7 +53,7 @@ t_lcd = &t_lcd; }; - memory { + memory@80000000 { reg = <0x80000000 0x40000000>; }; Index: sys/gnu/dts/arm/imx7d-pico.dtsi =================================================================== --- sys/gnu/dts/arm/imx7d-pico.dtsi +++ sys/gnu/dts/arm/imx7d-pico.dtsi @@ -48,7 +48,7 @@ model = "Technexion Pico i.MX7D Board"; compatible = "technexion,imx7d-pico", "fsl,imx7d"; - memory { + memory@80000000 { reg = <0x80000000 0x80000000>; }; Index: sys/gnu/dts/arm/imx7d-sdb.dts =================================================================== --- sys/gnu/dts/arm/imx7d-sdb.dts +++ sys/gnu/dts/arm/imx7d-sdb.dts @@ -48,7 +48,7 @@ model = "Freescale i.MX7 SabreSD Board"; compatible = "fsl,imx7d-sdb", "fsl,imx7d"; - memory { + memory@80000000 { reg = <0x80000000 0x80000000>; }; @@ -336,6 +336,11 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; }; &i2c3 { Index: sys/gnu/dts/arm/imx7s-colibri.dtsi =================================================================== --- sys/gnu/dts/arm/imx7s-colibri.dtsi +++ sys/gnu/dts/arm/imx7s-colibri.dtsi @@ -44,7 +44,7 @@ #include "imx7-colibri.dtsi" / { - memory { + memory@80000000 { reg = <0x80000000 0x10000000>; }; }; Index: sys/gnu/dts/arm/imx7s-warp.dts =================================================================== --- sys/gnu/dts/arm/imx7s-warp.dts +++ sys/gnu/dts/arm/imx7s-warp.dts @@ -50,7 +50,7 @@ model = "Warp i.MX7 Board"; compatible = "warp,imx7s-warp", "fsl,imx7s"; - memory { + memory@80000000 { reg = <0x80000000 0x20000000>; }; @@ -271,6 +271,15 @@ status = "okay"; }; +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + fsl,dte-mode; + status = "okay"; +}; + &usbotg1 { dr_mode = "peripheral"; status = "okay"; @@ -379,6 +388,13 @@ >; }; + pinctrl_uart6: uart6grp { + fsl,pins = < + MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX 0x79 + MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX 0x79 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX7D_PAD_SD1_CMD__SD1_CMD 0x59 Index: sys/gnu/dts/arm/imx7s.dtsi =================================================================== --- sys/gnu/dts/arm/imx7s.dtsi +++ sys/gnu/dts/arm/imx7s.dtsi @@ -58,7 +58,7 @@ * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; reg = <0 0>; }; + memory { device_type = "memory"; }; aliases { gpio0 = &gpio1; @@ -130,6 +130,12 @@ #phy-cells = <0>; }; + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupt-parent = <&gpc>; + interrupts = ; + interrupt-affinity = <&cpu0>; + }; replicator { /* @@ -499,6 +505,14 @@ status = "disabled"; }; + kpp: kpp@30320000 { + compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp"; + reg = <0x30320000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_KPP_ROOT_CLK>; + status = "disabled"; + }; + iomuxc: iomuxc@30330000 { compatible = "fsl,imx7d-iomuxc"; reg = <0x30330000 0x10000>; @@ -511,9 +525,29 @@ }; ocotp: ocotp-ctrl@30350000 { + #address-cells = <1>; + #size-cells = <1>; compatible = "fsl,imx7d-ocotp", "syscon"; reg = <0x30350000 0x10000>; clocks = <&clks IMX7D_OCOTP_CLK>; + + tempmon_calib: calib@3c { + reg = <0x3c 0x4>; + }; + + tempmon_temp_grade: temp-grade@10 { + reg = <0x10 0x4>; + }; + }; + + tempmon: tempmon { + compatible = "fsl,imx7d-tempmon"; + interrupts = ; + fsl,tempmon =<&anatop>; + nvmem-cells = <&tempmon_calib>, + <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; }; anatop: anatop@30360000 { @@ -551,6 +585,8 @@ offset = <0x34>; interrupts = , ; + clocks = <&clks IMX7D_SNVS_CLK>; + clock-names = "snvs-rtc"; }; snvs_poweroff: snvs-poweroff { @@ -708,118 +744,157 @@ reg = <0x30800000 0x400000>; ranges; - ecspi1: ecspi@30820000 { + spba-bus@30800000 { + compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; - reg = <0x30820000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, - <&clks IMX7D_ECSPI1_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; + #size-cells = <1>; + reg = <0x30800000 0x100000>; + ranges; - ecspi2: ecspi@30830000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; - reg = <0x30830000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, - <&clks IMX7D_ECSPI2_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; + ecspi1: ecspi@30820000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; + reg = <0x30820000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, + <&clks IMX7D_ECSPI1_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; - ecspi3: ecspi@30840000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; - reg = <0x30840000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, - <&clks IMX7D_ECSPI3_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; + ecspi2: ecspi@30830000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; + reg = <0x30830000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, + <&clks IMX7D_ECSPI2_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; - uart1: serial@30860000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30860000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_UART1_ROOT_CLK>, - <&clks IMX7D_UART1_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; + ecspi3: ecspi@30840000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; + reg = <0x30840000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, + <&clks IMX7D_ECSPI3_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; - uart2: serial@30890000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30890000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_UART2_ROOT_CLK>, - <&clks IMX7D_UART2_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; + uart1: serial@30860000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30860000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_UART1_ROOT_CLK>, + <&clks IMX7D_UART1_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; - uart3: serial@30880000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30880000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_UART3_ROOT_CLK>, - <&clks IMX7D_UART3_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; + uart2: serial@30890000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30890000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_UART2_ROOT_CLK>, + <&clks IMX7D_UART2_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; - sai1: sai@308a0000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; - reg = <0x308a0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_SAI1_IPG_CLK>, - <&clks IMX7D_SAI1_ROOT_CLK>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "rx", "tx"; - dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; - status = "disabled"; - }; + uart3: serial@30880000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30880000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_UART3_ROOT_CLK>, + <&clks IMX7D_UART3_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; - sai2: sai@308b0000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; - reg = <0x308b0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_SAI2_IPG_CLK>, - <&clks IMX7D_SAI2_ROOT_CLK>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "rx", "tx"; - dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; - status = "disabled"; + sai1: sai@308a0000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; + reg = <0x308a0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_SAI1_IPG_CLK>, + <&clks IMX7D_SAI1_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; + status = "disabled"; + }; + + sai2: sai@308b0000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; + reg = <0x308b0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_SAI2_IPG_CLK>, + <&clks IMX7D_SAI2_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; + status = "disabled"; + }; + + sai3: sai@308c0000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; + reg = <0x308c0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_SAI3_IPG_CLK>, + <&clks IMX7D_SAI3_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; + status = "disabled"; + }; }; - sai3: sai@308c0000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; - reg = <0x308c0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_SAI3_IPG_CLK>, - <&clks IMX7D_SAI3_ROOT_CLK>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "rx", "tx"; - dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; - status = "disabled"; + crypto: caam@30900000 { + compatible = "fsl,sec-v4.0"; + fsl,sec-era = <8>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30900000 0x40000>; + ranges = <0 0x30900000 0x40000>; + interrupts = ; + clocks = <&clks IMX7D_CAAM_CLK>, + <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; + clock-names = "ipg", "aclk"; + + sec_jr0: jr0@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = ; + }; + + sec_jr1: jr1@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = ; + }; + + sec_jr2: jr1@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = ; + }; }; flexcan1: can@30a00000 { Index: sys/gnu/dts/arm/keystone-k2e-clocks.dtsi =================================================================== --- sys/gnu/dts/arm/keystone-k2e-clocks.dtsi +++ sys/gnu/dts/arm/keystone-k2e-clocks.dtsi @@ -42,7 +42,7 @@ domain-id = <0>; }; - clkhyperlink0: clkhyperlink02350030 { + clkhyperlink0: clkhyperlink0@2350030 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk12>; Index: sys/gnu/dts/arm/keystone-k2e.dtsi =================================================================== --- sys/gnu/dts/arm/keystone-k2e.dtsi +++ sys/gnu/dts/arm/keystone-k2e.dtsi @@ -109,11 +109,14 @@ }; }; - dspgpio0: keystone_dsp_gpio@2620240 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x240>; + devctrl: device-state-control@2620000 { + dspgpio0: keystone_dsp_gpio@240 { + compatible = "ti,keystone-dsp-gpio"; + reg = <0x240 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x240>; + }; }; dsp0: dsp@10800000 { Index: sys/gnu/dts/arm/keystone-k2g.dtsi =================================================================== --- sys/gnu/dts/arm/keystone-k2g.dtsi +++ sys/gnu/dts/arm/keystone-k2g.dtsi @@ -69,6 +69,24 @@ interrupts = ; }; + usbphy { + #address-cells = <1>; + #size-cells = <0>; + compatible = "simple-bus"; + + usb0_phy: usb-phy@0 { + compatible = "usb-nop-xceiv"; + reg = <0>; + status = "disabled"; + }; + + usb1_phy: usb-phy@1 { + compatible = "usb-nop-xceiv"; + reg = <1>; + status = "disabled"; + }; + }; + soc0: soc@0 { #address-cells = <1>; #size-cells = <1>; @@ -97,8 +115,28 @@ }; devctrl: device-state-control@2620000 { - compatible = "ti,keystone-devctrl", "syscon"; + compatible = "ti,keystone-devctrl", "syscon", "simple-mfd"; reg = <0x02620000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x02620000 0x1000>; + + kirq0: keystone_irq@2a0 { + compatible = "ti,keystone-irq"; + reg = <0x2a0 0x10>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + ti,syscon-dev = <&devctrl 0x2a0>; + }; + + dspgpio0: keystone_dsp_gpio@240 { + compatible = "ti,keystone-dsp-gpio"; + reg = <0x240 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x240>; + }; }; uart0: serial@2530c00 { @@ -113,7 +151,7 @@ status = "disabled"; }; - uart1: serial@02531000 { + uart1: serial@2531000 { compatible = "ti,da830-uart", "ns16550a"; current-speed = <115200>; reg-shift = <2>; @@ -125,7 +163,7 @@ status = "disabled"; }; - uart2: serial@02531400 { + uart2: serial@2531400 { compatible = "ti,da830-uart", "ns16550a"; current-speed = <115200>; reg-shift = <2>; @@ -188,21 +226,6 @@ status = "disabled"; }; - kirq0: keystone_irq@26202a0 { - compatible = "ti,keystone-irq"; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - ti,syscon-dev = <&devctrl 0x2a0>; - }; - - dspgpio0: keystone_dsp_gpio@2620240 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x240>; - }; - dsp0: dsp@10800000 { compatible = "ti,k2g-dsp"; reg = <0x10800000 0x00100000>, @@ -460,11 +483,6 @@ status = "disabled"; }; - usb0_phy: usb-phy@0 { - compatible = "usb-nop-xceiv"; - status = "disabled"; - }; - keystone_usb0: keystone-dwc3@2680000 { compatible = "ti,keystone-dwc3"; #address-cells = <1>; @@ -488,11 +506,6 @@ }; }; - usb1_phy: usb-phy@1 { - compatible = "usb-nop-xceiv"; - status = "disabled"; - }; - keystone_usb1: keystone-dwc3@2580000 { compatible = "ti,keystone-dwc3"; #address-cells = <1>; @@ -583,5 +596,18 @@ power-domains = <&k2g_pds 0x0013>; clocks = <&k2g_clks 0x0013 0>; }; + + wdt: wdt@02250000 { + compatible = "ti,keystone-wdt", "ti,davinci-wdt"; + reg = <0x02250000 0x80>; + power-domains = <&k2g_pds 0x22>; + clocks = <&k2g_clks 0x22 0>; + }; + + emif: emif@21010000 { + compatible = "ti,emif-keystone"; + reg = <0x21010000 0x200>; + interrupts = ; + }; }; }; Index: sys/gnu/dts/arm/keystone-k2hk.dtsi =================================================================== --- sys/gnu/dts/arm/keystone-k2hk.dtsi +++ sys/gnu/dts/arm/keystone-k2hk.dtsi @@ -87,60 +87,70 @@ }; }; - dspgpio0: keystone_dsp_gpio@2620240 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x240>; - }; + devctrl: device-state-control@2620000 { + dspgpio0: keystone_dsp_gpio@240 { + compatible = "ti,keystone-dsp-gpio"; + reg = <0x240 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x240>; + }; - dspgpio1: keystone_dsp_gpio@2620244 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x244>; - }; + dspgpio1: keystone_dsp_gpio@244 { + compatible = "ti,keystone-dsp-gpio"; + reg = <0x244 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x244>; + }; - dspgpio2: keystone_dsp_gpio@2620248 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x248>; - }; + dspgpio2: keystone_dsp_gpio@248 { + compatible = "ti,keystone-dsp-gpio"; + reg = <0x248 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x248>; + }; - dspgpio3: keystone_dsp_gpio@262024c { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x24c>; - }; + dspgpio3: keystone_dsp_gpio@24c { + compatible = "ti,keystone-dsp-gpio"; + reg = <0x24c 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x24c>; + }; - dspgpio4: keystone_dsp_gpio@2620250 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x250>; - }; + dspgpio4: keystone_dsp_gpio@250 { + compatible = "ti,keystone-dsp-gpio"; + reg = <0x250 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x250>; + }; - dspgpio5: keystone_dsp_gpio@2620254 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x254>; - }; + dspgpio5: keystone_dsp_gpio@254 { + compatible = "ti,keystone-dsp-gpio"; + reg = <0x254 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x254>; + }; - dspgpio6: keystone_dsp_gpio@2620258 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x258>; - }; + dspgpio6: keystone_dsp_gpio@258 { + compatible = "ti,keystone-dsp-gpio"; + reg = <0x258 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x258>; + }; - dspgpio7: keystone_dsp_gpio@262025c { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x25c>; + dspgpio7: keystone_dsp_gpio@25c { + compatible = "ti,keystone-dsp-gpio"; + reg = <0x25c 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x25c>; + }; }; dsp0: dsp@10800000 { Index: sys/gnu/dts/arm/keystone-k2l.dtsi =================================================================== --- sys/gnu/dts/arm/keystone-k2l.dtsi +++ sys/gnu/dts/arm/keystone-k2l.dtsi @@ -289,32 +289,38 @@ clocks = <&clkosr>; }; - dspgpio0: keystone_dsp_gpio@2620240 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x240>; - }; + devctrl: device-state-control@2620000 { + dspgpio0: keystone_dsp_gpio@240 { + compatible = "ti,keystone-dsp-gpio"; + reg = <0x240 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x240>; + }; - dspgpio1: keystone_dsp_gpio@2620244 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x244>; - }; + dspgpio1: keystone_dsp_gpio@244 { + compatible = "ti,keystone-dsp-gpio"; + reg = <0x244 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x244>; + }; - dspgpio2: keystone_dsp_gpio@2620248 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x248>; - }; + dspgpio2: keystone_dsp_gpio@248 { + compatible = "ti,keystone-dsp-gpio"; + reg = <0x248 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x248>; + }; - dspgpio3: keystone_dsp_gpio@262024c { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x24c>; + dspgpio3: keystone_dsp_gpio@24c { + compatible = "ti,keystone-dsp-gpio"; + reg = <0x24c 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x24c>; + }; }; dsp0: dsp@10800000 { Index: sys/gnu/dts/arm/keystone.dtsi =================================================================== --- sys/gnu/dts/arm/keystone.dtsi +++ sys/gnu/dts/arm/keystone.dtsi @@ -87,15 +87,28 @@ }; devctrl: device-state-control@2620000 { - compatible = "ti,keystone-devctrl", "syscon"; + compatible = "ti,keystone-devctrl", "syscon", "simple-mfd"; reg = <0x02620000 0x1000>; - }; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x02620000 0x1000>; + + kirq0: keystone_irq@2a0 { + compatible = "ti,keystone-irq"; + reg = <0x2a0 0x4>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + ti,syscon-dev = <&devctrl 0x2a0>; + }; - rstctrl: reset-controller { - compatible = "ti,keystone-reset"; - ti,syscon-pll = <&pllctrl 0xe4>; - ti,syscon-dev = <&devctrl 0x328>; - ti,wdt-list = <0>; + rstctrl: reset-controller@328 { + compatible = "ti,keystone-reset"; + reg = <0x328 0x10>; + ti,syscon-pll = <&pllctrl 0xe4>; + ti,syscon-dev = <&devctrl 0x328>; + ti,wdt-list = <0>; + }; }; /include/ "keystone-clocks.dtsi" @@ -282,14 +295,6 @@ 1 0 0x21000A00 0x00000100>; }; - kirq0: keystone_irq@26202a0 { - compatible = "ti,keystone-irq"; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - ti,syscon-dev = <&devctrl 0x2a0>; - }; - pcie0: pcie@21800000 { compatible = "ti,keystone-pcie", "snps,dw-pcie"; clocks = <&clkpcie>; @@ -338,5 +343,12 @@ ; }; }; + + emif: emif@21010000 { + compatible = "ti,emif-keystone"; + reg = <0x21010000 0x200>; + interrupts = ; + interrupt-parent = <&gic>; + }; }; }; Index: sys/gnu/dts/arm/kirkwood-b3.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-b3.dts +++ sys/gnu/dts/arm/kirkwood-b3.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Device Tree file for Excito Bubba B3 * * Copyright (C) 2013, Andrew Lunn * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. * * Note: This requires a new'ish version of u-boot, which disables the * L2 cache. If your B3 silently fails to boot, u-boot is probably too Index: sys/gnu/dts/arm/kirkwood-blackarmor-nas220.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-blackarmor-nas220.dts +++ sys/gnu/dts/arm/kirkwood-blackarmor-nas220.dts @@ -1,9 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Device Tree file for Seagate Blackarmor NAS220 * * Copyright (C) 2014 Evgeni Dobrev - * - * Licensed under GPLv2 or later. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-d2net.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-d2net.dts +++ sys/gnu/dts/arm/kirkwood-d2net.dts @@ -1,11 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree file for d2 Network v2 * * Copyright (C) 2014 Simon Guinot * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-db-88f6281.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-db-88f6281.dts +++ sys/gnu/dts/arm/kirkwood-db-88f6281.dts @@ -1,12 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Marvell DB-88F6281-BP Development Board Setup * * Saeed Bishara * Thomas Petazzoni * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-db-88f6282.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-db-88f6282.dts +++ sys/gnu/dts/arm/kirkwood-db-88f6282.dts @@ -1,12 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Marvell DB-88F6282-BP Development Board Setup * * Saeed Bishara * Thomas Petazzoni * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-db.dtsi =================================================================== --- sys/gnu/dts/arm/kirkwood-db.dtsi +++ sys/gnu/dts/arm/kirkwood-db.dtsi @@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Marvell DB-{88F6281,88F6282}-BP Development Board Setup * * Saeed Bishara * Thomas Petazzoni * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * * This file contains the definitions that are common between the 6281 * and 6282 variants of the Marvell Kirkwood Development Board. */ Index: sys/gnu/dts/arm/kirkwood-dir665.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-dir665.dts +++ sys/gnu/dts/arm/kirkwood-dir665.dts @@ -1,9 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2014 Claudio Leite * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-ds109.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-ds109.dts +++ sys/gnu/dts/arm/kirkwood-ds109.dts @@ -1,10 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Andrew Lunn * Ben Peddell * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-ds110jv10.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-ds110jv10.dts +++ sys/gnu/dts/arm/kirkwood-ds110jv10.dts @@ -1,10 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Andrew Lunn * Ben Peddell * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-ds111.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-ds111.dts +++ sys/gnu/dts/arm/kirkwood-ds111.dts @@ -1,10 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Andrew Lunn * Ben Peddell * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-ds112.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-ds112.dts +++ sys/gnu/dts/arm/kirkwood-ds112.dts @@ -1,10 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Andrew Lunn * Ben Peddell * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-ds209.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-ds209.dts +++ sys/gnu/dts/arm/kirkwood-ds209.dts @@ -1,10 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Andrew Lunn * Ben Peddell * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-ds210.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-ds210.dts +++ sys/gnu/dts/arm/kirkwood-ds210.dts @@ -1,10 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Andrew Lunn * Ben Peddell * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-ds212.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-ds212.dts +++ sys/gnu/dts/arm/kirkwood-ds212.dts @@ -1,10 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Andrew Lunn * Ben Peddell * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-ds212j.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-ds212j.dts +++ sys/gnu/dts/arm/kirkwood-ds212j.dts @@ -1,10 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Andrew Lunn * Ben Peddell * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-ds409.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-ds409.dts +++ sys/gnu/dts/arm/kirkwood-ds409.dts @@ -1,10 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Andrew Lunn * Ben Peddell * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-ds409slim.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-ds409slim.dts +++ sys/gnu/dts/arm/kirkwood-ds409slim.dts @@ -1,10 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Andrew Lunn * Ben Peddell * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-ds411.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-ds411.dts +++ sys/gnu/dts/arm/kirkwood-ds411.dts @@ -1,10 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Andrew Lunn * Ben Peddell * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-ds411j.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-ds411j.dts +++ sys/gnu/dts/arm/kirkwood-ds411j.dts @@ -1,10 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Andrew Lunn * Ben Peddell * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-ds411slim.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-ds411slim.dts +++ sys/gnu/dts/arm/kirkwood-ds411slim.dts @@ -1,10 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Andrew Lunn * Ben Peddell * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-laplug.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-laplug.dts +++ sys/gnu/dts/arm/kirkwood-laplug.dts @@ -1,9 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2013 Maxime Hadjinlian * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-linkstation-6282.dtsi =================================================================== --- sys/gnu/dts/arm/kirkwood-linkstation-6282.dtsi +++ sys/gnu/dts/arm/kirkwood-linkstation-6282.dtsi @@ -1,46 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree common file for kirkwood-6282 based Buffalo Linkstation * * Copyright (C) 2015, 2016 * Roger Shimizu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include "kirkwood.dtsi" Index: sys/gnu/dts/arm/kirkwood-linkstation-duo-6281.dtsi =================================================================== --- sys/gnu/dts/arm/kirkwood-linkstation-duo-6281.dtsi +++ sys/gnu/dts/arm/kirkwood-linkstation-duo-6281.dtsi @@ -1,46 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree common file for kirkwood-6281 based 2-Bay Buffalo Linkstation * * Copyright (C) 2015, 2016 * Roger Shimizu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include "kirkwood.dtsi" Index: sys/gnu/dts/arm/kirkwood-linkstation-lsqvl.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-linkstation-lsqvl.dts +++ sys/gnu/dts/arm/kirkwood-linkstation-lsqvl.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Buffalo Linkstation LS-QVL * @@ -6,44 +7,6 @@ * Based on kirkwood-linkstation-lswvl.dts, * Copyright (C) 2015, 2016 * Roger Shimizu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-linkstation-lsvl.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-linkstation-lsvl.dts +++ sys/gnu/dts/arm/kirkwood-linkstation-lsvl.dts @@ -1,46 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Buffalo Linkstation LS-VL * * Copyright (C) 2015, 2016 * Roger Shimizu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-linkstation-lswsxl.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-linkstation-lswsxl.dts +++ sys/gnu/dts/arm/kirkwood-linkstation-lswsxl.dts @@ -1,46 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Buffalo Linkstation LS-WSXL * * Copyright (C) 2015, 2016 * Roger Shimizu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-linkstation-lswvl.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-linkstation-lswvl.dts +++ sys/gnu/dts/arm/kirkwood-linkstation-lswvl.dts @@ -1,46 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Buffalo Linkstation LS-WVL * * Copyright (C) 2015, 2016 * Roger Shimizu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-linkstation-lswxl.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-linkstation-lswxl.dts +++ sys/gnu/dts/arm/kirkwood-linkstation-lswxl.dts @@ -1,46 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Buffalo Linkstation LS-WXL * * Copyright (C) 2015, 2016 * Roger Shimizu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-linkstation.dtsi =================================================================== --- sys/gnu/dts/arm/kirkwood-linkstation.dtsi +++ sys/gnu/dts/arm/kirkwood-linkstation.dtsi @@ -1,46 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree common file for kirkwood based Buffalo Linkstation * * Copyright (C) 2015, 2016 * Roger Shimizu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ / { Index: sys/gnu/dts/arm/kirkwood-linksys-viper.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-linksys-viper.dts +++ sys/gnu/dts/arm/kirkwood-linksys-viper.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * kirkwood-viper.dts - Device Tree file for Linksys viper (E4200v2 / EA4500) * @@ -6,9 +7,6 @@ * (c) 2014 Luka Perkov * (c) 2014 Randy C. Will * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-mv88f6281gtw-ge.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-mv88f6281gtw-ge.dts +++ sys/gnu/dts/arm/kirkwood-mv88f6281gtw-ge.dts @@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Marvell 88F6281 GTW GE Board * * Lennert Buytenhek * Thomas Petazzoni * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * * This file contains the definitions that are common between the 6281 * and 6282 variants of the Marvell Kirkwood Development Board. */ Index: sys/gnu/dts/arm/kirkwood-nas2big.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-nas2big.dts +++ sys/gnu/dts/arm/kirkwood-nas2big.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree file for LaCie 2Big NAS * @@ -5,9 +6,6 @@ * * Author: Simon Guinot * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-net2big.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-net2big.dts +++ sys/gnu/dts/arm/kirkwood-net2big.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree file for LaCie 2Big Network v2 * @@ -8,9 +9,6 @@ * Based on netxbig_v2-setup.c, * Copyright (C) 2010 Simon Guinot * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-net5big.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-net5big.dts +++ sys/gnu/dts/arm/kirkwood-net5big.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree file for LaCie 5Big Network v2 * @@ -8,9 +9,6 @@ * Based on netxbig_v2-setup.c, * Copyright (C) 2010 Simon Guinot * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-netgear_readynas_duo_v2.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-netgear_readynas_duo_v2.dts +++ sys/gnu/dts/arm/kirkwood-netgear_readynas_duo_v2.dts @@ -1,12 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Device Tree file for NETGEAR ReadyNAS Duo v2 * * Copyright (C) 2013, Arnaud EBALARD - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-netgear_readynas_nv+_v2.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-netgear_readynas_nv+_v2.dts +++ sys/gnu/dts/arm/kirkwood-netgear_readynas_nv+_v2.dts @@ -1,12 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Device Tree file for NETGEAR ReadyNAS NV+ v2 * * Copyright (C) 2013, Arnaud EBALARD - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-netxbig.dtsi =================================================================== --- sys/gnu/dts/arm/kirkwood-netxbig.dtsi +++ sys/gnu/dts/arm/kirkwood-netxbig.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree common file for LaCie 2Big and 5Big Network v2 * @@ -8,9 +9,6 @@ * Based on netxbig_v2-setup.c, * Copyright (C) 2010 Simon Guinot * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ #include Index: sys/gnu/dts/arm/kirkwood-nsa320.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-nsa320.dts +++ sys/gnu/dts/arm/kirkwood-nsa320.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ /* Device tree file for the Zyxel NSA 320 NAS box. * * Copyright (c) 2014, Adam Baker * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. * * Based upon the board setup file created by Peter Schildmann */ Index: sys/gnu/dts/arm/kirkwood-nsa325.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-nsa325.dts +++ sys/gnu/dts/arm/kirkwood-nsa325.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ /* Device tree file for the Zyxel NSA 325 NAS box. * * Copyright (c) 2015, Hans Ulli Kroll * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. * * Based upon the board setup file created by Peter Schildmann */ Index: sys/gnu/dts/arm/kirkwood-openblocks_a7.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-openblocks_a7.dts +++ sys/gnu/dts/arm/kirkwood-openblocks_a7.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree file for OpenBlocks A7 board * @@ -5,9 +6,6 @@ * * Thomas Petazzoni * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-openrd-base.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-openrd-base.dts +++ sys/gnu/dts/arm/kirkwood-openrd-base.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Marvell OpenRD Base Board Description * * Andrew Lunn * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * * This file contains the definitions that are specific to OpenRD * base variant of the Marvell Kirkwood Development Board. */ Index: sys/gnu/dts/arm/kirkwood-openrd-client.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-openrd-client.dts +++ sys/gnu/dts/arm/kirkwood-openrd-client.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Marvell OpenRD Client Board Description * * Andrew Lunn * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * * This file contains the definitions that are specific to OpenRD * client variant of the Marvell Kirkwood Development Board. */ Index: sys/gnu/dts/arm/kirkwood-openrd-ultimate.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-openrd-ultimate.dts +++ sys/gnu/dts/arm/kirkwood-openrd-ultimate.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Marvell OpenRD Ultimate Board Description * * Andrew Lunn * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * * This file contains the definitions that are specific to OpenRD * ultimate variant of the Marvell Kirkwood Development Board. */ Index: sys/gnu/dts/arm/kirkwood-openrd.dtsi =================================================================== --- sys/gnu/dts/arm/kirkwood-openrd.dtsi +++ sys/gnu/dts/arm/kirkwood-openrd.dtsi @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Marvell OpenRD (Base|Client|Ultimate) Board Description * * Andrew Lunn * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * * This file contains the definitions that are common between the three * variants of the Marvell Kirkwood Development Board. */ Index: sys/gnu/dts/arm/kirkwood-pogo_e02.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-pogo_e02.dts +++ sys/gnu/dts/arm/kirkwood-pogo_e02.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * kirkwood-pogo_e02.dts - Device tree file for Pogoplug E02 * @@ -7,9 +8,6 @@ * Arch Linux ARM by Oleg Rakhmanov * OpenWrt by Felix Kaechele * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-pogoplug-series-4.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-pogoplug-series-4.dts +++ sys/gnu/dts/arm/kirkwood-pogoplug-series-4.dts @@ -35,7 +35,7 @@ pinctrl-names = "default"; eject { - debounce_interval = <50>; + debounce-interval = <50>; wakeup-source; linux,code = ; label = "Eject Button"; Index: sys/gnu/dts/arm/kirkwood-rd88f6192.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-rd88f6192.dts +++ sys/gnu/dts/arm/kirkwood-rd88f6192.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Marvell RD88F6192 Board descrition * * Andrew Lunn * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * * This file contains the definitions that are common between the three * variants of the Marvell Kirkwood Development Board. */ Index: sys/gnu/dts/arm/kirkwood-rd88f6281-a.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-rd88f6281-a.dts +++ sys/gnu/dts/arm/kirkwood-rd88f6281-a.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Marvell RD88F6181 A Board descrition * * Andrew Lunn * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * * This file contains the definitions for the board with the A0 or * higher stepping of the SoC. The ethernet switch does not have a * "wan" port. Index: sys/gnu/dts/arm/kirkwood-rd88f6281-z0.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-rd88f6281-z0.dts +++ sys/gnu/dts/arm/kirkwood-rd88f6281-z0.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Marvell RD88F6181 Z0 stepping descrition * * Andrew Lunn * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * * This file contains the definitions for the board using the Z0 * stepping of the SoC. The ethernet switch has a "wan" port. */ Index: sys/gnu/dts/arm/kirkwood-rd88f6281.dtsi =================================================================== --- sys/gnu/dts/arm/kirkwood-rd88f6281.dtsi +++ sys/gnu/dts/arm/kirkwood-rd88f6281.dtsi @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Marvell RD88F6181 Common Board descrition * * Andrew Lunn * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * * This file contains the definitions that are common between the two * variants of the Marvell Kirkwood Development Board. */ Index: sys/gnu/dts/arm/kirkwood-rs212.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-rs212.dts +++ sys/gnu/dts/arm/kirkwood-rs212.dts @@ -1,10 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Andrew Lunn * Ben Peddell * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-rs409.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-rs409.dts +++ sys/gnu/dts/arm/kirkwood-rs409.dts @@ -1,10 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Andrew Lunn * Ben Peddell * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-rs411.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-rs411.dts +++ sys/gnu/dts/arm/kirkwood-rs411.dts @@ -1,10 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Andrew Lunn * Ben Peddell * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-sheevaplug-common.dtsi =================================================================== --- sys/gnu/dts/arm/kirkwood-sheevaplug-common.dtsi +++ sys/gnu/dts/arm/kirkwood-sheevaplug-common.dtsi @@ -1,9 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * kirkwood-sheevaplug-common.dtsi - Common parts for Sheevaplugs * * Copyright (C) 2013 Simon Baatz - * - * Licensed under GPLv2 */ #include "kirkwood.dtsi" Index: sys/gnu/dts/arm/kirkwood-sheevaplug-esata.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-sheevaplug-esata.dts +++ sys/gnu/dts/arm/kirkwood-sheevaplug-esata.dts @@ -1,9 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * kirkwood-sheevaplug-esata.dts - Device tree file for eSATA Sheevaplug * * Copyright (C) 2013 Simon Baatz - * - * Licensed under GPLv2 */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-sheevaplug.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-sheevaplug.dts +++ sys/gnu/dts/arm/kirkwood-sheevaplug.dts @@ -1,9 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * kirkwood-sheevaplug.dts - Device tree file for Sheevaplug * * Copyright (C) 2013 Simon Baatz - * - * Licensed under GPLv2 */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-synology.dtsi =================================================================== --- sys/gnu/dts/arm/kirkwood-synology.dtsi +++ sys/gnu/dts/arm/kirkwood-synology.dtsi @@ -1,12 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Nodes for Marvell 628x Synology devices * * Andrew Lunn * Ben Peddell * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ / { Index: sys/gnu/dts/arm/kirkwood-t5325.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-t5325.dts +++ sys/gnu/dts/arm/kirkwood-t5325.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree file for HP t5325 Thin Client" * @@ -6,9 +7,6 @@ * Thomas Petazzoni * Andrew Lunn * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-ts419-6281.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-ts419-6281.dts +++ sys/gnu/dts/arm/kirkwood-ts419-6281.dts @@ -1,12 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Device Tree file for QNAP TS41X with 6281 SoC * * Copyright (C) 2013, Andrew Lunn - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-ts419-6282.dts =================================================================== --- sys/gnu/dts/arm/kirkwood-ts419-6282.dts +++ sys/gnu/dts/arm/kirkwood-ts419-6282.dts @@ -1,12 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Device Tree file for QNAP TS41X with 6282 SoC * * Copyright (C) 2013, Andrew Lunn - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. */ /dts-v1/; Index: sys/gnu/dts/arm/kirkwood-ts419.dtsi =================================================================== --- sys/gnu/dts/arm/kirkwood-ts419.dtsi +++ sys/gnu/dts/arm/kirkwood-ts419.dtsi @@ -1,12 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Device Tree include file for QNAP TS41X * * Copyright (C) 2013, Andrew Lunn - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. */ / { Index: sys/gnu/dts/arm/kirkwood.dtsi =================================================================== --- sys/gnu/dts/arm/kirkwood.dtsi +++ sys/gnu/dts/arm/kirkwood.dtsi @@ -382,7 +382,7 @@ audio0: audio-controller@a0000 { compatible = "marvell,kirkwood-audio"; - #sound-dai-cells = <1>; + #sound-dai-cells = <0>; reg = <0xa0000 0x2210>; interrupts = <24>; clocks = <&gate_clk 9>; Index: sys/gnu/dts/arm/logicpd-som-lv.dtsi =================================================================== --- sys/gnu/dts/arm/logicpd-som-lv.dtsi +++ sys/gnu/dts/arm/logicpd-som-lv.dtsi @@ -26,7 +26,7 @@ gpio = <&gpio1 3 0>; /* gpio_3 */ startup-delay-us = <70000>; enable-active-high; - vin-supply = <&vmmc2>; + vin-supply = <&vaux3>; }; /* HS USB Host PHY on PORT 1 */ @@ -82,16 +82,21 @@ twl_audio: audio { compatible = "ti,twl4030-audio"; codec { + ti,hs_extmute_gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>; }; }; }; }; &i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; clock-frequency = <400000>; }; &i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; clock-frequency = <400000>; }; @@ -195,6 +200,7 @@ pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ + OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */ >; }; }; @@ -209,10 +215,22 @@ }; wl127x_gpio: pinmux_wl127x_gpio_pin { pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a0c, PIN_INPUT | MUX_MODE4) /* sys_boot0.gpio_2 */ + OMAP3_WKUP_IOPAD(0x2a0a, PIN_INPUT | MUX_MODE4) /* sys_boot0.gpio_2 */ OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */ >; }; + i2c2_pins: pinmux_i2c2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ + OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ + >; + }; + i2c3_pins: pinmux_i2c3_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ + OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ + >; + }; }; &omap3_pmx_core2 { @@ -244,6 +262,11 @@ #include "twl4030.dtsi" #include "twl4030_omap3.dtsi" +&vaux3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + &twl { twl_power: power { compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle"; Index: sys/gnu/dts/arm/logicpd-torpedo-som.dtsi =================================================================== --- sys/gnu/dts/arm/logicpd-torpedo-som.dtsi +++ sys/gnu/dts/arm/logicpd-torpedo-som.dtsi @@ -83,10 +83,14 @@ }; &i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; clock-frequency = <400000>; }; &i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; clock-frequency = <400000>; at24@50 { compatible = "atmel,24c64"; @@ -144,6 +148,18 @@ OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ >; }; + i2c2_pins: pinmux_i2c2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ + OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ + >; + }; + i2c3_pins: pinmux_i2c3_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ + OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ + >; + }; }; &uart2 { Index: sys/gnu/dts/arm/lpc18xx.dtsi =================================================================== --- sys/gnu/dts/arm/lpc18xx.dtsi +++ sys/gnu/dts/arm/lpc18xx.dtsi @@ -115,7 +115,6 @@ compatible = "snps,dw-mshc"; reg = <0x40004000 0x1000>; interrupts = <6>; - num-slots = <1>; clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>; clock-names = "ciu", "biu"; resets = <&rgu 20>; Index: sys/gnu/dts/arm/ls1021a.dtsi =================================================================== --- sys/gnu/dts/arm/ls1021a.dtsi +++ sys/gnu/dts/arm/ls1021a.dtsi @@ -587,7 +587,8 @@ device_type = "mdio"; #address-cells = <1>; #size-cells = <0>; - reg = <0x0 0x2d24000 0x0 0x4000>; + reg = <0x0 0x2d24000 0x0 0x4000>, + <0x0 0x2d10030 0x0 0x4>; }; ptp_clock@2d10e00 { @@ -788,5 +789,21 @@ clock-names = "ipg", "per"; big-endian; }; + + ocram1: sram@10000000 { + compatible = "mmio-sram"; + reg = <0x0 0x10000000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x10000000 0x10000>; + }; + + ocram2: sram@10010000 { + compatible = "mmio-sram"; + reg = <0x0 0x10010000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x10010000 0x10000>; + }; }; }; Index: sys/gnu/dts/arm/meson8.dtsi =================================================================== --- sys/gnu/dts/arm/meson8.dtsi +++ sys/gnu/dts/arm/meson8.dtsi @@ -46,6 +46,7 @@ #include #include #include +#include #include "meson.dtsi" / { @@ -187,6 +188,12 @@ reg = <0x8000 0x4>, <0x4000 0x460>; }; + reset: reset-controller@4404 { + compatible = "amlogic,meson8b-reset"; + reg = <0x4404 0x9c>; + #reset-cells = <1>; + }; + analog_top: analog-top@81a8 { compatible = "amlogic,meson8-analog-top", "syscon"; reg = <0x81a8 0x14>; @@ -383,10 +390,12 @@ compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; clock-names = "usb_general", "usb"; + resets = <&reset RESET_USB_OTG>; }; &usb1_phy { compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; clock-names = "usb_general", "usb"; + resets = <&reset RESET_USB_OTG>; }; Index: sys/gnu/dts/arm/meson8b-odroidc1.dts =================================================================== --- sys/gnu/dts/arm/meson8b-odroidc1.dts +++ sys/gnu/dts/arm/meson8b-odroidc1.dts @@ -54,6 +54,7 @@ aliases { serial0 = &uart_AO; + mmc0 = &sd_card_slot; }; memory { @@ -69,6 +70,37 @@ default-state = "off"; }; }; + + tflash_vdd: regulator-tflash_vdd { + /* + * signal name from schematics: TFLASH_VDD_EN + */ + compatible = "regulator-fixed"; + + regulator-name = "TFLASH_VDD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio GPIOY_12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + tf_io: gpio-regulator-tf_io { + compatible = "regulator-gpio"; + + regulator-name = "TF_IO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + /* + * signal name from schematics: TF_3V3N_1V8_EN + */ + gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + + states = <3300000 0 + 1800000 1>; + }; }; &uart_AO { @@ -99,3 +131,59 @@ &usb1 { status = "okay"; }; + +&sdio { + status = "okay"; + + pinctrl-0 = <&sd_b_pins>; + pinctrl-names = "default"; + + /* SD card */ + sd_card_slot: slot@1 { + compatible = "mmc-slot"; + reg = <1>; + status = "okay"; + + bus-width = <4>; + no-sdio; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + vmmc-supply = <&tflash_vdd>; + vqmmc-supply = <&tf_io>; + }; +}; + +ðmac { + status = "okay"; + + snps,reset-gpio = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 30000>; + + pinctrl-0 = <ð_rgmii_pins>; + pinctrl-names = "default"; + + phy-mode = "rgmii"; + phy-handle = <ð_phy>; + amlogic,tx-delay-ns = <4>; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + /* Realtek RTL8211F (0x001cc916) */ + eth_phy: ethernet-phy@0 { + reg = <0>; + eee-broken-1000t; + interrupt-parent = <&gpio_intc>; + /* GPIOH_3 */ + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; Index: sys/gnu/dts/arm/meson8b.dtsi =================================================================== --- sys/gnu/dts/arm/meson8b.dtsi +++ sys/gnu/dts/arm/meson8b.dtsi @@ -152,7 +152,7 @@ reset: reset-controller@4404 { compatible = "amlogic,meson8b-reset"; - reg = <0x4404 0x20>; + reg = <0x4404 0x9c>; #reset-cells = <1>; }; @@ -183,7 +183,36 @@ reg-names = "mux", "pull", "pull-enable", "gpio"; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pinctrl_cbus 0 0 130>; + gpio-ranges = <&pinctrl_cbus 0 0 83>; + }; + + eth_rgmii_pins: eth-rgmii { + mux { + groups = "eth_tx_clk", + "eth_tx_en", + "eth_txd1_0", + "eth_txd1_1", + "eth_txd0_0", + "eth_txd0_1", + "eth_rx_clk", + "eth_rx_dv", + "eth_rxd1", + "eth_rxd0", + "eth_mdio_en", + "eth_mdc", + "eth_ref_clk", + "eth_txd2", + "eth_txd3"; + function = "ethernet"; + }; + }; + + sd_b_pins: sd-b { + mux { + groups = "sd_d0_b", "sd_d1_b", "sd_d2_b", + "sd_d3_b", "sd_clk_b", "sd_cmd_b"; + function = "sd_b"; + }; }; }; }; @@ -203,8 +232,18 @@ }; ðmac { - clocks = <&clkc CLKID_ETH>; - clock-names = "stmmaceth"; + compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac"; + + reg = <0xc9410000 0x10000 + 0xc1108140 0x4>; + + clocks = <&clkc CLKID_ETH>, + <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL2>; + clock-names = "stmmaceth", "clkin0", "clkin1"; + + resets = <&reset RESET_ETHERNET>; + reset-names = "stmmaceth"; }; &gpio_intc { @@ -219,6 +258,18 @@ clock-names = "core"; }; +&i2c_AO { + clocks = <&clkc CLKID_CLK81>; +}; + +&i2c_A { + clocks = <&clkc CLKID_I2C>; +}; + +&i2c_B { + clocks = <&clkc CLKID_I2C>; +}; + &L2 { arm,data-latency = <3 3 3>; arm,tag-latency = <2 2 2>; Index: sys/gnu/dts/arm/motorola-cpcap-mapphone.dtsi =================================================================== --- sys/gnu/dts/arm/motorola-cpcap-mapphone.dtsi +++ sys/gnu/dts/arm/motorola-cpcap-mapphone.dtsi @@ -68,6 +68,19 @@ }; }; + cpcap_audio: audio-codec { + #sound-dai-cells = <1>; + + port@0 { + cpcap_audio_codec0: endpoint { + }; + }; + port@1 { + cpcap_audio_codec1: endpoint { + }; + }; + }; + cpcap_rtc: rtc { compatible = "motorola,cpcap-rtc"; Index: sys/gnu/dts/arm/mt7623.dtsi =================================================================== --- sys/gnu/dts/arm/mt7623.dtsi +++ sys/gnu/dts/arm/mt7623.dtsi @@ -28,7 +28,7 @@ compatible = "mediatek,mt7623"; interrupt-parent = <&sysirq>; - cpu_opp_table: opp_table { + cpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-shared; @@ -87,8 +87,6 @@ clock-names = "cpu", "intermediate"; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; - cooling-min-level = <0>; - cooling-max-level = <7>; clock-frequency = <1300000000>; }; @@ -96,6 +94,9 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x1>; + clocks = <&infracfg CLK_INFRA_CPUSEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; operating-points-v2 = <&cpu_opp_table>; clock-frequency = <1300000000>; }; @@ -104,6 +105,9 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x2>; + clocks = <&infracfg CLK_INFRA_CPUSEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; operating-points-v2 = <&cpu_opp_table>; clock-frequency = <1300000000>; }; @@ -112,6 +116,9 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x3>; + clocks = <&infracfg CLK_INFRA_CPUSEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; operating-points-v2 = <&cpu_opp_table>; clock-frequency = <1300000000>; }; @@ -138,32 +145,32 @@ }; thermal-zones { - cpu_thermal: cpu_thermal { + cpu_thermal: cpu-thermal { polling-delay-passive = <1000>; polling-delay = <1000>; thermal-sensors = <&thermal 0>; trips { - cpu_passive: cpu_passive { + cpu_passive: cpu-passive { temperature = <47000>; hysteresis = <2000>; type = "passive"; }; - cpu_active: cpu_active { + cpu_active: cpu-active { temperature = <67000>; hysteresis = <2000>; type = "active"; }; - cpu_hot: cpu_hot { + cpu_hot: cpu-hot { temperature = <87000>; hysteresis = <2000>; type = "hot"; }; - cpu_crit { + cpu-crit { temperature = <107000>; hysteresis = <2000>; type = "critical"; @@ -670,6 +677,111 @@ #reset-cells = <1>; }; + pcie: pcie@1a140000 { + compatible = "mediatek,mt7623-pcie"; + device_type = "pci"; + reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */ + <0 0x1a142000 0 0x1000>, /* Port0 registers */ + <0 0x1a143000 0 0x1000>, /* Port1 registers */ + <0 0x1a144000 0 0x1000>; /* Port2 registers */ + reg-names = "subsys", "port0", "port1", "port2"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 0>; + interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_ETHIF_SEL>, + <&hifsys CLK_HIFSYS_PCIE0>, + <&hifsys CLK_HIFSYS_PCIE1>, + <&hifsys CLK_HIFSYS_PCIE2>; + clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; + resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>, + <&hifsys MT2701_HIFSYS_PCIE1_RST>, + <&hifsys MT2701_HIFSYS_PCIE2_RST>; + reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; + phys = <&pcie0_port PHY_TYPE_PCIE>, + <&pcie1_port PHY_TYPE_PCIE>, + <&u3port1 PHY_TYPE_PCIE>; + phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; + bus-range = <0x00 0xff>; + status = "disabled"; + ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 + 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; + ranges; + num-lanes = <1>; + status = "disabled"; + }; + + pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; + ranges; + num-lanes = <1>; + status = "disabled"; + }; + + pcie@2,0 { + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; + ranges; + num-lanes = <1>; + status = "disabled"; + }; + }; + + pcie0_phy: pcie-phy@1a149000 { + compatible = "mediatek,generic-tphy-v1"; + reg = <0 0x1a149000 0 0x0700>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + pcie0_port: pcie-phy@1a149900 { + reg = <0 0x1a149900 0 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + + pcie1_phy: pcie-phy@1a14a000 { + compatible = "mediatek,generic-tphy-v1"; + reg = <0 0x1a14a000 0 0x0700>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + pcie1_port: pcie-phy@1a14a900 { + reg = <0 0x1a14a900 0 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + usb1: usb@1a1c0000 { compatible = "mediatek,mt7623-xhci", "mediatek,mt8173-xhci"; Index: sys/gnu/dts/arm/mt7623n-bananapi-bpi-r2.dts =================================================================== --- sys/gnu/dts/arm/mt7623n-bananapi-bpi-r2.dts +++ sys/gnu/dts/arm/mt7623n-bananapi-bpi-r2.dts @@ -39,7 +39,34 @@ }; }; - gpio_keys { + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&key_pins_a>; @@ -120,7 +147,6 @@ #address-cells = <1>; #size-cells = <0>; reg = <0>; - pinctrl-names = "default"; reset-gpios = <&pio 33 0>; core-supply = <&mt6323_vpa_reg>; io-supply = <&mt6323_vemc3v3_reg>; @@ -191,8 +217,8 @@ bus-width = <8>; max-frequency = <50000000>; cap-mmc-highspeed; - vmmc-supply = <&mt6323_vemc3v3_reg>; - vqmmc-supply = <&mt6323_vio18_reg>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; non-removable; }; @@ -205,20 +231,42 @@ max-frequency = <50000000>; cap-sd-highspeed; cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>; - vmmc-supply = <&mt6323_vmch_reg>; - vqmmc-supply = <&mt6323_vio18_reg>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_default>; + status = "okay"; + + pcie@0,0 { + status = "okay"; + }; + + pcie@1,0 { + status = "okay"; + }; +}; + +&pcie0_phy { + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; }; &pio { cir_pins_a:cir@0 { - pins_cir { + pins-cir { pinmux = ; bias-disable; }; }; i2c0_pins_a: i2c@0 { - pins_i2c0 { + pins-i2c0 { pinmux = , ; bias-disable; @@ -226,7 +274,7 @@ }; i2c1_pins_a: i2c@1 { - pin_i2c1 { + pin-i2c1 { pinmux = , ; bias-disable; @@ -234,7 +282,7 @@ }; i2s0_pins_a: i2s@0 { - pin_i2s0 { + pin-i2s0 { pinmux = , , , @@ -246,7 +294,7 @@ }; i2s1_pins_a: i2s@1 { - pin_i2s1 { + pin-i2s1 { pinmux = , , , @@ -258,7 +306,7 @@ }; key_pins_a: keys@0 { - pins_keys { + pins-keys { pinmux = , ; input-enable; @@ -266,7 +314,7 @@ }; led_pins_a: leds@0 { - pins_leds { + pins-leds { pinmux = , , ; @@ -274,7 +322,7 @@ }; mmc0_pins_default: mmc0default { - pins_cmd_dat { + pins-cmd-dat { pinmux = , , , @@ -288,19 +336,19 @@ bias-pull-up; }; - pins_clk { + pins-clk { pinmux = ; bias-pull-down; }; - pins_rst { + pins-rst { pinmux = ; bias-pull-up; }; }; mmc0_pins_uhs: mmc0 { - pins_cmd_dat { + pins-cmd-dat { pinmux = , , , @@ -315,20 +363,20 @@ bias-pull-up = ; }; - pins_clk { + pins-clk { pinmux = ; drive-strength = ; bias-pull-down = ; }; - pins_rst { + pins-rst { pinmux = ; bias-pull-up; }; }; mmc1_pins_default: mmc1default { - pins_cmd_dat { + pins-cmd-dat { pinmux = , , , @@ -339,26 +387,26 @@ bias-pull-up = ; }; - pins_clk { + pins-clk { pinmux = ; bias-pull-down; drive-strength = ; }; - pins_wp { + pins-wp { pinmux = ; input-enable; bias-pull-up; }; - pins_insert { + pins-insert { pinmux = ; bias-pull-up; }; }; mmc1_pins_uhs: mmc1 { - pins_cmd_dat { + pins-cmd-dat { pinmux = , , , @@ -369,15 +417,23 @@ bias-pull-up = ; }; - pins_clk { + pins-clk { pinmux = ; drive-strength = ; bias-pull-down = ; }; }; + pcie_default: pcie_pin_default { + pins_cmd_dat { + pinmux = , + ; + bias-disable; + }; + }; + pwm_pins_a: pwm@0 { - pins_pwm { + pins-pwm { pinmux = , , , @@ -387,7 +443,7 @@ }; spi0_pins_a: spi@0 { - pins_spi { + pins-spi { pinmux = , , , @@ -397,18 +453,25 @@ }; uart0_pins_a: uart@0 { - pins_dat { + pins-dat { pinmux = , ; }; }; uart1_pins_a: uart@1 { - pins_dat { + pins-dat { pinmux = , ; }; }; + + uart2_pins_a: uart@2 { + pins-dat { + pinmux = , + ; + }; + }; }; &pwm { @@ -454,26 +517,30 @@ &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; - status = "disabled"; + status = "okay"; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins_a>; - status = "disabled"; + status = "okay"; }; &uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins_a>; status = "okay"; }; &usb1 { - vusb33-supply = <&mt6323_vusb_reg>; + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; status = "okay"; }; &usb2 { - vusb33-supply = <&mt6323_vusb_reg>; + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; status = "okay"; }; Index: sys/gnu/dts/arm/mt7623n-rfb-nand.dts =================================================================== --- sys/gnu/dts/arm/mt7623n-rfb-nand.dts +++ sys/gnu/dts/arm/mt7623n-rfb-nand.dts @@ -81,13 +81,13 @@ &pio { nand_pins_default: nanddefault { - pins_ale { + pins-ale { pinmux = ; drive-strength = ; bias-pull-down = ; }; - pins_dat { + pins-dat { pinmux = , , , @@ -102,7 +102,7 @@ bias-pull-up; }; - pins_we { + pins-we { pinmux = ; drive-strength = ; bias-pull-up = ; Index: sys/gnu/dts/arm/nuvoton-common-npcm7xx.dtsi =================================================================== --- /dev/null +++ sys/gnu/dts/arm/nuvoton-common-npcm7xx.dtsi @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com +// Copyright 2018 Google, Inc. + +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + /* external reference clock */ + clk_refclk: clk_refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "refclk"; + }; + + /* external reference clock for cpu. float in normal operation */ + clk_sysbypck: clk_sysbypck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "sysbypck"; + }; + + /* external reference clock for MC. float in normal operation */ + clk_mcbypck: clk_mcbypck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "mcbypck"; + }; + + /* external clock signal rg1refck, supplied by the phy */ + clk_rg1refck: clk_rg1refck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "clk_rg1refck"; + }; + + /* external clock signal rg2refck, supplied by the phy */ + clk_rg2refck: clk_rg2refck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "clk_rg2refck"; + }; + + clk_xin: clk_xin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "clk_xin"; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges = <0x0 0xf0000000 0x00900000>; + + gcr: gcr@800000 { + compatible = "nuvoton,npcm750-gcr", "syscon", + "simple-mfd"; + reg = <0x800000 0x1000>; + }; + + scu: scu@3fe000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x3fe000 0x1000>; + }; + + l2: cache-controller@3fc000 { + compatible = "arm,pl310-cache"; + reg = <0x3fc000 0x1000>; + interrupts = ; + cache-unified; + cache-level = <2>; + clocks = <&clk 10>; + arm,shared-override; + }; + + gic: interrupt-controller@3ff000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x3ff000 0x1000>, + <0x3fe100 0x100>; + }; + }; + + ahb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + clk: clock-controller@f0801000 { + compatible = "nuvoton,npcm750-clk", "syscon"; + #clock-cells = <1>; + clock-controller; + reg = <0xf0801000 0x1000>; + clock-names = "refclk", "sysbypck", "mcbypck"; + clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges = <0x0 0xf0000000 0x00300000>; + + timer0: timer@8000 { + compatible = "nuvoton,npcm750-timer"; + interrupts = ; + reg = <0x8000 0x50>; + clocks = <&clk 5>; + }; + + watchdog0: watchdog@801C { + compatible = "nuvoton,npcm750-wdt"; + interrupts = ; + reg = <0x801C 0x4>; + status = "disabled"; + clocks = <&clk 5>; + }; + + watchdog1: watchdog@901C { + compatible = "nuvoton,npcm750-wdt"; + interrupts = ; + reg = <0x901C 0x4>; + status = "disabled"; + clocks = <&clk 5>; + }; + + watchdog2: watchdog@a01C { + compatible = "nuvoton,npcm750-wdt"; + interrupts = ; + reg = <0xa01C 0x4>; + status = "disabled"; + clocks = <&clk 5>; + }; + + serial0: serial@1000 { + compatible = "nuvoton,npcm750-uart"; + reg = <0x1000 0x1000>; + clocks = <&clk 6>; + interrupts = ; + reg-shift = <2>; + status = "disabled"; + }; + + serial1: serial@2000 { + compatible = "nuvoton,npcm750-uart"; + reg = <0x2000 0x1000>; + clocks = <&clk 6>; + interrupts = ; + reg-shift = <2>; + status = "disabled"; + }; + + serial2: serial@3000 { + compatible = "nuvoton,npcm750-uart"; + reg = <0x3000 0x1000>; + clocks = <&clk 6>; + interrupts = ; + reg-shift = <2>; + status = "disabled"; + }; + + serial3: serial@4000 { + compatible = "nuvoton,npcm750-uart"; + reg = <0x4000 0x1000>; + clocks = <&clk 6>; + interrupts = ; + reg-shift = <2>; + status = "disabled"; + }; + }; + }; +}; Index: sys/gnu/dts/arm/nuvoton-npcm750-evb.dts =================================================================== --- /dev/null +++ sys/gnu/dts/arm/nuvoton-npcm750-evb.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com +// Copyright 2018 Google, Inc. + +/dts-v1/; +#include "nuvoton-npcm750.dtsi" + +/ { + model = "Nuvoton npcm750 Development Board (Device Tree)"; + compatible = "nuvoton,npcm750"; + + chosen { + stdout-path = &serial3; + }; + + memory { + reg = <0 0x40000000>; + }; +}; + +&watchdog1 { + status = "okay"; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&serial3 { + status = "okay"; +}; Index: sys/gnu/dts/arm/nuvoton-npcm750.dtsi =================================================================== --- /dev/null +++ sys/gnu/dts/arm/nuvoton-npcm750.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com +// Copyright 2018 Google, Inc. + +#include "nuvoton-common-npcm7xx.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "nuvoton,npcm750-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk 0>; + clock-names = "clk_cpu"; + reg = <0>; + next-level-cache = <&l2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk 0>; + clock-names = "clk_cpu"; + reg = <1>; + next-level-cache = <&l2>; + }; + }; + soc { + timer@3fe600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x3fe600 0x20>; + interrupts = ; + clocks = <&clk 5>; + }; + }; +}; Index: sys/gnu/dts/arm/omap3-n9.dts =================================================================== --- sys/gnu/dts/arm/omap3-n9.dts +++ sys/gnu/dts/arm/omap3-n9.dts @@ -39,6 +39,13 @@ }; }; +&i2c3 { + ak8975@0f { + compatible = "asahi-kasei,ak8975"; + reg = <0x0f>; + }; +}; + &isp { vdd-csiphy1-supply = <&vaux2>; vdd-csiphy2-supply = <&vaux2>; Index: sys/gnu/dts/arm/omap3-n900.dts =================================================================== --- sys/gnu/dts/arm/omap3-n900.dts +++ sys/gnu/dts/arm/omap3-n900.dts @@ -673,6 +673,7 @@ bq27200: bq27200@55 { compatible = "ti,bq27200"; reg = <0x55>; + power-supplies = <&bq24150a>; }; /* Stereo headphone amplifier */ Index: sys/gnu/dts/arm/omap3.dtsi =================================================================== --- sys/gnu/dts/arm/omap3.dtsi +++ sys/gnu/dts/arm/omap3.dtsi @@ -557,6 +557,7 @@ dma-names = "tx", "rx"; clocks = <&mcbsp4_fck>; clock-names = "fck"; + #sound-dai-cells = <0>; status = "disabled"; }; Index: sys/gnu/dts/arm/omap4-droid4-xt894.dts =================================================================== --- sys/gnu/dts/arm/omap4-droid4-xt894.dts +++ sys/gnu/dts/arm/omap4-droid4-xt894.dts @@ -70,8 +70,30 @@ regulator-always-on; }; - /* HS USB Host PHY on PORT 1 */ - hsusb1_phy: hsusb1_phy { + /* FS USB Host PHY on port 1 for mdm6600 */ + fsusb1_phy: usb-phy@1 { + compatible = "motorola,mapphone-mdm6600"; + pinctrl-0 = <&usb_mdm6600_pins>; + pinctrl-names = "default"; + enable-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; /* gpio_95 */ + power-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* gpio_54 */ + reset-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; /* gpio_49 */ + /* mode: gpio_148 gpio_149 */ + motorola,mode-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>, + <&gpio5 21 GPIO_ACTIVE_HIGH>; + /* cmd: gpio_103 gpio_104 gpio_142 */ + motorola,cmd-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>, + <&gpio4 8 GPIO_ACTIVE_HIGH>, + <&gpio5 14 GPIO_ACTIVE_HIGH>; + /* status: gpio_52 gpio_53 gpio_55 */ + motorola,status-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>, + <&gpio2 21 GPIO_ACTIVE_HIGH>, + <&gpio2 23 GPIO_ACTIVE_HIGH>; + #phy-cells = <0>; + }; + + /* HS USB host TLL nop-phy on port 2 for w3glte */ + hsusb2_phy: usb-phy@2 { compatible = "usb-nop-xceiv"; #phy-cells = <0>; }; @@ -117,6 +139,26 @@ }; }; + + soundcard { + compatible = "audio-graph-card"; + label = "Droid 4 Audio"; + + simple-graph-card,widgets = + "Speaker", "Earpiece", + "Speaker", "Loudspeaker", + "Headphone", "Headphone Jack", + "Microphone", "Internal Mic"; + + simple-graph-card,routing = + "Earpiece", "EP", + "Loudspeaker", "SPKR", + "Headphone Jack", "HSL", + "Headphone Jack", "HSR", + "MICR", "Internal Mic"; + + dais = <&mcbsp2_port>, <&mcbsp3_port>; + }; }; &dss { @@ -124,13 +166,6 @@ }; &gpio6 { - touchscreen_reset { - gpio-hog; - gpios = <13 0>; - output-high; - line-name = "touchscreen-reset"; - }; - pwm8: dmtimer-pwm-8 { pinctrl-names = "default"; pinctrl-0 = <&vibrator_direction_pin>; @@ -362,22 +397,18 @@ }; }; -/* - * REVISIT: Add gpio173 reset pin handling to the driver, see gpio-hog above. - * If the GPIO reset is used, we probably need to have /lib/firmware/maxtouch.fw - * available. See "mxt-app" and "droid4-touchscreen-firmware" tools for more - * information. - */ &i2c2 { - tsp@4a { + touchscreen@4a { compatible = "atmel,maxtouch"; reg = <0x4a>; pinctrl-names = "default"; pinctrl-0 = <&touchscreen_pins>; + reset-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; /* gpio173 */ + /* gpio_183 with sys_nirq2 pad as wakeup */ - interrupts-extended = <&gpio6 23 IRQ_TYPE_EDGE_FALLING - &omap4_pmx_core 0x160>; + interrupts-extended = <&gpio6 23 IRQ_TYPE_EDGE_FALLING>, + <&omap4_pmx_core 0x160>; interrupt-names = "irq", "wakeup"; wakeup-source; }; @@ -435,6 +466,7 @@ touchscreen_pins: pinmux_touchscreen_pins { pinctrl-single,pins = < + OMAP4_IOPAD(0x180, PIN_OUTPUT | MUX_MODE3) OMAP4_IOPAD(0x1a0, PIN_INPUT_PULLUP | MUX_MODE3) >; }; @@ -445,6 +477,43 @@ >; }; + usb_mdm6600_pins: pinmux_usb_mdm6600_pins { + pinctrl-single,pins = < + /* enable 0x4a1000d8 usbb1_ulpitll_dat7.gpio_95 ag16 */ + OMAP4_IOPAD(0x0d8, PIN_INPUT | MUX_MODE3) + + /* power 0x4a10007c gpmc_nwp.gpio_54 c25 */ + OMAP4_IOPAD(0x07c, PIN_OUTPUT | MUX_MODE3) + + /* reset 0x4a100072 gpmc_a25.gpio_49 d20 */ + OMAP4_IOPAD(0x072, PIN_OUTPUT | MUX_MODE3) + + /* mode0/bpwake 0x4a10014e sdmmc5_dat1.gpio_148 af4 */ + OMAP4_IOPAD(0x14e, PIN_OUTPUT | MUX_MODE3) + + /* mode1/apwake 0x4a100150 sdmmc5_dat2.gpio_149 ag3 */ + OMAP4_IOPAD(0x150, PIN_OFF_OUTPUT_LOW | PIN_INPUT | MUX_MODE3) + + /* status0 0x4a10007e gpmc_clk.gpio_55 b22 */ + OMAP4_IOPAD(0x07e, PIN_INPUT | MUX_MODE3) + + /* status1 0x4a10007a gpmc_ncs3.gpio_53 c22 */ + OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) + + /* status2 0x4a100078 gpmc_ncs2.gpio_52 d21 */ + OMAP4_IOPAD(0x078, PIN_INPUT | MUX_MODE3) + + /* cmd0 0x4a100094 gpmc_ncs6.gpio_103 c24 */ + OMAP4_IOPAD(0x094, PIN_OUTPUT | MUX_MODE3) + + /* cmd1 0x4a100096 gpmc_ncs7.gpio_104 d24 */ + OMAP4_IOPAD(0x096, PIN_OUTPUT | MUX_MODE3) + + /* cmd2 0x4a100142 uart3_rts_sd.gpio_142 f28 */ + OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE3) + >; + }; + usb_ulpi_pins: pinmux_usb_ulpi_pins { pinctrl-single,pins = < OMAP4_IOPAD(0x196, MUX_MODE7) @@ -484,6 +553,28 @@ >; }; + /* + * Note that the v3.0.8 stock userspace dynamically remuxes uart1 + * rts pin probably for PM purposes to PIN_INPUT_PULLUP | MUX_MODE7 + * when not used. If needed, we can add rts pin remux later based + * on power measurements. + */ + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + /* 0x4a10013c mcspi1_cs2.uart1_cts ag23 */ + OMAP4_IOPAD(0x13c, PIN_INPUT_PULLUP | MUX_MODE1) + + /* 0x4a10013e mcspi1_cs3.uart1_rts ah23 */ + OMAP4_IOPAD(0x13e, MUX_MODE1) + + /* 0x4a100140 uart3_cts_rctx.uart1_tx f27 */ + OMAP4_IOPAD(0x140, PIN_OUTPUT | MUX_MODE1) + + /* 0x4a1001ca dpm_emu14.uart1_rx aa3 */ + OMAP4_IOPAD(0x1ca, PIN_INPUT_PULLUP | MUX_MODE2) + >; + }; + /* uart3_tx_irtx and uart3_rx_irrx */ uart3_pins: pinmux_uart3_pins { pinctrl-single,pins = < @@ -512,6 +603,24 @@ OMAP4_IOPAD(0x112, PIN_OUTPUT_PULLUP | MUX_MODE5) /* uart4_rts */ >; }; + + mcbsp2_pins: pinmux_mcbsp2_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_clkx */ + OMAP4_IOPAD(0x0f8, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_dr */ + OMAP4_IOPAD(0x0fa, PIN_OUTPUT | MUX_MODE0) /* abe_mcbsp2_dx */ + OMAP4_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_fsx */ + >; + }; + + mcbsp3_pins: pinmux_mcbsp3_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x106, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_dr */ + OMAP4_IOPAD(0x108, PIN_OUTPUT | MUX_MODE1) /* abe_mcbsp3_dx */ + OMAP4_IOPAD(0x10a, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_clkx */ + OMAP4_IOPAD(0x10c, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_fsx */ + >; + }; }; &omap4_pmx_wkup { @@ -535,6 +644,17 @@ }; }; +/* + * As uart1 is wired to mdm6600 with rts and cts, we can use the cts pin for + * uart1 wakeirq. + */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + interrupts-extended = <&wakeupgen GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core 0xfc>; +}; + &uart3 { interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH &omap4_pmx_core 0x17c>; @@ -551,8 +671,13 @@ }; }; +&usbhsohci { + phys = <&fsusb1_phy>; + phy-names = "usb"; +}; + &usbhsehci { - phys = <&hsusb1_phy>; + phys = <&hsusb2_phy>; }; &usbhshost { @@ -597,3 +722,43 @@ "0", "0", "1"; }; }; + +&mcbsp2 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp2_pins>; + status = "okay"; + + mcbsp2_port: port { + cpu_dai2: endpoint { + dai-format = "i2s"; + remote-endpoint = <&cpcap_audio_codec0>; + frame-master = <&cpcap_audio_codec0>; + bitclock-master = <&cpcap_audio_codec0>; + }; + }; +}; + +&mcbsp3 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp3_pins>; + status = "okay"; + + mcbsp3_port: port { + cpu_dai3: endpoint { + dai-format = "dsp_a"; + frame-master = <&cpcap_audio_codec1>; + bitclock-master = <&cpcap_audio_codec1>; + remote-endpoint = <&cpcap_audio_codec1>; + }; + }; +}; + +&cpcap_audio_codec0 { + remote-endpoint = <&cpu_dai2>; +}; + +&cpcap_audio_codec1 { + remote-endpoint = <&cpu_dai3>; +}; Index: sys/gnu/dts/arm/omap4.dtsi =================================================================== --- sys/gnu/dts/arm/omap4.dtsi +++ sys/gnu/dts/arm/omap4.dtsi @@ -163,10 +163,10 @@ cm2: cm2@8000 { compatible = "ti,omap4-cm2", "simple-bus"; - reg = <0x8000 0x3000>; + reg = <0x8000 0x2000>; #address-cells = <1>; #size-cells = <1>; - ranges = <0 0x8000 0x3000>; + ranges = <0 0x8000 0x2000>; cm2_clocks: clocks { #address-cells = <1>; @@ -250,11 +250,11 @@ prm: prm@6000 { compatible = "ti,omap4-prm"; - reg = <0x6000 0x3000>; + reg = <0x6000 0x2000>; interrupts = ; #address-cells = <1>; #size-cells = <1>; - ranges = <0 0x6000 0x3000>; + ranges = <0 0x6000 0x2000>; prm_clocks: clocks { #address-cells = <1>; Index: sys/gnu/dts/arm/omap443x.dtsi =================================================================== --- sys/gnu/dts/arm/omap443x.dtsi +++ sys/gnu/dts/arm/omap443x.dtsi @@ -24,8 +24,6 @@ clock-latency = <300000>; /* From legacy driver */ /* cooling options */ - cooling-min-level = <0>; - cooling-max-level = <3>; #cooling-cells = <2>; /* min followed by max */ }; }; Index: sys/gnu/dts/arm/omap4460.dtsi =================================================================== --- sys/gnu/dts/arm/omap4460.dtsi +++ sys/gnu/dts/arm/omap4460.dtsi @@ -22,8 +22,6 @@ clock-latency = <300000>; /* From legacy driver */ /* cooling options */ - cooling-min-level = <0>; - cooling-max-level = <2>; #cooling-cells = <2>; /* min followed by max */ }; }; Index: sys/gnu/dts/arm/omap5-board-common.dtsi =================================================================== --- sys/gnu/dts/arm/omap5-board-common.dtsi +++ sys/gnu/dts/arm/omap5-board-common.dtsi @@ -659,8 +659,8 @@ v2v1-supply = <&smps9_reg>; enable-active-high; - clocks = <&clk32kgaudio>; - clock-names = "clk32k"; + clocks = <&clk32kgaudio>, <&fref_xtal_ck>; + clock-names = "clk32k", "mclk"; }; }; Index: sys/gnu/dts/arm/omap5.dtsi =================================================================== --- sys/gnu/dts/arm/omap5.dtsi +++ sys/gnu/dts/arm/omap5.dtsi @@ -55,8 +55,6 @@ clock-latency = <300000>; /* From omap-cpufreq driver */ /* cooling options */ - cooling-min-level = <0>; - cooling-max-level = <2>; #cooling-cells = <2>; /* min followed by max */ }; cpu@1 { @@ -289,6 +287,28 @@ pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0x7fff>; }; + + omap5_scm_wkup_pad_conf: omap5_scm_wkup_pad_conf@cda0 { + compatible = "ti,omap5-scm-wkup-pad-conf", + "simple-bus"; + reg = <0xcda0 0x60>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xcda0 0x60>; + + scm_wkup_pad_conf: scm_conf@0 { + compatible = "syscon", "simple-bus"; + reg = <0x0 0x60>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x60>; + + scm_wkup_pad_conf_clocks: clocks@0 { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; }; ocmcram: ocmcram@40300000 { Index: sys/gnu/dts/arm/omap54xx-clocks.dtsi =================================================================== --- sys/gnu/dts/arm/omap54xx-clocks.dtsi +++ sys/gnu/dts/arm/omap54xx-clocks.dtsi @@ -1179,3 +1179,13 @@ }; }; }; + +&scm_wkup_pad_conf_clocks { + fref_xtal_ck: fref_xtal_ck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_clkin>; + ti,bit-shift = <28>; + reg = <0x14>; + }; +}; Index: sys/gnu/dts/arm/orion5x-lacie-d2-network.dts =================================================================== --- sys/gnu/dts/arm/orion5x-lacie-d2-network.dts +++ sys/gnu/dts/arm/orion5x-lacie-d2-network.dts @@ -24,7 +24,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; - linux,stdout-path = &uart0; + stdout-path = &uart0; }; soc { Index: sys/gnu/dts/arm/orion5x-lacie-ethernet-disk-mini-v2.dts =================================================================== --- sys/gnu/dts/arm/orion5x-lacie-ethernet-disk-mini-v2.dts +++ sys/gnu/dts/arm/orion5x-lacie-ethernet-disk-mini-v2.dts @@ -30,7 +30,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; - linux,stdout-path = &uart0; + stdout-path = &uart0; }; soc { Index: sys/gnu/dts/arm/orion5x-linkstation.dtsi =================================================================== --- sys/gnu/dts/arm/orion5x-linkstation.dtsi +++ sys/gnu/dts/arm/orion5x-linkstation.dtsi @@ -48,7 +48,7 @@ / { chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; - linux,stdout-path = &uart0; + stdout-path = &uart0; }; soc { Index: sys/gnu/dts/arm/orion5x-lswsgl.dts =================================================================== --- sys/gnu/dts/arm/orion5x-lswsgl.dts +++ sys/gnu/dts/arm/orion5x-lswsgl.dts @@ -60,7 +60,7 @@ chosen { bootargs = "console=ttyS0,115200 earlyprintk"; - linux,stdout-path = &uart0; + stdout-path = &uart0; }; soc { Index: sys/gnu/dts/arm/orion5x-maxtor-shared-storage-2.dts =================================================================== --- sys/gnu/dts/arm/orion5x-maxtor-shared-storage-2.dts +++ sys/gnu/dts/arm/orion5x-maxtor-shared-storage-2.dts @@ -24,7 +24,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; - linux,stdout-path = &uart0; + stdout-path = &uart0; }; soc { Index: sys/gnu/dts/arm/orion5x-rd88f5182-nas.dts =================================================================== --- sys/gnu/dts/arm/orion5x-rd88f5182-nas.dts +++ sys/gnu/dts/arm/orion5x-rd88f5182-nas.dts @@ -21,7 +21,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; - linux,stdout-path = &uart0; + stdout-path = &uart0; }; soc { Index: sys/gnu/dts/arm/picoxcell-pc7302-pc3x2.dts =================================================================== --- sys/gnu/dts/arm/picoxcell-pc7302-pc3x2.dts +++ sys/gnu/dts/arm/picoxcell-pc7302-pc3x2.dts @@ -23,7 +23,7 @@ }; chosen { - linux,stdout-path = &uart0; + stdout-path = &uart0; }; clocks { Index: sys/gnu/dts/arm/picoxcell-pc7302-pc3x3.dts =================================================================== --- sys/gnu/dts/arm/picoxcell-pc7302-pc3x3.dts +++ sys/gnu/dts/arm/picoxcell-pc7302-pc3x3.dts @@ -23,7 +23,7 @@ }; chosen { - linux,stdout-path = &uart0; + stdout-path = &uart0; }; clocks { Index: sys/gnu/dts/arm/pxa3xx.dtsi =================================================================== --- sys/gnu/dts/arm/pxa3xx.dtsi +++ sys/gnu/dts/arm/pxa3xx.dtsi @@ -117,15 +117,15 @@ status = "disabled"; }; - nand0: nand@43100000 { - compatible = "marvell,pxa3xx-nand"; + nand_controller: nand-controller@43100000 { + compatible = "marvell,pxa3xx-nand-controller"; reg = <0x43100000 90>; interrupts = <45>; clocks = <&clks CLK_NAND>; dmas = <&pdma 97 3>; dma-names = "data"; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; status = "disabled"; }; Index: sys/gnu/dts/arm/qcom-apq8064-cm-qs600.dts =================================================================== --- sys/gnu/dts/arm/qcom-apq8064-cm-qs600.dts +++ sys/gnu/dts/arm/qcom-apq8064-cm-qs600.dts @@ -133,7 +133,7 @@ clock-frequency = <200000>; eeprom@50 { - compatible = "24c02"; + compatible = "atmel,24c02"; reg = <0x50>; pagesize = <32>; }; Index: sys/gnu/dts/arm/qcom-apq8064.dtsi =================================================================== --- sys/gnu/dts/arm/qcom-apq8064.dtsi +++ sys/gnu/dts/arm/qcom-apq8064.dtsi @@ -316,6 +316,23 @@ }; }; + + /* + * These channels from the ADC are simply hardware monitors. + * That is why the ADC is referred to as "HKADC" - HouseKeeping + * ADC. + */ + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&xoadc 0x00 0x01>, /* Battery */ + <&xoadc 0x00 0x02>, /* DC in (charger) */ + <&xoadc 0x00 0x04>, /* VPH the main system voltage */ + <&xoadc 0x00 0x0b>, /* Die temperature */ + <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */ + <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */ + <&xoadc 0x00 0x0e>; /* Charger temperature */ + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; @@ -770,6 +787,52 @@ debounce = <15625>; pull-up; }; + + xoadc: xoadc@197 { + compatible = "qcom,pm8921-adc"; + reg = <197>; + interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>; + #address-cells = <2>; + #size-cells = <0>; + #io-channel-cells = <2>; + + vcoin: adc-channel@00 { + reg = <0x00 0x00>; + }; + vbat: adc-channel@01 { + reg = <0x00 0x01>; + }; + dcin: adc-channel@02 { + reg = <0x00 0x02>; + }; + vph_pwr: adc-channel@04 { + reg = <0x00 0x04>; + }; + batt_therm: adc-channel@08 { + reg = <0x00 0x08>; + }; + batt_id: adc-channel@09 { + reg = <0x00 0x09>; + }; + usb_vbus: adc-channel@0a { + reg = <0x00 0x0a>; + }; + die_temp: adc-channel@0b { + reg = <0x00 0x0b>; + }; + ref_625mv: adc-channel@0c { + reg = <0x00 0x0c>; + }; + ref_1250mv: adc-channel@0d { + reg = <0x00 0x0d>; + }; + chg_temp: adc-channel@0e { + reg = <0x00 0x0e>; + }; + ref_muxoff: adc-channel@0f { + reg = <0x00 0x0f>; + }; + }; }; }; Index: sys/gnu/dts/arm/qcom-msm8974-samsung-klte.dts =================================================================== --- /dev/null +++ sys/gnu/dts/arm/qcom-msm8974-samsung-klte.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-msm8974pro.dtsi" +#include "qcom-pm8841.dtsi" +#include "qcom-pm8941.dtsi" + +/ { + model = "Samsung Galaxy S5"; + compatible = "samsung,klte", "qcom,msm8974"; + + aliases { + serial0 = &blsp1_uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&soc { + serial@f991e000 { + status = "ok"; + }; + +}; Index: sys/gnu/dts/arm/qcom-msm8974-sony-xperia-castor.dts =================================================================== --- sys/gnu/dts/arm/qcom-msm8974-sony-xperia-castor.dts +++ sys/gnu/dts/arm/qcom-msm8974-sony-xperia-castor.dts @@ -491,7 +491,7 @@ pinctrl-0 = <&i2c8_pins>; synaptics@2c { - compatible = "syna,rmi-i2c"; + compatible = "syna,rmi4-i2c"; reg = <0x2c>; interrupt-parent = <&msmgpio>; @@ -506,6 +506,8 @@ pinctrl-names = "default"; pinctrl-0 = <&ts_int_pin>; + syna,startup-delay-ms = <10>; + rmi-f01@1 { reg = <0x1>; syna,nosleep = <1>; Index: sys/gnu/dts/arm/r8a7743-iwg20m.dtsi =================================================================== --- sys/gnu/dts/arm/r8a7743-iwg20m.dtsi +++ sys/gnu/dts/arm/r8a7743-iwg20m.dtsi @@ -34,6 +34,10 @@ }; }; +&cmt0 { + status = "okay"; +}; + &extal_clk { clock-frequency = <20000000>; }; Index: sys/gnu/dts/arm/r8a7743.dtsi =================================================================== --- sys/gnu/dts/arm/r8a7743.dtsi +++ sys/gnu/dts/arm/r8a7743.dtsi @@ -141,29 +141,6 @@ #size-cells = <2>; ranges; - apmu@e6152000 { - compatible = "renesas,r8a7743-apmu", "renesas,apmu"; - reg = <0 0xe6152000 0 0x188>; - cpus = <&cpu0 &cpu1>; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7743", "renesas,rcar-gen2-gpio"; @@ -284,6 +261,48 @@ resets = <&cpg 904>; }; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a7743"; + reg = <0 0xe6060000 0 0x250>; + }; + + tpu: pwm@e60f0000 { + compatible = "renesas,tpu-r8a7743", "renesas,tpu"; + reg = <0 0xe60f0000 0 0x148>; + clocks = <&cpg CPG_MOD 304>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 304>; + #pwm-cells = <3>; + status = "disabled"; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7743-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + apmu@e6152000 { + compatible = "renesas,r8a7743-apmu", "renesas,apmu"; + reg = <0 0xe6152000 0 0x188>; + cpus = <&cpu0 &cpu1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7743-rst"; + reg = <0 0xe6160000 0 0x100>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7743-sysc"; + reg = <0 0xe6180000 0 0x200>; + #power-domain-cells = <1>; + }; + irqc: interrupt-controller@e61c0000 { compatible = "renesas,irqc-r8a7743", "renesas,irqc"; #interrupt-cells = <2>; @@ -316,268 +335,130 @@ #thermal-sensor-cells = <0>; }; - cmt0: timer@ffca0000 { - compatible = "renesas,r8a7743-cmt0", - "renesas,rcar-gen2-cmt0"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 124>; + ipmmu_sy0: mmu@e6280000 { + compatible = "renesas,ipmmu-r8a7743", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6280000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; status = "disabled"; }; - cmt1: timer@e6130000 { - compatible = "renesas,r8a7743-cmt1", - "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 329>; + ipmmu_sy1: mmu@e6290000 { + compatible = "renesas,ipmmu-r8a7743", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6290000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; status = "disabled"; }; - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7743-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; + ipmmu_ds: mmu@e6740000 { + compatible = "renesas,ipmmu-r8a7743", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6740000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; }; - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; + ipmmu_mp: mmu@ec680000 { + compatible = "renesas,ipmmu-r8a7743", + "renesas,ipmmu-vmsa"; + reg = <0 0xec680000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; }; - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7743-rst"; - reg = <0 0xe6160000 0 0x100>; + ipmmu_mx: mmu@fe951000 { + compatible = "renesas,ipmmu-r8a7743", + "renesas,ipmmu-vmsa"; + reg = <0 0xfe951000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; }; - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7743-sysc"; - reg = <0 0xe6180000 0 0x200>; - #power-domain-cells = <1>; + ipmmu_gp: mmu@e62a0000 { + compatible = "renesas,ipmmu-r8a7743", + "renesas,ipmmu-vmsa"; + reg = <0 0xe62a0000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; }; - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a7743"; - reg = <0 0xe6060000 0 0x250>; + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; }; - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7743", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; + + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x10>; + }; + }; + + icram2: sram@e6300000 { + compatible = "mmio-sram"; + reg = <0 0xe6300000 0 0x40000>; + }; + + /* The memory map in the User's Manual maps the cores to + * bus numbers + */ + i2c0: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7743", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; + resets = <&cpg 931>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; }; - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7743", - "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; + i2c1: i2c@e6518000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7743", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; + resets = <&cpg 930>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; }; - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7743", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; + i2c2: i2c@e6530000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7743", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7743", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7743-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7743-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - /* The memory map in the User's Manual maps the cores to bus - * numbers - */ - i2c0: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7743", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 931>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7743", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 930>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7743", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 929>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; + resets = <&cpg 929>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; }; i2c3: i2c@e6540000 { @@ -675,6 +556,168 @@ status = "disabled"; }; + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7743", + "renesas,rcar-gen2-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 704>; + renesas,buswait = <4>; + phys = <&usb0 1>; + phy-names = "usb"; + status = "disabled"; + }; + + usbphy: usb-phy@e6590100 { + compatible = "renesas,usb-phy-r8a7743", + "renesas,rcar-gen2-usb-phy"; + reg = <0 0xe6590100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cpg CPG_MOD 704>; + clock-names = "usbhs"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + + usb0: usb-channel@0 { + reg = <0>; + #phy-cells = <1>; + }; + usb2: usb-channel@2 { + reg = <2>; + #phy-cells = <1>; + }; + }; + + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a7743-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a7743-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7743", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a7743", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7743", + "renesas,etheravb-rcar-gen2"; + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupts = ; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 812>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7743", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 917>; + status = "disabled"; + }; + scifa0: serial@e6c40000 { compatible = "renesas,scifa-r8a7743", "renesas,rcar-gen2-scifa", "renesas,scifa"; @@ -954,88 +997,6 @@ status = "disabled"; }; - icram2: sram@e6300000 { - compatible = "mmio-sram"; - reg = <0 0xe6300000 0 0x40000>; - }; - - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - }; - - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; - - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x10>; - }; - }; - - ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7743", - "renesas,rcar-gen2-ether"; - reg = <0 0xee700000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 813>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 813>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7743", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = ; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 812>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7743", - "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = ; - clocks = <&cpg CPG_MOD 315>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 315>; - reg-io-width = <4>; - max-frequency = <97500000>; - status = "disabled"; - }; - - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7743", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 917>; - status = "disabled"; - }; - msiof0: spi@e6e20000 { compatible = "renesas,msiof-r8a7743", "renesas,rcar-gen2-msiof"; @@ -1084,26 +1045,6 @@ status = "disabled"; }; - /* - * pci1 and xhci share the same phy, therefore only one of them - * can be active at any one time. If both of them are enabled, - * a race condition will determine who'll control the phy. - * A firmware file is needed by the xhci driver in order for - * USB 3.0 to work properly. - */ - xhci: usb@ee000000 { - compatible = "renesas,xhci-r8a7743", - "renesas,rcar-gen2-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 328>; - phys = <&usb2 1>; - phy-names = "usb"; - status = "disabled"; - }; - pwm0: pwm@e6e30000 { compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; reg = <0 0xe6e30000 0 0x8>; @@ -1174,98 +1115,32 @@ status = "disabled"; }; - tpu: pwm@e60f0000 { - compatible = "renesas,tpu-r8a7743", "renesas,tpu"; - reg = <0 0xe60f0000 0 0x148>; - clocks = <&cpg CPG_MOD 304>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 304>; - #pwm-cells = <3>; - status = "disabled"; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7743", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: sd@ee140000 { - compatible = "renesas,sdhi-r8a7743", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - sdhi2: sd@ee160000 { - compatible = "renesas,sdhi-r8a7743", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee160000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7743", - "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; + can0: can@e6e80000 { + compatible = "renesas,can-r8a7743", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7743_CLK_RCAN>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 704>; - renesas,buswait = <4>; - phys = <&usb0 1>; - phy-names = "usb"; + resets = <&cpg 916>; status = "disabled"; }; - usbphy: usb-phy@e6590100 { - compatible = "renesas,usb-phy-r8a7743", - "renesas,rcar-gen2-usb-phy"; - reg = <0 0xe6590100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cpg CPG_MOD 704>; - clock-names = "usbhs"; + can1: can@e6e88000 { + compatible = "renesas,can-r8a7743", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A7743_CLK_RCAN>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 704>; + resets = <&cpg 915>; status = "disabled"; - - usb0: usb-channel@0 { - reg = <0>; - #phy-cells = <1>; - }; - usb2: usb-channel@2 { - reg = <2>; - #phy-cells = <1>; - }; }; vin0: video@e6ef0000 { @@ -1301,177 +1176,21 @@ status = "disabled"; }; - du: display@feb00000 { - compatible = "renesas,du-r8a7743"; - reg = <0 0xfeb00000 0 0x40000>, - <0 0xfeb90000 0 0x1c>; - reg-names = "du", "lvds.0"; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 726>; - clock-names = "du.0", "du.1", "lvds.0"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - }; - }; - }; - }; - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7743", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A7743_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6e88000 { - compatible = "renesas,can-r8a7743", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A7743_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - pci0: pci@ee090000 { - compatible = "renesas,pci-r8a7743", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee090000 0 0xc00>, - <0 0xee080000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; - interrupt-map-mask = <0xff00 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x800 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x1000 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - }; - - pci1: pci@ee0d0000 { - compatible = "renesas,pci-r8a7743", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee0d0000 0 0xc00>, - <0 0xee0c0000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <1 1>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; - interrupt-map-mask = <0xff00 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x10800 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x11000 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - }; - - pciec: pcie@fe000000 { - compatible = "renesas,pcie-r8a7743", - "renesas,pcie-rcar-gen2"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 - 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 - 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 - 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000 - 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7743", - "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a7743", + "renesas,rcar_sound-gen2"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; clocks = <&cpg CPG_MOD 1005>, <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, @@ -1641,6 +1360,369 @@ }; }; }; + + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7743", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <13>; + }; + + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a7743", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 501>; + #dma-cells = <1>; + dma-channels = <13>; + }; + + /* + * pci1 and xhci share the same phy, therefore only one of them + * can be active at any one time. If both of them are enabled, + * a race condition will determine who'll control the phy. + * A firmware file is needed by the xhci driver in order for + * USB 3.0 to work properly. + */ + xhci: usb@ee000000 { + compatible = "renesas,xhci-r8a7743", + "renesas,rcar-gen2-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 328>; + phys = <&usb2 1>; + phy-names = "usb"; + status = "disabled"; + }; + + pci0: pci@ee090000 { + compatible = "renesas,pci-r8a7743", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee090000 0 0xc00>, + <0 0xee080000 0 0x1100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + }; + + pci1: pci@ee0d0000 { + compatible = "renesas,pci-r8a7743", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee0d0000 0 0xc00>, + <0 0xee0c0000 0 0x1100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <1 1>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x10800 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x11000 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + }; + + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7743", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee100000 0 0x328>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: sd@ee140000 { + compatible = "renesas,sdhi-r8a7743", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee140000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, + <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi2: sd@ee160000 { + compatible = "renesas,sdhi-r8a7743", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee160000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; + + mmcif0: mmc@ee200000 { + compatible = "renesas,mmcif-r8a7743", + "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = ; + clocks = <&cpg CPG_MOD 315>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, + <&dmac1 0xd1>, <&dmac1 0xd2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 315>; + reg-io-width = <4>; + max-frequency = <97500000>; + status = "disabled"; + }; + + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7743", + "renesas,rcar-gen2-ether"; + reg = <0 0xee700000 0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 813>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + pciec: pcie@fe000000 { + compatible = "renesas,pcie-r8a7743", + "renesas,pcie-rcar-gen2"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 + 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 + 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 + 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000 + 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; + }; + + vsp@fe928000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe928000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 131>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 131>; + }; + + vsp@fe930000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe930000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 128>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 128>; + }; + + vsp@fe938000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe938000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 127>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 127>; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a7743"; + reg = <0 0xfeb00000 0 0x40000>, + <0 0xfeb90000 0 0x1c>; + reg-names = "du", "lvds.0"; + interrupts = , + ; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 726>; + clock-names = "du.0", "du.1", "lvds.0"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_lvds0: endpoint { + }; + }; + }; + }; + + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; + + cmt0: timer@ffca0000 { + compatible = "renesas,r8a7743-cmt0", + "renesas,rcar-gen2-cmt0"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 124>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a7743-cmt1", + "renesas,rcar-gen2-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 329>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 329>; + status = "disabled"; + }; }; thermal-zones { Index: sys/gnu/dts/arm/r8a7745-iwg22m.dtsi =================================================================== --- sys/gnu/dts/arm/r8a7745-iwg22m.dtsi +++ sys/gnu/dts/arm/r8a7745-iwg22m.dtsi @@ -29,6 +29,10 @@ }; }; +&cmt0 { + status = "okay"; +}; + &extal_clk { clock-frequency = <20000000>; }; Index: sys/gnu/dts/arm/r8a7745.dtsi =================================================================== --- sys/gnu/dts/arm/r8a7745.dtsi +++ sys/gnu/dts/arm/r8a7745.dtsi @@ -121,29 +121,6 @@ #size-cells = <2>; ranges; - apmu@e6151000 { - compatible = "renesas,r8a7745-apmu", "renesas,apmu"; - reg = <0 0xe6151000 0 0x188>; - cpus = <&cpu0 &cpu1>; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7745", "renesas,rcar-gen2-gpio"; @@ -249,55 +226,18 @@ resets = <&cpg 905>; }; - irqc: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7745", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - cmt0: timer@ffca0000 { - compatible = "renesas,r8a7745-cmt0", - "renesas,rcar-gen2-cmt0"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 124>; - status = "disabled"; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a7745"; + reg = <0 0xe6060000 0 0x11c>; }; - cmt1: timer@e6130000 { - compatible = "renesas,r8a7745-cmt1", - "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; + tpu: pwm@e60f0000 { + compatible = "renesas,tpu-r8a7745", "renesas,tpu"; + reg = <0 0xe60f0000 0 0x148>; + clocks = <&cpg CPG_MOD 304>; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 329>; + resets = <&cpg 304>; + #pwm-cells = <3>; status = "disabled"; }; @@ -311,9 +251,10 @@ #reset-cells = <1>; }; - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; + apmu@e6151000 { + compatible = "renesas,r8a7745-apmu", "renesas,apmu"; + reg = <0 0xe6151000 0 0x188>; + cpus = <&cpu0 &cpu1>; }; rst: reset-controller@e6160000 { @@ -327,450 +268,355 @@ #power-domain-cells = <1>; }; - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a7745"; - reg = <0 0xe6060000 0 0x11c>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7745", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; + irqc: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7745", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 407>; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; + resets = <&cpg 407>; }; - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7745", - "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; + ipmmu_sy0: mmu@e6280000 { + compatible = "renesas,ipmmu-r8a7745", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6280000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; }; - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7745", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <13>; + ipmmu_sy1: mmu@e6290000 { + compatible = "renesas,ipmmu-r8a7745", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6290000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; }; - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7745-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; + ipmmu_ds: mmu@e6740000 { + compatible = "renesas,ipmmu-r8a7745", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6740000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; }; - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7745-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; + ipmmu_mp: mmu@ec680000 { + compatible = "renesas,ipmmu-r8a7745", + "renesas,ipmmu-vmsa"; + reg = <0 0xec680000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; }; - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7745", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, - <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 204>; + ipmmu_mx: mmu@fe951000 { + compatible = "renesas,ipmmu-r8a7745", + "renesas,ipmmu-vmsa"; + reg = <0 0xfe951000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; status = "disabled"; }; - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7745", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c50000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>; - clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>, - <&dmac1 0x25>, <&dmac1 0x26>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 203>; + ipmmu_gp: mmu@e62a0000 { + compatible = "renesas,ipmmu-r8a7745", + "renesas,ipmmu-vmsa"; + reg = <0 0xe62a0000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; status = "disabled"; }; - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7745", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c60000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>; - clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>, - <&dmac1 0x27>, <&dmac1 0x28>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; }; - scifa3: serial@e6c70000 { - compatible = "renesas,scifa-r8a7745", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c70000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 1106>; - clock-names = "fck"; - dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, - <&dmac1 0x1b>, <&dmac1 0x1c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 1106>; - status = "disabled"; + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; + + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x10>; + }; }; - scifa4: serial@e6c78000 { - compatible = "renesas,scifa-r8a7745", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c78000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 1107>; - clock-names = "fck"; - dmas = <&dmac0 0x1f>, <&dmac0 0x20>, - <&dmac1 0x1f>, <&dmac1 0x20>; - dma-names = "tx", "rx", "tx", "rx"; + icram2: sram@e6300000 { + compatible = "mmio-sram"; + reg = <0 0xe6300000 0 0x40000>; + }; + i2c0: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7745", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 1107>; + resets = <&cpg 931>; + i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; - scifa5: serial@e6c80000 { - compatible = "renesas,scifa-r8a7745", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c80000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 1108>; - clock-names = "fck"; - dmas = <&dmac0 0x23>, <&dmac0 0x24>, - <&dmac1 0x23>, <&dmac1 0x24>; - dma-names = "tx", "rx", "tx", "rx"; + i2c1: i2c@e6518000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7745", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 1108>; + resets = <&cpg 930>; + i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7745", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>; - clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, - <&dmac1 0x3d>, <&dmac1 0x3e>; - dma-names = "tx", "rx", "tx", "rx"; + i2c2: i2c@e6530000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7745", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 206>; + resets = <&cpg 929>; + i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7745", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>; - clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>, - <&dmac1 0x19>, <&dmac1 0x1a>; - dma-names = "tx", "rx", "tx", "rx"; + i2c3: i2c@e6540000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7745", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 207>; + resets = <&cpg 928>; + i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7745", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 216>; - clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, - <&dmac1 0x1d>, <&dmac1 0x1e>; - dma-names = "tx", "rx", "tx", "rx"; + i2c4: i2c@e6520000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7745", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6520000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 927>; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 216>; + resets = <&cpg 927>; + i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7745", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 721>, - <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; + i2c5: i2c@e6528000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7745", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6528000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 925>; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 721>; + resets = <&cpg 925>; + i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7745", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 720>, - <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; + iic0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7745", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 318>; + dmas = <&dmac0 0x61>, <&dmac0 0x62>, + <&dmac1 0x61>, <&dmac1 0x62>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 720>; + resets = <&cpg 318>; status = "disabled"; }; - scif2: serial@e6e58000 { - compatible = "renesas,scif-r8a7745", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e58000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 719>, - <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; + iic1: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7745", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 323>; + dmas = <&dmac0 0x65>, <&dmac0 0x66>, + <&dmac1 0x65>, <&dmac1 0x66>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 719>; + resets = <&cpg 323>; status = "disabled"; }; - scif3: serial@e6ea8000 { - compatible = "renesas,scif-r8a7745", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ea8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 718>, - <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>, - <&dmac1 0x2f>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7745", + "renesas,rcar-gen2-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 718>; + resets = <&cpg 704>; + renesas,buswait = <4>; + phys = <&usb0 1>; + phy-names = "usb"; status = "disabled"; }; - scif4: serial@e6ee0000 { - compatible = "renesas,scif-r8a7745", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 715>, - <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, - <&dmac1 0xfb>, <&dmac1 0xfc>; - dma-names = "tx", "rx", "tx", "rx"; + usbphy: usb-phy@e6590100 { + compatible = "renesas,usb-phy-r8a7745", + "renesas,rcar-gen2-usb-phy"; + reg = <0 0xe6590100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cpg CPG_MOD 704>; + clock-names = "usbhs"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 715>; + resets = <&cpg 704>; status = "disabled"; + + usb0: usb-channel@0 { + reg = <0>; + #phy-cells = <1>; + }; + usb2: usb-channel@2 { + reg = <2>; + #phy-cells = <1>; + }; }; - scif5: serial@e6ee8000 { - compatible = "renesas,scif-r8a7745", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>, - <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, - <&dmac1 0xfd>, <&dmac1 0xfe>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - }; - - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7745", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 717>, - <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a7745-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; }; - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7745", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>, - <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a7745-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; }; - hscif2: serial@e62d0000 { - compatible = "renesas,hscif-r8a7745", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62d0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 713>, - <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, - <&dmac1 0x3b>, <&dmac1 0x3c>; - dma-names = "tx", "rx", "tx", "rx"; + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7745", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 713>; - status = "disabled"; - }; - - icram2: sram@e6300000 { - compatible = "mmio-sram"; - reg = <0 0xe6300000 0 0x40000>; - }; - - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - }; - - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; - - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x10>; - }; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <15>; }; - ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7745", - "renesas,rcar-gen2-ether"; - reg = <0 0xee700000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 813>; + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a7745", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 813>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <15>; }; avb: ethernet@e6800000 { @@ -786,257 +632,353 @@ status = "disabled"; }; - i2c0: i2c@e6508000 { + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7745", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + num-cs = <1>; #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,i2c-r8a7745", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 931>; - i2c-scl-internal-delay-ns = <6>; + resets = <&cpg 917>; status = "disabled"; }; - i2c1: i2c@e6518000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7745", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7745", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c40000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 930>; - i2c-scl-internal-delay-ns = <6>; + resets = <&cpg 204>; status = "disabled"; }; - i2c2: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7745", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7745", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c50000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 929>; - i2c-scl-internal-delay-ns = <6>; + resets = <&cpg 203>; status = "disabled"; }; - i2c3: i2c@e6540000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7745", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7745", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c60000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <6>; + resets = <&cpg 202>; status = "disabled"; }; - i2c4: i2c@e6520000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7745", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6520000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 927>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c5: i2c@e6528000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7745", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6528000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 925>; + scifa3: serial@e6c70000 { + compatible = "renesas,scifa-r8a7745", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c70000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 1106>; + clock-names = "fck"; + dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, + <&dmac1 0x1b>, <&dmac1 0x1c>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 925>; - i2c-scl-internal-delay-ns = <6>; + resets = <&cpg 1106>; status = "disabled"; }; - iic0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7745", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 318>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>, - <&dmac1 0x61>, <&dmac1 0x62>; + scifa4: serial@e6c78000 { + compatible = "renesas,scifa-r8a7745", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c78000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 1107>; + clock-names = "fck"; + dmas = <&dmac0 0x1f>, <&dmac0 0x20>, + <&dmac1 0x1f>, <&dmac1 0x20>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 318>; + resets = <&cpg 1107>; status = "disabled"; }; - iic1: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7745", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 323>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>, - <&dmac1 0x65>, <&dmac1 0x66>; + scifa5: serial@e6c80000 { + compatible = "renesas,scifa-r8a7745", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c80000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 1108>; + clock-names = "fck"; + dmas = <&dmac0 0x23>, <&dmac0 0x24>, + <&dmac1 0x23>, <&dmac1 0x24>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 323>; + resets = <&cpg 1108>; status = "disabled"; }; - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7745", - "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = ; - clocks = <&cpg CPG_MOD 315>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7745", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 315>; - reg-io-width = <4>; - max-frequency = <97500000>; + resets = <&cpg 206>; status = "disabled"; }; - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7745", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7745", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c30000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>; + clock-names = "fck"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 917>; + resets = <&cpg 207>; status = "disabled"; }; - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7745", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7745", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6ce0000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 811>; + resets = <&cpg 216>; status = "disabled"; }; - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7745", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7745", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 721>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 810>; + resets = <&cpg 721>; status = "disabled"; }; - du: display@feb00000 { - compatible = "renesas,du-r8a7745"; - reg = <0 0xfeb00000 0 0x40000>; - reg-names = "du"; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7745", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 720>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 720>; status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb0: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_rgb1: endpoint { - }; - }; - }; }; - msiof0: spi@e6e20000 { - compatible = "renesas,msiof-r8a7745", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e20000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 000>; - dmas = <&dmac0 0x51>, <&dmac0 0x52>, - <&dmac1 0x51>, <&dmac1 0x52>; + scif2: serial@e6e58000 { + compatible = "renesas,scif-r8a7745", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e58000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 719>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 000>; + resets = <&cpg 719>; status = "disabled"; }; - msiof1: spi@e6e10000 { - compatible = "renesas,msiof-r8a7745", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x55>, <&dmac0 0x56>, - <&dmac1 0x55>, <&dmac1 0x56>; + scif3: serial@e6ea8000 { + compatible = "renesas,scif-r8a7745", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ea8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 718>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>, + <&dmac1 0x2f>, <&dmac1 0x30>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 208>; + resets = <&cpg 718>; status = "disabled"; }; - msiof2: spi@e6e00000 { - compatible = "renesas,msiof-r8a7745", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 205>; - dmas = <&dmac0 0x41>, <&dmac0 0x42>, - <&dmac1 0x41>, <&dmac1 0x42>; + scif4: serial@e6ee0000 { + compatible = "renesas,scif-r8a7745", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 715>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, + <&dmac1 0xfb>, <&dmac1 0xfc>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 205>; + resets = <&cpg 715>; status = "disabled"; }; - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; + scif5: serial@e6ee8000 { + compatible = "renesas,scif-r8a7745", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 714>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, + <&dmac1 0xfd>, <&dmac1 0xfe>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; + }; + + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7745", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 717>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; + }; + + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7745", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + }; + + hscif2: serial@e62d0000 { + compatible = "renesas,hscif-r8a7745", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62d0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 713>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, + <&dmac1 0x3b>, <&dmac1 0x3c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 713>; + status = "disabled"; + }; + + msiof0: spi@e6e20000 { + compatible = "renesas,msiof-r8a7745", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e20000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 000>; + dmas = <&dmac0 0x51>, <&dmac0 0x52>, + <&dmac1 0x51>, <&dmac1 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 000>; + status = "disabled"; + }; + + msiof1: spi@e6e10000 { + compatible = "renesas,msiof-r8a7745", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x55>, <&dmac0 0x56>, + <&dmac1 0x55>, <&dmac1 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 208>; + status = "disabled"; + }; + + msiof2: spi@e6e00000 { + compatible = "renesas,msiof-r8a7745", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 205>; + dmas = <&dmac0 0x41>, <&dmac0 0x42>, + <&dmac1 0x41>, <&dmac1 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 205>; + status = "disabled"; + }; + + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; resets = <&cpg 523>; #pwm-cells = <2>; @@ -1103,249 +1045,107 @@ status = "disabled"; }; - tpu: pwm@e60f0000 { - compatible = "renesas,tpu-r8a7745", "renesas,tpu"; - reg = <0 0xe60f0000 0 0x148>; - clocks = <&cpg CPG_MOD 304>; + can0: can@e6e80000 { + compatible = "renesas,can-r8a7745", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7745_CLK_RCAN>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 304>; - #pwm-cells = <3>; + resets = <&cpg 916>; status = "disabled"; }; - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7745", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; + can1: can@e6e88000 { + compatible = "renesas,can-r8a7745", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A7745_CLK_RCAN>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 314>; + resets = <&cpg 915>; status = "disabled"; }; - sdhi1: sd@ee140000 { - compatible = "renesas,sdhi-r8a7745", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7745", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 312>; + resets = <&cpg 811>; status = "disabled"; }; - sdhi2: sd@ee160000 { - compatible = "renesas,sdhi-r8a7745", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee160000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7745", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 311>; + resets = <&cpg 810>; status = "disabled"; }; - pci0: pci@ee090000 { - compatible = "renesas,pci-r8a7745", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee090000 0 0xc00>, - <0 0xee080000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a7745", + "renesas,rcar_sound-gen2"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>, + <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>, + <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clka>, <&audio_clkb>, <&audio_clkc>, + <&cpg CPG_CORE R8A7745_CLK_M2>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0", + "src.6", "src.5", "src.4", "src.3", + "src.2", "src.1", + "ctu.0", "ctu.1", + "mix.0", "mix.1", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; - interrupt-map-mask = <0xff00 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x800 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x1000 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - }; - - pci1: pci@ee0d0000 { - compatible = "renesas,pci-r8a7745", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee0d0000 0 0xc00>, - <0 0xee0c0000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <1 1>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; - interrupt-map-mask = <0xff00 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x10800 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x11000 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7745", - "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 704>; - renesas,buswait = <4>; - phys = <&usb0 1>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy: usb-phy@e6590100 { - compatible = "renesas,usb-phy-r8a7745", - "renesas,rcar-gen2-usb-phy"; - reg = <0 0xe6590100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cpg CPG_MOD 704>; - clock-names = "usbhs"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 704>; - status = "disabled"; - - usb0: usb-channel@0 { - reg = <0>; - #phy-cells = <1>; - }; - usb2: usb-channel@2 { - reg = <2>; - #phy-cells = <1>; - }; - }; - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7745", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A7745_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6e88000 { - compatible = "renesas,can-r8a7745", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A7745_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7745", - "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>, - <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>, - <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clka>, <&audio_clkb>, <&audio_clkc>, - <&cpg CPG_CORE R8A7745_CLK_M2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.6", "src.5", "src.4", "src.3", - "src.2", "src.1", - "ctu.0", "ctu.1", - "mix.0", "mix.1", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, - <&cpg 1009>, <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, <&cpg 1014>, - <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, + <&cpg 1009>, <&cpg 1010>, <&cpg 1011>, + <&cpg 1012>, <&cpg 1013>, <&cpg 1014>, + <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0"; + status = "disabled"; rcar_sound,dvc { @@ -1474,6 +1274,278 @@ }; }; }; + + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7745", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <13>; + }; + + pci0: pci@ee090000 { + compatible = "renesas,pci-r8a7745", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee090000 0 0xc00>, + <0 0xee080000 0 0x1100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + }; + + pci1: pci@ee0d0000 { + compatible = "renesas,pci-r8a7745", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee0d0000 0 0xc00>, + <0 0xee0c0000 0 0x1100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <1 1>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x10800 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x11000 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + }; + + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7745", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee100000 0 0x328>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: sd@ee140000 { + compatible = "renesas,sdhi-r8a7745", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee140000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, + <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi2: sd@ee160000 { + compatible = "renesas,sdhi-r8a7745", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee160000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; + + mmcif0: mmc@ee200000 { + compatible = "renesas,mmcif-r8a7745", + "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = ; + clocks = <&cpg CPG_MOD 315>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, + <&dmac1 0xd1>, <&dmac1 0xd2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 315>; + reg-io-width = <4>; + max-frequency = <97500000>; + status = "disabled"; + }; + + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7745", + "renesas,rcar-gen2-ether"; + reg = <0 0xee700000 0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 813>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + vsp@fe928000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe928000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 131>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 131>; + }; + + vsp@fe930000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe930000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 128>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 128>; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a7745"; + reg = <0 0xfeb00000 0 0x40000>; + reg-names = "du"; + interrupts = , + ; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; + clock-names = "du.0", "du.1"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb0: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_rgb1: endpoint { + }; + }; + }; + }; + + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; + + cmt0: timer@ffca0000 { + compatible = "renesas,r8a7745-cmt0", + "renesas,rcar-gen2-cmt0"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 124>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a7745-cmt1", + "renesas,rcar-gen2-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 329>; + clock-names = "fck"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 329>; + status = "disabled"; + }; }; timer { Index: sys/gnu/dts/arm/r8a7779-marzen.dts =================================================================== --- sys/gnu/dts/arm/r8a7779-marzen.dts +++ sys/gnu/dts/arm/r8a7779-marzen.dts @@ -42,6 +42,19 @@ regulator-always-on; }; + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; + ethernet@18000000 { compatible = "smsc,lan9220", "smsc,lan9115"; reg = <0x18000000 0x100>; @@ -243,6 +256,7 @@ pinctrl-names = "default"; vmmc-supply = <&fixedregulator3v3>; + vqmmc-supply = <&vccq_sdhi0>; bus-width = <4>; status = "okay"; }; Index: sys/gnu/dts/arm/r8a7790-lager.dts =================================================================== --- sys/gnu/dts/arm/r8a7790-lager.dts +++ sys/gnu/dts/arm/r8a7790-lager.dts @@ -51,8 +51,11 @@ serial0 = &scif0; serial1 = &scifa1; i2c8 = &gpioi2c1; + i2c9 = &gpioi2c2; i2c10 = &i2cexio0; i2c11 = &i2cexio1; + i2c12 = &i2chdmi; + i2c13 = &i2cpwr; }; chosen { @@ -244,6 +247,12 @@ }; }; + cec_clock: cec-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + hdmi-out { compatible = "hdmi-connector"; type = "a"; @@ -272,8 +281,18 @@ #size-cells = <0>; compatible = "i2c-gpio"; status = "disabled"; - sda-gpios = <&gpio1 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <5>; + }; + + gpioi2c2: i2c-9 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + scl-gpios = <&gpio5 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <5>; }; @@ -308,6 +327,138 @@ #address-cells = <1>; #size-cells = <0>; }; + + /* + * IIC2 and I2C2 may be switched using pinmux. + * A fallback to GPIO is also provided. + */ + i2chdmi: i2c-12 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&iic2>, <&i2c2>, <&gpioi2c2>; + i2c-bus-name = "i2c-hdmi"; + #address-cells = <1>; + #size-cells = <0>; + + ak4643: codec@12 { + compatible = "asahi-kasei,ak4643"; + #sound-dai-cells = <0>; + reg = <0x12>; + }; + + composite-in@20 { + compatible = "adi,adv7180"; + reg = <0x20>; + remote = <&vin1>; + + port { + adv7180: endpoint { + bus-width = <8>; + remote-endpoint = <&vin1ep0>; + }; + }; + }; + + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&gpio1>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + clocks = <&cec_clock>; + clock-names = "cec"; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; + + hdmi-in@4c { + compatible = "adi,adv7612"; + reg = <0x4c>; + interrupt-parent = <&gpio1>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + default-input = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7612_in: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; + }; + + port@2 { + reg = <2>; + adv7612_out: endpoint { + remote-endpoint = <&vin0ep2>; + }; + }; + }; + }; + }; + + /* + * IIC3 and I2C3 may be switched using pinmux. + * IIC3/I2C3 does not appear to support fallback to GPIO. + */ + i2cpwr: i2c-13 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&iic3>, <&i2c3>; + i2c-bus-name = "i2c-pwr"; + #address-cells = <1>; + #size-cells = <0>; + + pmic@58 { + compatible = "dlg,da9063"; + reg = <0x58>; + interrupt-parent = <&irqc0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + + rtc { + compatible = "dlg,da9063-rtc"; + }; + + wdt { + compatible = "dlg,da9063-watchdog"; + }; + }; + + vdd_dvfs: regulator@68 { + compatible = "dlg,da9210"; + reg = <0x68>; + interrupt-parent = <&irqc0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; + }; }; &du { @@ -316,10 +467,8 @@ status = "okay"; clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>, - <&cpg CPG_MOD 726>, <&cpg CPG_MOD 725>, <&x13_clk>, <&x2_clk>; - clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1", - "dclkin.0", "dclkin.1"; + clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1"; ports { port@0 { @@ -327,12 +476,26 @@ remote-endpoint = <&adv7123_in>; }; }; + }; +}; + +&lvds0 { + status = "okay"; + + ports { port@1 { endpoint { remote-endpoint = <&adv7511_in>; }; }; - port@2 { + }; +}; + +&lvds1 { + status = "okay"; + + ports { + port@1 { lvds_connector: endpoint { }; }; @@ -437,11 +600,21 @@ function = "iic1"; }; + i2c2_pins: i2c2 { + groups = "i2c2"; + function = "i2c2"; + }; + iic2_pins: iic2 { groups = "iic2"; function = "iic2"; }; + i2c3_pins: i2c3 { + groups = "i2c3"; + function = "i2c3"; + }; + iic3_pins: iic3 { groups = "iic3"; function = "iic3"; @@ -643,124 +816,28 @@ pinctrl-names = "i2c-exio1"; }; -&iic2 { - status = "okay"; - pinctrl-0 = <&iic2_pins>; - pinctrl-names = "default"; +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "i2c-hdmi"; clock-frequency = <100000>; +}; - ak4643: codec@12 { - compatible = "asahi-kasei,ak4643"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - composite-in@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - remote = <&vin1>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin1ep0>; - }; - }; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio1>; - interrupts = <15 IRQ_TYPE_LEVEL_LOW>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con_out>; - }; - }; - }; - }; - - hdmi-in@4c { - compatible = "adi,adv7612"; - reg = <0x4c>; - interrupt-parent = <&gpio1>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - default-input = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; +&iic2 { + pinctrl-0 = <&iic2_pins>; + pinctrl-names = "i2c-hdmi"; - port@0 { - reg = <0>; - adv7612_in: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; - }; + clock-frequency = <100000>; +}; - port@2 { - reg = <2>; - adv7612_out: endpoint { - remote-endpoint = <&vin0ep2>; - }; - }; - }; - }; +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "i2c-pwr"; }; -&iic3 { - pinctrl-names = "default"; +&iic3 { pinctrl-0 = <&iic3_pins>; - status = "okay"; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - rtc { - compatible = "dlg,da9063-rtc"; - }; - - wdt { - compatible = "dlg,da9063-watchdog"; - }; - }; - - vdd_dvfs: regulator@68 { - compatible = "dlg,da9210"; - reg = <0x68>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - }; + pinctrl-names = "i2c-pwr"; }; &pci0 { Index: sys/gnu/dts/arm/r8a7790-stout.dts =================================================================== --- /dev/null +++ sys/gnu/dts/arm/r8a7790-stout.dts @@ -0,0 +1,363 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Stout board + * + * Copyright (C) 2018 Marek Vasut + */ + +/dts-v1/; +#include "r8a7790.dtsi" +#include +#include + +/ { + model = "Stout"; + compatible = "renesas,stout", "renesas,r8a7790"; + + aliases { + serial0 = &scifa0; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + leds { + compatible = "gpio-leds"; + led1 { + gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + }; + led2 { + gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; + }; + led3 { + gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; + }; + led5 { + gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + }; + }; + + fixedregulator3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_out: endpoint { + remote-endpoint = <&adv7511_out>; + }; + }; + }; + + osc1_clk: osc1-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148500000>; + }; + + osc4_clk: osc4-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; +}; + +&du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; + status = "okay"; + + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>, + <&cpg CPG_MOD 726>, <&cpg CPG_MOD 725>, + <&osc1_clk>; + clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1", "dclkin.0"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&adv7511_in>; + }; + }; + port@1 { + lvds_connector0: endpoint { + }; + }; + port@2 { + lvds_connector1: endpoint { + }; + }; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&pfc { + + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + du_pins: du { + groups = "du_rgb888", "du_sync_1", "du_clk_out_0"; + function = "du"; + }; + + scifa0_pins: scifa0 { + groups = "scifa0_data_b"; + function = "scifa0"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk"; + function = "scif_clk"; + }; + + ether_pins: ether { + groups = "eth_link", "eth_mdio", "eth_rmii"; + function = "eth"; + }; + + phy1_pins: phy1 { + groups = "intc_irq1"; + function = "intc"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + qspi_pins: qspi { + groups = "qspi_ctrl", "qspi_data4"; + function = "qspi"; + }; + + iic2_pins: iic2 { + groups = "iic2_b"; + function = "iic2"; + }; + + iic3_pins: iic3 { + groups = "iic3"; + function = "iic3"; + }; + + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; +}; + +ðer { + pinctrl-0 = <ðer_pins &phy1_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&irqc0>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + }; +}; + +&cmt0 { + status = "okay"; +}; + +&qspi { + pinctrl-0 = <&qspi_pins>; + pinctrl-names = "default"; + + status = "okay"; + + flash: flash@0 { + compatible = "spansion,s25fl512s", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <30000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + spi-cpha; + spi-cpol; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "loader"; + reg = <0x00000000 0x00080000>; + read-only; + }; + partition@80000 { + label = "uboot"; + reg = <0x00080000 0x00040000>; + read-only; + }; + partition@c0000 { + label = "uboot-env"; + reg = <0x000c0000 0x00040000>; + read-only; + }; + partition@100000 { + label = "flash"; + reg = <0x00100000 0x03f00000>; + }; + }; + }; +}; + +&scifa0 { + pinctrl-0 = <&scifa0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi0>; + cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&cpu0 { + cpu0-supply = <&vdd_dvfs>; +}; + +&iic2 { + status = "okay"; + pinctrl-0 = <&iic2_pins>; + pinctrl-names = "default"; + + clock-frequency = <100000>; + + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&gpio1>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + clocks = <&osc4_clk>; + clock-names = "cec"; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&du_out_rgb>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; +}; + +&iic3 { + pinctrl-names = "default"; + pinctrl-0 = <&iic3_pins>; + status = "okay"; + + pmic@58 { + compatible = "dlg,da9063"; + reg = <0x58>; + interrupt-parent = <&irqc0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + + rtc { + compatible = "dlg,da9063-rtc"; + }; + + wdt { + compatible = "dlg,da9063-watchdog"; + }; + }; + + vdd_dvfs: regulator@68 { + compatible = "dlg,da9210"; + reg = <0x68>; + interrupt-parent = <&irqc0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd: regulator@70 { + compatible = "dlg,da9210"; + reg = <0x70>; + interrupt-parent = <&irqc0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&pci0 { + status = "okay"; + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; +}; + +&usbphy { + status = "okay"; +}; Index: sys/gnu/dts/arm/r8a7790.dtsi =================================================================== --- sys/gnu/dts/arm/r8a7790.dtsi +++ sys/gnu/dts/arm/r8a7790.dtsi @@ -17,7 +17,6 @@ / { compatible = "renesas,r8a7790"; - interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; @@ -41,6 +40,35 @@ vin3 = &vin3; }; + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -159,1510 +187,1602 @@ }; }; - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&thermal>; - - trips { - cpu-crit { - temperature = <95000>; - hysteresis = <0>; - type = "critical"; - }; - }; - cooling-maps { - }; - }; + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; }; - apmu@e6151000 { - compatible = "renesas,r8a7790-apmu", "renesas,apmu"; - reg = <0 0xe6151000 0 0x188>; - cpus = <&cpu4 &cpu5 &cpu6 &cpu7>; + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; }; - apmu@e6152000 { - compatible = "renesas,r8a7790-apmu", "renesas,apmu"; - reg = <0 0xe6152000 0 0x188>; - cpus = <&cpu0 &cpu1 &cpu2 &cpu3>; + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; }; - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7790", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 30>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7790", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 30>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 30>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7790", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 30>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7790", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7790", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7790", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; - thermal: thermal@e61f0000 { - compatible = "renesas,thermal-r8a7790", - "renesas,rcar-gen2-thermal", - "renesas,rcar-thermal"; - reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; - interrupts = ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a7790"; + reg = <0 0xe6060000 0 0x250>; + }; - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7790-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; - cmt0: timer@ffca0000 { - compatible = "renesas,r8a7790-cmt0", "renesas,rcar-gen2-cmt0"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 124>; - - status = "disabled"; - }; + apmu@e6151000 { + compatible = "renesas,r8a7790-apmu", "renesas,apmu"; + reg = <0 0xe6151000 0 0x188>; + cpus = <&cpu4 &cpu5 &cpu6 &cpu7>; + }; - cmt1: timer@e6130000 { - compatible = "renesas,r8a7790-cmt1", "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 329>; - - status = "disabled"; - }; + apmu@e6152000 { + compatible = "renesas,r8a7790-apmu", "renesas,apmu"; + reg = <0 0xe6152000 0 0x188>; + cpus = <&cpu0 &cpu1 &cpu2 &cpu3>; + }; - irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7790", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7790-rst"; + reg = <0 0xe6160000 0 0x0100>; + }; - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; - }; + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7790-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; - }; + irqc0: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7790", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + ; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <13>; - }; + thermal: thermal@e61f0000 { + compatible = "renesas,thermal-r8a7790", + "renesas,rcar-gen2-thermal", + "renesas,rcar-thermal"; + reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; + interrupts = ; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <0>; + }; - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <13>; - }; + ipmmu_sy0: mmu@e6280000 { + compatible = "renesas,ipmmu-r8a7790", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6280000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; + ipmmu_sy1: mmu@e6290000 { + compatible = "renesas,ipmmu-r8a7790", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6290000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; + ipmmu_ds: mmu@e6740000 { + compatible = "renesas,ipmmu-r8a7790", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6740000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; - i2c0: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 931>; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; + ipmmu_mp: mmu@ec680000 { + compatible = "renesas,ipmmu-r8a7790", + "renesas,ipmmu-vmsa"; + reg = <0 0xec680000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; - i2c1: i2c@e6518000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 930>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + ipmmu_mx: mmu@fe951000 { + compatible = "renesas,ipmmu-r8a7790", + "renesas,ipmmu-vmsa"; + reg = <0 0xfe951000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; - i2c2: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 929>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-r8a7790", + "renesas,ipmmu-vmsa"; + reg = <0 0xffc80000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; - i2c3: i2c@e6540000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + }; - iic0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 318>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>, - <&dmac1 0x61>, <&dmac1 0x62>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; - iic1: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 323>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>, - <&dmac1 0x65>, <&dmac1 0x66>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 323>; - status = "disabled"; - }; + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x10>; + }; + }; - iic2: i2c@e6520000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6520000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 300>; - dmas = <&dmac0 0x69>, <&dmac0 0x6a>, - <&dmac1 0x69>, <&dmac1 0x6a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; + i2c0: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7790", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 931>; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; - iic3: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - dmas = <&dmac0 0x77>, <&dmac0 0x78>, - <&dmac1 0x77>, <&dmac1 0x78>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 926>; - status = "disabled"; - }; + i2c1: i2c@e6518000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7790", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 930>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = ; - clocks = <&cpg CPG_MOD 315>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 315>; - reg-io-width = <4>; - status = "disabled"; - max-frequency = <97500000>; - }; + i2c2: i2c@e6530000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7790", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 929>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - mmcif1: mmc@ee220000 { - compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; - reg = <0 0xee220000 0 0x80>; - interrupts = ; - clocks = <&cpg CPG_MOD 305>; - dmas = <&dmac0 0xe1>, <&dmac0 0xe2>, - <&dmac1 0xe1>, <&dmac1 0xe2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 305>; - reg-io-width = <4>; - status = "disabled"; - max-frequency = <97500000>; - }; + i2c3: i2c@e6540000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7790", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 928>; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a7790"; - reg = <0 0xe6060000 0 0x250>; - }; + iic0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7790", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 318>; + dmas = <&dmac0 0x61>, <&dmac0 0x62>, + <&dmac1 0x61>, <&dmac1 0x62>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; + }; - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7790", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; + iic1: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7790", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 323>; + dmas = <&dmac0 0x65>, <&dmac0 0x66>, + <&dmac1 0x65>, <&dmac1 0x66>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 323>; + status = "disabled"; + }; - sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-r8a7790", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee120000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - dmas = <&dmac0 0xc9>, <&dmac0 0xca>, - <&dmac1 0xc9>, <&dmac1 0xca>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 313>; - status = "disabled"; - }; + iic2: i2c@e6520000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7790", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6520000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 300>; + dmas = <&dmac0 0x69>, <&dmac0 0x6a>, + <&dmac1 0x69>, <&dmac1 0x6a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 300>; + status = "disabled"; + }; - sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-r8a7790", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; + iic3: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7790", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 926>; + dmas = <&dmac0 0x77>, <&dmac0 0x78>, + <&dmac1 0x77>, <&dmac1 0x78>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 926>; + status = "disabled"; + }; - sdhi3: sd@ee160000 { - compatible = "renesas,sdhi-r8a7790", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee160000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7790", + "renesas,rcar-gen2-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 704>; + renesas,buswait = <4>; + phys = <&usb0 1>; + phy-names = "usb"; + status = "disabled"; + }; - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7790", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, - <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; + usbphy: usb-phy@e6590100 { + compatible = "renesas,usb-phy-r8a7790", + "renesas,rcar-gen2-usb-phy"; + reg = <0 0xe6590100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cpg CPG_MOD 704>; + clock-names = "usbhs"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7790", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>; - clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>, - <&dmac1 0x25>, <&dmac1 0x26>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; + usb0: usb-channel@0 { + reg = <0>; + #phy-cells = <1>; + }; + usb2: usb-channel@2 { + reg = <2>; + #phy-cells = <1>; + }; + }; - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7790", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>; - clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>, - <&dmac1 0x27>, <&dmac1 0x28>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a7790-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7790", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>; - clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, - <&dmac1 0x3d>, <&dmac1 0x3e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a7790-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7790", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>; - clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>, - <&dmac1 0x19>, <&dmac1 0x1a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7790", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <15>; + }; - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7790", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 216>; - clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, - <&dmac1 0x1d>, <&dmac1 0x1e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 216>; - status = "disabled"; - }; + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a7790", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <15>; + }; - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7790_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 721>; - status = "disabled"; - }; + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7790", + "renesas,etheravb-rcar-gen2"; + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupts = ; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 812>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7790_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 720>; - status = "disabled"; - }; + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7790", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 917>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - scif2: serial@e6e56000 { - compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e56000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, <&cpg CPG_CORE R8A7790_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7790", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c40000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7790", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7790_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7790", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c50000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7790", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7790_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7790", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - }; + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7790", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7790", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c30000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>; + clock-names = "fck"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x10>; + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7790", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6ce0000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 216>; + status = "disabled"; }; - }; - ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7790", - "renesas,rcar-gen2-ether"; - reg = <0 0xee700000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 813>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 813>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7790", + "renesas,rcar-gen2-scif", + "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 721>, + <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 721>; + status = "disabled"; + }; - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7790", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = ; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 812>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7790", + "renesas,rcar-gen2-scif", + "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 720>, + <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 720>; + status = "disabled"; + }; - sata0: sata@ee300000 { - compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata"; - reg = <0 0xee300000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 815>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 815>; - status = "disabled"; - }; + scif2: serial@e6e56000 { + compatible = "renesas,scif-r8a7790", + "renesas,rcar-gen2-scif", + "renesas,scif"; + reg = <0 0xe6e56000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 310>; + status = "disabled"; + }; - sata1: sata@ee500000 { - compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata"; - reg = <0 0xee500000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 814>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 814>; - status = "disabled"; - }; + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7790", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 717>, + <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; + }; - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7790", "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 704>; - renesas,buswait = <4>; - phys = <&usb0 1>; - phy-names = "usb"; - status = "disabled"; - }; + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7790", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>, + <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + }; - usbphy: usb-phy@e6590100 { - compatible = "renesas,usb-phy-r8a7790", - "renesas,rcar-gen2-usb-phy"; - reg = <0 0xe6590100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cpg CPG_MOD 704>; - clock-names = "usbhs"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 704>; - status = "disabled"; + msiof0: spi@e6e20000 { + compatible = "renesas,msiof-r8a7790", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e20000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 0>; + dmas = <&dmac0 0x51>, <&dmac0 0x52>, + <&dmac1 0x51>, <&dmac1 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - usb0: usb-channel@0 { - reg = <0>; - #phy-cells = <1>; + msiof1: spi@e6e10000 { + compatible = "renesas,msiof-r8a7790", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x55>, <&dmac0 0x56>, + <&dmac1 0x55>, <&dmac1 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; - usb2: usb-channel@2 { - reg = <2>; - #phy-cells = <1>; + + msiof2: spi@e6e00000 { + compatible = "renesas,msiof-r8a7790", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 205>; + dmas = <&dmac0 0x41>, <&dmac0 0x42>, + <&dmac1 0x41>, <&dmac1 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 205>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; - }; - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 811>; - status = "disabled"; - }; + msiof3: spi@e6c90000 { + compatible = "renesas,msiof-r8a7790", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6c90000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 215>; + dmas = <&dmac0 0x45>, <&dmac0 0x46>, + <&dmac1 0x45>, <&dmac1 0x46>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 215>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 810>; - status = "disabled"; - }; + can0: can@e6e80000 { + compatible = "renesas,can-r8a7790", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7790_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 809>; - status = "disabled"; - }; + can1: can@e6e88000 { + compatible = "renesas,can-r8a7790", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A7790_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 808>; - status = "disabled"; - }; + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7790", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 811>; + status = "disabled"; + }; - vsp@fe920000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe920000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 130>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 130>; - }; + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7790", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 810>; + status = "disabled"; + }; - vsp@fe928000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe928000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 131>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 131>; - }; + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7790", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 809>; + status = "disabled"; + }; - vsp@fe930000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe930000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 128>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 128>; - }; + vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a7790", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 808>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 808>; + status = "disabled"; + }; - vsp@fe938000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe938000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 127>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 127>; - }; + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a7790", + "renesas,rcar_sound-gen2"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, + <&cpg CPG_CORE R8A7790_CLK_M2>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0", + "src.9", "src.8", "src.7", "src.6", + "src.5", "src.4", "src.3", "src.2", + "src.1", "src.0", + "ctu.0", "ctu.1", + "mix.0", "mix.1", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, + <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, + <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0"; + + status = "disabled"; + + rcar_sound,dvc { + dvc0: dvc-0 { + dmas = <&audma1 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma1 0xbe>; + dma-names = "tx"; + }; + }; - du: display@feb00000 { - compatible = "renesas,du-r8a7790"; - reg = <0 0xfeb00000 0 0x70000>, - <0 0xfeb90000 0 0x1c>, - <0 0xfeb94000 0 0x1c>; - reg-names = "du", "lvds.0", "lvds.1"; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, <&cpg CPG_MOD 726>, - <&cpg CPG_MOD 725>; - clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; + rcar_sound,mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; }; - port@1 { - reg = <1>; - du_out_lvds0: endpoint { + + rcar_sound,src { + src0: src-0 { + interrupts = ; + dmas = <&audma0 0x85>, <&audma1 0x9a>; + dma-names = "rx", "tx"; + }; + src1: src-1 { + interrupts = ; + dmas = <&audma0 0x87>, <&audma1 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = ; + dmas = <&audma0 0x89>, <&audma1 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = ; + dmas = <&audma0 0x8b>, <&audma1 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = ; + dmas = <&audma0 0x8d>, <&audma1 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = ; + dmas = <&audma0 0x8f>, <&audma1 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = ; + dmas = <&audma0 0x91>, <&audma1 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src-7 { + interrupts = ; + dmas = <&audma0 0x93>, <&audma1 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src-8 { + interrupts = ; + dmas = <&audma0 0x95>, <&audma1 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src-9 { + interrupts = ; + dmas = <&audma0 0x97>, <&audma1 0xba>; + dma-names = "rx", "tx"; }; }; - port@2 { - reg = <2>; - du_out_lvds1: endpoint { + + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = ; + dmas = <&audma0 0x01>, <&audma1 0x02>, + <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi-1 { + interrupts = ; + dmas = <&audma0 0x03>, <&audma1 0x04>, + <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi-2 { + interrupts = ; + dmas = <&audma0 0x05>, <&audma1 0x06>, + <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi-3 { + interrupts = ; + dmas = <&audma0 0x07>, <&audma1 0x08>, + <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi-4 { + interrupts = ; + dmas = <&audma0 0x09>, <&audma1 0x0a>, + <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi-5 { + interrupts = ; + dmas = <&audma0 0x0b>, <&audma1 0x0c>, + <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi-6 { + interrupts = ; + dmas = <&audma0 0x0d>, <&audma1 0x0e>, + <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi-7 { + interrupts = ; + dmas = <&audma0 0x0f>, <&audma1 0x10>, + <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi-8 { + interrupts = ; + dmas = <&audma0 0x11>, <&audma1 0x12>, + <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi-9 { + interrupts = ; + dmas = <&audma0 0x13>, <&audma1 0x14>, + <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; }; }; }; - }; - can0: can@e6e80000 { - compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7790_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6e88000 { - compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7790_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7790", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <13>; + }; - jpu: jpeg-codec@fe980000 { - compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu"; - reg = <0 0xfe980000 0 0x10300>; - interrupts = ; - clocks = <&cpg CPG_MOD 106>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 106>; - }; + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a7790", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 501>; + #dma-cells = <1>; + dma-channels = <13>; + }; - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + xhci: usb@ee000000 { + compatible = "renesas,xhci-r8a7790", + "renesas,rcar-gen2-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 328>; + phys = <&usb2 1>; + phy-names = "usb"; + status = "disabled"; + }; - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; + pci0: pci@ee090000 { + compatible = "renesas,pci-r8a7790", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee090000 0 0xc00>, + <0 0xee080000 0 0x1100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + }; - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + pci1: pci@ee0b0000 { + compatible = "renesas,pci-r8a7790", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee0b0000 0 0xc00>, + <0 0xee0a0000 0 0x1100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <1 1>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + }; - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; + pci2: pci@ee0d0000 { + compatible = "renesas,pci-r8a7790", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 703>; + reg = <0 0xee0d0000 0 0xc00>, + <0 0xee0c0000 0 0x1100>; + interrupts = ; + status = "disabled"; + + bus-range = <2 2>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x20800 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + usb@2,0 { + reg = <0x21000 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + }; - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7790-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7790", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee100000 0 0x328>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; + sdhi1: sd@ee120000 { + compatible = "renesas,sdhi-r8a7790", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee120000 0 0x328>; + interrupts = ; + clocks = <&cpg CPG_MOD 313>; + dmas = <&dmac0 0xc9>, <&dmac0 0xca>, + <&dmac1 0xc9>, <&dmac1 0xca>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 313>; + status = "disabled"; + }; - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7790-rst"; - reg = <0 0xe6160000 0 0x0100>; - }; + sdhi2: sd@ee140000 { + compatible = "renesas,sdhi-r8a7790", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee140000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, + <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7790-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; + sdhi3: sd@ee160000 { + compatible = "renesas,sdhi-r8a7790", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee160000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7790", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 917>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + mmcif0: mmc@ee200000 { + compatible = "renesas,mmcif-r8a7790", + "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = ; + clocks = <&cpg CPG_MOD 315>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, + <&dmac1 0xd1>, <&dmac1 0xd2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 315>; + reg-io-width = <4>; + status = "disabled"; + max-frequency = <97500000>; + }; - msiof0: spi@e6e20000 { - compatible = "renesas,msiof-r8a7790", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e20000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 0>; - dmas = <&dmac0 0x51>, <&dmac0 0x52>, - <&dmac1 0x51>, <&dmac1 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + mmcif1: mmc@ee220000 { + compatible = "renesas,mmcif-r8a7790", + "renesas,sh-mmcif"; + reg = <0 0xee220000 0 0x80>; + interrupts = ; + clocks = <&cpg CPG_MOD 305>; + dmas = <&dmac0 0xe1>, <&dmac0 0xe2>, + <&dmac1 0xe1>, <&dmac1 0xe2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 305>; + reg-io-width = <4>; + status = "disabled"; + max-frequency = <97500000>; + }; - msiof1: spi@e6e10000 { - compatible = "renesas,msiof-r8a7790", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x55>, <&dmac0 0x56>, - <&dmac1 0x55>, <&dmac1 0x56>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + sata0: sata@ee300000 { + compatible = "renesas,sata-r8a7790", + "renesas,rcar-gen2-sata"; + reg = <0 0xee300000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 815>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 815>; + status = "disabled"; + }; - msiof2: spi@e6e00000 { - compatible = "renesas,msiof-r8a7790", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 205>; - dmas = <&dmac0 0x41>, <&dmac0 0x42>, - <&dmac1 0x41>, <&dmac1 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 205>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + sata1: sata@ee500000 { + compatible = "renesas,sata-r8a7790", + "renesas,rcar-gen2-sata"; + reg = <0 0xee500000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 814>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 814>; + status = "disabled"; + }; - msiof3: spi@e6c90000 { - compatible = "renesas,msiof-r8a7790", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6c90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 215>; - dmas = <&dmac0 0x45>, <&dmac0 0x46>, - <&dmac1 0x45>, <&dmac1 0x46>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 215>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7790", + "renesas,rcar-gen2-ether"; + reg = <0 0xee700000 0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 813>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - xhci: usb@ee000000 { - compatible = "renesas,xhci-r8a7790", "renesas,rcar-gen2-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 328>; - phys = <&usb2 1>; - phy-names = "usb"; - status = "disabled"; - }; + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; - pci0: pci@ee090000 { - compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee090000 0 0xc00>, - <0 0xee080000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; - interrupt-map-mask = <0xff00 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x800 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; + pciec: pcie@fe000000 { + compatible = "renesas,pcie-r8a7790", + "renesas,pcie-rcar-gen2"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 + 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 + 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 + 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000 + 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; }; - usb@2,0 { - reg = <0x1000 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; + vsp@fe920000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe920000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 130>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 130>; }; - }; - pci1: pci@ee0b0000 { - compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee0b0000 0 0xc00>, - <0 0xee0a0000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <1 1>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>; - interrupt-map-mask = <0xff00 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; - }; + vsp@fe928000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe928000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 131>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 131>; + }; - pci2: pci@ee0d0000 { - compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2"; - device_type = "pci"; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 703>; - reg = <0 0xee0d0000 0 0xc00>, - <0 0xee0c0000 0 0x1100>; - interrupts = ; - status = "disabled"; - - bus-range = <2 2>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; - interrupt-map-mask = <0xff00 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x20800 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; + vsp@fe930000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe930000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 128>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 128>; }; - usb@2,0 { - reg = <0x21000 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; + vsp@fe938000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe938000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 127>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 127>; }; - }; - pciec: pcie@fe000000 { - compatible = "renesas,pcie-r8a7790", "renesas,pcie-rcar-gen2"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 - 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 - 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 - 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000 - 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; + jpu: jpeg-codec@fe980000 { + compatible = "renesas,jpu-r8a7790", + "renesas,rcar-gen2-jpu"; + reg = <0 0xfe980000 0 0x10300>; + interrupts = ; + clocks = <&cpg CPG_MOD 106>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 106>; + }; - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A7790_CLK_M2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", - "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", "src.5", - "src.4", "src.3", "src.2", "src.1", "src.0", - "ctu.0", "ctu.1", - "mix.0", "mix.1", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", - "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0"; - - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; + du: display@feb00000 { + compatible = "renesas,du-r8a7790"; + reg = <0 0xfeb00000 0 0x70000>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>; + clock-names = "du.0", "du.1", "du.2"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; + port@2 { + reg = <2>; + du_out_lvds1: endpoint { + remote-endpoint = <&lvds1_in>; + }; + }; }; }; - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; + lvds0: lvds@feb90000 { + compatible = "renesas,r8a7790-lvds"; + reg = <0 0xfeb90000 0 0x1c>; + clocks = <&cpg CPG_MOD 726>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 726>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&du_out_lvds0>; + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { + }; + }; + }; }; - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; + lvds1: lvds@feb94000 { + compatible = "renesas,r8a7790-lvds"; + reg = <0 0xfeb94000 0 0x1c>; + clocks = <&cpg CPG_MOD 725>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 725>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds1_in: endpoint { + remote-endpoint = <&du_out_lvds1>; + }; + }; + port@1 { + reg = <1>; + lvds1_out: endpoint { + }; + }; + }; }; - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; }; - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; + cmt0: timer@ffca0000 { + compatible = "renesas,r8a7790-cmt0", + "renesas,rcar-gen2-cmt0"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 124>; + + status = "disabled"; }; - }; - ipmmu_sy0: mmu@e6280000 { - compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; - reg = <0 0xe6280000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; + cmt1: timer@e6130000 { + compatible = "renesas,r8a7790-cmt1", + "renesas,rcar-gen2-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 329>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 329>; + + status = "disabled"; + }; }; - ipmmu_sy1: mmu@e6290000 { - compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; - reg = <0 0xe6290000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; - ipmmu_ds: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; - reg = <0 0xe6740000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; + thermal-sensors = <&thermal>; - ipmmu_mp: mmu@ec680000 { - compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; - reg = <0 0xec680000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; + trips { + cpu-crit { + temperature = <95000>; + hysteresis = <0>; + type = "critical"; + }; + }; + cooling-maps { + }; + }; }; - ipmmu_mx: mmu@fe951000 { - compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; + timer { + compatible = "arm,armv7-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; - ipmmu_rt: mmu@ffc80000 { - compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; - reg = <0 0xffc80000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; }; }; Index: sys/gnu/dts/arm/r8a7791-koelsch.dts =================================================================== --- sys/gnu/dts/arm/r8a7791-koelsch.dts +++ sys/gnu/dts/arm/r8a7791-koelsch.dts @@ -51,7 +51,11 @@ serial0 = &scif0; serial1 = &scif1; i2c9 = &gpioi2c1; + i2c10 = &gpioi2c2; + i2c11 = &gpioi2c4; i2c12 = &i2cexio1; + i2c13 = &i2chdmi; + i2c14 = &i2cexio4; }; chosen { @@ -312,8 +316,28 @@ #size-cells = <0>; compatible = "i2c-gpio"; status = "disabled"; - sda-gpios = <&gpio7 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; scl-gpios = <&gpio7 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio7 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <5>; + }; + + gpioi2c2: i2c-10 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <5>; + }; + + gpioi2c4: i2c-11 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + scl-gpios = <&gpio7 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio7 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <5>; }; @@ -328,6 +352,115 @@ #address-cells = <1>; #size-cells = <0>; }; + + /* + * A fallback to GPIO is provided for I2C2. + */ + i2chdmi: i2c-13 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&i2c2>, <&gpioi2c2>; + i2c-bus-name = "i2c-hdmi"; + #address-cells = <1>; + #size-cells = <0>; + + ak4643: codec@12 { + compatible = "asahi-kasei,ak4643"; + #sound-dai-cells = <0>; + reg = <0x12>; + }; + + composite-in@20 { + compatible = "adi,adv7180"; + reg = <0x20>; + remote = <&vin1>; + + port { + adv7180: endpoint { + bus-width = <8>; + remote-endpoint = <&vin1ep>; + }; + }; + }; + + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&gpio3>; + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; + clocks = <&cec_clock>; + clock-names = "cec"; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&du_out_rgb>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; + + hdmi-in@4c { + compatible = "adi,adv7612"; + reg = <0x4c>; + interrupt-parent = <&gpio4>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + default-input = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7612_in: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; + }; + + port@2 { + reg = <2>; + adv7612_out: endpoint { + remote-endpoint = <&vin0ep2>; + }; + }; + }; + }; + + eeprom@50 { + compatible = "renesas,r1ex24002", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + }; + + /* + * I2C4 is routed to EXIO connector E, pins 37 (SCL) + 39 (SDA). + * A fallback to GPIO is provided. + */ + i2cexio4: i2c-14 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&i2c4>, <&gpioi2c4>; + i2c-bus-name = "i2c-exio4"; + #address-cells = <1>; + #size-cells = <0>; + }; }; &du { @@ -335,10 +468,9 @@ pinctrl-names = "default"; status = "okay"; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>, + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x13_clk>, <&x2_clk>; - clock-names = "du.0", "du.1", "lvds.0", - "dclkin.0", "dclkin.1"; + clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; ports { port@0 { @@ -346,6 +478,13 @@ remote-endpoint = <&adv7511_in>; }; }; + }; +}; + +&lvds0 { + status = "okay"; + + ports { port@1 { lvds_connector: endpoint { }; @@ -371,6 +510,11 @@ function = "i2c2"; }; + i2c4_pins: i2c4 { + groups = "i2c4_c"; + function = "i2c4"; + }; + du_pins: du { groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; function = "du"; @@ -621,96 +765,14 @@ &i2c2 { pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "default"; + pinctrl-names = "i2c-hdmi"; - status = "okay"; clock-frequency = <100000>; +}; - ak4643: codec@12 { - compatible = "asahi-kasei,ak4643"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - composite-in@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - remote = <&vin1>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin1ep>; - }; - }; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio3>; - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - clocks = <&cec_clock>; - clock-names = "cec"; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con_out>; - }; - }; - }; - }; - - hdmi-in@4c { - compatible = "adi,adv7612"; - reg = <0x4c>; - interrupt-parent = <&gpio4>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - default-input = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7612_in: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; - }; - - port@2 { - reg = <2>; - adv7612_out: endpoint { - remote-endpoint = <&vin0ep2>; - }; - }; - }; - }; - - eeprom@50 { - compatible = "renesas,r1ex24002", "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; +&i2c4 { + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "i2c-exio4"; }; &i2c6 { Index: sys/gnu/dts/arm/r8a7791-porter.dts =================================================================== --- sys/gnu/dts/arm/r8a7791-porter.dts +++ sys/gnu/dts/arm/r8a7791-porter.dts @@ -29,6 +29,8 @@ aliases { serial0 = &scif0; + i2c9 = &gpioi2c2; + i2c10 = &i2chdmi; }; chosen { @@ -135,6 +137,78 @@ clocks = <&x14_clk>; }; }; + + gpioi2c2: i2c-9 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <5>; + }; + + /* + * A fallback to GPIO is provided for I2C2. + */ + i2chdmi: i2c-10 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&i2c2>, <&gpioi2c2>; + i2c-bus-name = "i2c-hdmi"; + #address-cells = <1>; + #size-cells = <0>; + + ak4642: codec@12 { + compatible = "asahi-kasei,ak4642"; + #sound-dai-cells = <0>; + reg = <0x12>; + }; + + composite-in@20 { + compatible = "adi,adv7180"; + reg = <0x20>; + remote = <&vin0>; + + port { + adv7180: endpoint { + bus-width = <8>; + remote-endpoint = <&vin0ep>; + }; + }; + }; + + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&gpio3>; + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&du_out_rgb>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + }; }; &extal_clk { @@ -296,61 +370,9 @@ &i2c2 { pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "default"; + pinctrl-names = "i2c-hdmi"; - status = "okay"; clock-frequency = <400000>; - - ak4642: codec@12 { - compatible = "asahi-kasei,ak4642"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - composite-in@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - remote = <&vin0>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin0ep>; - }; - }; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio3>; - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; }; &sata0 { @@ -419,13 +441,12 @@ pinctrl-names = "default"; status = "okay"; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>, + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x3_clk>, <&x16_clk>; - clock-names = "du.0", "du.1", "lvds.0", - "dclkin.0", "dclkin.1"; + clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; ports { - port@1 { + port@0 { endpoint { remote-endpoint = <&adv7511_in>; }; @@ -433,6 +454,17 @@ }; }; +&lvds0 { + status = "okay"; + + ports { + port@1 { + lvds_connector: endpoint { + }; + }; + }; +}; + &rcar_sound { pinctrl-0 = <&ssi_pins &audio_clk_pins>; pinctrl-names = "default"; Index: sys/gnu/dts/arm/r8a7791.dtsi =================================================================== --- sys/gnu/dts/arm/r8a7791.dtsi +++ sys/gnu/dts/arm/r8a7791.dtsi @@ -17,7 +17,6 @@ / { compatible = "renesas,r8a7791"; - interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; @@ -40,6 +39,35 @@ vin2 = &vin2; }; + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -83,1585 +111,1651 @@ }; }; - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&thermal>; - - trips { - cpu-crit { - temperature = <95000>; - hysteresis = <0>; - type = "critical"; - }; - }; - cooling-maps { - }; - }; - }; - - apmu@e6152000 { - compatible = "renesas,r8a7791-apmu", "renesas,apmu"; - reg = <0 0xe6152000 0 0x188>; - cpus = <&cpu0 &cpu1>; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 910>; + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; }; - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 909>; + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; }; - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 908>; + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; }; - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7791", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 904>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 904>; - }; + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7791", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; - thermal: thermal@e61f0000 { - compatible = "renesas,thermal-r8a7791", - "renesas,rcar-gen2-thermal", - "renesas,rcar-thermal"; - reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; - interrupts = ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7791", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7791", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; - cmt0: timer@ffca0000 { - compatible = "renesas,r8a7791-cmt0", "renesas,rcar-gen2-cmt0"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 124>; - - status = "disabled"; - }; + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7791", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; - cmt1: timer@e6130000 { - compatible = "renesas,r8a7791-cmt1", "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 329>; - - status = "disabled"; - }; + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7791", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; - irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7791", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a7791", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055400 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 905>; + }; - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; - }; + gpio7: gpio@e6055800 { + compatible = "renesas,gpio-r8a7791", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055800 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 904>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 904>; + }; - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; - }; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a7791"; + reg = <0 0xe6060000 0 0x250>; + }; - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <13>; - }; + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7791-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <13>; - }; + apmu@e6152000 { + compatible = "renesas,r8a7791-apmu", "renesas,apmu"; + reg = <0 0xe6152000 0 0x188>; + cpus = <&cpu0 &cpu1>; + }; - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7791-rst"; + reg = <0 0xe6160000 0 0x0100>; + }; - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7791-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; - /* The memory map in the User's Manual maps the cores to bus numbers */ - i2c0: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 931>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + irqc0: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7791", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; - i2c1: i2c@e6518000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 930>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + thermal: thermal@e61f0000 { + compatible = "renesas,thermal-r8a7791", + "renesas,rcar-gen2-thermal", + "renesas,rcar-thermal"; + reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; + interrupts = ; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <0>; + }; - i2c2: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 929>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + ipmmu_sy0: mmu@e6280000 { + compatible = "renesas,ipmmu-r8a7791", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6280000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; - i2c3: i2c@e6540000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + ipmmu_sy1: mmu@e6290000 { + compatible = "renesas,ipmmu-r8a7791", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6290000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; - i2c4: i2c@e6520000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6520000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 927>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + ipmmu_ds: mmu@e6740000 { + compatible = "renesas,ipmmu-r8a7791", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6740000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; - i2c5: i2c@e6528000 { - /* doesn't need pinmux */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6528000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 925>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 925>; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; + ipmmu_mp: mmu@ec680000 { + compatible = "renesas,ipmmu-r8a7791", + "renesas,ipmmu-vmsa"; + reg = <0 0xec680000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; - i2c6: i2c@e60b0000 { - /* doesn't need pinmux */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7791", "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - dmas = <&dmac0 0x77>, <&dmac0 0x78>, - <&dmac1 0x77>, <&dmac1 0x78>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 926>; - status = "disabled"; - }; + ipmmu_mx: mmu@fe951000 { + compatible = "renesas,ipmmu-r8a7791", + "renesas,ipmmu-vmsa"; + reg = <0 0xfe951000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; - i2c7: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7791", "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 318>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>, - <&dmac1 0x61>, <&dmac1 0x62>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-r8a7791", + "renesas,ipmmu-vmsa"; + reg = <0 0xffc80000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; - i2c8: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7791", "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 323>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>, - <&dmac1 0x65>, <&dmac1 0x66>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 323>; - status = "disabled"; - }; + ipmmu_gp: mmu@e62a0000 { + compatible = "renesas,ipmmu-r8a7791", + "renesas,ipmmu-vmsa"; + reg = <0 0xe62a0000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a7791"; - reg = <0 0xe6060000 0 0x250>; - }; + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + }; - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = ; - clocks = <&cpg CPG_MOD 315>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 315>; - reg-io-width = <4>; - status = "disabled"; - max-frequency = <97500000>; - }; + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7791", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x10>; + }; + }; - sdhi1: sd@ee140000 { - compatible = "renesas,sdhi-r8a7791", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; + /* The memory map in the User's Manual maps the cores to + * bus numbers + */ + i2c0: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7791", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 931>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - sdhi2: sd@ee160000 { - compatible = "renesas,sdhi-r8a7791", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee160000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; + i2c1: i2c@e6518000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7791", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 930>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, - <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; + i2c2: i2c@e6530000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7791", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 929>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>; - clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>, - <&dmac1 0x25>, <&dmac1 0x26>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; + i2c3: i2c@e6540000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7791", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 928>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>; - clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>, - <&dmac1 0x27>, <&dmac1 0x28>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; + i2c4: i2c@e6520000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7791", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6520000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 927>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - scifa3: serial@e6c70000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c70000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1106>; - clock-names = "fck"; - dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, - <&dmac1 0x1b>, <&dmac1 0x1c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 1106>; - status = "disabled"; - }; + i2c5: i2c@e6528000 { + /* doesn't need pinmux */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7791", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6528000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 925>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 925>; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; - scifa4: serial@e6c78000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c78000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1107>; - clock-names = "fck"; - dmas = <&dmac0 0x1f>, <&dmac0 0x20>, - <&dmac1 0x1f>, <&dmac1 0x20>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 1107>; - status = "disabled"; - }; + i2c6: i2c@e60b0000 { + /* doesn't need pinmux */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7791", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 926>; + dmas = <&dmac0 0x77>, <&dmac0 0x78>, + <&dmac1 0x77>, <&dmac1 0x78>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 926>; + status = "disabled"; + }; - scifa5: serial@e6c80000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c80000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1108>; - clock-names = "fck"; - dmas = <&dmac0 0x23>, <&dmac0 0x24>, - <&dmac1 0x23>, <&dmac1 0x24>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 1108>; - status = "disabled"; - }; + i2c7: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7791", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 318>; + dmas = <&dmac0 0x61>, <&dmac0 0x62>, + <&dmac1 0x61>, <&dmac1 0x62>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; + }; - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7791", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>; - clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, - <&dmac1 0x3d>, <&dmac1 0x3e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; + i2c8: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7791", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 323>; + dmas = <&dmac0 0x65>, <&dmac0 0x66>, + <&dmac1 0x65>, <&dmac1 0x66>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 323>; + status = "disabled"; + }; - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7791", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>; - clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>, - <&dmac1 0x19>, <&dmac1 0x1a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7791", + "renesas,rcar-gen2-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 704>; + renesas,buswait = <4>; + phys = <&usb0 1>; + phy-names = "usb"; + status = "disabled"; + }; - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7791", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 216>; - clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, - <&dmac1 0x1d>, <&dmac1 0x1e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 216>; - status = "disabled"; - }; + usbphy: usb-phy@e6590100 { + compatible = "renesas,usb-phy-r8a7791", + "renesas,rcar-gen2-usb-phy"; + reg = <0 0xe6590100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cpg CPG_MOD 704>; + clock-names = "usbhs"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 721>; - status = "disabled"; - }; + usb0: usb-channel@0 { + reg = <0>; + #phy-cells = <1>; + }; + usb2: usb-channel@2 { + reg = <2>; + #phy-cells = <1>; + }; + }; - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 720>; - status = "disabled"; - }; + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a7791-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; - adc: adc@e6e54000 { - compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc"; - reg = <0 0xe6e54000 0 64>; - clocks = <&cpg CPG_MOD 901>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 901>; - status = "disabled"; - }; + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a7791-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; - scif2: serial@e6e58000 { - compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e58000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 719>; - status = "disabled"; - }; + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7791", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <15>; + }; - scif3: serial@e6ea8000 { - compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6ea8000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>, - <&dmac1 0x2f>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 718>; - status = "disabled"; - }; + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a7791", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <15>; + }; - scif4: serial@e6ee0000 { - compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6ee0000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, - <&dmac1 0xfb>, <&dmac1 0xfc>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 715>; - status = "disabled"; - }; + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7791", + "renesas,etheravb-rcar-gen2"; + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupts = ; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 812>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - scif5: serial@e6ee8000 { - compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6ee8000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, - <&dmac1 0xfd>, <&dmac1 0xfe>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - }; + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7791", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 917>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7791", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7791", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c40000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7791", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7791", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c50000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; - hscif2: serial@e62d0000 { - compatible = "renesas,hscif-r8a7791", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62d0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, - <&dmac1 0x3b>, <&dmac1 0x3c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 713>; - status = "disabled"; - }; + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7791", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - }; + scifa3: serial@e6c70000 { + compatible = "renesas,scifa-r8a7791", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c70000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 1106>; + clock-names = "fck"; + dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, + <&dmac1 0x1b>, <&dmac1 0x1c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 1106>; + status = "disabled"; + }; - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; + scifa4: serial@e6c78000 { + compatible = "renesas,scifa-r8a7791", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c78000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 1107>; + clock-names = "fck"; + dmas = <&dmac0 0x1f>, <&dmac0 0x20>, + <&dmac1 0x1f>, <&dmac1 0x20>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 1107>; + status = "disabled"; + }; - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x10>; + scifa5: serial@e6c80000 { + compatible = "renesas,scifa-r8a7791", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c80000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 1108>; + clock-names = "fck"; + dmas = <&dmac0 0x23>, <&dmac0 0x24>, + <&dmac1 0x23>, <&dmac1 0x24>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 1108>; + status = "disabled"; }; - }; - ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7791", - "renesas,rcar-gen2-ether"; - reg = <0 0xee700000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 813>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 813>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7791", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7791", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = ; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 812>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7791", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c30000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>; + clock-names = "fck"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; - sata0: sata@ee300000 { - compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata"; - reg = <0 0xee300000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 815>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 815>; - status = "disabled"; - }; + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7791", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6ce0000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 216>; + status = "disabled"; + }; - sata1: sata@ee500000 { - compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata"; - reg = <0 0xee500000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 814>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 814>; - status = "disabled"; - }; + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7791", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 721>; + status = "disabled"; + }; - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7791", "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 704>; - renesas,buswait = <4>; - phys = <&usb0 1>; - phy-names = "usb"; - status = "disabled"; - }; + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7791", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7791_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 720>; + status = "disabled"; + }; - usbphy: usb-phy@e6590100 { - compatible = "renesas,usb-phy-r8a7791", - "renesas,rcar-gen2-usb-phy"; - reg = <0 0xe6590100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cpg CPG_MOD 704>; - clock-names = "usbhs"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 704>; - status = "disabled"; + scif2: serial@e6e58000 { + compatible = "renesas,scif-r8a7791", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e58000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7791_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 719>; + status = "disabled"; + }; - usb0: usb-channel@0 { - reg = <0>; - #phy-cells = <1>; + scif3: serial@e6ea8000 { + compatible = "renesas,scif-r8a7791", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ea8000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7791_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>, + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 718>; + status = "disabled"; }; - usb2: usb-channel@2 { - reg = <2>; - #phy-cells = <1>; + + scif4: serial@e6ee0000 { + compatible = "renesas,scif-r8a7791", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee0000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7791_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, + <&dmac1 0xfb>, <&dmac1 0xfc>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 715>; + status = "disabled"; }; - }; - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 811>; - status = "disabled"; - }; + scif5: serial@e6ee8000 { + compatible = "renesas,scif-r8a7791", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee8000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7791_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, + <&dmac1 0xfd>, <&dmac1 0xfe>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; + }; - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 810>; - status = "disabled"; - }; + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7791", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7791_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; + }; - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 809>; - status = "disabled"; - }; + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7791", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7791_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + }; - vsp@fe928000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe928000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 131>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 131>; - }; + hscif2: serial@e62d0000 { + compatible = "renesas,hscif-r8a7791", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62d0000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7791_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, + <&dmac1 0x3b>, <&dmac1 0x3c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 713>; + status = "disabled"; + }; - vsp@fe930000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe930000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 128>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 128>; - }; + msiof0: spi@e6e20000 { + compatible = "renesas,msiof-r8a7791", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e20000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 000>; + dmas = <&dmac0 0x51>, <&dmac0 0x52>, + <&dmac1 0x51>, <&dmac1 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - vsp@fe938000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe938000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 127>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 127>; - }; + msiof1: spi@e6e10000 { + compatible = "renesas,msiof-r8a7791", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x55>, <&dmac0 0x56>, + <&dmac1 0x55>, <&dmac1 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - du: display@feb00000 { - compatible = "renesas,du-r8a7791"; - reg = <0 0xfeb00000 0 0x40000>, - <0 0xfeb90000 0 0x1c>; - reg-names = "du", "lvds.0"; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 726>; - clock-names = "du.0", "du.1", "lvds.0"; - status = "disabled"; - - ports { + msiof2: spi@e6e00000 { + compatible = "renesas,msiof-r8a7791", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 205>; + dmas = <&dmac0 0x41>, <&dmac0 0x42>, + <&dmac1 0x41>, <&dmac1 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 205>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; + }; - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - }; - }; + adc: adc@e6e54000 { + compatible = "renesas,r8a7791-gyroadc", + "renesas,rcar-gyroadc"; + reg = <0 0xe6e54000 0 64>; + clocks = <&cpg CPG_MOD 901>; + clock-names = "fck"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 901>; + status = "disabled"; }; - }; - can0: can@e6e80000 { - compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7791_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; + can0: can@e6e80000 { + compatible = "renesas,can-r8a7791", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7791_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; - can1: can@e6e88000 { - compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7791_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; + can1: can@e6e88000 { + compatible = "renesas,can-r8a7791", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A7791_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; - jpu: jpeg-codec@fe980000 { - compatible = "renesas,jpu-r8a7791", "renesas,rcar-gen2-jpu"; - reg = <0 0xfe980000 0 0x10300>; - interrupts = ; - clocks = <&cpg CPG_MOD 106>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 106>; - }; + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7791", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 811>; + status = "disabled"; + }; - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7791", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 810>; + status = "disabled"; + }; - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7791", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 809>; + status = "disabled"; + }; - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a7791", + "renesas,rcar_sound-gen2"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, + <&cpg CPG_CORE R8A7791_CLK_M2>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0", "src.9", "src.8", + "src.7", "src.6", "src.5", "src.4", + "src.3", "src.2", "src.1", "src.0", + "ctu.0", "ctu.1", + "mix.0", "mix.1", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, + <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, + <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0"; + + status = "disabled"; + + rcar_sound,dvc { + dvc0: dvc-0 { + dmas = <&audma1 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma1 0xbe>; + dma-names = "tx"; + }; + }; - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + rcar_sound,mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; + }; - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + rcar_sound,src { + src0: src-0 { + interrupts = ; + dmas = <&audma0 0x85>, <&audma1 0x9a>; + dma-names = "rx", "tx"; + }; + src1: src-1 { + interrupts = ; + dmas = <&audma0 0x87>, <&audma1 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = ; + dmas = <&audma0 0x89>, <&audma1 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = ; + dmas = <&audma0 0x8b>, <&audma1 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = ; + dmas = <&audma0 0x8d>, <&audma1 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = ; + dmas = <&audma0 0x8f>, <&audma1 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = ; + dmas = <&audma0 0x91>, <&audma1 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src-7 { + interrupts = ; + dmas = <&audma0 0x93>, <&audma1 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src-8 { + interrupts = ; + dmas = <&audma0 0x95>, <&audma1 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src-9 { + interrupts = ; + dmas = <&audma0 0x97>, <&audma1 0xba>; + dma-names = "rx", "tx"; + }; + }; - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7791-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = ; + dmas = <&audma0 0x01>, <&audma1 0x02>, + <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi-1 { + interrupts = ; + dmas = <&audma0 0x03>, <&audma1 0x04>, + <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi-2 { + interrupts = ; + dmas = <&audma0 0x05>, <&audma1 0x06>, + <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi-3 { + interrupts = ; + dmas = <&audma0 0x07>, <&audma1 0x08>, + <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi-4 { + interrupts = ; + dmas = <&audma0 0x09>, <&audma1 0x0a>, + <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi-5 { + interrupts = ; + dmas = <&audma0 0x0b>, <&audma1 0x0c>, + <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi-6 { + interrupts = ; + dmas = <&audma0 0x0d>, <&audma1 0x0e>, + <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi-7 { + interrupts = ; + dmas = <&audma0 0x0f>, <&audma1 0x10>, + <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi-8 { + interrupts = ; + dmas = <&audma0 0x11>, <&audma1 0x12>, + <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi-9 { + interrupts = ; + dmas = <&audma0 0x13>, <&audma1 0x14>, + <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + }; + }; - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7791-rst"; - reg = <0 0xe6160000 0 0x0100>; - }; + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7791", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <13>; + }; - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a7791", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 501>; + #dma-cells = <1>; + dma-channels = <13>; + }; - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7791-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; + xhci: usb@ee000000 { + compatible = "renesas,xhci-r8a7791", + "renesas,rcar-gen2-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 328>; + phys = <&usb2 1>; + phy-names = "usb"; + status = "disabled"; + }; - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7791", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 917>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + pci0: pci@ee090000 { + compatible = "renesas,pci-r8a7791", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee090000 0 0xc00>, + <0 0xee080000 0 0x1100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; - msiof0: spi@e6e20000 { - compatible = "renesas,msiof-r8a7791", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e20000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 000>; - dmas = <&dmac0 0x51>, <&dmac0 0x52>, - <&dmac1 0x51>, <&dmac1 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + }; - msiof1: spi@e6e10000 { - compatible = "renesas,msiof-r8a7791", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x55>, <&dmac0 0x56>, - <&dmac1 0x55>, <&dmac1 0x56>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + pci1: pci@ee0d0000 { + compatible = "renesas,pci-r8a7791", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee0d0000 0 0xc00>, + <0 0xee0c0000 0 0x1100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <1 1>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x10800 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; - msiof2: spi@e6e00000 { - compatible = "renesas,msiof-r8a7791", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 205>; - dmas = <&dmac0 0x41>, <&dmac0 0x42>, - <&dmac1 0x41>, <&dmac1 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 205>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + usb@2,0 { + reg = <0x11000 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + }; - xhci: usb@ee000000 { - compatible = "renesas,xhci-r8a7791", "renesas,rcar-gen2-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 328>; - phys = <&usb2 1>; - phy-names = "usb"; - status = "disabled"; - }; + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7791", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee100000 0 0x328>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; - pci0: pci@ee090000 { - compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee090000 0 0xc00>, - <0 0xee080000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; - interrupt-map-mask = <0xff00 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x800 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; + sdhi1: sd@ee140000 { + compatible = "renesas,sdhi-r8a7791", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee140000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, + <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; }; - usb@2,0 { - reg = <0x1000 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; + sdhi2: sd@ee160000 { + compatible = "renesas,sdhi-r8a7791", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee160000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; }; - }; - pci1: pci@ee0d0000 { - compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee0d0000 0 0xc00>, - <0 0xee0c0000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <1 1>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; - interrupt-map-mask = <0xff00 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x10800 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; + mmcif0: mmc@ee200000 { + compatible = "renesas,mmcif-r8a7791", + "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = ; + clocks = <&cpg CPG_MOD 315>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, + <&dmac1 0xd1>, <&dmac1 0xd2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 315>; + reg-io-width = <4>; + status = "disabled"; + max-frequency = <97500000>; }; - usb@2,0 { - reg = <0x11000 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; + sata0: sata@ee300000 { + compatible = "renesas,sata-r8a7791", + "renesas,rcar-gen2-sata"; + reg = <0 0xee300000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 815>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 815>; + status = "disabled"; }; - }; - pciec: pcie@fe000000 { - compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 - 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 - 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 - 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000 - 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; + sata1: sata@ee500000 { + compatible = "renesas,sata-r8a7791", + "renesas,rcar-gen2-sata"; + reg = <0 0xee500000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 814>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 814>; + status = "disabled"; + }; - ipmmu_sy0: mmu@e6280000 { - compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; - reg = <0 0xe6280000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7791", + "renesas,rcar-gen2-ether"; + reg = <0 0xee700000 0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 813>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - ipmmu_sy1: mmu@e6290000 { - compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; - reg = <0 0xe6290000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; - ipmmu_ds: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; - reg = <0 0xe6740000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; + pciec: pcie@fe000000 { + compatible = "renesas,pcie-r8a7791", + "renesas,pcie-rcar-gen2"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 + 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 + 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 + 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000 + 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; + }; - ipmmu_mp: mmu@ec680000 { - compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; - reg = <0 0xec680000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; + vsp@fe928000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe928000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 131>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 131>; + }; - ipmmu_mx: mmu@fe951000 { - compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; + vsp@fe930000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe930000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 128>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 128>; + }; - ipmmu_rt: mmu@ffc80000 { - compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; - reg = <0 0xffc80000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; + vsp@fe938000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe938000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 127>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 127>; + }; - ipmmu_gp: mmu@e62a0000 { - compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; - reg = <0 0xe62a0000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; + jpu: jpeg-codec@fe980000 { + compatible = "renesas,jpu-r8a7791", + "renesas,rcar-gen2-jpu"; + reg = <0 0xfe980000 0 0x10300>; + interrupts = ; + clocks = <&cpg CPG_MOD 106>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 106>; + }; - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A7791_CLK_M2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", - "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", "src.5", - "src.4", "src.3", "src.2", "src.1", "src.0", - "ctu.0", "ctu.1", - "mix.0", "mix.1", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", - "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0"; - - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; + du: display@feb00000 { + compatible = "renesas,du-r8a7791"; + reg = <0 0xfeb00000 0 0x40000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>; + clock-names = "du.0", "du.1"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; + }; + + lvds0: lvds@feb90000 { + compatible = "renesas,r8a7791-lvds"; + reg = <0 0xfeb90000 0 0x1c>; + clocks = <&cpg CPG_MOD 726>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 726>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&du_out_lvds0>; + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { + }; + }; }; }; - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; }; - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; + cmt0: timer@ffca0000 { + compatible = "renesas,r8a7791-cmt0", + "renesas,rcar-gen2-cmt0"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 124>; + + status = "disabled"; }; - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; + cmt1: timer@e6130000 { + compatible = "renesas,r8a7791-cmt1", + "renesas,rcar-gen2-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 329>; + clock-names = "fck"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 329>; + + status = "disabled"; }; + }; - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&thermal>; + + trips { + cpu-crit { + temperature = <95000>; + hysteresis = <0>; + type = "critical"; + }; }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; + cooling-maps { }; }; }; + + timer { + compatible = "arm,armv7-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; }; Index: sys/gnu/dts/arm/r8a7792.dtsi =================================================================== --- sys/gnu/dts/arm/r8a7792.dtsi +++ sys/gnu/dts/arm/r8a7792.dtsi @@ -101,63 +101,6 @@ #size-cells = <2>; ranges; - apmu@e6152000 { - compatible = "renesas,r8a7792-apmu", "renesas,apmu"; - reg = <0 0xe6152000 0 0x188>; - cpus = <&cpu0 &cpu1>; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - irqc: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7792", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7792-rst"; - reg = <0 0xe6160000 0 0x0100>; - }; - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7792-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; - - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a7792"; - reg = <0 0xe6060000 0 0x144>; - }; - gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7792", "renesas,rcar-gen2-gpio"; @@ -338,6 +281,155 @@ resets = <&cpg 913>; }; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a7792"; + reg = <0 0xe6060000 0 0x144>; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7792-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + apmu@e6152000 { + compatible = "renesas,r8a7792-apmu", "renesas,apmu"; + reg = <0 0xe6152000 0 0x188>; + cpus = <&cpu0 &cpu1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7792-rst"; + reg = <0 0xe6160000 0 0x0100>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7792-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; + + irqc: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7792", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + ; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + }; + + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; + + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x10>; + }; + }; + + /* I2C doesn't need pinmux */ + i2c0: i2c@e6508000 { + compatible = "renesas,i2c-r8a7792", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 931>; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@e6518000 { + compatible = "renesas,i2c-r8a7792", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 930>; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@e6530000 { + compatible = "renesas,i2c-r8a7792", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 929>; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@e6540000 { + compatible = "renesas,i2c-r8a7792", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 928>; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@e6520000 { + compatible = "renesas,i2c-r8a7792", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6520000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 927>; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@e6528000 { + compatible = "renesas,i2c-r8a7792", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6528000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 925>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 925>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + dmac0: dma-controller@e6700000 { compatible = "renesas,dmac-r8a7792", "renesas,rcar-dmac"; @@ -404,6 +496,35 @@ dma-channels = <15>; }; + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7792", + "renesas,etheravb-rcar-gen2"; + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupts = ; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 812>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7792", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 917>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + scif0: serial@e6e60000 { compatible = "renesas,scif-r8a7792", "renesas,rcar-gen2-scif", "renesas,scif"; @@ -500,162 +621,6 @@ status = "disabled"; }; - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - }; - - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; - - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x10>; - }; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7792", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - clocks = <&cpg CPG_MOD 314>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - jpu: jpeg-codec@fe980000 { - compatible = "renesas,jpu-r8a7792", - "renesas,rcar-gen2-jpu"; - reg = <0 0xfe980000 0 0x10300>; - interrupts = ; - clocks = <&cpg CPG_MOD 106>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 106>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7792", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = ; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 812>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - /* I2C doesn't need pinmux */ - i2c0: i2c@e6508000 { - compatible = "renesas,i2c-r8a7792", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 931>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - compatible = "renesas,i2c-r8a7792", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 930>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - compatible = "renesas,i2c-r8a7792", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 929>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@e6540000 { - compatible = "renesas,i2c-r8a7792", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@e6520000 { - compatible = "renesas,i2c-r8a7792", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6520000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 927>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@e6528000 { - compatible = "renesas,i2c-r8a7792", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6528000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 925>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 925>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7792", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 917>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - msiof0: spi@e6e20000 { compatible = "renesas,msiof-r8a7792", "renesas,rcar-gen2-msiof"; @@ -688,34 +653,6 @@ status = "disabled"; }; - du: display@feb00000 { - compatible = "renesas,du-r8a7792"; - reg = <0 0xfeb00000 0 0x40000>; - reg-names = "du"; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb0: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_rgb1: endpoint { - }; - }; - }; - }; - can0: can@e6e80000 { compatible = "renesas,can-r8a7792", "renesas,rcar-gen2-can"; @@ -808,6 +745,36 @@ status = "disabled"; }; + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7792", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee100000 0 0x328>; + interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + clocks = <&cpg CPG_MOD 314>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + vsp@fe928000 { compatible = "renesas,vsp1"; reg = <0 0xfe928000 0 0x8000>; @@ -835,14 +802,47 @@ resets = <&cpg 127>; }; - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7792-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>; - clock-names = "extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; + jpu: jpeg-codec@fe980000 { + compatible = "renesas,jpu-r8a7792", + "renesas,rcar-gen2-jpu"; + reg = <0 0xfe980000 0 0x10300>; + interrupts = ; + clocks = <&cpg CPG_MOD 106>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 106>; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a7792"; + reg = <0 0xfeb00000 0 0x40000>; + reg-names = "du"; + interrupts = , + ; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>; + clock-names = "du.0", "du.1"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb0: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_rgb1: endpoint { + }; + }; + }; + }; + + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; }; }; Index: sys/gnu/dts/arm/r8a7793-gose.dts =================================================================== --- sys/gnu/dts/arm/r8a7793-gose.dts +++ sys/gnu/dts/arm/r8a7793-gose.dts @@ -48,6 +48,10 @@ aliases { serial0 = &scif0; serial1 = &scif1; + i2c9 = &gpioi2c2; + i2c10 = &gpioi2c4; + i2c11 = &i2chdmi; + i2c12 = &i2cexio4; }; chosen { @@ -296,6 +300,146 @@ #clock-cells = <0>; clock-frequency = <148500000>; }; + + gpioi2c2: i2c-9 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <5>; + }; + + gpioi2c4: i2c-10 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + scl-gpios = <&gpio7 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio7 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <5>; + }; + + /* + * A fallback to GPIO is provided for I2C2. + */ + i2chdmi: i2c-11 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&i2c2>, <&gpioi2c2>; + i2c-bus-name = "i2c-hdmi"; + #address-cells = <1>; + #size-cells = <0>; + + ak4643: codec@12 { + compatible = "asahi-kasei,ak4643"; + #sound-dai-cells = <0>; + reg = <0x12>; + }; + + composite-in@20 { + compatible = "adi,adv7180cp"; + reg = <0x20>; + remote = <&vin1>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7180_in: endpoint { + remote-endpoint = <&composite_con_in>; + }; + }; + + port@3 { + reg = <3>; + adv7180_out: endpoint { + bus-width = <8>; + remote-endpoint = <&vin1ep>; + }; + }; + }; + }; + + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&gpio3>; + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&du_out_rgb>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; + + hdmi-in@4c { + compatible = "adi,adv7612"; + reg = <0x4c>; + interrupt-parent = <&gpio4>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + default-input = <0>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7612_in: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; + }; + + port@2 { + reg = <2>; + adv7612_out: endpoint { + remote-endpoint = <&vin0ep2>; + }; + }; + }; + }; + + eeprom@50 { + compatible = "renesas,r1ex24002", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + }; + + /* + * I2C4 is routed to EXIO connector E, pins 37 (SCL) + 39 (SDA). + * A fallback to GPIO is provided. + */ + i2cexio4: i2c-12 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&i2c4>, <&gpioi2c4>; + i2c-bus-name = "i2c-exio4"; + #address-cells = <1>; + #size-cells = <0>; + }; }; &du { @@ -303,10 +447,9 @@ pinctrl-names = "default"; status = "okay"; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>, + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x13_clk>, <&x2_clk>; - clock-names = "du.0", "du.1", "lvds.0", - "dclkin.0", "dclkin.1"; + clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; ports { port@0 { @@ -314,6 +457,11 @@ remote-endpoint = <&adv7511_in>; }; }; + }; +}; + +&lvds0 { + ports { port@1 { lvds_connector: endpoint { }; @@ -334,6 +482,11 @@ function = "i2c2"; }; + i2c4_pins: i2c4 { + groups = "i2c4_c"; + function = "i2c4"; + }; + du_pins: du { groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; function = "du"; @@ -544,107 +697,11 @@ &i2c2 { pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "default"; + pinctrl-names = "i2c-hdmi"; status = "okay"; clock-frequency = <100000>; - ak4643: codec@12 { - compatible = "asahi-kasei,ak4643"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - composite-in@20 { - compatible = "adi,adv7180cp"; - reg = <0x20>; - remote = <&vin1>; - - port { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7180_in: endpoint { - remote-endpoint = <&composite_con_in>; - }; - }; - - port@3 { - reg = <3>; - adv7180_out: endpoint { - bus-width = <8>; - remote-endpoint = <&vin1ep>; - }; - }; - }; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio3>; - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con_out>; - }; - }; - }; - }; - - hdmi-in@4c { - compatible = "adi,adv7612"; - reg = <0x4c>; - interrupt-parent = <&gpio4>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - default-input = <0>; - - port { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7612_in: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; - }; - - port@2 { - reg = <2>; - adv7612_out: endpoint { - remote-endpoint = <&vin0ep2>; - }; - }; - }; - }; - - eeprom@50 { - compatible = "renesas,r1ex24002", "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; }; &i2c6 { @@ -668,6 +725,11 @@ }; }; +&i2c4 { + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "i2c-exio4"; +}; + &rcar_sound { pinctrl-0 = <&sound_pins &sound_clk_pins>; pinctrl-names = "default"; Index: sys/gnu/dts/arm/r8a7793.dtsi =================================================================== --- sys/gnu/dts/arm/r8a7793.dtsi +++ sys/gnu/dts/arm/r8a7793.dtsi @@ -15,7 +15,6 @@ / { compatible = "renesas,r8a7793"; - interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; @@ -32,6 +31,35 @@ spi0 = &qspi; }; + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -74,1261 +102,1320 @@ }; }; - apmu@e6152000 { - compatible = "renesas,r8a7793-apmu", "renesas,apmu"; - reg = <0 0xe6152000 0 0x188>; - cpus = <&cpu0 &cpu1>; + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; }; - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - thermal-sensors = <&thermal>; + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7793", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; - trips { - cpu-crit { - temperature = <95000>; - hysteresis = <0>; - type = "critical"; - }; - }; - cooling-maps { - }; + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7793", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 911>; }; - }; - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7793", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7793", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7793", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7793", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a7793", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055400 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 905>; + }; - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; + gpio7: gpio@e6055800 { + compatible = "renesas,gpio-r8a7793", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055800 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 904>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 904>; + }; - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a7793"; + reg = <0 0xe6060000 0 0x250>; + }; - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; + /* Special CPG clocks */ + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7793-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 904>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 904>; - }; + apmu@e6152000 { + compatible = "renesas,r8a7793-apmu", "renesas,apmu"; + reg = <0 0xe6152000 0 0x188>; + cpus = <&cpu0 &cpu1>; + }; - thermal: thermal@e61f0000 { - compatible = "renesas,thermal-r8a7793", - "renesas,rcar-gen2-thermal", - "renesas,rcar-thermal"; - reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; - interrupts = ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7793-rst"; + reg = <0 0xe6160000 0 0x0100>; + }; - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7793-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; - cmt0: timer@ffca0000 { - compatible = "renesas,r8a7793-cmt0", "renesas,rcar-gen2-cmt0"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 124>; - - status = "disabled"; - }; + irqc0: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7793", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; - cmt1: timer@e6130000 { - compatible = "renesas,r8a7793-cmt1", "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 329>; - - status = "disabled"; - }; + thermal: thermal@e61f0000 { + compatible = "renesas,thermal-r8a7793", + "renesas,rcar-gen2-thermal", + "renesas,rcar-thermal"; + reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; + interrupts = ; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <0>; + }; - irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7793", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; + ipmmu_sy0: mmu@e6280000 { + compatible = "renesas,ipmmu-r8a7793", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6280000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; - }; + ipmmu_sy1: mmu@e6290000 { + compatible = "renesas,ipmmu-r8a7793", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6290000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; - }; + ipmmu_ds: mmu@e6740000 { + compatible = "renesas,ipmmu-r8a7793", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6740000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <13>; - }; + ipmmu_mp: mmu@ec680000 { + compatible = "renesas,ipmmu-r8a7793", + "renesas,ipmmu-vmsa"; + reg = <0 0xec680000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <13>; - }; + ipmmu_mx: mmu@fe951000 { + compatible = "renesas,ipmmu-r8a7793", + "renesas,ipmmu-vmsa"; + reg = <0 0xfe951000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; - /* The memory map in the User's Manual maps the cores to bus numbers */ - i2c0: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 931>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-r8a7793", + "renesas,ipmmu-vmsa"; + reg = <0 0xffc80000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; - i2c1: i2c@e6518000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 930>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + ipmmu_gp: mmu@e62a0000 { + compatible = "renesas,ipmmu-r8a7793", + "renesas,ipmmu-vmsa"; + reg = <0 0xe62a0000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; - i2c2: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 929>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + }; - i2c3: i2c@e6540000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; - i2c4: i2c@e6520000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6520000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 927>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x10>; + }; + }; - i2c5: i2c@e6528000 { - /* doesn't need pinmux */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6528000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 925>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 925>; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; + /* The memory map in the User's Manual maps the cores to + * bus numbers + */ + i2c0: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7793", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 931>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - i2c6: i2c@e60b0000 { - /* doesn't need pinmux */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7793", "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - dmas = <&dmac0 0x77>, <&dmac0 0x78>, - <&dmac1 0x77>, <&dmac1 0x78>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 926>; - status = "disabled"; - }; + i2c1: i2c@e6518000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7793", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 930>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - i2c7: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7793", "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 318>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>, - <&dmac1 0x61>, <&dmac1 0x62>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; + i2c2: i2c@e6530000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7793", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 929>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - i2c8: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7793", "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 323>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>, - <&dmac1 0x65>, <&dmac1 0x66>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 323>; - status = "disabled"; - }; + i2c3: i2c@e6540000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7793", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 928>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a7793"; - reg = <0 0xe6060000 0 0x250>; - }; + i2c4: i2c@e6520000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7793", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6520000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 927>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7793", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; + i2c5: i2c@e6528000 { + /* doesn't need pinmux */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7793", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6528000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 925>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 925>; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; - sdhi1: sd@ee140000 { - compatible = "renesas,sdhi-r8a7793", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; + i2c6: i2c@e60b0000 { + /* doesn't need pinmux */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7793", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 926>; + dmas = <&dmac0 0x77>, <&dmac0 0x78>, + <&dmac1 0x77>, <&dmac1 0x78>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 926>; + status = "disabled"; + }; - sdhi2: sd@ee160000 { - compatible = "renesas,sdhi-r8a7793", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee160000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; + i2c7: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7793", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 318>; + dmas = <&dmac0 0x61>, <&dmac0 0x62>, + <&dmac1 0x61>, <&dmac1 0x62>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; + }; - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7793", "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = ; - clocks = <&cpg CPG_MOD 315>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 315>; - reg-io-width = <4>; - status = "disabled"; - max-frequency = <97500000>; - }; + i2c8: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7793", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 323>; + dmas = <&dmac0 0x65>, <&dmac0 0x66>, + <&dmac1 0x65>, <&dmac1 0x66>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 323>; + status = "disabled"; + }; - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, - <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7793", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <15>; + }; - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>; - clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>, - <&dmac1 0x25>, <&dmac1 0x26>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a7793", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <15>; + }; - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>; - clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>, - <&dmac1 0x27>, <&dmac1 0x28>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7793", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 917>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - scifa3: serial@e6c70000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c70000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1106>; - clock-names = "fck"; - dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, - <&dmac1 0x1b>, <&dmac1 0x1c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 1106>; - status = "disabled"; - }; + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7793", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c40000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; - scifa4: serial@e6c78000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c78000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1107>; - clock-names = "fck"; - dmas = <&dmac0 0x1f>, <&dmac0 0x20>, - <&dmac1 0x1f>, <&dmac1 0x20>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 1107>; - status = "disabled"; - }; + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7793", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c50000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; - scifa5: serial@e6c80000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c80000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1108>; - clock-names = "fck"; - dmas = <&dmac0 0x23>, <&dmac0 0x24>, - <&dmac1 0x23>, <&dmac1 0x24>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 1108>; - status = "disabled"; - }; + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7793", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7793", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>; - clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, - <&dmac1 0x3d>, <&dmac1 0x3e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; + scifa3: serial@e6c70000 { + compatible = "renesas,scifa-r8a7793", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c70000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 1106>; + clock-names = "fck"; + dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, + <&dmac1 0x1b>, <&dmac1 0x1c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 1106>; + status = "disabled"; + }; - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7793", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>; - clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>, - <&dmac1 0x19>, <&dmac1 0x1a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; + scifa4: serial@e6c78000 { + compatible = "renesas,scifa-r8a7793", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c78000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 1107>; + clock-names = "fck"; + dmas = <&dmac0 0x1f>, <&dmac0 0x20>, + <&dmac1 0x1f>, <&dmac1 0x20>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 1107>; + status = "disabled"; + }; - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7793", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 216>; - clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, - <&dmac1 0x1d>, <&dmac1 0x1e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 216>; - status = "disabled"; - }; + scifa5: serial@e6c80000 { + compatible = "renesas,scifa-r8a7793", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c80000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 1108>; + clock-names = "fck"; + dmas = <&dmac0 0x23>, <&dmac0 0x24>, + <&dmac1 0x23>, <&dmac1 0x24>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 1108>; + status = "disabled"; + }; - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 721>; - status = "disabled"; - }; + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7793", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 720>; - status = "disabled"; - }; + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7793", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c30000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>; + clock-names = "fck"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; - scif2: serial@e6e58000 { - compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e58000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 719>; - status = "disabled"; - }; + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7793", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6ce0000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 216>; + status = "disabled"; + }; - scif3: serial@e6ea8000 { - compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6ea8000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>, - <&dmac1 0x2f>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 718>; - status = "disabled"; - }; + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7793", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7793_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 721>; + status = "disabled"; + }; - scif4: serial@e6ee0000 { - compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6ee0000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, - <&dmac1 0xfb>, <&dmac1 0xfc>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 715>; - status = "disabled"; - }; + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7793", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7793_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 720>; + status = "disabled"; + }; - scif5: serial@e6ee8000 { - compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6ee8000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, - <&dmac1 0xfd>, <&dmac1 0xfe>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - }; + scif2: serial@e6e58000 { + compatible = "renesas,scif-r8a7793", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e58000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7793_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 719>; + status = "disabled"; + }; - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7793", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; + scif3: serial@e6ea8000 { + compatible = "renesas,scif-r8a7793", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ea8000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7793_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>, + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 718>; + status = "disabled"; + }; - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7793", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; + scif4: serial@e6ee0000 { + compatible = "renesas,scif-r8a7793", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee0000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7793_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, + <&dmac1 0xfb>, <&dmac1 0xfc>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 715>; + status = "disabled"; + }; - hscif2: serial@e62d0000 { - compatible = "renesas,hscif-r8a7793", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62d0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, - <&dmac1 0x3b>, <&dmac1 0x3c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 713>; - status = "disabled"; - }; + scif5: serial@e6ee8000 { + compatible = "renesas,scif-r8a7793", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee8000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7793_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, + <&dmac1 0xfd>, <&dmac1 0xfe>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; + }; - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - }; + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7793", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7793_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; + }; - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7793", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7793_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + }; - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x10>; + hscif2: serial@e62d0000 { + compatible = "renesas,hscif-r8a7793", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62d0000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7793_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, + <&dmac1 0x3b>, <&dmac1 0x3c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 713>; + status = "disabled"; }; - }; - ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7793", - "renesas,rcar-gen2-ether"; - reg = <0 0xee700000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 813>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 813>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + can0: can@e6e80000 { + compatible = "renesas,can-r8a7793", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7793_CLK_RCAN>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 811>; - status = "disabled"; - }; + can1: can@e6e88000 { + compatible = "renesas,can-r8a7793", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7793_CLK_RCAN>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 810>; - status = "disabled"; - }; + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7793", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 811>; + status = "disabled"; + }; - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 809>; - status = "disabled"; - }; + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7793", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 810>; + status = "disabled"; + }; - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7793", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 917>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7793", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 809>; + status = "disabled"; + }; - du: display@feb00000 { - compatible = "renesas,du-r8a7793"; - reg = <0 0xfeb00000 0 0x40000>, - <0 0xfeb90000 0 0x1c>; - reg-names = "du", "lvds.0"; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 726>; - clock-names = "du.0", "du.1", "lvds.0"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a7793", + "renesas,rcar_sound-gen2"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, + <&cpg CPG_CORE R8A7793_CLK_M2>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0", + "src.9", "src.8", "src.7", "src.6", + "src.5", "src.4", "src.3", "src.2", + "src.1", "src.0", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, + <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, + <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0"; + + status = "disabled"; + + rcar_sound,dvc { + dvc0: dvc-0 { + dmas = <&audma1 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma1 0xbe>; + dma-names = "tx"; + }; + }; - port@0 { - reg = <0>; - du_out_rgb: endpoint { + rcar_sound,src { + src0: src-0 { + interrupts = ; + dmas = <&audma0 0x85>, <&audma1 0x9a>; + dma-names = "rx", "tx"; + }; + src1: src-1 { + interrupts = ; + dmas = <&audma0 0x87>, <&audma1 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = ; + dmas = <&audma0 0x89>, <&audma1 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = ; + dmas = <&audma0 0x8b>, <&audma1 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = ; + dmas = <&audma0 0x8d>, <&audma1 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = ; + dmas = <&audma0 0x8f>, <&audma1 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = ; + dmas = <&audma0 0x91>, <&audma1 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src-7 { + interrupts = ; + dmas = <&audma0 0x93>, <&audma1 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src-8 { + interrupts = ; + dmas = <&audma0 0x95>, <&audma1 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src-9 { + interrupts = ; + dmas = <&audma0 0x97>, <&audma1 0xba>; + dma-names = "rx", "tx"; }; }; - port@1 { - reg = <1>; - du_out_lvds0: endpoint { + + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = ; + dmas = <&audma0 0x01>, <&audma1 0x02>, + <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi-1 { + interrupts = ; + dmas = <&audma0 0x03>, <&audma1 0x04>, + <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi-2 { + interrupts = ; + dmas = <&audma0 0x05>, <&audma1 0x06>, + <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi-3 { + interrupts = ; + dmas = <&audma0 0x07>, <&audma1 0x08>, + <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi-4 { + interrupts = ; + dmas = <&audma0 0x09>, <&audma1 0x0a>, + <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi-5 { + interrupts = ; + dmas = <&audma0 0x0b>, <&audma1 0x0c>, + <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi-6 { + interrupts = ; + dmas = <&audma0 0x0d>, <&audma1 0x0e>, + <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi-7 { + interrupts = ; + dmas = <&audma0 0x0f>, <&audma1 0x10>, + <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi-8 { + interrupts = ; + dmas = <&audma0 0x11>, <&audma1 0x12>, + <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi-9 { + interrupts = ; + dmas = <&audma0 0x13>, <&audma1 0x14>, + <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; }; }; }; - }; - can0: can@e6e80000 { - compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7793_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7793", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <13>; + }; - can1: can@e6e88000 { - compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7793_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a7793", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 501>; + #dma-cells = <1>; + dma-channels = <13>; + }; - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7793", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee100000 0 0x328>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; + sdhi1: sd@ee140000 { + compatible = "renesas,sdhi-r8a7793", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee140000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, + <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; + sdhi2: sd@ee160000 { + compatible = "renesas,sdhi-r8a7793", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee160000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + mmcif0: mmc@ee200000 { + compatible = "renesas,mmcif-r8a7793", + "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = ; + clocks = <&cpg CPG_MOD 315>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, + <&dmac1 0xd1>, <&dmac1 0xd2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 315>; + reg-io-width = <4>; + status = "disabled"; + max-frequency = <97500000>; + }; - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7793", + "renesas,rcar-gen2-ether"; + reg = <0 0xee700000 0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 813>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - /* Special CPG clocks */ - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7793-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7793-rst"; - reg = <0 0xe6160000 0 0x0100>; - }; + du: display@feb00000 { + compatible = "renesas,du-r8a7793"; + reg = <0 0xfeb00000 0 0x40000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>; + clock-names = "du.0", "du.1"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; + }; + }; - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; + lvds0: lvds@feb90000 { + compatible = "renesas,r8a7793-lvds"; + reg = <0 0xfeb90000 0 0x1c>; + clocks = <&cpg CPG_MOD 726>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 726>; - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7793-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; + status = "disabled"; - ipmmu_sy0: mmu@e6280000 { - compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; - reg = <0 0xe6280000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; + ports { + #address-cells = <1>; + #size-cells = <0>; - ipmmu_sy1: mmu@e6290000 { - compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; - reg = <0 0xe6290000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&du_out_lvds0>; + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { + }; + }; + }; + }; - ipmmu_ds: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; - reg = <0 0xe6740000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; - ipmmu_mp: mmu@ec680000 { - compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; - reg = <0 0xec680000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; + cmt0: timer@ffca0000 { + compatible = "renesas,r8a7793-cmt0", + "renesas,rcar-gen2-cmt0"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 124>; + + status = "disabled"; + }; - ipmmu_mx: mmu@fe951000 { - compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; + cmt1: timer@e6130000 { + compatible = "renesas,r8a7793-cmt1", + "renesas,rcar-gen2-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 329>; + clock-names = "fck"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 329>; + + status = "disabled"; + }; }; - ipmmu_rt: mmu@ffc80000 { - compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; - reg = <0 0xffc80000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; - ipmmu_gp: mmu@e62a0000 { - compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; - reg = <0 0xe62a0000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; + thermal-sensors = <&thermal>; - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7793", "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A7793_CLK_M2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", - "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", "src.5", - "src.4", "src.3", "src.2", "src.1", "src.0", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", - "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0"; - - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; + trips { + cpu-crit { + temperature = <95000>; + hysteresis = <0>; + type = "critical"; + }; }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; + cooling-maps { }; }; + }; - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; + timer { + compatible = "arm,armv7-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; }; }; Index: sys/gnu/dts/arm/r8a7794-alt.dts =================================================================== --- sys/gnu/dts/arm/r8a7794-alt.dts +++ sys/gnu/dts/arm/r8a7794-alt.dts @@ -18,7 +18,9 @@ aliases { serial0 = &scif2; + i2c9 = &gpioi2c1; i2c10 = &gpioi2c4; + i2c11 = &i2chdmi; i2c12 = &i2cexio4; }; @@ -138,17 +140,50 @@ clock-frequency = <148500000>; }; + gpioi2c1: i2c-9 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + scl-gpios = <&gpio4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + }; + gpioi2c4: i2c-10 { #address-cells = <1>; #size-cells = <0>; compatible = "i2c-gpio"; status = "disabled"; - sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; scl-gpios = <&gpio4 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <5>; }; /* + * A fallback to GPIO is provided for I2C1. + */ + i2chdmi: i2c-11 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&i2c1>, <&gpioi2c1>; + i2c-bus-name = "i2c-hdmi"; + #address-cells = <1>; + #size-cells = <0>; + + composite-in@20 { + compatible = "adi,adv7180"; + reg = <0x20>; + remote = <&vin0>; + + port { + adv7180: endpoint { + bus-width = <8>; + remote-endpoint = <&vin0ep>; + }; + }; + }; + }; + + /* * I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA). * A fallback to GPIO is provided. */ @@ -324,23 +359,9 @@ &i2c1 { pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; + pinctrl-names = "i2c-hdmi"; - status = "okay"; clock-frequency = <400000>; - - composite-in@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - remote = <&vin0>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin0ep>; - }; - }; - }; }; &i2c4 { Index: sys/gnu/dts/arm/r8a7794-silk.dts =================================================================== --- sys/gnu/dts/arm/r8a7794-silk.dts +++ sys/gnu/dts/arm/r8a7794-silk.dts @@ -24,6 +24,7 @@ /dts-v1/; #include "r8a7794.dtsi" #include +#include / { model = "SILK"; @@ -31,6 +32,8 @@ aliases { serial0 = &scif2; + i2c9 = &gpioi2c1; + i2c10 = &i2chdmi; }; chosen { @@ -43,6 +46,60 @@ reg = <0 0x40000000 0 0x40000000>; }; + gpio-keys { + compatible = "gpio-keys"; + + key-3 { + gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW3"; + wakeup-source; + debounce-interval = <20>; + }; + key-4 { + gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW4"; + wakeup-source; + debounce-interval = <20>; + }; + key-6 { + gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW6"; + wakeup-source; + debounce-interval = <20>; + }; + key-a { + gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW12-1"; + wakeup-source; + debounce-interval = <20>; + }; + key-b { + gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW12-2"; + wakeup-source; + debounce-interval = <20>; + }; + key-c { + gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW12-3"; + wakeup-source; + debounce-interval = <20>; + }; + key-d { + gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW12-4"; + wakeup-source; + debounce-interval = <20>; + }; + }; + d3_3v: regulator-d3-3v { compatible = "regulator-fixed"; regulator-name = "D3.3V"; @@ -153,6 +210,84 @@ clocks = <&x9_clk>; }; }; + + gpioi2c1: i2c-9 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + scl-gpios = <&gpio4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <5>; + }; + + /* + * A fallback to GPIO is provided for I2C1. + */ + i2chdmi: i2c-10 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&i2c1>, <&gpioi2c1>; + i2c-bus-name = "i2c-hdmi"; + #address-cells = <1>; + #size-cells = <0>; + + ak4643: codec@12 { + compatible = "asahi-kasei,ak4643"; + #sound-dai-cells = <0>; + reg = <0x12>; + }; + + composite-in@20 { + compatible = "adi,adv7180"; + reg = <0x20>; + remote = <&vin0>; + + port { + adv7180: endpoint { + bus-width = <8>; + remote-endpoint = <&vin0ep>; + }; + }; + }; + + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&gpio5>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&du_out_rgb0>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + eeprom@50 { + compatible = "renesas,r1ex24002", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + }; }; &extal_clk { @@ -268,61 +403,9 @@ &i2c1 { pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; + pinctrl-names = "i2c-hdmi"; - status = "okay"; clock-frequency = <400000>; - - ak4643: codec@12 { - compatible = "asahi-kasei,ak4643"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - composite-in@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - remote = <&vin0>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin0ep>; - }; - }; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio5>; - interrupts = <23 IRQ_TYPE_LEVEL_LOW>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb0>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; }; &mmcif0 { Index: sys/gnu/dts/arm/r8a7794.dtsi =================================================================== --- sys/gnu/dts/arm/r8a7794.dtsi +++ sys/gnu/dts/arm/r8a7794.dtsi @@ -16,7 +16,6 @@ / { compatible = "renesas,r8a7794"; - interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; @@ -34,6 +33,35 @@ vin1 = &vin1; }; + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clka: audio_clka { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clkb: audio_clkb { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clkc: audio_clkc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -67,1290 +95,1313 @@ }; }; - apmu@e6151000 { - compatible = "renesas,r8a7794-apmu", "renesas,apmu"; - reg = <0 0xe6151000 0 0x188>; - cpus = <&cpu0 &cpu1>; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 408>; + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; }; - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 912>; + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; }; - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7794", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7794", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7794", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 28>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7794", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7794", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; - cmt0: timer@ffca0000 { - compatible = "renesas,r8a7794-cmt0", "renesas,rcar-gen2-cmt0"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 124>; - - status = "disabled"; - }; + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7794", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 28>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; - cmt1: timer@e6130000 { - compatible = "renesas,r8a7794-cmt1", "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 329>; - - status = "disabled"; - }; + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a7794", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055400 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 905>; + }; - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a7794"; + reg = <0 0xe6060000 0 0x11c>; + }; - irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7794", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7794-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a7794"; - reg = <0 0xe6060000 0 0x11c>; - }; + apmu@e6151000 { + compatible = "renesas,r8a7794-apmu", "renesas,apmu"; + reg = <0 0xe6151000 0 0x188>; + cpus = <&cpu0 &cpu1>; + }; - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; - }; + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7794-rst"; + reg = <0 0xe6160000 0 0x0100>; + }; - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; - }; + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7794-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", - "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <13>; - }; + irqc0: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7794", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, - <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; + ipmmu_sy0: mmu@e6280000 { + compatible = "renesas,ipmmu-r8a7794", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6280000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>; - clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>, - <&dmac1 0x25>, <&dmac1 0x26>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; + ipmmu_sy1: mmu@e6290000 { + compatible = "renesas,ipmmu-r8a7794", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6290000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>; - clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>, - <&dmac1 0x27>, <&dmac1 0x28>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; + ipmmu_ds: mmu@e6740000 { + compatible = "renesas,ipmmu-r8a7794", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6740000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; - scifa3: serial@e6c70000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c70000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1106>; - clock-names = "fck"; - dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, - <&dmac1 0x1b>, <&dmac1 0x1c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 1106>; - status = "disabled"; - }; + ipmmu_mp: mmu@ec680000 { + compatible = "renesas,ipmmu-r8a7794", + "renesas,ipmmu-vmsa"; + reg = <0 0xec680000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; - scifa4: serial@e6c78000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c78000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1107>; - clock-names = "fck"; - dmas = <&dmac0 0x1f>, <&dmac0 0x20>, - <&dmac1 0x1f>, <&dmac1 0x20>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 1107>; - status = "disabled"; - }; + ipmmu_mx: mmu@fe951000 { + compatible = "renesas,ipmmu-r8a7794", + "renesas,ipmmu-vmsa"; + reg = <0 0xfe951000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; - scifa5: serial@e6c80000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c80000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1108>; - clock-names = "fck"; - dmas = <&dmac0 0x23>, <&dmac0 0x24>, - <&dmac1 0x23>, <&dmac1 0x24>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 1108>; - status = "disabled"; - }; + ipmmu_gp: mmu@e62a0000 { + compatible = "renesas,ipmmu-r8a7794", + "renesas,ipmmu-vmsa"; + reg = <0 0xe62a0000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7794", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>; - clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, - <&dmac1 0x3d>, <&dmac1 0x3e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + }; - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7794", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>; - clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>, - <&dmac1 0x19>, <&dmac1 0x1a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7794", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 216>; - clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, - <&dmac1 0x1d>, <&dmac1 0x1e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 216>; - status = "disabled"; - }; + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x10>; + }; + }; - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 721>; - status = "disabled"; - }; + /* The memory map in the User's Manual maps the cores to + * bus numbers + */ + i2c0: i2c@e6508000 { + compatible = "renesas,i2c-r8a7794", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 931>; + #address-cells = <1>; + #size-cells = <0>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 720>; - status = "disabled"; - }; + i2c1: i2c@e6518000 { + compatible = "renesas,i2c-r8a7794", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 930>; + #address-cells = <1>; + #size-cells = <0>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - scif2: serial@e6e58000 { - compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e58000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 719>; - status = "disabled"; - }; + i2c2: i2c@e6530000 { + compatible = "renesas,i2c-r8a7794", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 929>; + #address-cells = <1>; + #size-cells = <0>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - scif3: serial@e6ea8000 { - compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6ea8000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>, - <&dmac1 0x2f>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 718>; - status = "disabled"; - }; + i2c3: i2c@e6540000 { + compatible = "renesas,i2c-r8a7794", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 928>; + #address-cells = <1>; + #size-cells = <0>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - scif4: serial@e6ee0000 { - compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6ee0000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, - <&dmac1 0xfb>, <&dmac1 0xfc>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 715>; - status = "disabled"; - }; + i2c4: i2c@e6520000 { + compatible = "renesas,i2c-r8a7794", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6520000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 927>; + #address-cells = <1>; + #size-cells = <0>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - scif5: serial@e6ee8000 { - compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6ee8000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, - <&dmac1 0xfd>, <&dmac1 0xfe>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - }; + i2c5: i2c@e6528000 { + compatible = "renesas,i2c-r8a7794", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6528000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 925>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 925>; + #address-cells = <1>; + #size-cells = <0>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7794", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; + i2c6: i2c@e6500000 { + compatible = "renesas,iic-r8a7794", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 318>; + dmas = <&dmac0 0x61>, <&dmac0 0x62>, + <&dmac1 0x61>, <&dmac1 0x62>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 318>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7794", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; + i2c7: i2c@e6510000 { + compatible = "renesas,iic-r8a7794", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 323>; + dmas = <&dmac0 0x65>, <&dmac0 0x66>, + <&dmac1 0x65>, <&dmac1 0x66>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 323>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - hscif2: serial@e62d0000 { - compatible = "renesas,hscif-r8a7794", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62d0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, - <&dmac1 0x3b>, <&dmac1 0x3c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 713>; - status = "disabled"; - }; + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7794", + "renesas,rcar-gen2-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 704>; + renesas,buswait = <4>; + phys = <&usb0 1>; + phy-names = "usb"; + status = "disabled"; + }; - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - }; + usbphy: usb-phy@e6590100 { + compatible = "renesas,usb-phy-r8a7794", + "renesas,rcar-gen2-usb-phy"; + reg = <0 0xe6590100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cpg CPG_MOD 704>; + clock-names = "usbhs"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; + usb0: usb-channel@0 { + reg = <0>; + #phy-cells = <1>; + }; + usb2: usb-channel@2 { + reg = <2>; + #phy-cells = <1>; + }; + }; - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x10>; + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7794", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <15>; }; - }; - ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7794", - "renesas,rcar-gen2-ether"; - reg = <0 0xee700000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 813>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 813>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a7794", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <15>; + }; - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7794", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = ; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 812>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7794", + "renesas,etheravb-rcar-gen2"; + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupts = ; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 812>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - /* The memory map in the User's Manual maps the cores to bus numbers */ - i2c0: i2c@e6508000 { - compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 931>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7794", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 917>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - i2c1: i2c@e6518000 { - compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 930>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7794", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c40000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; - i2c2: i2c@e6530000 { - compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 929>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7794", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c50000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; - i2c3: i2c@e6540000 { - compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 928>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7794", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; - i2c4: i2c@e6520000 { - compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6520000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 927>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + scifa3: serial@e6c70000 { + compatible = "renesas,scifa-r8a7794", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c70000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 1106>; + clock-names = "fck"; + dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, + <&dmac1 0x1b>, <&dmac1 0x1c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 1106>; + status = "disabled"; + }; - i2c5: i2c@e6528000 { - compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6528000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 925>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 925>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; + scifa4: serial@e6c78000 { + compatible = "renesas,scifa-r8a7794", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c78000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 1107>; + clock-names = "fck"; + dmas = <&dmac0 0x1f>, <&dmac0 0x20>, + <&dmac1 0x1f>, <&dmac1 0x20>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 1107>; + status = "disabled"; + }; - i2c6: i2c@e6500000 { - compatible = "renesas,iic-r8a7794", "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 318>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>, - <&dmac1 0x61>, <&dmac1 0x62>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 318>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + scifa5: serial@e6c80000 { + compatible = "renesas,scifa-r8a7794", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c80000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 1108>; + clock-names = "fck"; + dmas = <&dmac0 0x23>, <&dmac0 0x24>, + <&dmac1 0x23>, <&dmac1 0x24>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 1108>; + status = "disabled"; + }; - i2c7: i2c@e6510000 { - compatible = "renesas,iic-r8a7794", "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 323>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>, - <&dmac1 0x65>, <&dmac1 0x66>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 323>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7794", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = ; - clocks = <&cpg CPG_MOD 315>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 315>; - reg-io-width = <4>; - status = "disabled"; - }; + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7794", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c30000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>; + clock-names = "fck"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7794", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7794", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6ce0000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 216>; + status = "disabled"; + }; - sdhi1: sd@ee140000 { - compatible = "renesas,sdhi-r8a7794", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7794", + "renesas,rcar-gen2-scif", + "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7794_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 721>; + status = "disabled"; + }; - sdhi2: sd@ee160000 { - compatible = "renesas,sdhi-r8a7794", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee160000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7794", + "renesas,rcar-gen2-scif", + "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7794_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 720>; + status = "disabled"; + }; - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7794", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 917>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + scif2: serial@e6e58000 { + compatible = "renesas,scif-r8a7794", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e58000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7794_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 719>; + status = "disabled"; + }; - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 811>; - status = "disabled"; - }; + scif3: serial@e6ea8000 { + compatible = "renesas,scif-r8a7794", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ea8000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7794_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>, + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 718>; + status = "disabled"; + }; - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 810>; - status = "disabled"; - }; + scif4: serial@e6ee0000 { + compatible = "renesas,scif-r8a7794", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee0000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7794_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, + <&dmac1 0xfb>, <&dmac1 0xfc>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 715>; + status = "disabled"; + }; - pci0: pci@ee090000 { - compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee090000 0 0xc00>, - <0 0xee080000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; - interrupt-map-mask = <0xff00 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x800 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; + scif5: serial@e6ee8000 { + compatible = "renesas,scif-r8a7794", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee8000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7794_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, + <&dmac1 0xfd>, <&dmac1 0xfe>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; }; - usb@2,0 { - reg = <0x1000 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7794", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 717>, + <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; }; - }; - pci1: pci@ee0d0000 { - compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee0d0000 0 0xc00>, - <0 0xee0c0000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <1 1>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; - interrupt-map-mask = <0xff00 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x10800 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7794", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>, + <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; }; - usb@2,0 { - reg = <0x11000 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; + hscif2: serial@e62d0000 { + compatible = "renesas,hscif-r8a7794", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62d0000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7794_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, + <&dmac1 0x3b>, <&dmac1 0x3c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 713>; + status = "disabled"; }; - }; - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 704>; - renesas,buswait = <4>; - phys = <&usb0 1>; - phy-names = "usb"; - status = "disabled"; - }; + can0: can@e6e80000 { + compatible = "renesas,can-r8a7794", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7794_CLK_RCAN>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; - usbphy: usb-phy@e6590100 { - compatible = "renesas,usb-phy-r8a7794", - "renesas,rcar-gen2-usb-phy"; - reg = <0 0xe6590100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cpg CPG_MOD 704>; - clock-names = "usbhs"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 704>; - status = "disabled"; + can1: can@e6e88000 { + compatible = "renesas,can-r8a7794", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7794_CLK_RCAN>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; - usb0: usb-channel@0 { - reg = <0>; - #phy-cells = <1>; + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7794", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 811>; + status = "disabled"; }; - usb2: usb-channel@2 { - reg = <2>; - #phy-cells = <1>; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7794", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 810>; + status = "disabled"; }; - }; - vsp@fe928000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe928000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 131>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 131>; - }; + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a7794", + "renesas,rcar_sound-gen2"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>, + <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>, + <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clka>, <&audio_clkb>, <&audio_clkc>, + <&cpg CPG_CORE R8A7794_CLK_M2>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0", + "src.6", "src.5", "src.4", "src.3", + "src.2", "src.1", + "ctu.0", "ctu.1", + "mix.0", "mix.1", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, + <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, + <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0"; + + status = "disabled"; + + rcar_sound,dvc { + dvc0: dvc-0 { + dmas = <&audma0 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma0 0xbe>; + dma-names = "tx"; + }; + }; - vsp@fe930000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe930000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 128>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 128>; - }; + rcar_sound,mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; - du: display@feb00000 { - compatible = "renesas,du-r8a7794"; - reg = <0 0xfeb00000 0 0x40000>; - reg-names = "du"; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; + }; - port@0 { - reg = <0>; - du_out_rgb0: endpoint { + rcar_sound,src { + src-0 { + status = "disabled"; + }; + src1: src-1 { + interrupts = ; + dmas = <&audma0 0x87>, <&audma0 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = ; + dmas = <&audma0 0x89>, <&audma0 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = ; + dmas = <&audma0 0x8b>, <&audma0 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = ; + dmas = <&audma0 0x8d>, <&audma0 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = ; + dmas = <&audma0 0x8f>, <&audma0 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = ; + dmas = <&audma0 0x91>, <&audma0 0xb4>; + dma-names = "rx", "tx"; }; }; - port@1 { - reg = <1>; - du_out_rgb1: endpoint { + + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = ; + dmas = <&audma0 0x01>, <&audma0 0x02>, + <&audma0 0x15>, <&audma0 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi-1 { + interrupts = ; + dmas = <&audma0 0x03>, <&audma0 0x04>, + <&audma0 0x49>, <&audma0 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi-2 { + interrupts = ; + dmas = <&audma0 0x05>, <&audma0 0x06>, + <&audma0 0x63>, <&audma0 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi-3 { + interrupts = ; + dmas = <&audma0 0x07>, <&audma0 0x08>, + <&audma0 0x6f>, <&audma0 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi-4 { + interrupts = ; + dmas = <&audma0 0x09>, <&audma0 0x0a>, + <&audma0 0x71>, <&audma0 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi-5 { + interrupts = ; + dmas = <&audma0 0x0b>, <&audma0 0x0c>, + <&audma0 0x73>, <&audma0 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi-6 { + interrupts = ; + dmas = <&audma0 0x0d>, <&audma0 0x0e>, + <&audma0 0x75>, <&audma0 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi-7 { + interrupts = ; + dmas = <&audma0 0x0f>, <&audma0 0x10>, + <&audma0 0x79>, <&audma0 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi-8 { + interrupts = ; + dmas = <&audma0 0x11>, <&audma0 0x12>, + <&audma0 0x7b>, <&audma0 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi-9 { + interrupts = ; + dmas = <&audma0 0x13>, <&audma0 0x14>, + <&audma0 0x7d>, <&audma0 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; }; }; }; - }; - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7794_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - can1: can@e6e88000 { - compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7794_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; - - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7794", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", "ch4", + "ch5", "ch6", "ch7", "ch8", "ch9", + "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <13>; + }; - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + pci0: pci@ee090000 { + compatible = "renesas,pci-r8a7794", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee090000 0 0xc00>, + <0 0xee080000 0 0x1100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; - /* - * The external audio clocks are configured as 0 Hz fixed - * frequency clocks by default. Boards that provide audio - * clocks should override them. - */ - audio_clka: audio_clka { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clkb: audio_clkb { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clkc: audio_clkc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + }; - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7794-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; + pci1: pci@ee0d0000 { + compatible = "renesas,pci-r8a7794", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee0d0000 0 0xc00>, + <0 0xee0c0000 0 0x1100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <1 1>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x10800 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7794-rst"; - reg = <0 0xe6160000 0 0x0100>; - }; + usb@2,0 { + reg = <0x11000 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + }; - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7794", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee100000 0 0x328>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7794-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; + sdhi1: sd@ee140000 { + compatible = "renesas,sdhi-r8a7794", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee140000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, + <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; - ipmmu_sy0: mmu@e6280000 { - compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; - reg = <0 0xe6280000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; + sdhi2: sd@ee160000 { + compatible = "renesas,sdhi-r8a7794", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee160000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; - ipmmu_sy1: mmu@e6290000 { - compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; - reg = <0 0xe6290000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; + mmcif0: mmc@ee200000 { + compatible = "renesas,mmcif-r8a7794", + "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = ; + clocks = <&cpg CPG_MOD 315>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, + <&dmac1 0xd1>, <&dmac1 0xd2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 315>; + reg-io-width = <4>; + status = "disabled"; + }; - ipmmu_ds: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; - reg = <0 0xe6740000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7794", + "renesas,rcar-gen2-ether"; + reg = <0 0xee700000 0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 813>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - ipmmu_mp: mmu@ec680000 { - compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; - reg = <0 0xec680000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; - ipmmu_mx: mmu@fe951000 { - compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; + vsp@fe928000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe928000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 131>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 131>; + }; - ipmmu_gp: mmu@e62a0000 { - compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; - reg = <0 0xe62a0000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; + vsp@fe930000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe930000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 128>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 128>; + }; - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7794", - "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>, - <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>, - <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clka>, <&audio_clkb>, <&audio_clkc>, - <&cpg CPG_CORE R8A7794_CLK_M2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", - "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", - "src.6", "src.5", "src.4", "src.3", "src.2", - "src.1", - "ctu.0", "ctu.1", - "mix.0", "mix.1", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", - "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0"; - - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma0 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma0 0xbe>; - dma-names = "tx"; + du: display@feb00000 { + compatible = "renesas,du-r8a7794"; + reg = <0 0xfeb00000 0 0x40000>; + reg-names = "du"; + interrupts = , + ; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; + clock-names = "du.0", "du.1"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb0: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_rgb1: endpoint { + }; + }; }; }; - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; }; - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; + cmt0: timer@ffca0000 { + compatible = "renesas,r8a7794-cmt0", + "renesas,rcar-gen2-cmt0"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 124>; + + status = "disabled"; }; - rcar_sound,src { - src-0 { - status = "disabled"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma0 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma0 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma0 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma0 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma0 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma0 0xb4>; - dma-names = "rx", "tx"; - }; + cmt1: timer@e6130000 { + compatible = "renesas,r8a7794-cmt1", + "renesas,rcar-gen2-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 329>; + clock-names = "fck"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 329>; + + status = "disabled"; }; + }; - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma0 0x02>, - <&audma0 0x15>, <&audma0 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma0 0x04>, - <&audma0 0x49>, <&audma0 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma0 0x06>, - <&audma0 0x63>, <&audma0 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma0 0x08>, - <&audma0 0x6f>, <&audma0 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma0 0x0a>, - <&audma0 0x71>, <&audma0 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma0 0x0c>, - <&audma0 0x73>, <&audma0 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma0 0x0e>, - <&audma0 0x75>, <&audma0 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma0 0x10>, - <&audma0 0x79>, <&audma0 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma0 0x12>, - <&audma0 0x7b>, <&audma0 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma0 0x14>, - <&audma0 0x7d>, <&audma0 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; + timer { + compatible = "arm,armv7-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; }; }; Index: sys/gnu/dts/arm/rk322x.dtsi =================================================================== --- sys/gnu/dts/arm/rk322x.dtsi +++ sys/gnu/dts/arm/rk322x.dtsi @@ -233,7 +233,7 @@ }; grf: syscon@11000000 { - compatible = "syscon", "simple-mfd"; + compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd"; reg = <0x11000000 0x1000>; #address-cells = <1>; #size-cells = <1>; Index: sys/gnu/dts/arm/rk3288-phycore-rdk.dts =================================================================== --- sys/gnu/dts/arm/rk3288-phycore-rdk.dts +++ sys/gnu/dts/arm/rk3288-phycore-rdk.dts @@ -265,7 +265,11 @@ disable-wp; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - vmmc-supply = <&vdd_io_sd>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vdd_sd>; vqmmc-supply = <&vdd_io_sd>; status = "okay"; }; Index: sys/gnu/dts/arm/rk3288-phycore-som.dtsi =================================================================== --- sys/gnu/dts/arm/rk3288-phycore-som.dtsi +++ sys/gnu/dts/arm/rk3288-phycore-som.dtsi @@ -336,11 +336,10 @@ regulator-name = "vdd_io_sd"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; + regulator-off-in-suspend; }; }; }; Index: sys/gnu/dts/arm/rk3288-rock2-som.dtsi =================================================================== --- sys/gnu/dts/arm/rk3288-rock2-som.dtsi +++ sys/gnu/dts/arm/rk3288-rock2-som.dtsi @@ -280,6 +280,10 @@ }; }; +&saradc { + vref-supply = <&vcc_18>; +}; + &tsadc { rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ Index: sys/gnu/dts/arm/rk3288-rock2-square.dts =================================================================== --- sys/gnu/dts/arm/rk3288-rock2-square.dts +++ sys/gnu/dts/arm/rk3288-rock2-square.dts @@ -39,6 +39,7 @@ */ /dts-v1/; +#include #include "rk3288-rock2-som.dtsi" / { @@ -49,6 +50,32 @@ stdout-path = "serial2:115200n8"; }; + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + + button-recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <0>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "GPIO Power"; + linux,code = ; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + wakeup-source; + }; + }; + gpio-leds { compatible = "gpio-leds"; @@ -220,6 +247,12 @@ }; }; + keys { + pwr_key: pwr-key { + rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + pmic { pmic_int: pmic-int { rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>; @@ -261,6 +294,10 @@ }; }; +&saradc { + status = "okay"; +}; + &spdif { status = "okay"; }; @@ -284,3 +321,7 @@ &usb_host1 { status = "okay"; }; + +&usb_otg { + status = "okay"; +}; Index: sys/gnu/dts/arm/rk3288-veyron-chromebook.dtsi =================================================================== --- sys/gnu/dts/arm/rk3288-veyron-chromebook.dtsi +++ sys/gnu/dts/arm/rk3288-veyron-chromebook.dtsi @@ -92,7 +92,6 @@ 248 249 250 251 252 253 254 255>; default-brightness-level = <128>; enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>; - backlight-boot-off; pinctrl-names = "default"; pinctrl-0 = <&bl_en>; pwms = <&pwm0 0 1000000 0>; Index: sys/gnu/dts/arm/rk3288-vyasa.dts =================================================================== --- sys/gnu/dts/arm/rk3288-vyasa.dts +++ sys/gnu/dts/arm/rk3288-vyasa.dts @@ -155,6 +155,17 @@ cpu0-supply = <&vdd_cpu>; }; +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; + vmmc-supply = <&vcc_io>; + status = "okay"; +}; + &gmac { assigned-clocks = <&cru SCLK_MAC>; assigned-clock-parents = <&ext_gmac>; Index: sys/gnu/dts/arm/sama5d3.dtsi =================================================================== --- sys/gnu/dts/arm/sama5d3.dtsi +++ sys/gnu/dts/arm/sama5d3.dtsi @@ -861,24 +861,24 @@ uart0 { pinctrl_uart0: uart0-0 { atmel,pins = - ; /* conflicts with ISI_PCK */ + ; /* conflicts with ISI_PCK */ }; }; uart1 { pinctrl_uart1: uart1-0 { atmel,pins = - ; /* conflicts with TWCK0, ISI_HSYNC */ + ; /* conflicts with TWCK0, ISI_HSYNC */ }; }; usart0 { pinctrl_usart0: usart0-0 { atmel,pins = - ; /* PD18 periph A with pullup */ + ; }; pinctrl_usart0_rts_cts: usart0_rts_cts-0 { @@ -891,8 +891,8 @@ usart1 { pinctrl_usart1: usart1-0 { atmel,pins = - ; /* PB29 periph A with pullup */ + ; }; pinctrl_usart1_rts_cts: usart1_rts_cts-0 { @@ -905,8 +905,8 @@ usart2 { pinctrl_usart2: usart2-0 { atmel,pins = - ; /* PE26 periph B with pullup, conflicts NCS0 */ + ; /* conflicts NCS0 */ }; pinctrl_usart2_rts_cts: usart2_rts_cts-0 { @@ -919,8 +919,8 @@ usart3 { pinctrl_usart3: usart3-0 { atmel,pins = - ; /* PE19 periph B with pullup, conflicts with A19 */ + ; /* conflicts with A19 */ }; pinctrl_usart3_rts_cts: usart3_rts_cts-0 { Index: sys/gnu/dts/arm/sama5d34ek.dts =================================================================== --- sys/gnu/dts/arm/sama5d34ek.dts +++ sys/gnu/dts/arm/sama5d34ek.dts @@ -38,7 +38,7 @@ status = "okay"; 24c256@50 { - compatible = "24c256"; + compatible = "atmel,24c256"; reg = <0x50>; pagesize = <64>; }; Index: sys/gnu/dts/arm/sama5d3_uart.dtsi =================================================================== --- sys/gnu/dts/arm/sama5d3_uart.dtsi +++ sys/gnu/dts/arm/sama5d3_uart.dtsi @@ -23,16 +23,16 @@ uart0 { pinctrl_uart0: uart0-0 { atmel,pins = - ; /* PC30 periph A with pullup, conflicts with ISI_PCK */ + ; /* conflicts with ISI_PCK */ }; }; uart1 { pinctrl_uart1: uart1-0 { atmel,pins = - ; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */ + ; /* conflicts with TWCK0, ISI_HSYNC */ }; }; }; Index: sys/gnu/dts/arm/sama5d4.dtsi =================================================================== --- sys/gnu/dts/arm/sama5d4.dtsi +++ sys/gnu/dts/arm/sama5d4.dtsi @@ -1379,7 +1379,7 @@ pinctrl@fc06a000 { #address-cells = <1>; #size-cells = <1>; - compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; + compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus"; ranges = <0xfc068000 0xfc068000 0x100 0xfc06a000 0xfc06a000 0x4000>; /* WARNING: revisit as pin spec has changed */ @@ -1926,8 +1926,8 @@ uart0 { pinctrl_uart0: uart0-0 { atmel,pins = - ; }; }; @@ -1935,8 +1935,8 @@ uart1 { pinctrl_uart1: uart1-0 { atmel,pins = - ; }; }; @@ -1944,8 +1944,8 @@ usart0 { pinctrl_usart0: usart0-0 { atmel,pins = - ; }; pinctrl_usart0_rts: usart0_rts-0 { @@ -1959,8 +1959,8 @@ usart1 { pinctrl_usart1: usart1-0 { atmel,pins = - ; }; pinctrl_usart1_rts: usart1_rts-0 { @@ -1974,8 +1974,8 @@ usart2 { pinctrl_usart2: usart2-0 { atmel,pins = - ; }; pinctrl_usart2_rts: usart2_rts-0 { @@ -1989,8 +1989,8 @@ usart3 { pinctrl_usart3: usart3-0 { atmel,pins = - ; }; }; @@ -1998,8 +1998,8 @@ usart4 { pinctrl_usart4: usart4-0 { atmel,pins = - ; }; pinctrl_usart4_rts: usart4_rts-0 { Index: sys/gnu/dts/arm/samsung_k3pe0e000b.dtsi =================================================================== --- sys/gnu/dts/arm/samsung_k3pe0e000b.dtsi +++ /dev/null @@ -1,68 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Timings and Geometry for Samsung K3PE0E000B memory part - */ - -/ { - samsung_K3PE0E000B: lpddr2 { - compatible = "Samsung,K3PE0E000B","jedec,lpddr2-s4"; - density = <4096>; - io-width = <32>; - - tRPab-min-tck = <3>; - tRCD-min-tck = <3>; - tWR-min-tck = <3>; - tRASmin-min-tck = <3>; - tRRD-min-tck = <2>; - tWTR-min-tck = <2>; - tXP-min-tck = <2>; - tRTP-min-tck = <2>; - tCKE-min-tck = <3>; - tCKESR-min-tck = <3>; - tFAW-min-tck = <8>; - - timings_samsung_K3PE0E000B_533MHz: lpddr2-timings@0 { - compatible = "jedec,lpddr2-timings"; - min-freq = <10000000>; - max-freq = <533333333>; - tRPab = <21000>; - tRCD = <18000>; - tWR = <15000>; - tRAS-min = <42000>; - tRRD = <10000>; - tWTR = <7500>; - tXP = <7500>; - tRTP = <7500>; - tCKESR = <15000>; - tDQSCK-max = <5500>; - tFAW = <50000>; - tZQCS = <90000>; - tZQCL = <360000>; - tZQinit = <1000000>; - tRAS-max-ns = <70000>; - tDQSCK-max-derated = <6000>; - }; - - timings_samsung_K3PE0E000B_266MHz: lpddr2-timings@1 { - compatible = "jedec,lpddr2-timings"; - min-freq = <10000000>; - max-freq = <266666666>; - tRPab = <21000>; - tRCD = <18000>; - tWR = <15000>; - tRAS-min = <42000>; - tRRD = <10000>; - tWTR = <7500>; - tXP = <7500>; - tRTP = <7500>; - tCKESR = <15000>; - tDQSCK-max = <5500>; - tFAW = <50000>; - tZQCS = <90000>; - tZQCL = <360000>; - tZQinit = <1000000>; - tRAS-max-ns = <70000>; - tDQSCK-max-derated = <6000>; - }; - }; -}; Index: sys/gnu/dts/arm/socfpga.dtsi =================================================================== --- sys/gnu/dts/arm/socfpga.dtsi +++ sys/gnu/dts/arm/socfpga.dtsi @@ -831,7 +831,7 @@ timer@fffec600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xfffec600 0x100>; - interrupts = <1 13 0xf04>; + interrupts = <1 13 0xf01>; clocks = <&mpu_periph_clk>; }; Index: sys/gnu/dts/arm/socfpga_arria10_socdk_sdmmc.dts =================================================================== --- sys/gnu/dts/arm/socfpga_arria10_socdk_sdmmc.dts +++ sys/gnu/dts/arm/socfpga_arria10_socdk_sdmmc.dts @@ -20,7 +20,6 @@ &mmc { status = "okay"; - num-slots = <1>; cap-sd-highspeed; broken-cd; bus-width = <4>; Index: sys/gnu/dts/arm/socfpga_arria5.dtsi =================================================================== --- sys/gnu/dts/arm/socfpga_arria5.dtsi +++ sys/gnu/dts/arm/socfpga_arria5.dtsi @@ -30,7 +30,6 @@ }; mmc0: dwmmc0@ff704000 { - num-slots = <1>; broken-cd; bus-width = <4>; cap-mmc-highspeed; Index: sys/gnu/dts/arm/socfpga_cyclone5.dtsi =================================================================== --- sys/gnu/dts/arm/socfpga_cyclone5.dtsi +++ sys/gnu/dts/arm/socfpga_cyclone5.dtsi @@ -31,7 +31,6 @@ }; mmc0: dwmmc0@ff704000 { - num-slots = <1>; broken-cd; bus-width = <4>; cap-mmc-highspeed; Index: sys/gnu/dts/arm/socfpga_vt.dts =================================================================== --- sys/gnu/dts/arm/socfpga_vt.dts +++ sys/gnu/dts/arm/socfpga_vt.dts @@ -42,7 +42,6 @@ }; dwmmc0@ff704000 { - num-slots = <1>; broken-cd; bus-width = <4>; cap-mmc-highspeed; Index: sys/gnu/dts/arm/stih407-b2120.dts =================================================================== --- sys/gnu/dts/arm/stih407-b2120.dts +++ sys/gnu/dts/arm/stih407-b2120.dts @@ -14,17 +14,17 @@ compatible = "st,stih407-b2120", "st,stih407"; chosen { - bootargs = "console=ttyAS0,115200 clk_ignore_unused"; - linux,stdout-path = &sbc_serial0; + bootargs = "clk_ignore_unused"; + stdout-path = &sbc_serial0; }; - memory { + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x80000000>; }; aliases { - ttyAS0 = &sbc_serial0; + serial0 = &sbc_serial0; ethernet0 = ðernet0; }; Index: sys/gnu/dts/arm/stih407-clock.dtsi =================================================================== --- sys/gnu/dts/arm/stih407-clock.dtsi +++ sys/gnu/dts/arm/stih407-clock.dtsi @@ -7,33 +7,27 @@ */ #include / { + /* + * Fixed 30MHz oscillator inputs to SoC + */ + clk_sysin: clk-sysin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <30000000>; + }; + + clk_tmdsout_hdmi: clk-tmdsout-hdmi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + clocks { #address-cells = <1>; #size-cells = <1>; ranges; /* - * Fixed 30MHz oscillator inputs to SoC - */ - clk_sysin: clk-sysin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <30000000>; - }; - - /* - * ARM Peripheral clock for timers - */ - arm_periph_clk: clk-m-a9-periphs { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* * A9 PLL. */ clockgen-a9@92b0000 { @@ -62,32 +56,19 @@ <&clockgen_a9_pll 0>, <&clk_s_c0_flexgen 13>, <&clk_m_a9_ext2f_div2>; - }; - /* - * ARM Peripheral clock for timers - */ - clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - - clocks = <&clk_s_c0_flexgen 13>; - - clock-output-names = "clk-m-a9-ext2f-div2"; - clock-div = <2>; - clock-mult = <1>; - }; + /* + * ARM Peripheral clock for timers + */ + arm_periph_clk: clk-m-a9-periphs { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; - /* - * Bootloader initialized system infrastructure clock for - * serial devices. - */ - clk_ext2f_a9: clockgen-c0@13 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; - clock-output-names = "clk-s-icn-reg-0"; + clocks = <&clk_m_a9>; + clock-div = <2>; + clock-mult = <1>; + }; }; clockgen-a@90ff000 { @@ -204,6 +185,21 @@ , , ; + + /* + * ARM Peripheral clock for timers + */ + clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + + clocks = <&clk_s_c0_flexgen 13>; + + clock-output-names = "clk-m-a9-ext2f-div2"; + + clock-div = <2>; + clock-mult = <1>; + }; }; }; @@ -254,13 +250,7 @@ "clk-s-d2-fs0-ch3"; }; - clk_tmdsout_hdmi: clk-tmdsout-hdmi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clockgen-d2@x9106000 { + clockgen-d2@9106000 { compatible = "st,clkgen-c32"; reg = <0x9106000 0x1000>; Index: sys/gnu/dts/arm/stih407-family.dtsi =================================================================== --- sys/gnu/dts/arm/stih407-family.dtsi +++ sys/gnu/dts/arm/stih407-family.dtsi @@ -92,7 +92,7 @@ clocks = <&arm_periph_clk>; }; - l2: cache-controller { + l2: cache-controller@8762000 { compatible = "arm,pl310-cache"; reg = <0x08762000 0x1000>; arm,data-latency = <3 3 3>; @@ -125,24 +125,28 @@ ranges; compatible = "simple-bus"; - restart { + restart: restart-controller@0 { compatible = "st,stih407-restart"; + reg = <0 0>; st,syscfg = <&syscfg_sbc_reg>; status = "okay"; }; - powerdown: powerdown-controller { + powerdown: powerdown-controller@0 { compatible = "st,stih407-powerdown"; + reg = <0 0>; #reset-cells = <1>; }; - softreset: softreset-controller { + softreset: softreset-controller@0 { compatible = "st,stih407-softreset"; + reg = <0 0>; #reset-cells = <1>; }; - picophyreset: picophyreset-controller { + picophyreset: picophyreset-controller@0 { compatible = "st,stih407-picophyreset"; + reg = <0 0>; #reset-cells = <1>; }; @@ -174,6 +178,13 @@ syscfg_core: core-syscfg@92b0000 { compatible = "st,stih407-core-syscfg", "syscon"; reg = <0x92b0000 0x1000>; + + sti_sasg_codec: sti-sasg-codec { + compatible = "st,stih407-sas-codec"; + #sound-dai-cells = <1>; + status = "disabled"; + st,syscfg = <&syscfg_core>; + }; }; syscfg_lpm: lpm-syscfg@94b5100 { @@ -181,8 +192,9 @@ reg = <0x94b5100 0x1000>; }; - irq-syscfg { + irq-syscfg@0 { compatible = "st,stih407-irq-syscfg"; + reg = <0 0>; st,syscfg = <&syscfg_core>; st,irq-device = , ; @@ -380,8 +392,9 @@ status = "disabled"; }; - usb2_picophy0: phy1 { + usb2_picophy0: phy1@0 { compatible = "st,stih407-usb2-phy"; + reg = <0 0>; #phy-cells = <0>; st,syscfg = <&syscfg_core 0x100 0xf4>; resets = <&softreset STIH407_PICOPHY_SOFTRESET>, @@ -389,12 +402,13 @@ reset-names = "global", "port"; }; - miphy28lp_phy: miphy28lp@9b22000 { + miphy28lp_phy: miphy28lp@0 { compatible = "st,miphy28lp-phy"; st,syscfg = <&syscfg_core>; #address-cells = <1>; #size-cells = <1>; ranges; + reg = <0 0>; phy_port0: port@9b22000 { reg = <0x9b22000 0xff>, @@ -805,6 +819,7 @@ st231_gp0: st231-gp0@0 { compatible = "st,st231-rproc"; + reg = <0 0>; memory-region = <&gp0_reserved>; resets = <&softreset STIH407_ST231_GP0_SOFTRESET>; reset-names = "sw_reset"; @@ -818,6 +833,7 @@ st231_delta: st231-delta@0 { compatible = "st,st231-rproc"; + reg = <0 0>; memory-region = <&delta_reserved>; resets = <&softreset STIH407_ST231_DMU_SOFTRESET>; reset-names = "sw_reset"; @@ -885,13 +901,6 @@ status = "disabled"; }; - sti_sasg_codec: sti-sasg-codec { - compatible = "st,stih407-sas-codec"; - #sound-dai-cells = <1>; - status = "disabled"; - st,syscfg = <&syscfg_core>; - }; - sti_uni_player0: sti-uni-player@8d80000 { compatible = "st,stih407-uni-player-hdmi"; #sound-dai-cells = <0>; @@ -980,8 +989,9 @@ status = "disabled"; }; - delta0 { + delta0@0 { compatible = "st,st-delta"; + reg = <0 0>; clock-names = "delta", "delta-st231", "delta-flash-promip"; Index: sys/gnu/dts/arm/stih407-pinctrl.dtsi =================================================================== --- sys/gnu/dts/arm/stih407-pinctrl.dtsi +++ sys/gnu/dts/arm/stih407-pinctrl.dtsi @@ -45,7 +45,7 @@ }; soc { - pin-controller-sbc { + pin-controller-sbc@961f080 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stih407-sbc-pinctrl"; @@ -369,7 +369,7 @@ }; }; - pin-controller-front0 { + pin-controller-front0@920f080 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stih407-front-pinctrl"; @@ -929,7 +929,7 @@ }; }; - pin-controller-front1 { + pin-controller-front1@921f080 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stih407-front-pinctrl"; @@ -962,7 +962,7 @@ }; }; - pin-controller-rear { + pin-controller-rear@922f080 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stih407-rear-pinctrl"; @@ -1157,7 +1157,7 @@ }; }; - pin-controller-flash { + pin-controller-flash@923f080 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stih407-flash-pinctrl"; Index: sys/gnu/dts/arm/stih407.dtsi =================================================================== --- sys/gnu/dts/arm/stih407.dtsi +++ sys/gnu/dts/arm/stih407.dtsi @@ -11,11 +11,11 @@ #include / { soc { - sti-display-subsystem { + sti-display-subsystem@0 { compatible = "st,sti-display-subsystem"; #address-cells = <1>; #size-cells = <1>; - + reg = <0 0>; assigned-clocks = <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>, <&clk_s_c0_pll1 0>, @@ -107,6 +107,7 @@ compatible = "st,stih407-hdmi"; reg = <0x8d04000 0x1000>; reg-names = "hdmi-reg"; + #sound-dai-cells = <0>; interrupts = ; interrupt-names = "irq"; clock-names = "pix", Index: sys/gnu/dts/arm/stih410-b2120.dts =================================================================== --- sys/gnu/dts/arm/stih410-b2120.dts +++ sys/gnu/dts/arm/stih410-b2120.dts @@ -14,17 +14,17 @@ compatible = "st,stih410-b2120", "st,stih410"; chosen { - bootargs = "console=ttyAS0,115200 clk_ignore_unused"; - linux,stdout-path = &sbc_serial0; + bootargs = "clk_ignore_unused"; + stdout-path = &sbc_serial0; }; - memory { + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x80000000>; }; aliases { - ttyAS0 = &sbc_serial0; + serial0 = &sbc_serial0; ethernet0 = ðernet0; }; @@ -37,11 +37,11 @@ sd-uhs-ddr50; }; - usb2_picophy1: phy2 { + usb2_picophy1: phy2@0 { status = "okay"; }; - usb2_picophy2: phy3 { + usb2_picophy2: phy3@0 { status = "okay"; }; @@ -61,7 +61,7 @@ status = "okay"; }; - sti-display-subsystem { + sti-display-subsystem@0 { sti-hda@8d02000 { status = "okay"; }; Index: sys/gnu/dts/arm/stih410-b2260.dts =================================================================== --- sys/gnu/dts/arm/stih410-b2260.dts +++ sys/gnu/dts/arm/stih410-b2260.dts @@ -15,50 +15,68 @@ compatible = "st,stih410-b2260", "st,stih410"; chosen { - bootargs = "console=ttyAS1,115200 clk_ignore_unused"; - linux,stdout-path = &uart1; + bootargs = "clk_ignore_unused"; + stdout-path = &uart1; }; - memory { + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x40000000>; }; aliases { - ttyAS1 = &uart1; + serial1 = &uart1; ethernet0 = ðernet0; }; - soc { + leds { + compatible = "gpio-leds"; + user_green_1 { + label = "User_green_1"; + gpios = <&pio1 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; - leds { - compatible = "gpio-leds"; - user_green_1 { - label = "User_green_1"; - gpios = <&pio1 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; + user_green_2 { + label = "User_green_2"; + gpios = <&pio4 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; - user_green_2 { - label = "User_green_2"; - gpios = <&pio4 1 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; + user_green_3 { + label = "User_green_3"; + gpios = <&pio2 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + user_green_4 { + label = "User_green_4"; + gpios = <&pio2 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; - user_green_3 { - label = "User_green_3"; - gpios = <&pio2 1 GPIO_ACTIVE_LOW>; - default-state = "off"; + sound: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "STI-B2260"; + status = "okay"; + + simple-audio-card,dai-link0 { + /* DAC */ + format = "i2s"; + mclk-fs = <128>; + cpu { + sound-dai = <&sti_uni_player0>; }; - user_green_4 { - label = "User_green_4"; - gpios = <&pio2 5 GPIO_ACTIVE_LOW>; - default-state = "off"; + codec { + sound-dai = <&sti_hdmi>; }; }; + }; + soc { /* Low speed expansion connector */ uart0: serial@9830000 { label = "LS-UART0"; @@ -128,11 +146,11 @@ status = "okay"; }; - usb2_picophy1: phy2 { + usb2_picophy1: phy2@0 { status = "okay"; }; - usb2_picophy2: phy3 { + usb2_picophy2: phy3@0 { status = "okay"; }; @@ -182,26 +200,7 @@ status = "okay"; }; - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "STI-B2260"; - status = "okay"; - - simple-audio-card,dai-link@0 { - /* DAC */ - format = "i2s"; - mclk-fs = <128>; - cpu { - sound-dai = <&sti_uni_player0>; - }; - - codec { - sound-dai = <&sti_hdmi>; - }; - }; - }; - - miphy28lp_phy: miphy28lp@9b22000 { + miphy28lp_phy: miphy28lp@0 { phy_port1: port@9b2a000 { st,osc-force-ext; Index: sys/gnu/dts/arm/stih410-clock.dtsi =================================================================== --- sys/gnu/dts/arm/stih410-clock.dtsi +++ sys/gnu/dts/arm/stih410-clock.dtsi @@ -7,6 +7,22 @@ */ #include / { + /* + * Fixed 30MHz oscillator inputs to SoC + */ + clk_sysin: clk-sysin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <30000000>; + clock-output-names = "CLK_SYSIN"; + }; + + clk_tmdsout_hdmi: clk-tmdsout-hdmi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + clocks { #address-cells = <1>; #size-cells = <1>; @@ -15,27 +31,6 @@ compatible = "st,stih410-clk", "simple-bus"; /* - * Fixed 30MHz oscillator inputs to SoC - */ - clk_sysin: clk-sysin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <30000000>; - clock-output-names = "CLK_SYSIN"; - }; - - /* - * ARM Peripheral clock for timers - */ - arm_periph_clk: clk-m-a9-periphs { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* * A9 PLL. */ clockgen-a9@92b0000 { @@ -64,32 +59,16 @@ <&clockgen_a9_pll 0>, <&clk_s_c0_flexgen 13>, <&clk_m_a9_ext2f_div2>; - }; - - /* - * ARM Peripheral clock for timers - */ - clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - - clocks = <&clk_s_c0_flexgen 13>; - - clock-output-names = "clk-m-a9-ext2f-div2"; - - clock-div = <2>; - clock-mult = <1>; - }; - - /* - * Bootloader initialized system infrastructure clock for - * serial devices. - */ - clk_ext2f_a9: clockgen-c0@13 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; - clock-output-names = "clk-s-icn-reg-0"; + /* + * ARM Peripheral clock for timers + */ + arm_periph_clk: clk-m-a9-periphs { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&clk_m_a9>; + clock-div = <2>; + clock-mult = <1>; + }; }; clockgen-a@90ff000 { @@ -214,6 +193,21 @@ , , ; + + /* + * ARM Peripheral clock for timers + */ + clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + + clocks = <&clk_s_c0_flexgen 13>; + + clock-output-names = "clk-m-a9-ext2f-div2"; + + clock-div = <2>; + clock-mult = <1>; + }; }; }; @@ -266,13 +260,7 @@ "clk-s-d2-fs0-ch3"; }; - clk_tmdsout_hdmi: clk-tmdsout-hdmi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clockgen-d2@x9106000 { + clockgen-d2@9106000 { compatible = "st,clkgen-c32"; reg = <0x9106000 0x1000>; Index: sys/gnu/dts/arm/stih410-pinctrl.dtsi =================================================================== --- sys/gnu/dts/arm/stih410-pinctrl.dtsi +++ sys/gnu/dts/arm/stih410-pinctrl.dtsi @@ -10,7 +10,7 @@ / { soc { - pin-controller-rear { + pin-controller-rear@922f080 { usb0 { pinctrl_usb0: usb2-0 { Index: sys/gnu/dts/arm/stih410.dtsi =================================================================== --- sys/gnu/dts/arm/stih410.dtsi +++ sys/gnu/dts/arm/stih410.dtsi @@ -16,8 +16,9 @@ }; soc { - usb2_picophy1: phy2 { + usb2_picophy1: phy2@0 { compatible = "st,stih407-usb2-phy"; + reg = <0 0>; #phy-cells = <0>; st,syscfg = <&syscfg_core 0xf8 0xf4>; resets = <&softreset STIH407_PICOPHY_SOFTRESET>, @@ -27,8 +28,9 @@ status = "disabled"; }; - usb2_picophy2: phy3 { + usb2_picophy2: phy3@0 { compatible = "st,stih407-usb2-phy"; + reg = <0 0>; #phy-cells = <0>; st,syscfg = <&syscfg_core 0xfc 0xf4>; resets = <&softreset STIH407_PICOPHY_SOFTRESET>, @@ -102,11 +104,12 @@ status = "disabled"; }; - sti-display-subsystem { + sti-display-subsystem@0 { compatible = "st,sti-display-subsystem"; #address-cells = <1>; #size-cells = <1>; + reg = <0 0>; assigned-clocks = <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>, <&clk_s_c0_pll1 0>, @@ -198,6 +201,7 @@ compatible = "st,stih407-hdmi"; reg = <0x8d04000 0x1000>; reg-names = "hdmi-reg"; + #sound-dai-cells = <0>; interrupts = ; interrupt-names = "irq"; clock-names = "pix", @@ -235,7 +239,7 @@ <&clk_s_d2_quadfs 1>; }; - sti-hqvdp@9c000000 { + sti-hqvdp@9c00000 { compatible = "st,stih407-hqvdp"; reg = <0x9C00000 0x100000>; clock-names = "hqvdp", "pix_main"; @@ -273,7 +277,7 @@ interrupts = ; }; - delta0 { + delta0@0 { compatible = "st,st-delta"; clock-names = "delta", "delta-st231", Index: sys/gnu/dts/arm/stih418-b2199.dts =================================================================== --- sys/gnu/dts/arm/stih418-b2199.dts +++ sys/gnu/dts/arm/stih418-b2199.dts @@ -14,38 +14,38 @@ compatible = "st,stih418-b2199", "st,stih418"; chosen { - bootargs = "console=ttyAS0,115200 clk_ignore_unused"; - linux,stdout-path = &sbc_serial0; + bootargs = "clk_ignore_unused"; + stdout-path = &sbc_serial0; }; - memory { + memory@40000000 { device_type = "memory"; reg = <0x40000000 0xc0000000>; }; aliases { - ttyAS0 = &sbc_serial0; + serial0 = &sbc_serial0; ethernet0 = ðernet0; }; + leds { + compatible = "gpio-leds"; + red { + label = "Front Panel LED"; + gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + green { + gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + soc { sbc_serial0: serial@9530000 { status = "okay"; }; - leds { - compatible = "gpio-leds"; - red { - label = "Front Panel LED"; - gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - green { - gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - i2c@9842000 { status = "okay"; }; @@ -88,7 +88,7 @@ non-removable; }; - miphy28lp_phy: miphy28lp@9b22000 { + miphy28lp_phy: miphy28lp@0 { phy_port0: port@9b22000 { st,osc-rdy; Index: sys/gnu/dts/arm/stih418-clock.dtsi =================================================================== --- sys/gnu/dts/arm/stih418-clock.dtsi +++ sys/gnu/dts/arm/stih418-clock.dtsi @@ -7,6 +7,22 @@ */ #include / { + /* + * Fixed 30MHz oscillator inputs to SoC + */ + clk_sysin: clk-sysin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <30000000>; + clock-output-names = "CLK_SYSIN"; + }; + + clk_tmdsout_hdmi: clk-tmdsout-hdmi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + clocks { #address-cells = <1>; #size-cells = <1>; @@ -15,27 +31,6 @@ compatible = "st,stih418-clk", "simple-bus"; /* - * Fixed 30MHz oscillator inputs to SoC - */ - clk_sysin: clk-sysin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <30000000>; - clock-output-names = "CLK_SYSIN"; - }; - - /* - * ARM Peripheral clock for timers - */ - arm_periph_clk: clk-m-a9-periphs { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* * A9 PLL. */ clockgen-a9@92b0000 { @@ -64,32 +59,17 @@ <&clockgen_a9_pll 0>, <&clk_s_c0_flexgen 13>, <&clk_m_a9_ext2f_div2>; - }; - - /* - * ARM Peripheral clock for timers - */ - clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - - clocks = <&clk_s_c0_flexgen 13>; - clock-output-names = "clk-m-a9-ext2f-div2"; - - clock-div = <2>; - clock-mult = <1>; - }; - - /* - * Bootloader initialized system infrastructure clock for - * serial devices. - */ - clk_ext2f_a9: clockgen-c0@13 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; - clock-output-names = "clk-s-icn-reg-0"; + /* + * ARM Peripheral clock for timers + */ + arm_periph_clk: clk-m-a9-periphs { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&clk_m_a9>; + clock-div = <2>; + clock-mult = <1>; + }; }; clockgen-a@90ff000 { @@ -207,6 +187,21 @@ "clk-proc-mixer", "clk-proc-sc", "clk-avsp-hevc"; + + /* + * ARM Peripheral clock for timers + */ + clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + + clocks = <&clk_s_c0_flexgen 13>; + + clock-output-names = "clk-m-a9-ext2f-div2"; + + clock-div = <2>; + clock-mult = <1>; + }; }; }; @@ -259,13 +254,7 @@ "clk-s-d2-fs0-ch3"; }; - clk_tmdsout_hdmi: clk-tmdsout-hdmi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clockgen-d2@x9106000 { + clockgen-d2@9106000 { compatible = "st,clkgen-c32"; reg = <0x9106000 0x1000>; Index: sys/gnu/dts/arm/stih418.dtsi =================================================================== --- sys/gnu/dts/arm/stih418.dtsi +++ sys/gnu/dts/arm/stih418.dtsi @@ -30,8 +30,9 @@ }; soc { - usb2_picophy1: phy2 { + usb2_picophy1: phy2@0 { compatible = "st,stih407-usb2-phy"; + reg = <0 0>; #phy-cells = <0>; st,syscfg = <&syscfg_core 0xf8 0xf4>; resets = <&softreset STIH407_PICOPHY_SOFTRESET>, @@ -39,8 +40,9 @@ reset-names = "global", "port"; }; - usb2_picophy2: phy3 { + usb2_picophy2: phy3@0 { compatible = "st,stih407-usb2-phy"; + reg = <0 0>; #phy-cells = <0>; st,syscfg = <&syscfg_core 0xfc 0xf4>; resets = <&softreset STIH407_PICOPHY_SOFTRESET>, Index: sys/gnu/dts/arm/stihxxx-b2120.dtsi =================================================================== --- sys/gnu/dts/arm/stihxxx-b2120.dtsi +++ sys/gnu/dts/arm/stihxxx-b2120.dtsi @@ -10,23 +10,69 @@ #include #include / { - soc { - sbc_serial0: serial@9530000 { - status = "okay"; + leds { + compatible = "gpio-leds"; + red { + label = "Front Panel LED"; + gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + green { + gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + sound: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "STI-B2120"; + status = "okay"; + + simple-audio-card,dai-link0 { + /* HDMI */ + format = "i2s"; + mclk-fs = <128>; + cpu { + sound-dai = <&sti_uni_player0>; + }; + + codec { + sound-dai = <&sti_hdmi>; + }; + }; + + simple-audio-card,dai-link1 { + /* DAC */ + format = "i2s"; + mclk-fs = <256>; + frame-inversion = <1>; + cpu { + sound-dai = <&sti_uni_player2>; + }; + + codec { + sound-dai = <&sti_sasg_codec 1>; + }; }; - leds { - compatible = "gpio-leds"; - red { - label = "Front Panel LED"; - gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; + simple-audio-card,dai-link2 { + /* SPDIF */ + format = "left_j"; + mclk-fs = <128>; + cpu { + sound-dai = <&sti_uni_player3>; }; - green { - gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; + + codec { + sound-dai = <&sti_sasg_codec 0>; }; }; + }; + + soc { + sbc_serial0: serial@9530000 { + status = "okay"; + }; pwm0: pwm@9810000 { status = "okay"; @@ -80,7 +126,7 @@ st,i2c-min-sda-pulse-width-us = <5>; }; - miphy28lp_phy: miphy28lp@9b22000 { + miphy28lp_phy: miphy28lp@0 { phy_port0: port@9b22000 { st,osc-rdy; @@ -126,7 +172,7 @@ clock-names = "c8sectpfe"; /* tsin0 is TSA on NIMA */ - tsin0: port@0 { + tsin0: port { tsin-num = <0>; serial-not-parallel; i2c-bus = <&ssc2>; @@ -147,53 +193,11 @@ status = "okay"; }; - sti_sasg_codec: sti-sasg-codec { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif_out>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "STI-B2120"; - status = "okay"; - - simple-audio-card,dai-link@0 { - /* HDMI */ - format = "i2s"; - mclk-fs = <128>; - cpu { - sound-dai = <&sti_uni_player0>; - }; - - codec { - sound-dai = <&sti_hdmi>; - }; - }; - simple-audio-card,dai-link@1 { - /* DAC */ - format = "i2s"; - mclk-fs = <256>; - frame-inversion = <1>; - cpu { - sound-dai = <&sti_uni_player2>; - }; - - codec { - sound-dai = <&sti_sasg_codec 1>; - }; - }; - simple-audio-card,dai-link@2 { - /* SPDIF */ - format = "left_j"; - mclk-fs = <128>; - cpu { - sound-dai = <&sti_uni_player3>; - }; - - codec { - sound-dai = <&sti_sasg_codec 0>; - }; + syscfg_core: core-syscfg@92b0000 { + sti_sasg_codec: sti-sasg-codec { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif_out>; }; }; }; Index: sys/gnu/dts/arm/stm32429i-eval.dts =================================================================== --- sys/gnu/dts/arm/stm32429i-eval.dts +++ sys/gnu/dts/arm/stm32429i-eval.dts @@ -144,6 +144,13 @@ }; }; }; + + mmc_vcard: mmc_vcard { + compatible = "regulator-fixed"; + regulator-name = "mmc_vcard"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; &adc { @@ -254,6 +261,18 @@ status = "okay"; }; +&sdio { + status = "okay"; + vmmc-supply = <&mmc_vcard>; + cd-gpios = <&stmpegpio 15 GPIO_ACTIVE_HIGH>; + cd-inverted; + pinctrl-names = "default", "opendrain"; + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_pins_od>; + bus-width = <4>; + max-frequency = <12500000>; +}; + &timers1 { status = "okay"; Index: sys/gnu/dts/arm/stm32746g-eval.dts =================================================================== --- sys/gnu/dts/arm/stm32746g-eval.dts +++ sys/gnu/dts/arm/stm32746g-eval.dts @@ -42,6 +42,7 @@ /dts-v1/; #include "stm32f746.dtsi" +#include "stm32f746-pinctrl.dtsi" #include / { @@ -90,6 +91,13 @@ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>; clock-names = "main_clk"; }; + + mmc_vcard: mmc_vcard { + compatible = "regulator-fixed"; + regulator-name = "mmc_vcard"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; &clk_hse { @@ -112,6 +120,16 @@ status = "okay"; }; +&sdio1 { + status = "okay"; + vmmc-supply = <&mmc_vcard>; + broken-cd; + pinctrl-names = "default", "opendrain"; + pinctrl-0 = <&sdio_pins_a>; + pinctrl-1 = <&sdio_pins_od_a>; + bus-width = <4>; +}; + &usart1 { pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; @@ -119,7 +137,7 @@ }; &usbotg_hs { - dr_mode = "host"; + dr_mode = "otg"; phys = <&usbotg_hs_phy>; phy-names = "usb2-phy"; pinctrl-0 = <&usbotg_hs_pins_a>; Index: sys/gnu/dts/arm/stm32f4-pinctrl.dtsi =================================================================== --- sys/gnu/dts/arm/stm32f4-pinctrl.dtsi +++ sys/gnu/dts/arm/stm32f4-pinctrl.dtsi @@ -338,6 +338,37 @@ slew-rate = <3>; }; }; + + sdio_pins: sdio_pins@0 { + pins { + pinmux = , /* SDIO_D0 */ + , /* SDIO_D1 */ + , /* SDIO_D2 */ + , /* SDIO_D3 */ + , /* SDIO_CK */ + ; /* SDIO_CMD */ + drive-push-pull; + slew-rate = <2>; + }; + }; + + sdio_pins_od: sdio_pins_od@0 { + pins1 { + pinmux = , /* SDIO_D0 */ + , /* SDIO_D1 */ + , /* SDIO_D2 */ + , /* SDIO_D3 */ + ; /* SDIO_CK */ + drive-push-pull; + slew-rate = <2>; + }; + + pins2 { + pinmux = ; /* SDIO_CMD */ + drive-open-drain; + slew-rate = <2>; + }; + }; }; }; }; Index: sys/gnu/dts/arm/stm32f429.dtsi =================================================================== --- sys/gnu/dts/arm/stm32f429.dtsi +++ sys/gnu/dts/arm/stm32f429.dtsi @@ -511,6 +511,17 @@ }; }; + sdio: sdio@40012c00 { + compatible = "arm,pl180", "arm,primecell"; + arm,primecell-periphid = <0x00880180>; + reg = <0x40012c00 0x400>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>; + clock-names = "apb_pclk"; + interrupts = <49>; + max-frequency = <48000000>; + status = "disabled"; + }; + syscfg: system-config@40013800 { compatible = "syscon"; reg = <0x40013800 0x400>; Index: sys/gnu/dts/arm/stm32f469-disco.dts =================================================================== --- sys/gnu/dts/arm/stm32f469-disco.dts +++ sys/gnu/dts/arm/stm32f469-disco.dts @@ -48,6 +48,8 @@ /dts-v1/; #include "stm32f429.dtsi" #include "stm32f469-pinctrl.dtsi" +#include +#include / { model = "STMicroelectronics STM32F469i-DISCO board"; @@ -66,10 +68,46 @@ serial0 = &usart3; }; + mmc_vcard: mmc_vcard { + compatible = "regulator-fixed"; + regulator-name = "mmc_vcard"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + soc { dma-ranges = <0xc0000000 0x0 0x10000000>; }; + leds { + compatible = "gpio-leds"; + green { + gpios = <&gpiog 6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + orange { + gpios = <&gpiod 4 GPIO_ACTIVE_LOW>; + }; + red { + gpios = <&gpiod 5 GPIO_ACTIVE_LOW>; + }; + blue { + gpios = <&gpiok 3 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + button@0 { + label = "User"; + linux,code = ; + gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; + }; + }; + /* This turns on vbus for otg for host mode (dwc2) */ vcc5v_otg: vcc5v-otg-regulator { compatible = "regulator-fixed"; @@ -120,6 +158,18 @@ }; }; +&sdio { + status = "okay"; + vmmc-supply = <&mmc_vcard>; + cd-gpios = <&gpiog 2 GPIO_ACTIVE_HIGH>; + cd-inverted; + broken-cd; + pinctrl-names = "default", "opendrain"; + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_pins_od>; + bus-width = <4>; +}; + &usart3 { pinctrl-0 = <&usart3_pins_a>; pinctrl-names = "default"; Index: sys/gnu/dts/arm/stm32f7-pinctrl.dtsi =================================================================== --- /dev/null +++ sys/gnu/dts/arm/stm32f7-pinctrl.dtsi @@ -0,0 +1,289 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +#include +#include + +/ { + soc { + pinctrl: pin-controller { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40020000 0x3000>; + interrupt-parent = <&exti>; + st,syscfg = <&syscfg 0x8>; + pins-are-numbered; + + gpioa: gpio@40020000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>; + st,bank-name = "GPIOA"; + }; + + gpiob: gpio@40020400 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x400 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>; + st,bank-name = "GPIOB"; + }; + + gpioc: gpio@40020800 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x800 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>; + st,bank-name = "GPIOC"; + }; + + gpiod: gpio@40020c00 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xc00 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>; + st,bank-name = "GPIOD"; + }; + + gpioe: gpio@40021000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1000 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>; + st,bank-name = "GPIOE"; + }; + + gpiof: gpio@40021400 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1400 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>; + st,bank-name = "GPIOF"; + }; + + gpiog: gpio@40021800 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1800 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>; + st,bank-name = "GPIOG"; + }; + + gpioh: gpio@40021c00 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1c00 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>; + st,bank-name = "GPIOH"; + }; + + gpioi: gpio@40022000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2000 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>; + st,bank-name = "GPIOI"; + }; + + gpioj: gpio@40022400 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2400 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>; + st,bank-name = "GPIOJ"; + }; + + gpiok: gpio@40022800 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2800 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>; + st,bank-name = "GPIOK"; + }; + + cec_pins_a: cec@0 { + pins { + pinmux = ; /* HDMI CEC */ + slew-rate = <0>; + drive-open-drain; + bias-disable; + }; + }; + + usart1_pins_a: usart1@0 { + pins1 { + pinmux = ; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART1_RX */ + bias-disable; + }; + }; + + usart1_pins_b: usart1@1 { + pins1 { + pinmux = ; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART1_RX */ + bias-disable; + }; + }; + + i2c1_pins_b: i2c1@0 { + pins { + pinmux = , /* I2C1 SDA */ + ; /* I2C1 SCL */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + usbotg_hs_pins_a: usbotg-hs@0 { + pins { + pinmux = , /* OTG_HS_ULPI_NXT */ + , /* OTG_HS_ULPI_DIR */ + , /* OTG_HS_ULPI_STP */ + , /* OTG_HS_ULPI_CK */ + , /* OTG_HS_ULPI_D0 */ + , /* OTG_HS_ULPI_D1 */ + , /* OTG_HS_ULPI_D2 */ + , /* OTG_HS_ULPI_D3 */ + , /* OTG_HS_ULPI_D4 */ + , /* OTG_HS_ULPI_D5 */ + , /* OTG_HS_ULPI_D6 */ + ; /* OTG_HS_ULPI_D7 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + usbotg_hs_pins_b: usbotg-hs@1 { + pins { + pinmux = , /* OTG_HS_ULPI_NXT */ + , /* OTG_HS_ULPI_DIR */ + , /* OTG_HS_ULPI_STP */ + , /* OTG_HS_ULPI_CK */ + , /* OTG_HS_ULPI_D0 */ + , /* OTG_HS_ULPI_D1 */ + , /* OTG_HS_ULPI_D2 */ + , /* OTG_HS_ULPI_D3 */ + , /* OTG_HS_ULPI_D4 */ + , /* OTG_HS_ULPI_D5 */ + , /* OTG_HS_ULPI_D6 */ + ; /* OTG_HS_ULPI_D7 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + usbotg_fs_pins_a: usbotg-fs@0 { + pins { + pinmux = , /* OTG_FS_ID */ + , /* OTG_FS_DM */ + ; /* OTG_FS_DP */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + sdio_pins_a: sdio_pins_a@0 { + pins { + pinmux = , /* SDMMC1 D0 */ + , /* SDMMC1 D1 */ + , /* SDMMC1 D2 */ + , /* SDMMC1 D3 */ + , /* SDMMC1 CLK */ + ; /* SDMMC1 CMD */ + drive-push-pull; + slew-rate = <2>; + }; + }; + + sdio_pins_od_a: sdio_pins_od_a@0 { + pins1 { + pinmux = , /* SDMMC1 D0 */ + , /* SDMMC1 D1 */ + , /* SDMMC1 D2 */ + , /* SDMMC1 D3 */ + ; /* SDMMC1 CLK */ + drive-push-pull; + slew-rate = <2>; + }; + + pins2 { + pinmux = ; /* SDMMC1 CMD */ + drive-open-drain; + slew-rate = <2>; + }; + }; + + sdio_pins_b: sdio_pins_b@0 { + pins { + pinmux = , /* SDMMC2 D0 */ + , /* SDMMC2 D1 */ + , /* SDMMC2 D2 */ + , /* SDMMC2 D3 */ + , /* SDMMC2 CLK */ + ; /* SDMMC2 CMD */ + drive-push-pull; + slew-rate = <2>; + }; + }; + + sdio_pins_od_b: sdio_pins_od_b@0 { + pins1 { + pinmux = , /* SDMMC2 D0 */ + , /* SDMMC2 D1 */ + , /* SDMMC2 D2 */ + , /* SDMMC2 D3 */ + ; /* SDMMC2 CLK */ + drive-push-pull; + slew-rate = <2>; + }; + + pins2 { + pinmux = ; /* SDMMC2 CMD */ + drive-open-drain; + slew-rate = <2>; + }; + }; + }; + }; +}; Index: sys/gnu/dts/arm/stm32f746-disco.dts =================================================================== --- sys/gnu/dts/arm/stm32f746-disco.dts +++ sys/gnu/dts/arm/stm32f746-disco.dts @@ -42,7 +42,9 @@ /dts-v1/; #include "stm32f746.dtsi" +#include "stm32f746-pinctrl.dtsi" #include +#include / { model = "STMicroelectronics STM32F746-DISCO board"; @@ -75,12 +77,30 @@ regulator-name = "vcc5_host1"; regulator-always-on; }; + + mmc_vcard: mmc_vcard { + compatible = "regulator-fixed"; + regulator-name = "mmc_vcard"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; &clk_hse { clock-frequency = <25000000>; }; +&sdio1 { + status = "okay"; + vmmc-supply = <&mmc_vcard>; + cd-gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>; + cd-inverted; + pinctrl-names = "default", "opendrain"; + pinctrl-0 = <&sdio_pins_a>; + pinctrl-1 = <&sdio_pins_od_a>; + bus-width = <4>; +}; + &usart1 { pinctrl-0 = <&usart1_pins_b>; pinctrl-names = "default"; Index: sys/gnu/dts/arm/stm32f746-pinctrl.dtsi =================================================================== --- /dev/null +++ sys/gnu/dts/arm/stm32f746-pinctrl.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +#include "stm32f7-pinctrl.dtsi" + +&pinctrl{ + compatible = "st,stm32f746-pinctrl"; +}; Index: sys/gnu/dts/arm/stm32f746.dtsi =================================================================== --- sys/gnu/dts/arm/stm32f746.dtsi +++ sys/gnu/dts/arm/stm32f746.dtsi @@ -42,7 +42,6 @@ #include "skeleton.dtsi" #include "armv7-m.dtsi" -#include #include #include @@ -429,6 +428,28 @@ status = "disabled"; }; + sdio2: sdio2@40011c00 { + compatible = "arm,pl180", "arm,primecell"; + arm,primecell-periphid = <0x00880180>; + reg = <0x40011c00 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>; + clock-names = "apb_pclk"; + interrupts = <103>; + max-frequency = <48000000>; + status = "disabled"; + }; + + sdio1: sdio1@40012c00 { + compatible = "arm,pl180", "arm,primecell"; + arm,primecell-periphid = <0x00880180>; + reg = <0x40012c00 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>; + clock-names = "apb_pclk"; + interrupts = <49>; + max-frequency = <48000000>; + status = "disabled"; + }; + syscfg: system-config@40013800 { compatible = "syscon"; reg = <0x40013800 0x400>; @@ -498,222 +519,6 @@ reg = <0x40007000 0x400>; }; - pin-controller { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stm32f746-pinctrl"; - ranges = <0 0x40020000 0x3000>; - interrupt-parent = <&exti>; - st,syscfg = <&syscfg 0x8>; - pins-are-numbered; - - gpioa: gpio@40020000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>; - st,bank-name = "GPIOA"; - }; - - gpiob: gpio@40020400 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x400 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>; - st,bank-name = "GPIOB"; - }; - - gpioc: gpio@40020800 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x800 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>; - st,bank-name = "GPIOC"; - }; - - gpiod: gpio@40020c00 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0xc00 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>; - st,bank-name = "GPIOD"; - }; - - gpioe: gpio@40021000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>; - st,bank-name = "GPIOE"; - }; - - gpiof: gpio@40021400 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1400 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>; - st,bank-name = "GPIOF"; - }; - - gpiog: gpio@40021800 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1800 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>; - st,bank-name = "GPIOG"; - }; - - gpioh: gpio@40021c00 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1c00 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>; - st,bank-name = "GPIOH"; - }; - - gpioi: gpio@40022000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>; - st,bank-name = "GPIOI"; - }; - - gpioj: gpio@40022400 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2400 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>; - st,bank-name = "GPIOJ"; - }; - - gpiok: gpio@40022800 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2800 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>; - st,bank-name = "GPIOK"; - }; - - cec_pins_a: cec@0 { - pins { - pinmux = ; /* HDMI CEC */ - slew-rate = <0>; - drive-open-drain; - bias-disable; - }; - }; - - usart1_pins_a: usart1@0 { - pins1 { - pinmux = ; /* USART1_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* USART1_RX */ - bias-disable; - }; - }; - - usart1_pins_b: usart1@1 { - pins1 { - pinmux = ; /* USART1_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* USART1_RX */ - bias-disable; - }; - }; - - i2c1_pins_b: i2c1@0 { - pins { - pinmux = , /* I2C1 SDA */ - ; /* I2C1 SCL */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - usbotg_hs_pins_a: usbotg-hs@0 { - pins { - pinmux = , /* OTG_HS_ULPI_NXT */ - , /* OTG_HS_ULPI_DIR */ - , /* OTG_HS_ULPI_STP */ - , /* OTG_HS_ULPI_CK */ - , /* OTG_HS_ULPI_D0 */ - , /* OTG_HS_ULPI_D1 */ - , /* OTG_HS_ULPI_D2 */ - , /* OTG_HS_ULPI_D3 */ - , /* OTG_HS_ULPI_D4 */ - , /* OTG_HS_ULPI_D5 */ - , /* OTG_HS_ULPI_D6 */ - ; /* OTG_HS_ULPI_D7 */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - - usbotg_hs_pins_b: usbotg-hs@1 { - pins { - pinmux = , /* OTG_HS_ULPI_NXT */ - , /* OTG_HS_ULPI_DIR */ - , /* OTG_HS_ULPI_STP */ - , /* OTG_HS_ULPI_CK */ - , /* OTG_HS_ULPI_D0 */ - , /* OTG_HS_ULPI_D1 */ - , /* OTG_HS_ULPI_D2 */ - , /* OTG_HS_ULPI_D3 */ - , /* OTG_HS_ULPI_D4 */ - , /* OTG_HS_ULPI_D5 */ - , /* OTG_HS_ULPI_D6 */ - ; /* OTG_HS_ULPI_D7 */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - - usbotg_fs_pins_a: usbotg-fs@0 { - pins { - pinmux = , /* OTG_FS_ID */ - , /* OTG_FS_DM */ - ; /* OTG_FS_DP */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - }; - crc: crc@40023000 { compatible = "st,stm32f7-crc"; reg = <0x40023000 0x400>; @@ -771,6 +576,9 @@ interrupts = <77>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>; clock-names = "otg"; + g-rx-fifo-size = <256>; + g-np-tx-fifo-size = <32>; + g-tx-fifo-size = <128 128 64 64 64 64 32 32>; status = "disabled"; }; Index: sys/gnu/dts/arm/stm32f769-disco.dts =================================================================== --- sys/gnu/dts/arm/stm32f769-disco.dts +++ sys/gnu/dts/arm/stm32f769-disco.dts @@ -42,11 +42,13 @@ /dts-v1/; #include "stm32f746.dtsi" +#include "stm32f769-pinctrl.dtsi" #include +#include / { model = "STMicroelectronics STM32F769-DISCO board"; - compatible = "st,stm32f769-disco", "st,stm32f7"; + compatible = "st,stm32f769-disco", "st,stm32f769"; chosen { bootargs = "root=/dev/ram"; @@ -61,6 +63,42 @@ serial0 = &usart1; }; + leds { + compatible = "gpio-leds"; + green { + gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + red { + gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + button@0 { + label = "User"; + linux,code = ; + gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; + }; + }; + + usbotg_hs_phy: usb-phy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>; + clock-names = "main_clk"; + }; + + mmc_vcard: mmc_vcard { + compatible = "regulator-fixed"; + regulator-name = "mmc_vcard"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; &cec { @@ -73,8 +111,33 @@ clock-frequency = <25000000>; }; +&rtc { + status = "okay"; +}; + +&sdio2 { + status = "okay"; + vmmc-supply = <&mmc_vcard>; + cd-gpios = <&gpioi 15 GPIO_ACTIVE_HIGH>; + cd-inverted; + broken-cd; + pinctrl-names = "default", "opendrain"; + pinctrl-0 = <&sdio_pins_b>; + pinctrl-1 = <&sdio_pins_od_b>; + bus-width = <4>; +}; + &usart1 { pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; status = "okay"; }; + +&usbotg_hs { + dr_mode = "otg"; + phys = <&usbotg_hs_phy>; + phy-names = "usb2-phy"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; Index: sys/gnu/dts/arm/stm32f769-pinctrl.dtsi =================================================================== --- /dev/null +++ sys/gnu/dts/arm/stm32f769-pinctrl.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +#include "stm32f7-pinctrl.dtsi" + +&pinctrl{ + compatible = "st,stm32f769-pinctrl"; +}; Index: sys/gnu/dts/arm/stm32h743-pinctrl.dtsi =================================================================== --- sys/gnu/dts/arm/stm32h743-pinctrl.dtsi +++ sys/gnu/dts/arm/stm32h743-pinctrl.dtsi @@ -49,6 +49,8 @@ #size-cells = <1>; compatible = "st,stm32h743-pinctrl"; ranges = <0 0x58020000 0x3000>; + interrupt-parent = <&exti>; + st,syscfg = <&syscfg 0x8>; pins-are-numbered; gpioa: gpio@58020000 { @@ -57,6 +59,8 @@ reg = <0x0 0x400>; clocks = <&rcc GPIOA_CK>; st,bank-name = "GPIOA"; + interrupt-controller; + #interrupt-cells = <2>; }; gpiob: gpio@58020400 { @@ -65,6 +69,8 @@ reg = <0x400 0x400>; clocks = <&rcc GPIOB_CK>; st,bank-name = "GPIOB"; + interrupt-controller; + #interrupt-cells = <2>; }; gpioc: gpio@58020800 { @@ -73,6 +79,8 @@ reg = <0x800 0x400>; clocks = <&rcc GPIOC_CK>; st,bank-name = "GPIOC"; + interrupt-controller; + #interrupt-cells = <2>; }; gpiod: gpio@58020c00 { @@ -81,6 +89,8 @@ reg = <0xc00 0x400>; clocks = <&rcc GPIOD_CK>; st,bank-name = "GPIOD"; + interrupt-controller; + #interrupt-cells = <2>; }; gpioe: gpio@58021000 { @@ -89,6 +99,8 @@ reg = <0x1000 0x400>; clocks = <&rcc GPIOE_CK>; st,bank-name = "GPIOE"; + interrupt-controller; + #interrupt-cells = <2>; }; gpiof: gpio@58021400 { @@ -97,6 +109,8 @@ reg = <0x1400 0x400>; clocks = <&rcc GPIOF_CK>; st,bank-name = "GPIOF"; + interrupt-controller; + #interrupt-cells = <2>; }; gpiog: gpio@58021800 { @@ -105,6 +119,8 @@ reg = <0x1800 0x400>; clocks = <&rcc GPIOG_CK>; st,bank-name = "GPIOG"; + interrupt-controller; + #interrupt-cells = <2>; }; gpioh: gpio@58021c00 { @@ -113,6 +129,8 @@ reg = <0x1c00 0x400>; clocks = <&rcc GPIOH_CK>; st,bank-name = "GPIOH"; + interrupt-controller; + #interrupt-cells = <2>; }; gpioi: gpio@58022000 { @@ -121,6 +139,8 @@ reg = <0x2000 0x400>; clocks = <&rcc GPIOI_CK>; st,bank-name = "GPIOI"; + interrupt-controller; + #interrupt-cells = <2>; }; gpioj: gpio@58022400 { @@ -129,6 +149,8 @@ reg = <0x2400 0x400>; clocks = <&rcc GPIOJ_CK>; st,bank-name = "GPIOJ"; + interrupt-controller; + #interrupt-cells = <2>; }; gpiok: gpio@58022800 { @@ -137,6 +159,8 @@ reg = <0x2800 0x400>; clocks = <&rcc GPIOK_CK>; st,bank-name = "GPIOK"; + interrupt-controller; + #interrupt-cells = <2>; }; usart1_pins: usart1@0 { @@ -164,6 +188,26 @@ bias-disable; }; }; + + usbotg_hs_pins_a: usbotg-hs@0 { + pins { + pinmux = , /* ULPI_NXT */ + , /* ULPI_DIR> */ + , /* ULPI_STP> */ + , /* ULPI_CK> */ + , /* ULPI_D0> */ + , /* ULPI_D1> */ + , /* ULPI_D2> */ + , /* ULPI_D3> */ + , /* ULPI_D4> */ + , /* ULPI_D5> */ + , /* ULPI_D6> */ + ; /* ULPI_D7> */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; }; }; }; Index: sys/gnu/dts/arm/stm32h743.dtsi =================================================================== --- sys/gnu/dts/arm/stm32h743.dtsi +++ sys/gnu/dts/arm/stm32h743.dtsi @@ -44,6 +44,7 @@ #include "armv7-m.dtsi" #include #include +#include / { clocks { @@ -100,6 +101,27 @@ }; }; + spi2: spi@40003800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x40003800 0x400>; + interrupts = <36>; + clocks = <&rcc SPI2_CK>; + status = "disabled"; + + }; + + spi3: spi@40003c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x40003c00 0x400>; + interrupts = <51>; + clocks = <&rcc SPI3_CK>; + status = "disabled"; + }; + usart2: serial@40004400 { compatible = "st,stm32f7-uart"; reg = <0x40004400 0x400>; @@ -140,6 +162,36 @@ clocks = <&rcc USART1_CK>; }; + spi1: spi@40013000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x40013000 0x400>; + interrupts = <35>; + clocks = <&rcc SPI1_CK>; + status = "disabled"; + }; + + spi4: spi@40013400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x40013400 0x400>; + interrupts = <84>; + clocks = <&rcc SPI4_CK>; + status = "disabled"; + }; + + spi5: spi@40015000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x40015000 0x400>; + interrupts = <85>; + clocks = <&rcc SPI5_CK>; + status = "disabled"; + }; + dma1: dma@40020000 { compatible = "st,stm32-dma"; reg = <0x40020000 0x400>; @@ -217,6 +269,27 @@ }; }; + usbotg_hs: usb@40040000 { + compatible = "st,stm32f7-hsotg"; + reg = <0x40040000 0x40000>; + interrupts = <77>; + clocks = <&rcc USB1OTG_CK>; + clock-names = "otg"; + g-rx-fifo-size = <256>; + g-np-tx-fifo-size = <32>; + g-tx-fifo-size = <128 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + usbotg_fs: usb@40080000 { + compatible = "st,stm32f4x9-fsotg"; + reg = <0x40080000 0x40000>; + interrupts = <101>; + clocks = <&rcc USB2OTG_CK>; + clock-names = "otg"; + status = "disabled"; + }; + mdma1: dma@52000000 { compatible = "st,stm32h7-mdma"; reg = <0x52000000 0x1000>; @@ -227,6 +300,29 @@ dma-requests = <32>; }; + exti: interrupt-controller@58000000 { + compatible = "st,stm32h7-exti"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x58000000 0x400>; + interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>; + }; + + syscfg: system-config@58000400 { + compatible = "syscon"; + reg = <0x58000400 0x400>; + }; + + spi6: spi@58001400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x58001400 0x400>; + interrupts = <86>; + clocks = <&rcc SPI6_CK>; + status = "disabled"; + }; + lptimer2: timer@58002400 { #address-cells = <1>; #size-cells = <0>; @@ -304,7 +400,7 @@ }; }; - vrefbuf: regulator@58003C00 { + vrefbuf: regulator@58003c00 { compatible = "st,stm32-vrefbuf"; reg = <0x58003C00 0x8>; clocks = <&rcc VREF_CK>; @@ -313,6 +409,20 @@ status = "disabled"; }; + rtc: rtc@58004000 { + compatible = "st,stm32h7-rtc"; + reg = <0x58004000 0x400>; + clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>; + clock-names = "pclk", "rtc_ck"; + assigned-clocks = <&rcc RTC_CK>; + assigned-clock-parents = <&rcc LSE_CK>; + interrupt-parent = <&exti>; + interrupts = <17 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "alarm"; + st,syscfg = <&pwrcfg>; + status = "disabled"; + }; + rcc: reset-clock-controller@58024400 { compatible = "st,stm32h743-rcc", "st,stm32-rcc"; reg = <0x58024400 0x400>; Index: sys/gnu/dts/arm/stm32h743i-disco.dts =================================================================== --- sys/gnu/dts/arm/stm32h743i-disco.dts +++ sys/gnu/dts/arm/stm32h743i-disco.dts @@ -63,7 +63,7 @@ }; &clk_hse { - clock-frequency = <125000000>; + clock-frequency = <25000000>; }; &usart2 { Index: sys/gnu/dts/arm/stm32h743i-eval.dts =================================================================== --- sys/gnu/dts/arm/stm32h743i-eval.dts +++ sys/gnu/dts/arm/stm32h743i-eval.dts @@ -68,6 +68,14 @@ regulator-max-microvolt = <3300000>; regulator-always-on; }; + + usbotg_hs_phy: usb-phy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + clocks = <&rcc USB1ULPI_CK>; + clock-names = "main_clk"; + }; + }; &adc_12 { @@ -84,9 +92,21 @@ clock-frequency = <25000000>; }; +&rtc { + status = "okay"; +}; + &usart1 { pinctrl-0 = <&usart1_pins>; pinctrl-names = "default"; status = "okay"; }; +&usbotg_hs { + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phys = <&usbotg_hs_phy>; + phy-names = "usb2-phy"; + dr_mode = "otg"; + status = "okay"; +}; Index: sys/gnu/dts/arm/stm32mp157-pinctrl.dtsi =================================================================== --- /dev/null +++ sys/gnu/dts/arm/stm32mp157-pinctrl.dtsi @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Ludovic Barre for STMicroelectronics. + */ +#include + +/ { + soc { + pinctrl: pin-controller { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32mp157-pinctrl"; + ranges = <0 0x50002000 0xa400>; + pins-are-numbered; + + gpioa: gpio@50002000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x400>; + clocks = <&clk_pll3_p>; + st,bank-name = "GPIOA"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@50003000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1000 0x400>; + clocks = <&clk_pll3_p>; + st,bank-name = "GPIOB"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@50004000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2000 0x400>; + clocks = <&clk_pll3_p>; + st,bank-name = "GPIOC"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@50005000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x3000 0x400>; + clocks = <&clk_pll3_p>; + st,bank-name = "GPIOD"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@50006000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x4000 0x400>; + clocks = <&clk_pll3_p>; + st,bank-name = "GPIOE"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@50007000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x5000 0x400>; + clocks = <&clk_pll3_p>; + st,bank-name = "GPIOF"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@50008000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x6000 0x400>; + clocks = <&clk_pll3_p>; + st,bank-name = "GPIOG"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@50009000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x7000 0x400>; + clocks = <&clk_pll3_p>; + st,bank-name = "GPIOH"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 112 16>; + }; + + gpioi: gpio@5000a000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x8000 0x400>; + clocks = <&clk_pll3_p>; + st,bank-name = "GPIOI"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 128 16>; + }; + + gpioj: gpio@5000b000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x9000 0x400>; + clocks = <&clk_pll3_p>; + st,bank-name = "GPIOJ"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 144 16>; + }; + + gpiok: gpio@5000c000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xa000 0x400>; + clocks = <&clk_pll3_p>; + st,bank-name = "GPIOK"; + ngpios = <8>; + gpio-ranges = <&pinctrl 0 160 8>; + }; + + uart4_pins_a: uart4@0 { + pins1 { + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + }; + + pinctrl_z: pin-controller-z { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32mp157-z-pinctrl"; + ranges = <0 0x54004000 0x400>; + pins-are-numbered; + status = "disabled"; + + gpioz: gpio@54004000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0 0x400>; + clocks = <&clk_pll2_p>; + st,bank-name = "GPIOZ"; + st,bank-ioport = <11>; + ngpios = <8>; + gpio-ranges = <&pinctrl_z 0 400 8>; + }; + }; + }; +}; Index: sys/gnu/dts/arm/stm32mp157c-ed1.dts =================================================================== --- /dev/null +++ sys/gnu/dts/arm/stm32mp157c-ed1.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Ludovic Barre for STMicroelectronics. + */ +/dts-v1/; + +#include "stm32mp157c.dtsi" +#include "stm32mp157-pinctrl.dtsi" + +/ { + model = "STMicroelectronics STM32MP157C eval daughter"; + compatible = "st,stm32mp157c-ed1", "st,stm32mp157"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0xC0000000 0x40000000>; + }; + + aliases { + serial0 = &uart4; + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + status = "okay"; +}; Index: sys/gnu/dts/arm/stm32mp157c-ev1.dts =================================================================== --- /dev/null +++ sys/gnu/dts/arm/stm32mp157c-ev1.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Ludovic Barre for STMicroelectronics. + */ +/dts-v1/; + +#include "stm32mp157c-ed1.dts" + +/ { + model = "STMicroelectronics STM32MP157C eval daughter on eval mother"; + compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &uart4; + }; +}; Index: sys/gnu/dts/arm/stm32mp157c.dtsi =================================================================== --- /dev/null +++ sys/gnu/dts/arm/stm32mp157c.dtsi @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Ludovic Barre for STMicroelectronics. + */ +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + }; + }; + + psci { + compatible = "arm,psci"; + method = "smc"; + cpu_off = <0x84000002>; + cpu_on = <0x84000003>; + }; + + aliases { + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio9 = &gpioj; + gpio10 = &gpiok; + }; + + intc: interrupt-controller@a0021000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xa0021000 0x1000>, + <0xa0022000 0x2000>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + interrupt-parent = <&intc>; + }; + + clocks { + clk_hse: clk-hse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + clk_pll_per: clk-pll-per { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <64000000>; + }; + + clk_hsi: clk-hsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <64000000>; + }; + + clk_lse: clk-lse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + clk_lsi: clk-lsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32000>; + }; + + clk_csi: clk-csi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <4000000>; + }; + + clk_pclk1: clk-pclk1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <86000000>; + }; + + clk_pll3_p: clk-pll3_p { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <172000000>; + }; + + clk_pll2_p: clk-pll2_p { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <264000000>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges; + + usart2: serial@4000e000 { + compatible = "st,stm32h7-uart"; + reg = <0x4000e000 0x400>; + interrupts = ; + clocks = <&clk_pclk1>; + status = "disabled"; + }; + + usart3: serial@4000f000 { + compatible = "st,stm32h7-uart"; + reg = <0x4000f000 0x400>; + interrupts = ; + clocks = <&clk_pclk1>; + status = "disabled"; + }; + + uart4: serial@40010000 { + compatible = "st,stm32h7-uart"; + reg = <0x40010000 0x400>; + interrupts = ; + clocks = <&clk_pclk1>; + status = "disabled"; + }; + + uart5: serial@40011000 { + compatible = "st,stm32h7-uart"; + reg = <0x40011000 0x400>; + interrupts = ; + clocks = <&clk_pclk1>; + status = "disabled"; + }; + + uart7: serial@40018000 { + compatible = "st,stm32h7-uart"; + reg = <0x40018000 0x400>; + interrupts = ; + clocks = <&clk_pclk1>; + status = "disabled"; + }; + + uart8: serial@40019000 { + compatible = "st,stm32h7-uart"; + reg = <0x40019000 0x400>; + interrupts = ; + clocks = <&clk_pclk1>; + status = "disabled"; + }; + + usart6: serial@44003000 { + compatible = "st,stm32h7-uart"; + reg = <0x44003000 0x400>; + interrupts = ; + clocks = <&clk_pclk1>; + status = "disabled"; + }; + + usart1: serial@5c000000 { + compatible = "st,stm32h7-uart"; + reg = <0x5c000000 0x400>; + interrupts = ; + clocks = <&clk_pclk1>; + status = "disabled"; + }; + }; +}; Index: sys/gnu/dts/arm/sun4i-a10-a1000.dts =================================================================== --- sys/gnu/dts/arm/sun4i-a10-a1000.dts +++ sys/gnu/dts/arm/sun4i-a10-a1000.dts @@ -164,8 +164,7 @@ &mmc0 { vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun4i-a10-ba10-tvbox.dts =================================================================== --- sys/gnu/dts/arm/sun4i-a10-ba10-tvbox.dts +++ sys/gnu/dts/arm/sun4i-a10-ba10-tvbox.dts @@ -106,8 +106,7 @@ &mmc0 { vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun4i-a10-chuwi-v7-cw0825.dts =================================================================== --- sys/gnu/dts/arm/sun4i-a10-chuwi-v7-cw0825.dts +++ sys/gnu/dts/arm/sun4i-a10-chuwi-v7-cw0825.dts @@ -123,8 +123,7 @@ &mmc0 { vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun4i-a10-cubieboard.dts =================================================================== --- sys/gnu/dts/arm/sun4i-a10-cubieboard.dts +++ sys/gnu/dts/arm/sun4i-a10-cubieboard.dts @@ -162,8 +162,7 @@ &mmc0 { vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun4i-a10-dserve-dsrv9703c.dts =================================================================== --- sys/gnu/dts/arm/sun4i-a10-dserve-dsrv9703c.dts +++ sys/gnu/dts/arm/sun4i-a10-dserve-dsrv9703c.dts @@ -150,8 +150,7 @@ &mmc0 { vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun4i-a10-gemei-g9.dts =================================================================== --- sys/gnu/dts/arm/sun4i-a10-gemei-g9.dts +++ sys/gnu/dts/arm/sun4i-a10-gemei-g9.dts @@ -141,8 +141,7 @@ &mmc0 { vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH01 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH01 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun4i-a10-hackberry.dts =================================================================== --- sys/gnu/dts/arm/sun4i-a10-hackberry.dts +++ sys/gnu/dts/arm/sun4i-a10-hackberry.dts @@ -106,8 +106,7 @@ &mmc0 { vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun4i-a10-hyundai-a7hd.dts =================================================================== --- sys/gnu/dts/arm/sun4i-a10-hyundai-a7hd.dts +++ sys/gnu/dts/arm/sun4i-a10-hyundai-a7hd.dts @@ -78,8 +78,7 @@ &mmc0 { vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun4i-a10-inet1.dts =================================================================== --- sys/gnu/dts/arm/sun4i-a10-inet1.dts +++ sys/gnu/dts/arm/sun4i-a10-inet1.dts @@ -152,8 +152,7 @@ &mmc0 { vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun4i-a10-inet9f-rev03.dts =================================================================== --- sys/gnu/dts/arm/sun4i-a10-inet9f-rev03.dts +++ sys/gnu/dts/arm/sun4i-a10-inet9f-rev03.dts @@ -300,8 +300,7 @@ &mmc0 { vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun4i-a10-itead-iteaduino-plus.dts =================================================================== --- sys/gnu/dts/arm/sun4i-a10-itead-iteaduino-plus.dts +++ sys/gnu/dts/arm/sun4i-a10-itead-iteaduino-plus.dts @@ -106,8 +106,7 @@ pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun4i-a10-jesurun-q5.dts =================================================================== --- sys/gnu/dts/arm/sun4i-a10-jesurun-q5.dts +++ sys/gnu/dts/arm/sun4i-a10-jesurun-q5.dts @@ -133,8 +133,7 @@ &mmc0 { vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun4i-a10-marsboard.dts =================================================================== --- sys/gnu/dts/arm/sun4i-a10-marsboard.dts +++ sys/gnu/dts/arm/sun4i-a10-marsboard.dts @@ -132,8 +132,7 @@ &mmc0 { vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun4i-a10-mini-xplus.dts =================================================================== --- sys/gnu/dts/arm/sun4i-a10-mini-xplus.dts +++ sys/gnu/dts/arm/sun4i-a10-mini-xplus.dts @@ -96,8 +96,7 @@ &mmc0 { vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun4i-a10-mk802.dts =================================================================== --- sys/gnu/dts/arm/sun4i-a10-mk802.dts +++ sys/gnu/dts/arm/sun4i-a10-mk802.dts @@ -56,12 +56,27 @@ chosen { stdout-path = "serial0:115200n8"; }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; }; &codec { status = "okay"; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -70,11 +85,20 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &mmc0 { vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun4i-a10-mk802ii.dts =================================================================== --- sys/gnu/dts/arm/sun4i-a10-mk802ii.dts +++ sys/gnu/dts/arm/sun4i-a10-mk802ii.dts @@ -82,8 +82,7 @@ &mmc0 { vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun4i-a10-olinuxino-lime.dts =================================================================== --- sys/gnu/dts/arm/sun4i-a10-olinuxino-lime.dts +++ sys/gnu/dts/arm/sun4i-a10-olinuxino-lime.dts @@ -97,7 +97,6 @@ 864000 1300000 624000 1250000 >; - cooling-max-level = <2>; }; &de { @@ -165,8 +164,7 @@ &mmc0 { vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun4i-a10-pcduino.dts =================================================================== --- sys/gnu/dts/arm/sun4i-a10-pcduino.dts +++ sys/gnu/dts/arm/sun4i-a10-pcduino.dts @@ -140,8 +140,7 @@ &mmc0 { vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun4i-a10-pov-protab2-ips9.dts =================================================================== --- sys/gnu/dts/arm/sun4i-a10-pov-protab2-ips9.dts +++ sys/gnu/dts/arm/sun4i-a10-pov-protab2-ips9.dts @@ -138,8 +138,7 @@ &mmc0 { vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun4i-a10.dtsi =================================================================== --- sys/gnu/dts/arm/sun4i-a10.dtsi +++ sys/gnu/dts/arm/sun4i-a10.dtsi @@ -76,7 +76,7 @@ allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi"; clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, - <&ccu CLK_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, + <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>, <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>, <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; status = "disabled"; @@ -88,7 +88,7 @@ allwinner,pipeline = "de_fe0-de_be0-lcd0"; clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>, - <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_TCON0_CH0>, + <&ccu CLK_DE_FE0>, <&ccu CLK_TCON0_CH0>, <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; status = "disabled"; }; @@ -99,7 +99,7 @@ allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0"; clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, - <&ccu CLK_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, + <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>, <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; status = "disabled"; @@ -123,8 +123,6 @@ 624000 1250000 >; #cooling-cells = <2>; - cooling-min-level = <0>; - cooling-max-level = <3>; }; }; Index: sys/gnu/dts/arm/sun5i-a10s-auxtek-t003.dts =================================================================== --- sys/gnu/dts/arm/sun5i-a10s-auxtek-t003.dts +++ sys/gnu/dts/arm/sun5i-a10s-auxtek-t003.dts @@ -93,8 +93,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_t003>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - cd-inverted; + cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun5i-a10s-auxtek-t004.dts =================================================================== --- sys/gnu/dts/arm/sun5i-a10s-auxtek-t004.dts +++ sys/gnu/dts/arm/sun5i-a10s-auxtek-t004.dts @@ -104,8 +104,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_t004>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - cd-inverted; + cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun5i-a10s-mk802.dts =================================================================== --- sys/gnu/dts/arm/sun5i-a10s-mk802.dts +++ sys/gnu/dts/arm/sun5i-a10s-mk802.dts @@ -92,8 +92,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_mk802>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - cd-inverted; + cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun5i-a10s-olinuxino-micro.dts =================================================================== --- sys/gnu/dts/arm/sun5i-a10s-olinuxino-micro.dts +++ sys/gnu/dts/arm/sun5i-a10s-olinuxino-micro.dts @@ -201,8 +201,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino_micro>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - cd-inverted; + cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ status = "okay"; }; @@ -211,8 +210,7 @@ pinctrl-0 = <&mmc1_pins_a>, <&mmc1_cd_pin_olinuxino_micro>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ - cd-inverted; + cd-gpios = <&pio 6 13 GPIO_ACTIVE_LOW>; /* PG13 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun5i-a10s-r7-tv-dongle.dts =================================================================== --- sys/gnu/dts/arm/sun5i-a10s-r7-tv-dongle.dts +++ sys/gnu/dts/arm/sun5i-a10s-r7-tv-dongle.dts @@ -80,8 +80,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_r7>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - cd-inverted; + cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun5i-a10s-wobo-i5.dts =================================================================== --- sys/gnu/dts/arm/sun5i-a10s-wobo-i5.dts +++ sys/gnu/dts/arm/sun5i-a10s-wobo-i5.dts @@ -130,8 +130,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_wobo_i5>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ - cd-inverted; + cd-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun5i-a13-empire-electronix-d709.dts =================================================================== --- sys/gnu/dts/arm/sun5i-a13-empire-electronix-d709.dts +++ sys/gnu/dts/arm/sun5i-a13-empire-electronix-d709.dts @@ -125,8 +125,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_d709>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ - cd-inverted; + cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun5i-a13-hsg-h702.dts =================================================================== --- sys/gnu/dts/arm/sun5i-a13-hsg-h702.dts +++ sys/gnu/dts/arm/sun5i-a13-hsg-h702.dts @@ -120,8 +120,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_h702>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ - cd-inverted; + cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun5i-a13-olinuxino-micro.dts =================================================================== --- sys/gnu/dts/arm/sun5i-a13-olinuxino-micro.dts +++ sys/gnu/dts/arm/sun5i-a13-olinuxino-micro.dts @@ -99,8 +99,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxinom>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ - cd-inverted; + cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun5i-a13-olinuxino.dts =================================================================== --- sys/gnu/dts/arm/sun5i-a13-olinuxino.dts +++ sys/gnu/dts/arm/sun5i-a13-olinuxino.dts @@ -194,8 +194,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ - cd-inverted; + cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun5i-a13.dtsi =================================================================== --- sys/gnu/dts/arm/sun5i-a13.dtsi +++ sys/gnu/dts/arm/sun5i-a13.dtsi @@ -116,8 +116,6 @@ 432000 1200000 >; #cooling-cells = <2>; - cooling-min-level = <0>; - cooling-max-level = <5>; }; &pio { Index: sys/gnu/dts/arm/sun5i-gr8-evb.dts =================================================================== --- sys/gnu/dts/arm/sun5i-gr8-evb.dts +++ sys/gnu/dts/arm/sun5i-gr8-evb.dts @@ -236,8 +236,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_gr8_evb>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ - cd-inverted; + cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun5i-reference-design-tablet.dtsi =================================================================== --- sys/gnu/dts/arm/sun5i-reference-design-tablet.dtsi +++ sys/gnu/dts/arm/sun5i-reference-design-tablet.dtsi @@ -127,8 +127,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ - cd-inverted; + cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun6i-a31-colombus.dts =================================================================== --- sys/gnu/dts/arm/sun6i-a31-colombus.dts +++ sys/gnu/dts/arm/sun6i-a31-colombus.dts @@ -117,8 +117,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_colombus>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; - cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ - cd-inverted; + cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun6i-a31-hummingbird.dts =================================================================== --- sys/gnu/dts/arm/sun6i-a31-hummingbird.dts +++ sys/gnu/dts/arm/sun6i-a31-hummingbird.dts @@ -218,8 +218,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_hummingbird>; vmmc-supply = <®_dcdc1>; bus-width = <4>; - cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ - cd-inverted; + cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun6i-a31-i7.dts =================================================================== --- sys/gnu/dts/arm/sun6i-a31-i7.dts +++ sys/gnu/dts/arm/sun6i-a31-i7.dts @@ -58,6 +58,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -93,6 +104,10 @@ status = "okay"; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -113,6 +128,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; @@ -124,8 +149,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_i7>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ - cd-inverted; + cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ status = "okay"; }; @@ -161,6 +185,10 @@ status = "okay"; }; +&tcon0 { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; Index: sys/gnu/dts/arm/sun6i-a31-m9.dts =================================================================== --- sys/gnu/dts/arm/sun6i-a31-m9.dts +++ sys/gnu/dts/arm/sun6i-a31-m9.dts @@ -107,8 +107,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>; vmmc-supply = <®_dcdc1>; bus-width = <4>; - cd-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ - cd-inverted; + cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun6i-a31-mele-a1000g-quad.dts =================================================================== --- sys/gnu/dts/arm/sun6i-a31-mele-a1000g-quad.dts +++ sys/gnu/dts/arm/sun6i-a31-mele-a1000g-quad.dts @@ -107,8 +107,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>; vmmc-supply = <®_dcdc1>; bus-width = <4>; - cd-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ - cd-inverted; + cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun6i-a31.dtsi =================================================================== --- sys/gnu/dts/arm/sun6i-a31.dtsi +++ sys/gnu/dts/arm/sun6i-a31.dtsi @@ -113,8 +113,6 @@ 480000 1000000 >; #cooling-cells = <2>; - cooling-min-level = <0>; - cooling-max-level = <3>; }; cpu@1 { Index: sys/gnu/dts/arm/sun6i-a31s-primo81.dts =================================================================== --- sys/gnu/dts/arm/sun6i-a31s-primo81.dts +++ sys/gnu/dts/arm/sun6i-a31s-primo81.dts @@ -151,8 +151,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_primo81>; vmmc-supply = <®_dcdc1>; bus-width = <4>; - cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ - cd-inverted; + cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun6i-a31s-sina31s.dts =================================================================== --- sys/gnu/dts/arm/sun6i-a31s-sina31s.dts +++ sys/gnu/dts/arm/sun6i-a31s-sina31s.dts @@ -167,8 +167,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_sina31s>; vmmc-supply = <®_dcdc1>; bus-width = <4>; - cd-gpios = <&pio 0 4 GPIO_ACTIVE_HIGH>; /* PA4 */ - cd-inverted; + cd-gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun6i-a31s-sinovoip-bpi-m2.dts =================================================================== --- sys/gnu/dts/arm/sun6i-a31s-sinovoip-bpi-m2.dts +++ sys/gnu/dts/arm/sun6i-a31s-sinovoip-bpi-m2.dts @@ -120,8 +120,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bpi_m2>; vmmc-supply = <®_dcdc1>; bus-width = <4>; - cd-gpios = <&pio 0 4 GPIO_ACTIVE_HIGH>; /* PA4 */ - cd-inverted; + cd-gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun6i-a31s-yones-toptech-bs1078-v2.dts =================================================================== --- sys/gnu/dts/arm/sun6i-a31s-yones-toptech-bs1078-v2.dts +++ sys/gnu/dts/arm/sun6i-a31s-yones-toptech-bs1078-v2.dts @@ -102,8 +102,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bs1078v2>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; - cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ - cd-inverted; + cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun6i-reference-design-tablet.dtsi =================================================================== --- sys/gnu/dts/arm/sun6i-reference-design-tablet.dtsi +++ sys/gnu/dts/arm/sun6i-reference-design-tablet.dtsi @@ -69,8 +69,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_e708_q1>; vmmc-supply = <®_dcdc1>; bus-width = <4>; - cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ - cd-inverted; + cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun7i-a20-bananapi-m1-plus.dts =================================================================== --- sys/gnu/dts/arm/sun7i-a20-bananapi-m1-plus.dts +++ sys/gnu/dts/arm/sun7i-a20-bananapi-m1-plus.dts @@ -184,8 +184,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bpi_m1p>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ - cd-inverted; + cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun7i-a20-bananapi.dts =================================================================== --- sys/gnu/dts/arm/sun7i-a20-bananapi.dts +++ sys/gnu/dts/arm/sun7i-a20-bananapi.dts @@ -63,6 +63,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -109,6 +120,10 @@ >; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -130,6 +145,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; @@ -159,8 +184,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapi>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ - cd-inverted; + cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun7i-a20-bananapro.dts =================================================================== --- sys/gnu/dts/arm/sun7i-a20-bananapro.dts +++ sys/gnu/dts/arm/sun7i-a20-bananapro.dts @@ -158,8 +158,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapro>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ - cd-inverted; + cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun7i-a20-cubieboard2.dts =================================================================== --- sys/gnu/dts/arm/sun7i-a20-cubieboard2.dts +++ sys/gnu/dts/arm/sun7i-a20-cubieboard2.dts @@ -165,8 +165,7 @@ pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun7i-a20-cubietruck.dts =================================================================== --- sys/gnu/dts/arm/sun7i-a20-cubietruck.dts +++ sys/gnu/dts/arm/sun7i-a20-cubietruck.dts @@ -206,8 +206,7 @@ pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun7i-a20-hummingbird.dts =================================================================== --- sys/gnu/dts/arm/sun7i-a20-hummingbird.dts +++ sys/gnu/dts/arm/sun7i-a20-hummingbird.dts @@ -163,8 +163,7 @@ pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun7i-a20-i12-tvbox.dts =================================================================== --- sys/gnu/dts/arm/sun7i-a20-i12-tvbox.dts +++ sys/gnu/dts/arm/sun7i-a20-i12-tvbox.dts @@ -160,8 +160,7 @@ pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun7i-a20-icnova-swac.dts =================================================================== --- sys/gnu/dts/arm/sun7i-a20-icnova-swac.dts +++ sys/gnu/dts/arm/sun7i-a20-icnova-swac.dts @@ -107,8 +107,7 @@ pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 8 5 GPIO_ACTIVE_HIGH>; /* PI5 */ - cd-inverted; + cd-gpios = <&pio 8 5 GPIO_ACTIVE_LOW>; /* PI5 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun7i-a20-itead-ibox.dts =================================================================== --- sys/gnu/dts/arm/sun7i-a20-itead-ibox.dts +++ sys/gnu/dts/arm/sun7i-a20-itead-ibox.dts @@ -124,8 +124,7 @@ pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun7i-a20-lamobo-r1.dts =================================================================== --- sys/gnu/dts/arm/sun7i-a20-lamobo-r1.dts +++ sys/gnu/dts/arm/sun7i-a20-lamobo-r1.dts @@ -227,8 +227,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_lamobo_r1>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ - cd-inverted; + cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun7i-a20-m3.dts =================================================================== --- sys/gnu/dts/arm/sun7i-a20-m3.dts +++ sys/gnu/dts/arm/sun7i-a20-m3.dts @@ -120,8 +120,7 @@ pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun7i-a20-mk808c.dts =================================================================== --- sys/gnu/dts/arm/sun7i-a20-mk808c.dts +++ sys/gnu/dts/arm/sun7i-a20-mk808c.dts @@ -66,12 +66,27 @@ chosen { stdout-path = "serial0:115200n8"; }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; }; &codec { status = "okay"; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -80,6 +95,16 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; @@ -112,8 +137,7 @@ pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun7i-a20-olimex-som-evb.dts =================================================================== --- sys/gnu/dts/arm/sun7i-a20-olimex-som-evb.dts +++ sys/gnu/dts/arm/sun7i-a20-olimex-som-evb.dts @@ -61,6 +61,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -79,6 +90,10 @@ status = "okay"; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -107,6 +122,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; @@ -190,8 +215,7 @@ pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -200,8 +224,7 @@ pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olimex_som_evb>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 0 GPIO_ACTIVE_HIGH>; /* PH0 */ - cd-inverted; + cd-gpios = <&pio 7 0 GPIO_ACTIVE_LOW>; /* PH0 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun7i-a20-olimex-som204-evb-emmc.dts =================================================================== --- /dev/null +++ sys/gnu/dts/arm/sun7i-a20-olimex-som204-evb-emmc.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Source for A20-SOM204-EVB-eMMC Board + * + * Copyright (C) 2018 Olimex Ltd. + * Author: Stefan Mavrodiev + */ + +/dts-v1/; +#include "sun7i-a20-olimex-som204-evb.dts" + +/ { + model = "Olimex A20-SOM204-EVB-eMMC"; + compatible = "olimex,a20-olimex-som204-evb-emmc", "allwinner,sun7i-a20"; + + mmc2_pwrseq: mmc2_pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_a>; + vmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&mmc2_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + emmc: emmc@0 { + reg = <0>; + compatible = "mmc-card"; + broken-hpi; + }; +}; Index: sys/gnu/dts/arm/sun7i-a20-olimex-som204-evb.dts =================================================================== --- /dev/null +++ sys/gnu/dts/arm/sun7i-a20-olimex-som204-evb.dts @@ -0,0 +1,335 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Source for A20-SOM204-EVB Board + * + * Copyright (C) 2018 Olimex Ltd. + * Author: Stefan Mavrodiev + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + + +#include +#include +#include + +/ { + model = "Olimex A20-SOM204-EVB"; + compatible = "olimex,a20-olimex-som204-evb", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + serial1 = &uart4; + serial2 = &uart7; + spi0 = &spi1; + spi1 = &spi2; + ethernet1 = &rtl8723bs; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + stat { + label = "a20-som204-evb:green:stat"; + gpios = <&pio 8 0 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led1 { + label = "a20-som204-evb:green:led1"; + gpios = <&pio 8 10 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led2 { + label = "a20-som204-evb:yellow:led2"; + gpios = <&pio 8 11 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + rtl_pwrseq: rtl_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 6 9 GPIO_ACTIVE_LOW>; + }; +}; + +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins_a>; + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_rgmii_a>; + phy = <&phy3>; + phy-mode = "rgmii"; + phy-supply = <®_vcc3v3>; + + snps,reset-gpio = <&pio 0 17 GPIO_ACTIVE_HIGH>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + status = "okay"; + + phy3: ethernet-phy@3 { + reg = <3>; + }; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +/* Exposed to UEXT1 */ +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + + eeprom: eeprom@50 { + compatible = "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +/* Exposed to UEXT2 */ +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; + cd-inverted; + status = "okay"; +}; + +&mmc3 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins_a>; + vmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&rtl_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + rtl8723bs: sdio_wifi@1 { + reg = <1>; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + bt_uart_pins: bt_uart_pins@0 { + pins = "PG6", "PG7", "PG8"; + function = "uart3"; + }; +}; + +#include "axp209.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + +®_ahci_5v { + gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-always-on; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_ldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pg"; +}; + +®_usb0_vbus { + gpio = <&pio 2 17 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +/* Exposed to UEXT1 */ +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>, + <&spi1_cs0_pins_a>; + status = "okay"; +}; + +/* Exposed to UEXT2 */ +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>, + <&spi2_cs0_pins_a>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +/* Used for RTL8723BS bluetooth */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&bt_uart_pins>; + status = "okay"; +}; + +/* Exposed to UEXT1 */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + status = "okay"; +}; + +/* Exposed to UEXT2 */ +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_a>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; Index: sys/gnu/dts/arm/sun7i-a20-olinuxino-lime.dts =================================================================== --- sys/gnu/dts/arm/sun7i-a20-olinuxino-lime.dts +++ sys/gnu/dts/arm/sun7i-a20-olinuxino-lime.dts @@ -158,8 +158,7 @@ pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun7i-a20-olinuxino-lime2.dts =================================================================== --- sys/gnu/dts/arm/sun7i-a20-olinuxino-lime2.dts +++ sys/gnu/dts/arm/sun7i-a20-olinuxino-lime2.dts @@ -159,8 +159,7 @@ pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun7i-a20-olinuxino-micro.dts =================================================================== --- sys/gnu/dts/arm/sun7i-a20-olinuxino-micro.dts +++ sys/gnu/dts/arm/sun7i-a20-olinuxino-micro.dts @@ -226,8 +226,7 @@ pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -236,8 +235,7 @@ pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olinuxinom>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ - cd-inverted; + cd-gpios = <&pio 7 11 GPIO_ACTIVE_LOW>; /* PH11 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun7i-a20-orangepi-mini.dts =================================================================== --- sys/gnu/dts/arm/sun7i-a20-orangepi-mini.dts +++ sys/gnu/dts/arm/sun7i-a20-orangepi-mini.dts @@ -61,6 +61,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -98,6 +109,10 @@ status = "okay"; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -119,6 +134,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; @@ -144,8 +169,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_orangepi>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ - cd-inverted; + cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ status = "okay"; }; @@ -154,8 +178,7 @@ pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_orangepi>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ - cd-inverted; + cd-gpios = <&pio 7 11 GPIO_ACTIVE_LOW>; /* PH11 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun7i-a20-orangepi.dts =================================================================== --- sys/gnu/dts/arm/sun7i-a20-orangepi.dts +++ sys/gnu/dts/arm/sun7i-a20-orangepi.dts @@ -135,8 +135,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_orangepi>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ - cd-inverted; + cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun7i-a20-pcduino3-nano.dts =================================================================== --- sys/gnu/dts/arm/sun7i-a20-pcduino3-nano.dts +++ sys/gnu/dts/arm/sun7i-a20-pcduino3-nano.dts @@ -158,8 +158,7 @@ pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun7i-a20-pcduino3.dts =================================================================== --- sys/gnu/dts/arm/sun7i-a20-pcduino3.dts +++ sys/gnu/dts/arm/sun7i-a20-pcduino3.dts @@ -159,8 +159,7 @@ pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun7i-a20-wexler-tab7200.dts =================================================================== --- sys/gnu/dts/arm/sun7i-a20-wexler-tab7200.dts +++ sys/gnu/dts/arm/sun7i-a20-wexler-tab7200.dts @@ -154,8 +154,7 @@ pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun7i-a20-wits-pro-a20-dkt.dts =================================================================== --- sys/gnu/dts/arm/sun7i-a20-wits-pro-a20-dkt.dts +++ sys/gnu/dts/arm/sun7i-a20-wits-pro-a20-dkt.dts @@ -123,8 +123,7 @@ pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun7i-a20.dtsi =================================================================== --- sys/gnu/dts/arm/sun7i-a20.dtsi +++ sys/gnu/dts/arm/sun7i-a20.dtsi @@ -47,7 +47,7 @@ #include #include #include -#include +#include #include / { @@ -116,8 +116,6 @@ 144000 1000000 >; #cooling-cells = <2>; - cooling-min-level = <0>; - cooling-max-level = <6>; }; cpu@1 { @@ -1217,6 +1215,31 @@ #size-cells = <0>; }; + mali: gpu@1c40000 { + compatible = "allwinner,sun7i-a20-mali", "arm,mali-400"; + reg = <0x01c40000 0x10000>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pmu"; + clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>; + clock-names = "bus", "core"; + resets = <&ccu RST_GPU>; + + assigned-clocks = <&ccu CLK_GPU>; + assigned-clock-rates = <384000000>; + }; + gmac: ethernet@1c50000 { compatible = "allwinner,sun7i-a20-gmac"; reg = <0x01c50000 0x10000>; Index: sys/gnu/dts/arm/sun8i-a23-evb.dts =================================================================== --- sys/gnu/dts/arm/sun8i-a23-evb.dts +++ sys/gnu/dts/arm/sun8i-a23-evb.dts @@ -107,8 +107,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_evb>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ - cd-inverted; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun8i-a33-olinuxino.dts =================================================================== --- sys/gnu/dts/arm/sun8i-a33-olinuxino.dts +++ sys/gnu/dts/arm/sun8i-a33-olinuxino.dts @@ -43,7 +43,6 @@ /dts-v1/; #include "sun8i-a33.dtsi" -#include "sunxi-common-regulators.dtsi" #include #include @@ -62,8 +61,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pin_olinuxino>; green { label = "a33-olinuxino:green:usr"; @@ -72,17 +69,24 @@ }; }; +&codec { + status = "okay"; +}; + +&dai { + status = "okay"; +}; + &ehci0 { status = "okay"; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_dcdc1>; bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ - cd-inverted; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ status = "okay"; }; @@ -90,23 +94,6 @@ status = "okay"; }; -&pio { - led_pin_olinuxino: led_pins@0 { - pins = "PB7"; - function = "gpio_out"; - }; - - mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 { - pins = "PB4"; - function = "gpio_in"; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - pins = "PB3"; - function = "gpio_in"; - }; -}; - &r_rsb { status = "okay"; @@ -122,6 +109,14 @@ #include "axp223.dtsi" +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + ®_aldo1 { regulator-always-on; regulator-min-microvolt = <3300000>; @@ -195,6 +190,21 @@ vcc-lcd-supply = <®_dc1sw>; }; +&sound { + /* Board level jack widgets */ + simple-audio-card,widgets = "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack"; + /* Board level routing. First 2 routes copied from SoC level */ + simple-audio-card,routing = + "Left DAC", "AIF1 Slot 0 Left", + "Right DAC", "AIF1 Slot 0 Right", + "HP", "HPCOM", + "Headphone Jack", "HP", + "MIC1", "Microphone Jack", + "Microphone Jack", "MBIAS"; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_b>; @@ -211,8 +221,6 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; usb0_id_det-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_drivevbus>; Index: sys/gnu/dts/arm/sun8i-a33-sinlinx-sina33.dts =================================================================== --- sys/gnu/dts/arm/sun8i-a33-sinlinx-sina33.dts +++ sys/gnu/dts/arm/sun8i-a33-sinlinx-sina33.dts @@ -144,8 +144,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_sina33>; vmmc-supply = <®_dcdc1>; bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ - cd-inverted; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun8i-a33.dtsi =================================================================== --- sys/gnu/dts/arm/sun8i-a33.dtsi +++ sys/gnu/dts/arm/sun8i-a33.dtsi @@ -289,7 +289,6 @@ clock-names = "ahb", "mod", "ram"; resets = <&ccu RST_BUS_DE_FE>; - status = "disabled"; ports { #address-cells = <1>; Index: sys/gnu/dts/arm/sun8i-a83t-allwinner-h8homlet-v2.dts =================================================================== --- sys/gnu/dts/arm/sun8i-a83t-allwinner-h8homlet-v2.dts +++ sys/gnu/dts/arm/sun8i-a83t-allwinner-h8homlet-v2.dts @@ -87,9 +87,8 @@ pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ bus-width = <4>; - cd-inverted; status = "okay"; }; Index: sys/gnu/dts/arm/sun8i-a83t-bananapi-m3.dts =================================================================== --- sys/gnu/dts/arm/sun8i-a83t-bananapi-m3.dts +++ sys/gnu/dts/arm/sun8i-a83t-bananapi-m3.dts @@ -60,6 +60,31 @@ stdout-path = "serial0:115200n8"; }; + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + blue { + label = "bananapi-m3:blue:usr"; + gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>; + }; + + green { + label = "bananapi-m3:green:usr"; + gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; + }; + }; + reg_usb1_vbus: reg-usb1-vbus { compatible = "regulator-fixed"; regulator-name = "usb1-vbus"; @@ -82,6 +107,10 @@ }; }; +&de { + status = "okay"; +}; + &ehci0 { /* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */ status = "okay"; @@ -100,6 +129,16 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &mdio { rgmii_phy: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; @@ -112,8 +151,7 @@ pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ - cd-inverted; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun8i-a83t-cubietruck-plus.dts =================================================================== --- sys/gnu/dts/arm/sun8i-a83t-cubietruck-plus.dts +++ sys/gnu/dts/arm/sun8i-a83t-cubietruck-plus.dts @@ -176,8 +176,7 @@ pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ - cd-inverted; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun8i-a83t-tbs-a711.dts =================================================================== --- sys/gnu/dts/arm/sun8i-a83t-tbs-a711.dts +++ sys/gnu/dts/arm/sun8i-a83t-tbs-a711.dts @@ -128,6 +128,14 @@ }; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu100 { + cpu-supply = <®_dcdc3>; +}; + &de { status = "okay"; }; @@ -231,6 +239,10 @@ #include "axp81x.dtsi" +&battery_power_supply { + status = "okay"; +}; + ®_aldo1 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; Index: sys/gnu/dts/arm/sun8i-a83t.dtsi =================================================================== --- sys/gnu/dts/arm/sun8i-a83t.dtsi +++ sys/gnu/dts/arm/sun8i-a83t.dtsi @@ -60,51 +60,63 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { + clocks = <&ccu CLK_C0CPUX>; + clock-names = "cpu"; compatible = "arm,cortex-a7"; device_type = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; reg = <0>; }; cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; reg = <1>; }; cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; reg = <2>; }; cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; reg = <3>; }; - cpu@100 { + cpu100: cpu@100 { + clocks = <&ccu CLK_C1CPUX>; + clock-names = "cpu"; compatible = "arm,cortex-a7"; device_type = "cpu"; + operating-points-v2 = <&cpu1_opp_table>; reg = <0x100>; }; cpu@101 { compatible = "arm,cortex-a7"; device_type = "cpu"; + operating-points-v2 = <&cpu1_opp_table>; reg = <0x101>; }; cpu@102 { compatible = "arm,cortex-a7"; device_type = "cpu"; + operating-points-v2 = <&cpu1_opp_table>; reg = <0x102>; }; cpu@103 { compatible = "arm,cortex-a7"; device_type = "cpu"; + operating-points-v2 = <&cpu1_opp_table>; reg = <0x103>; }; }; @@ -155,7 +167,7 @@ de: display-engine { compatible = "allwinner,sun8i-a83t-display-engine"; - allwinner,pipelines = <&mixer0>; + allwinner,pipelines = <&mixer0>, <&mixer1>; status = "disabled"; }; @@ -164,6 +176,112 @@ device_type = "memory"; }; + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-864000000 { + opp-hz = /bits/ 64 <864000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-912000000 { + opp-hz = /bits/ 64 <912000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1128000000 { + opp-hz = /bits/ 64 <1128000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + }; + + cpu1_opp_table: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-864000000 { + opp-hz = /bits/ 64 <864000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-912000000 { + opp-hz = /bits/ 64 <912000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1128000000 { + opp-hz = /bits/ 64 <1128000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -208,6 +326,29 @@ }; }; + mixer1: mixer@1200000 { + compatible = "allwinner,sun8i-a83t-de2-mixer-1"; + reg = <0x01200000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER1>, + <&display_clocks CLK_MIXER1>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_WB>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer1_out: port@1 { + reg = <1>; + + mixer1_out_tcon1: endpoint { + remote-endpoint = <&tcon1_in_mixer1>; + }; + }; + }; + }; + syscon: syscon@1c00000 { compatible = "allwinner,sun8i-a83t-system-controller", "syscon"; @@ -256,6 +397,40 @@ }; }; + tcon1: lcd-controller@1c0d000 { + compatible = "allwinner,sun8i-a83t-tcon-tv"; + reg = <0x01c0d000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; + clock-names = "ahb", "tcon-ch1"; + resets = <&ccu RST_BUS_TCON1>; + reset-names = "lcd"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon1_in: port@0 { + reg = <0>; + + tcon1_in_mixer1: endpoint { + remote-endpoint = <&mixer1_out_tcon1>; + }; + }; + + tcon1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon1_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon1>; + }; + }; + }; + }; + mmc0: mmc@1c0f000 { compatible = "allwinner,sun8i-a83t-mmc", "allwinner,sun7i-a20-mmc"; @@ -427,6 +602,11 @@ drive-strength = <40>; }; + hdmi_pins: hdmi-pins { + pins = "PH6", "PH7", "PH8"; + function = "hdmi"; + }; + i2c0_pins: i2c0-pins { pins = "PH0", "PH1"; function = "i2c0"; @@ -685,6 +865,50 @@ interrupts = ; }; + hdmi: hdmi@1ee0000 { + compatible = "allwinner,sun8i-a83t-dw-hdmi"; + reg = <0x01ee0000 0x10000>; + reg-io-width = <1>; + interrupts = ; + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, + <&ccu CLK_HDMI>; + clock-names = "iahb", "isfr", "tmds"; + resets = <&ccu RST_BUS_HDMI1>; + reset-names = "ctrl"; + phys = <&hdmi_phy>; + phy-names = "hdmi-phy"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + + hdmi_in_tcon1: endpoint { + remote-endpoint = <&tcon1_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + + hdmi_phy: hdmi-phy@1ef0000 { + compatible = "allwinner,sun8i-a83t-hdmi-phy"; + reg = <0x01ef0000 0x10000>; + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_HDMI0>; + reset-names = "phy"; + #phy-cells = <0>; + }; + r_intc: interrupt-controller@1f00c00 { compatible = "allwinner,sun8i-a83t-r-intc", "allwinner,sun6i-a31-r-intc"; Index: sys/gnu/dts/arm/sun8i-h2-plus-bananapi-m2-zero.dts =================================================================== --- /dev/null +++ sys/gnu/dts/arm/sun8i-h2-plus-bananapi-m2-zero.dts @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2017 Icenowy Zheng + * + * Based on sun8i-h3-bananapi-m2-plus.dts, which is: + * Copyright (C) 2016 Chen-Yu Tsai + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Banana Pi BPI-M2-Zero"; + compatible = "sinovoip,bpi-m2-zero", "allwinner,sun8i-h2-plus"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + + pwr_led { + label = "bananapi-m2-zero:red:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ + default-state = "on"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + + sw4 { + label = "power"; + linux,code = ; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + }; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + }; +}; + +&ehci0 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + /* + * On the production batch of this board the card detect GPIO is + * high active (card inserted), although on the early samples it's + * low active. + */ + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&pio>; + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ + interrupt-names = "host-wake"; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + /* + * There're two micro-USB connectors, one is power-only and another is + * OTG. The Vbus of these two connectors are connected together, so + * the external USB device will be powered just by the power input + * from the power-only USB port. + */ + status = "okay"; +}; Index: sys/gnu/dts/arm/sun8i-h2-plus-orangepi-r1.dts =================================================================== --- sys/gnu/dts/arm/sun8i-h2-plus-orangepi-r1.dts +++ sys/gnu/dts/arm/sun8i-h2-plus-orangepi-r1.dts @@ -68,6 +68,14 @@ }; }; +&spi0 { + status = "okay"; + + flash@0 { + compatible = "mxicy,mx25l12805d", "jedec,spi-nor"; + }; +}; + &ohci1 { /* * RTL8152B USB-Ethernet adapter is connected to USB1, Index: sys/gnu/dts/arm/sun8i-h2-plus-orangepi-zero.dts =================================================================== --- sys/gnu/dts/arm/sun8i-h2-plus-orangepi-zero.dts +++ sys/gnu/dts/arm/sun8i-h2-plus-orangepi-zero.dts @@ -112,18 +112,13 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ - cd-inverted; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ status = "okay"; }; &mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; vmmc-supply = <®_vcc_wifi>; mmc-pwrseq = <&wifi_pwrseq>; bus-width = <4>; @@ -139,10 +134,6 @@ }; }; -&mmc1_pins_a { - bias-pull-up; -}; - &ohci0 { status = "okay"; }; Index: sys/gnu/dts/arm/sun8i-h3-bananapi-m2-plus.dts =================================================================== --- sys/gnu/dts/arm/sun8i-h3-bananapi-m2-plus.dts +++ sys/gnu/dts/arm/sun8i-h3-bananapi-m2-plus.dts @@ -61,6 +61,17 @@ stdout-path = "serial0:115200n8"; }; + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -100,6 +111,10 @@ }; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -129,6 +144,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; @@ -136,18 +161,13 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ - cd-inverted; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ status = "okay"; }; &mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; vmmc-supply = <®_vcc3v3>; vqmmc-supply = <®_vcc3v3>; mmc-pwrseq = <&wifi_pwrseq>; Index: sys/gnu/dts/arm/sun8i-h3-beelink-x2.dts =================================================================== --- sys/gnu/dts/arm/sun8i-h3-beelink-x2.dts +++ sys/gnu/dts/arm/sun8i-h3-beelink-x2.dts @@ -61,6 +61,17 @@ stdout-path = "serial0:115200n8"; }; + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -100,6 +111,10 @@ }; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -108,6 +123,16 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; @@ -115,18 +140,13 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ - cd-inverted; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ status = "okay"; }; &mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; non-removable; Index: sys/gnu/dts/arm/sun8i-h3-libretech-all-h3-cc.dts =================================================================== --- sys/gnu/dts/arm/sun8i-h3-libretech-all-h3-cc.dts +++ sys/gnu/dts/arm/sun8i-h3-libretech-all-h3-cc.dts @@ -23,6 +23,17 @@ stdout-path = "serial0:115200n8"; }; + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -120,6 +131,10 @@ status = "okay"; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -143,6 +158,16 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; @@ -150,12 +175,9 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc_io>; bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ - cd-inverted; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun8i-h3-nanopi-m1-plus.dts =================================================================== --- sys/gnu/dts/arm/sun8i-h3-nanopi-m1-plus.dts +++ sys/gnu/dts/arm/sun8i-h3-nanopi-m1-plus.dts @@ -101,8 +101,6 @@ }; &mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; vmmc-supply = <®_vcc3v3>; vqmmc-supply = <®_vcc3v3>; mmc-pwrseq = <&wifi_pwrseq>; @@ -119,6 +117,16 @@ }; }; +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + &ohci1 { status = "okay"; }; Index: sys/gnu/dts/arm/sun8i-h3-nanopi-m1.dts =================================================================== --- sys/gnu/dts/arm/sun8i-h3-nanopi-m1.dts +++ sys/gnu/dts/arm/sun8i-h3-nanopi-m1.dts @@ -49,6 +49,21 @@ aliases { ethernet0 = &emac; }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; +}; + +&de { + status = "okay"; }; &ehci1 { @@ -66,6 +81,16 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; Index: sys/gnu/dts/arm/sun8i-h3-nanopi-neo-air.dts =================================================================== --- sys/gnu/dts/arm/sun8i-h3-nanopi-neo-air.dts +++ sys/gnu/dts/arm/sun8i-h3-nanopi-neo-air.dts @@ -72,16 +72,35 @@ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ }; }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + }; }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ - cd-inverted; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&pio>; + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ + interrupt-names = "host-wake"; + }; }; &uart0 { Index: sys/gnu/dts/arm/sun8i-h3-nanopi.dtsi =================================================================== --- sys/gnu/dts/arm/sun8i-h3-nanopi.dtsi +++ sys/gnu/dts/arm/sun8i-h3-nanopi.dtsi @@ -95,10 +95,7 @@ &mmc0 { bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; - cd-inverted; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; status = "okay"; vmmc-supply = <®_vcc3v3>; }; Index: sys/gnu/dts/arm/sun8i-h3-orangepi-2.dts =================================================================== --- sys/gnu/dts/arm/sun8i-h3-orangepi-2.dts +++ sys/gnu/dts/arm/sun8i-h3-orangepi-2.dts @@ -62,6 +62,17 @@ stdout-path = "serial0:115200n8"; }; + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -114,6 +125,10 @@ status = "okay"; }; +&de { + status = "okay"; +}; + &ehci1 { status = "okay"; }; @@ -125,6 +140,16 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; @@ -132,18 +157,13 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ - cd-inverted; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ status = "okay"; }; &mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; vmmc-supply = <®_vcc3v3>; mmc-pwrseq = <&wifi_pwrseq>; bus-width = <4>; Index: sys/gnu/dts/arm/sun8i-h3-orangepi-lite.dts =================================================================== --- sys/gnu/dts/arm/sun8i-h3-orangepi-lite.dts +++ sys/gnu/dts/arm/sun8i-h3-orangepi-lite.dts @@ -61,6 +61,17 @@ stdout-path = "serial0:115200n8"; }; + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -91,6 +102,10 @@ }; }; +&de { + status = "okay"; +}; + &ehci1 { status = "okay"; }; @@ -99,6 +114,16 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; @@ -106,18 +131,13 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ - cd-inverted; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ status = "okay"; }; &mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; non-removable; Index: sys/gnu/dts/arm/sun8i-h3-orangepi-one.dts =================================================================== --- sys/gnu/dts/arm/sun8i-h3-orangepi-one.dts +++ sys/gnu/dts/arm/sun8i-h3-orangepi-one.dts @@ -60,6 +60,17 @@ stdout-path = "serial0:115200n8"; }; + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -90,6 +101,10 @@ }; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -105,13 +120,20 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ - cd-inverted; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun8i-h3-orangepi-pc-plus.dts =================================================================== --- sys/gnu/dts/arm/sun8i-h3-orangepi-pc-plus.dts +++ sys/gnu/dts/arm/sun8i-h3-orangepi-pc-plus.dts @@ -59,8 +59,6 @@ }; &mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; non-removable; Index: sys/gnu/dts/arm/sun8i-h3-orangepi-pc.dts =================================================================== --- sys/gnu/dts/arm/sun8i-h3-orangepi-pc.dts +++ sys/gnu/dts/arm/sun8i-h3-orangepi-pc.dts @@ -60,6 +60,17 @@ stdout-path = "serial0:115200n8"; }; + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -98,6 +109,10 @@ status = "okay"; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -121,6 +136,16 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; @@ -128,12 +153,9 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ - cd-inverted; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun8i-h3.dtsi =================================================================== --- sys/gnu/dts/arm/sun8i-h3.dtsi +++ sys/gnu/dts/arm/sun8i-h3.dtsi @@ -79,6 +79,33 @@ , ; }; + + soc { + mali: gpu@1c40000 { + compatible = "allwinner,sun8i-h3-mali", "arm,mali-400"; + reg = <0x01c40000 0x10000>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pmu"; + clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; + clock-names = "bus", "core"; + resets = <&ccu RST_BUS_GPU>; + + assigned-clocks = <&ccu CLK_GPU>; + assigned-clock-rates = <384000000>; + }; + }; }; &ccu { Index: sys/gnu/dts/arm/sun8i-r16-bananapi-m2m.dts =================================================================== --- sys/gnu/dts/arm/sun8i-r16-bananapi-m2m.dts +++ sys/gnu/dts/arm/sun8i-r16-bananapi-m2m.dts @@ -150,8 +150,7 @@ pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_dcdc1>; bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ - cd-inverted; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun8i-r40-bananapi-m2-ultra.dts =================================================================== --- sys/gnu/dts/arm/sun8i-r40-bananapi-m2-ultra.dts +++ sys/gnu/dts/arm/sun8i-r40-bananapi-m2-ultra.dts @@ -164,8 +164,7 @@ &mmc0 { vmmc-supply = <®_dcdc1>; bus-width = <4>; - cd-gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */ - cd-inverted; + cd-gpios = <&pio 7 13 GPIO_ACTIVE_LOW>; /* PH13 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun8i-reference-design-tablet.dtsi =================================================================== --- sys/gnu/dts/arm/sun8i-reference-design-tablet.dtsi +++ sys/gnu/dts/arm/sun8i-reference-design-tablet.dtsi @@ -85,8 +85,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; vmmc-supply = <®_dcdc1>; bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ - cd-inverted; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ status = "okay"; }; @@ -125,6 +124,14 @@ #include "axp223.dtsi" +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + ®_aldo1 { regulator-always-on; regulator-min-microvolt = <3000000>; Index: sys/gnu/dts/arm/sun8i-v3s-licheepi-zero-dock.dts =================================================================== --- sys/gnu/dts/arm/sun8i-v3s-licheepi-zero-dock.dts +++ sys/gnu/dts/arm/sun8i-v3s-licheepi-zero-dock.dts @@ -51,7 +51,7 @@ leds { /* The LEDs use PG0~2 pins, which conflict with MMC1 */ - status = "disbaled"; + status = "disabled"; }; }; Index: sys/gnu/dts/arm/sun8i-v40-bananapi-m2-berry.dts =================================================================== --- sys/gnu/dts/arm/sun8i-v40-bananapi-m2-berry.dts +++ sys/gnu/dts/arm/sun8i-v40-bananapi-m2-berry.dts @@ -150,8 +150,7 @@ &mmc0 { vmmc-supply = <®_dcdc1>; bus-width = <4>; - cd-gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */ - cd-inverted; + cd-gpios = <&pio 7 13 GPIO_ACTIVE_LOW>; /* PH13 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun9i-a80-cubieboard4.dts =================================================================== --- sys/gnu/dts/arm/sun9i-a80-cubieboard4.dts +++ sys/gnu/dts/arm/sun9i-a80-cubieboard4.dts @@ -74,6 +74,52 @@ }; }; + vga-connector { + compatible = "vga-connector"; + label = "vga"; + ddc-i2c-bus = <&i2c3>; + + port { + vga_con_in: endpoint { + remote-endpoint = <&vga_dac_out>; + }; + }; + }; + + vga-dac { + compatible = "corpro,gm7123", "adi,adv7123", "dumb-vga-dac"; + vdd-supply = <®_dcdc1>; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + vga_dac_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_vga>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + vga_dac_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&vga_con_in>; + }; + }; + }; + }; + wifi_pwrseq: wifi-pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&ac100_rtc 1>; @@ -83,13 +129,22 @@ }; }; +&de { + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + status = "okay"; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; bus-width = <4>; - cd-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH18 */ - cd-inverted; + cd-gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; /* PH18 */ status = "okay"; }; @@ -403,6 +458,18 @@ #include "axp809.dtsi" +&tcon0 { + pinctrl-names = "default"; + pinctrl-0 = <&lcd0_rgb888_pins>; +}; + +&tcon0_out { + tcon0_out_vga: endpoint@0 { + reg = <0>; + remote-endpoint = <&vga_dac_in>; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_ph_pins>; Index: sys/gnu/dts/arm/sun9i-a80-optimus.dts =================================================================== --- sys/gnu/dts/arm/sun9i-a80-optimus.dts +++ sys/gnu/dts/arm/sun9i-a80-optimus.dts @@ -125,8 +125,7 @@ pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; bus-width = <4>; - cd-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH8 */ - cd-inverted; + cd-gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; /* PH8 */ status = "okay"; }; Index: sys/gnu/dts/arm/sun9i-a80.dtsi =================================================================== --- sys/gnu/dts/arm/sun9i-a80.dtsi +++ sys/gnu/dts/arm/sun9i-a80.dtsi @@ -63,48 +63,72 @@ cpu0: cpu@0 { compatible = "arm,cortex-a7"; device_type = "cpu"; + cci-control-port = <&cci_control0>; + clock-frequency = <12000000>; + enable-method = "allwinner,sun9i-a80-smp"; reg = <0x0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; + cci-control-port = <&cci_control0>; + clock-frequency = <12000000>; + enable-method = "allwinner,sun9i-a80-smp"; reg = <0x1>; }; cpu2: cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; + cci-control-port = <&cci_control0>; + clock-frequency = <12000000>; + enable-method = "allwinner,sun9i-a80-smp"; reg = <0x2>; }; cpu3: cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; + cci-control-port = <&cci_control0>; + clock-frequency = <12000000>; + enable-method = "allwinner,sun9i-a80-smp"; reg = <0x3>; }; cpu4: cpu@100 { compatible = "arm,cortex-a15"; device_type = "cpu"; + cci-control-port = <&cci_control1>; + clock-frequency = <18000000>; + enable-method = "allwinner,sun9i-a80-smp"; reg = <0x100>; }; cpu5: cpu@101 { compatible = "arm,cortex-a15"; device_type = "cpu"; + cci-control-port = <&cci_control1>; + clock-frequency = <18000000>; + enable-method = "allwinner,sun9i-a80-smp"; reg = <0x101>; }; cpu6: cpu@102 { compatible = "arm,cortex-a15"; device_type = "cpu"; + cci-control-port = <&cci_control1>; + clock-frequency = <18000000>; + enable-method = "allwinner,sun9i-a80-smp"; reg = <0x102>; }; cpu7: cpu@103 { compatible = "arm,cortex-a15"; device_type = "cpu"; + cci-control-port = <&cci_control1>; + clock-frequency = <18000000>; + enable-method = "allwinner,sun9i-a80-smp"; reg = <0x103>; }; }; @@ -224,6 +248,12 @@ }; }; + de: display-engine { + compatible = "allwinner,sun9i-a80-display-engine"; + allwinner,pipelines = <&fe0>, <&fe1>; + status = "disabled"; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -234,6 +264,25 @@ */ ranges = <0 0 0 0x20000000>; + sram_b: sram@20000 { + /* 256 KiB secure SRAM at 0x20000 */ + compatible = "mmio-sram"; + reg = <0x00020000 0x40000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00020000 0x40000>; + + smp-sram@1000 { + /* + * This is checked by BROM to determine if + * cpu0 should jump to SMP entry vector + */ + compatible = "allwinner,sun9i-a80-smp-sram"; + reg = <0x1000 0x8>; + }; + }; + ehci0: usb@a00000 { compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; reg = <0x00a00000 0x100>; @@ -347,6 +396,11 @@ #reset-cells = <1>; }; + cpucfg@1700000 { + compatible = "allwinner,sun9i-a80-cpucfg"; + reg = <0x01700000 0x100>; + }; + mmc0: mmc@1c0f000 { compatible = "allwinner,sun9i-a80-mmc"; reg = <0x01c0f000 0x1000>; @@ -431,6 +485,36 @@ interrupts = ; }; + cci: cci@1c90000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x01c90000 0x1000>; + ranges = <0x0 0x01c90000 0x10000>; + + cci_control0: slave-if@4000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; + }; + + cci_control1: slave-if@5000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; + }; + + pmu@9000 { + compatible = "arm,cci-400-pmu,r1"; + reg = <0x9000 0x5000>; + interrupts = , + , + , + , + ; + }; + }; + de_clocks: clock@3000000 { compatible = "allwinner,sun9i-a80-de-clks"; reg = <0x03000000 0x30>; @@ -445,6 +529,381 @@ #reset-cells = <1>; }; + fe0: display-frontend@3100000 { + compatible = "allwinner,sun9i-a80-display-frontend"; + reg = <0x03100000 0x40000>; + interrupts = ; + clocks = <&de_clocks CLK_BUS_FE0>, <&de_clocks CLK_FE0>, + <&de_clocks CLK_DRAM_FE0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&de_clocks RST_FE0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe0_out_deu0: endpoint@0 { + reg = <0>; + remote-endpoint = <&deu0_in_fe0>; + }; + }; + }; + }; + + fe1: display-frontend@3140000 { + compatible = "allwinner,sun9i-a80-display-frontend"; + reg = <0x03140000 0x40000>; + interrupts = ; + clocks = <&de_clocks CLK_BUS_FE1>, <&de_clocks CLK_FE1>, + <&de_clocks CLK_DRAM_FE1>; + clock-names = "ahb", "mod", + "ram"; + resets = <&de_clocks RST_FE0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe1_out_deu1: endpoint@0 { + reg = <0>; + remote-endpoint = <&deu1_in_fe1>; + }; + }; + }; + }; + + be0: display-backend@3200000 { + compatible = "allwinner,sun9i-a80-display-backend"; + reg = <0x03200000 0x40000>; + interrupts = ; + clocks = <&de_clocks CLK_BUS_BE0>, <&de_clocks CLK_BE0>, + <&de_clocks CLK_DRAM_BE0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&de_clocks RST_BE0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be0_in_deu0: endpoint@0 { + reg = <0>; + remote-endpoint = <&deu0_out_be0>; + }; + + be0_in_deu1: endpoint@1 { + reg = <1>; + remote-endpoint = <&deu1_out_be0>; + }; + }; + + be0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be0_out_drc0: endpoint@0 { + reg = <0>; + remote-endpoint = <&drc0_in_be0>; + }; + }; + }; + }; + + be1: display-backend@3240000 { + compatible = "allwinner,sun9i-a80-display-backend"; + reg = <0x03240000 0x40000>; + interrupts = ; + clocks = <&de_clocks CLK_BUS_BE1>, <&de_clocks CLK_BE1>, + <&de_clocks CLK_DRAM_BE1>; + clock-names = "ahb", "mod", + "ram"; + resets = <&de_clocks RST_BE1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be1_in_deu0: endpoint@0 { + reg = <0>; + remote-endpoint = <&deu0_out_be1>; + }; + + be1_in_deu1: endpoint@1 { + reg = <1>; + remote-endpoint = <&deu1_out_be1>; + }; + }; + + be1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be1_out_drc1: endpoint@0 { + reg = <0>; + remote-endpoint = <&drc1_in_be1>; + }; + }; + }; + }; + + deu0: deu@3300000 { + compatible = "allwinner,sun9i-a80-deu"; + reg = <0x03300000 0x40000>; + interrupts = ; + clocks = <&de_clocks CLK_BUS_DEU0>, + <&de_clocks CLK_IEP_DEU0>, + <&de_clocks CLK_DRAM_DEU0>; + clock-names = "ahb", + "mod", + "ram"; + resets = <&de_clocks RST_DEU0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + deu0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + deu0_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_deu0>; + }; + }; + + deu0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + deu0_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_deu0>; + }; + + deu0_out_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_in_deu0>; + }; + }; + }; + }; + + deu1: deu@3340000 { + compatible = "allwinner,sun9i-a80-deu"; + reg = <0x03340000 0x40000>; + interrupts = ; + clocks = <&de_clocks CLK_BUS_DEU1>, + <&de_clocks CLK_IEP_DEU1>, + <&de_clocks CLK_DRAM_DEU1>; + clock-names = "ahb", + "mod", + "ram"; + resets = <&de_clocks RST_DEU1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + deu1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + deu1_in_fe1: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe1_out_deu1>; + }; + }; + + deu1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + deu1_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_deu1>; + }; + + deu1_out_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_in_deu1>; + }; + }; + }; + }; + + drc0: drc@3400000 { + compatible = "allwinner,sun9i-a80-drc"; + reg = <0x03400000 0x40000>; + interrupts = ; + clocks = <&de_clocks CLK_BUS_DRC0>, + <&de_clocks CLK_IEP_DRC0>, + <&de_clocks CLK_DRAM_DRC0>; + clock-names = "ahb", + "mod", + "ram"; + resets = <&de_clocks RST_DRC0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + drc0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + drc0_in_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_drc0>; + }; + }; + + drc0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + drc0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_drc0>; + }; + }; + }; + }; + + drc1: drc@3440000 { + compatible = "allwinner,sun9i-a80-drc"; + reg = <0x03440000 0x40000>; + interrupts = ; + clocks = <&de_clocks CLK_BUS_DRC1>, + <&de_clocks CLK_IEP_DRC1>, + <&de_clocks CLK_DRAM_DRC1>; + clock-names = "ahb", + "mod", + "ram"; + resets = <&de_clocks RST_DRC1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + drc1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + drc1_in_be1: endpoint@0 { + reg = <0>; + remote-endpoint = <&be1_out_drc1>; + }; + }; + + drc1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + drc1_out_tcon1: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon1_in_drc1>; + }; + }; + }; + }; + + tcon0: lcd-controller@3c00000 { + compatible = "allwinner,sun9i-a80-tcon-lcd"; + reg = <0x03c00000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>; + clock-names = "ahb", "tcon-ch0"; + resets = <&ccu RST_BUS_LCD0>, <&ccu RST_BUS_EDP>; + reset-names = "lcd", "edp"; + clock-output-names = "tcon0-pixel-clock"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_drc0: endpoint@0 { + reg = <0>; + remote-endpoint = <&drc0_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + + tcon1: lcd-controller@3c10000 { + compatible = "allwinner,sun9i-a80-tcon-tv"; + reg = <0x03c10000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_BUS_LCD1>, <&ccu CLK_LCD1>; + clock-names = "ahb", "tcon-ch1"; + resets = <&ccu RST_BUS_LCD1>, <&ccu RST_BUS_EDP>; + reset-names = "lcd", "edp"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon1_in_drc1: endpoint@0 { + reg = <0>; + remote-endpoint = <&drc1_out_tcon1>; + }; + }; + + tcon1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + ccu: clock@6000000 { compatible = "allwinner,sun9i-a80-ccu"; reg = <0x06000000 0x800>; @@ -494,6 +953,17 @@ function = "i2c3"; }; + lcd0_rgb888_pins: lcd0-rgb888-pins { + pins = "PD0", "PD1", "PD2", "PD3", + "PD4", "PD5", "PD6", "PD7", + "PD8", "PD9", "PD10", "PD11", + "PD12", "PD13", "PD14", "PD15", + "PD16", "PD17", "PD18", "PD19", + "PD20", "PD21", "PD22", "PD23", + "PD24", "PD25", "PD26", "PD27"; + function = "lcd0"; + }; + mmc0_pins: mmc0-pins { pins = "PF0", "PF1" ,"PF2", "PF3", "PF4", "PF5"; @@ -658,6 +1128,11 @@ interrupts = ; }; + prcm@8001400 { + compatible = "allwinner,sun9i-a80-prcm"; + reg = <0x08001400 0x200>; + }; + apbs_rst: reset@80014b0 { reg = <0x080014b0 0x4>; compatible = "allwinner,sun6i-a31-clock-reset"; Index: sys/gnu/dts/arm/sunxi-h3-h5.dtsi =================================================================== --- sys/gnu/dts/arm/sunxi-h3-h5.dtsi +++ sys/gnu/dts/arm/sunxi-h3-h5.dtsi @@ -105,6 +105,12 @@ }; }; + de: display-engine { + compatible = "allwinner,sun8i-h3-display-engine"; + allwinner,pipelines = <&mixer0>; + status = "disabled"; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -123,6 +129,29 @@ #reset-cells = <1>; }; + mixer0: mixer@1100000 { + compatible = "allwinner,sun8i-h3-de2-mixer-0"; + reg = <0x01100000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER0>, + <&display_clocks CLK_MIXER0>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_MIXER0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer0_out: port@1 { + reg = <1>; + + mixer0_out_tcon0: endpoint { + remote-endpoint = <&tcon0_in_mixer0>; + }; + }; + }; + }; + syscon: syscon@1c00000 { compatible = "allwinner,sun8i-h3-system-controller", "syscon"; @@ -138,9 +167,46 @@ #dma-cells = <1>; }; + tcon0: lcd-controller@1c0c000 { + compatible = "allwinner,sun8i-h3-tcon-tv", + "allwinner,sun8i-a83t-tcon-tv"; + reg = <0x01c0c000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; + clock-names = "ahb", "tcon-ch1"; + resets = <&ccu RST_BUS_TCON0>; + reset-names = "lcd"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + reg = <0>; + + tcon0_in_mixer0: endpoint { + remote-endpoint = <&mixer0_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon0_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon0>; + }; + }; + }; + }; + mmc0: mmc@1c0f000 { /* compatible and clocks are in per SoC .dtsi file */ reg = <0x01c0f000 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; resets = <&ccu RST_BUS_MMC0>; reset-names = "ahb"; interrupts = ; @@ -152,6 +218,8 @@ mmc1: mmc@1c10000 { /* compatible and clocks are in per SoC .dtsi file */ reg = <0x01c10000 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; resets = <&ccu RST_BUS_MMC1>; reset-names = "ahb"; interrupts = ; @@ -348,7 +416,7 @@ function = "i2c2"; }; - mmc0_pins_a: mmc0 { + mmc0_pins: mmc0 { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; function = "mmc0"; @@ -356,13 +424,7 @@ bias-pull-up; }; - mmc0_cd_pin: mmc0_cd_pin { - pins = "PF6"; - function = "gpio_in"; - bias-pull-up; - }; - - mmc1_pins_a: mmc1 { + mmc1_pins: mmc1 { pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; function = "mmc1"; @@ -684,6 +746,50 @@ interrupts = ; }; + hdmi: hdmi@1ee0000 { + compatible = "allwinner,sun8i-h3-dw-hdmi", + "allwinner,sun8i-a83t-dw-hdmi"; + reg = <0x01ee0000 0x10000>; + reg-io-width = <1>; + interrupts = ; + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, + <&ccu CLK_HDMI>; + clock-names = "iahb", "isfr", "tmds"; + resets = <&ccu RST_BUS_HDMI1>; + reset-names = "ctrl"; + phys = <&hdmi_phy>; + phy-names = "hdmi-phy"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + + hdmi_in_tcon0: endpoint { + remote-endpoint = <&tcon0_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + + hdmi_phy: hdmi-phy@1ef0000 { + compatible = "allwinner,sun8i-h3-hdmi-phy"; + reg = <0x01ef0000 0x10000>; + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, + <&ccu 6>; + clock-names = "bus", "mod", "pll-0"; + resets = <&ccu RST_BUS_HDMI0>; + reset-names = "phy"; + #phy-cells = <0>; + }; + rtc: rtc@1f00000 { compatible = "allwinner,sun6i-a31-rtc"; reg = <0x01f00000 0x54>; Index: sys/gnu/dts/arm/tegra114-dalmore.dts =================================================================== --- sys/gnu/dts/arm/tegra114-dalmore.dts +++ sys/gnu/dts/arm/tegra114-dalmore.dts @@ -780,7 +780,7 @@ compatible = "realtek,rt5640"; reg = <0x1c>; interrupt-parent = <&gpio>; - interrupts = ; + interrupts = ; realtek,ldo1-en-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; }; Index: sys/gnu/dts/arm/tegra124-apalis-eval.dts =================================================================== --- sys/gnu/dts/arm/tegra124-apalis-eval.dts +++ sys/gnu/dts/arm/tegra124-apalis-eval.dts @@ -1,5 +1,5 @@ /* - * Copyright 2016 Toradex AG + * Copyright 2016-2018 Toradex AG * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -105,7 +105,7 @@ */ i2c@7000c000 { status = "okay"; - clock-frequency = <100000>; + clock-frequency = <400000>; pcie-switch@58 { compatible = "plx,pex8605"; @@ -114,7 +114,7 @@ /* M41T0M6 real time clock on carrier board */ rtc@68 { - compatible = "st,m41t00"; + compatible = "st,m41t0"; reg = <0x68>; }; }; @@ -124,7 +124,6 @@ */ hdmi_ddc: i2c@7000c400 { status = "okay"; - clock-frequency = <100000>; }; /* @@ -133,7 +132,7 @@ */ i2c@7000c500 { status = "okay"; - clock-frequency = <100000>; + clock-frequency = <400000>; }; /* I2C4 (DDC): unused */ @@ -226,9 +225,7 @@ backlight: backlight { compatible = "pwm-backlight"; - - /* BKL1_PWM */ - pwms = <&pwm 3 5000000>; + pwms = <&pwm 3 5000000>; /* BKL1_PWM */ brightness-levels = <255 231 223 207 191 159 127 0>; default-brightness-level = <6>; /* BKL1_ON */ @@ -276,3 +273,13 @@ vin-supply = <®_5v0>; }; }; + +&gpio { + /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ + pex_perst_n { + gpio-hog; + gpios = ; + output-high; + line-name = "PEX_PERST_N"; + }; +}; Index: sys/gnu/dts/arm/tegra124-apalis-v1.2-eval.dts =================================================================== --- sys/gnu/dts/arm/tegra124-apalis-v1.2-eval.dts +++ sys/gnu/dts/arm/tegra124-apalis-v1.2-eval.dts @@ -1,53 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* - * Copyright 2016 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright 2016-2018 Toradex AG */ /dts-v1/; #include -#include "tegra124-apalis.dtsi" +#include "tegra124-apalis-v1.2.dtsi" / { model = "Toradex Apalis TK1 on Apalis Evaluation Board"; - compatible = "toradex,apalis-tk1-eval", "toradex,apalis-tk1", - "nvidia,tegra124"; + compatible = "toradex,apalis-tk1-v1.2-eval", "toradex,apalis-tk1-eval", + "toradex,apalis-tk1", "nvidia,tegra124"; aliases { rtc0 = "/i2c@7000c000/rtc@68"; @@ -105,7 +69,7 @@ */ i2c@7000c000 { status = "okay"; - clock-frequency = <100000>; + clock-frequency = <400000>; pcie-switch@58 { compatible = "plx,pex8605"; @@ -114,18 +78,12 @@ /* M41T0M6 real time clock on carrier board */ rtc@68 { - compatible = "st,m41t00"; + compatible = "st,m41t0"; reg = <0x68>; }; }; - /* - * GEN2_I2C: I2C2_SDA/SCL (DDC) on MXM3 pin 205/207 (e.g. display EDID) - */ - hdmi_ddc: i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; + /* GEN2_I2C: unused */ /* * CAM_I2C: I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor @@ -133,10 +91,16 @@ */ i2c@7000c500 { status = "okay"; - clock-frequency = <100000>; + clock-frequency = <400000>; }; - /* I2C4 (DDC): unused */ + /* + * I2C4 (DDC): I2C4_SDA/SCL (DDC) on MXM3 pin 205/207 + * (e.g. display EDID) + */ + hdmi_ddc: i2c@7000c700 { + status = "okay"; + }; /* SPI1: Apalis SPI1 */ spi@7000d400 { @@ -226,9 +190,7 @@ backlight: backlight { compatible = "pwm-backlight"; - - /* BKL1_PWM */ - pwms = <&pwm 3 5000000>; + pwms = <&pwm 3 5000000>; /* BKL1_PWM */ brightness-levels = <255 231 223 207 191 159 127 0>; default-brightness-level = <6>; /* BKL1_ON */ @@ -260,7 +222,7 @@ regulator-name = "VCC_USBO1"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; enable-active-high; vin-supply = <®_5v0>; }; @@ -271,8 +233,18 @@ regulator-name = "VCC_USBH(2A|2C|2D|3|4)"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; + gpio = <&gpio TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>; enable-active-high; vin-supply = <®_5v0>; }; }; + +&gpio { + /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ + pex_perst_n { + gpio-hog; + gpios = ; + output-high; + line-name = "PEX_PERST_N"; + }; +}; Index: sys/gnu/dts/arm/tegra124-apalis-v1.2.dtsi =================================================================== --- sys/gnu/dts/arm/tegra124-apalis-v1.2.dtsi +++ sys/gnu/dts/arm/tegra124-apalis-v1.2.dtsi @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* - * Copyright 2016 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright 2016-2018 Toradex AG */ #include "tegra124.dtsi" @@ -44,11 +8,12 @@ /* * Toradex Apalis TK1 Module Device Tree - * Compatible for Revisions 2GB: V1.0A, V1.0B, V1.1A + * Compatible for Revisions 2GB: V1.2A */ / { model = "Toradex Apalis TK1"; - compatible = "toradex,apalis-tk1", "nvidia,tegra124"; + compatible = "toradex,apalis-tk1-v1.2", "toradex,apalis-tk1", + "nvidia,tegra124"; memory { reg = <0x0 0x80000000 0x0 0x80000000>; @@ -56,7 +21,6 @@ pcie@1003000 { status = "okay"; - avddio-pex-supply = <&vdd_1v05>; avdd-pex-pll-supply = <&vdd_1v05>; avdd-pll-erefe-supply = <&avdd_1v05>; @@ -85,7 +49,6 @@ hdmi@54280000 { pll-supply = <®_1v05_avdd_hdmi_pll>; vdd-supply = <®_3v3_avdd_hdmi>; - nvidia,ddc-i2c-bus = <&hdmi_ddc>; nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; @@ -213,19 +176,21 @@ }; /* Apalis GPIO */ - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4"; + usb_vbus_en0_pn4 { + nvidia,pins = "usb_vbus_en0_pn4"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; + nvidia,open-drain = ; }; - ddc_sda_pv5 { - nvidia,pins = "ddc_sda_pv5"; + usb_vbus_en1_pn5 { + nvidia,pins = "usb_vbus_en1_pn5"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; + nvidia,open-drain = ; }; pex_l0_rst_n_pdd1 { nvidia,pins = "pex_l0_rst_n_pdd1"; @@ -316,40 +281,40 @@ nvidia,open-drain = ; }; - /* Apalis I2C2 (DDC) */ - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "i2c2"; + /* Apalis I2C3 (CAM) */ + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1"; + nvidia,function = "i2c3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; nvidia,open-drain = ; }; - gen2_i2c_sda_pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; + cam_i2c_sda_pbb2 { + nvidia,pins = "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; nvidia,open-drain = ; }; - /* Apalis I2C3 (CAM) */ - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1"; - nvidia,function = "i2c3"; + /* Apalis I2C4 (DDC) */ + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4"; + nvidia,function = "i2c4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,open-drain = ; + nvidia,rcv-sel = ; }; - cam_i2c_sda_pbb2 { - nvidia,pins = "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; + ddc_sda_pv5 { + nvidia,pins = "ddc_sda_pv5"; + nvidia,function = "i2c4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,open-drain = ; + nvidia,rcv-sel = ; }; /* Apalis MMC1 */ @@ -453,12 +418,12 @@ nvidia,tristate = ; nvidia,enable-input = ; }; - /* PWM3 active on pu6 being Apalis BKL1_PWM */ + /* PWM3 active on pu6 being Apalis BKL1_PWM as well */ ph3 { nvidia,pins = "ph3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; @@ -719,8 +684,8 @@ }; /* Apalis USBH_EN */ - usb_vbus_en1_pn5 { - nvidia,pins = "usb_vbus_en1_pn5"; + gen2_i2c_sda_pt6 { + nvidia,pins = "gen2_i2c_sda_pt6"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; @@ -738,8 +703,8 @@ }; /* Apalis USBO1_EN */ - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4"; + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; @@ -1484,7 +1449,11 @@ nvidia,tristate = ; nvidia,enable-input = ; }; - pv0 { /* NC */ + /* + * PCB Version Indication: V1.2 and later have GPIO_PV0 + * wired to GND, was NC before + */ + pv0 { nvidia,pins = "pv0"; nvidia,function = "rsvd1"; nvidia,pull = ; @@ -1578,8 +1547,8 @@ compatible = "nvidia,tegra124-hsuart"; }; - hdmi_ddc: i2c@7000c400 { - clock-frequency = <100000>; + hdmi_ddc: i2c@7000c700 { + clock-frequency = <10000>; }; /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */ @@ -1600,15 +1569,11 @@ compatible = "ams,as3722"; reg = <0x40>; interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - ams,system-power-controller; - #interrupt-cells = <2>; interrupt-controller; - gpio-controller; #gpio-cells = <2>; - pinctrl-names = "default"; pinctrl-0 = <&as3722_default>; @@ -1620,9 +1585,9 @@ bias-pull-up; }; - gpio1_3_4_5_6 { - pins = "gpio1", "gpio3", "gpio4", - "gpio5", "gpio6"; + gpio0_1_3_4_5_6 { + pins = "gpio0", "gpio1", "gpio3", + "gpio4", "gpio5", "gpio6"; bias-high-impedance; }; }; @@ -1783,7 +1748,6 @@ reg = <0x4c>; interrupt-parent = <&gpio>; interrupts = ; - #thermal-sensor-cells = <1>; }; }; @@ -1816,7 +1780,6 @@ sata@70020000 { phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; phy-names = "sata-0"; - avdd-supply = <&vdd_1v05>; hvdd-supply = <®_3v3>; vddio-supply = <&vdd_1v05>; @@ -1830,7 +1793,6 @@ <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0"; - avddio-pex-supply = <&vdd_1v05>; avdd-pll-erefe-supply = <&avdd_1v05>; avdd-pll-utmip-supply = <&vddio_1v8>; @@ -2041,53 +2003,50 @@ thermal-zones { cpu { trips { - trip@0 { + cpu-shutdown-trip { temperature = <101000>; hysteresis = <0>; type = "critical"; }; }; - - cooling-maps { - /* - * There are currently no cooling maps because - * there are no cooling devices - */ - }; }; mem { trips { - trip@0 { + mem-shutdown-trip { temperature = <101000>; hysteresis = <0>; type = "critical"; }; }; - - cooling-maps { - /* - * There are currently no cooling maps because - * there are no cooling devices - */ - }; }; gpu { trips { - trip@0 { + gpu-shutdown-trip { temperature = <101000>; hysteresis = <0>; type = "critical"; }; }; - - cooling-maps { - /* - * There are currently no cooling maps because - * there are no cooling devices - */ - }; }; }; }; + +&gpio { + /* I210 Gigabit Ethernet Controller Reset */ + lan_reset_n { + gpio-hog; + gpios = ; + output-high; + line-name = "LAN_RESET_N"; + }; + + /* Control MXM3 pin 26 Reset Module Output Carrier Input */ + reset_moci_ctrl { + gpio-hog; + gpios = ; + output-high; + line-name = "RESET_MOCI_CTRL"; + }; +}; Index: sys/gnu/dts/arm/tegra124-apalis.dtsi =================================================================== --- sys/gnu/dts/arm/tegra124-apalis.dtsi +++ sys/gnu/dts/arm/tegra124-apalis.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2016 Toradex AG + * Copyright 2016-2018 Toradex AG * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -56,7 +56,6 @@ pcie@1003000 { status = "okay"; - avddio-pex-supply = <&vdd_1v05>; avdd-pex-pll-supply = <&vdd_1v05>; avdd-pll-erefe-supply = <&avdd_1v05>; @@ -85,7 +84,6 @@ hdmi@54280000 { pll-supply = <®_1v05_avdd_hdmi_pll>; vdd-supply = <®_3v3_avdd_hdmi>; - nvidia,ddc-i2c-bus = <&hdmi_ddc>; nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; @@ -453,12 +451,12 @@ nvidia,tristate = ; nvidia,enable-input = ; }; - /* PWM3 active on pu6 being Apalis BKL1_PWM */ + /* PWM3 active on pu6 being Apalis BKL1_PWM as well */ ph3 { nvidia,pins = "ph3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; @@ -1579,7 +1577,7 @@ }; hdmi_ddc: i2c@7000c400 { - clock-frequency = <100000>; + clock-frequency = <10000>; }; /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */ @@ -1600,15 +1598,11 @@ compatible = "ams,as3722"; reg = <0x40>; interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - ams,system-power-controller; - #interrupt-cells = <2>; interrupt-controller; - gpio-controller; #gpio-cells = <2>; - pinctrl-names = "default"; pinctrl-0 = <&as3722_default>; @@ -1620,9 +1614,9 @@ bias-pull-up; }; - gpio1_3_4_5_6 { - pins = "gpio1", "gpio3", "gpio4", - "gpio5", "gpio6"; + gpio0_1_3_4_5_6 { + pins = "gpio0", "gpio1", "gpio3", + "gpio4", "gpio5", "gpio6"; bias-high-impedance; }; }; @@ -1783,7 +1777,6 @@ reg = <0x4c>; interrupt-parent = <&gpio>; interrupts = ; - #thermal-sensor-cells = <1>; }; }; @@ -1816,7 +1809,6 @@ sata@70020000 { phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; phy-names = "sata-0"; - avdd-supply = <&vdd_1v05>; hvdd-supply = <®_3v3>; vddio-supply = <&vdd_1v05>; @@ -1830,7 +1822,6 @@ <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0"; - avddio-pex-supply = <&vdd_1v05>; avdd-pll-erefe-supply = <&avdd_1v05>; avdd-pll-utmip-supply = <&vddio_1v8>; @@ -2041,53 +2032,50 @@ thermal-zones { cpu { trips { - trip@0 { + cpu-shutdown-trip { temperature = <101000>; hysteresis = <0>; type = "critical"; }; }; - - cooling-maps { - /* - * There are currently no cooling maps because - * there are no cooling devices - */ - }; }; mem { trips { - trip@0 { + mem-shutdown-trip { temperature = <101000>; hysteresis = <0>; type = "critical"; }; }; - - cooling-maps { - /* - * There are currently no cooling maps because - * there are no cooling devices - */ - }; }; gpu { trips { - trip@0 { + gpu-shutdown-trip { temperature = <101000>; hysteresis = <0>; type = "critical"; }; }; - - cooling-maps { - /* - * There are currently no cooling maps because - * there are no cooling devices - */ - }; }; }; }; + +&gpio { + /* I210 Gigabit Ethernet Controller Reset */ + lan_reset_n { + gpio-hog; + gpios = ; + output-high; + line-name = "LAN_RESET_N"; + }; + + /* Control MXM3 pin 26 Reset Module Output Carrier Input */ + reset_moci_ctrl { + gpio-hog; + gpios = ; + output-high; + line-name = "RESET_MOCI_CTRL"; + }; +}; Index: sys/gnu/dts/arm/tegra124-jetson-tk1.dts =================================================================== --- sys/gnu/dts/arm/tegra124-jetson-tk1.dts +++ sys/gnu/dts/arm/tegra124-jetson-tk1.dts @@ -1418,7 +1418,7 @@ compatible = "realtek,rt5639"; reg = <0x1c>; interrupt-parent = <&gpio>; - interrupts = ; + interrupts = ; realtek,ldo1-en-gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>; }; Index: sys/gnu/dts/arm/tegra124-venice2.dts =================================================================== --- sys/gnu/dts/arm/tegra124-venice2.dts +++ sys/gnu/dts/arm/tegra124-venice2.dts @@ -613,7 +613,7 @@ compatible = "maxim,max98090"; reg = <0x10>; interrupt-parent = <&gpio>; - interrupts = ; + interrupts = ; }; }; @@ -859,7 +859,7 @@ reg = <0x9>; interrupt-parent = <&gpio>; interrupts = ; + IRQ_TYPE_EDGE_BOTH>; ti,ac-detect-gpios = <&gpio TEGRA_GPIO(J, 0) GPIO_ACTIVE_HIGH>; @@ -956,11 +956,6 @@ nvidia,function = "usb3-ss"; status = "okay"; }; - - pcie-1 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; }; }; }; Index: sys/gnu/dts/arm/tegra20-colibri-512.dtsi =================================================================== --- sys/gnu/dts/arm/tegra20-colibri-512.dtsi +++ sys/gnu/dts/arm/tegra20-colibri-512.dtsi @@ -213,21 +213,27 @@ GPIO_ACTIVE_HIGH>; }; + /* + * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier + * board) + */ i2c@7000c000 { clock-frequency = <400000>; }; + /* DDC_SCL/SDA on X3 pin 15/16 (e.g. display EDID) */ i2c_ddc: i2c@7000c400 { - clock-frequency = <100000>; + clock-frequency = <10000>; }; - i2c@7000c500 { - clock-frequency = <400000>; - }; + /* GEN2_I2C: unused */ + /* CAM/GEN3_I2C: used as EXT_IO1/2 GPIOs on SODIMM pin 133/127 */ + + /* PWR_I2C: power I2C to PMIC and temperature sensor (On-module) */ i2c@7000d000 { status = "okay"; - clock-frequency = <400000>; + clock-frequency = <100000>; pmic: tps6586x@34 { compatible = "ti,tps6586x"; Index: sys/gnu/dts/arm/tegra20.dtsi =================================================================== --- sys/gnu/dts/arm/tegra20.dtsi +++ sys/gnu/dts/arm/tegra20.dtsi @@ -17,7 +17,7 @@ #size-cells = <1>; ranges = <0 0x40000000 0x40000>; - vde_pool: vde { + vde_pool: vde@400 { reg = <0x400 0x3fc00>; pool; }; Index: sys/gnu/dts/arm/tegra30-apalis-eval.dts =================================================================== --- sys/gnu/dts/arm/tegra30-apalis-eval.dts +++ sys/gnu/dts/arm/tegra30-apalis-eval.dts @@ -79,7 +79,7 @@ */ i2c@7000c000 { status = "okay"; - clock-frequency = <100000>; + clock-frequency = <400000>; pcie-switch@58 { compatible = "plx,pex8605"; @@ -88,7 +88,7 @@ /* M41T0M6 real time clock on carrier board */ rtc@68 { - compatible = "st,m41t00"; + compatible = "st,m41t0"; reg = <0x68>; }; }; Index: sys/gnu/dts/arm/tegra30-apalis.dtsi =================================================================== --- sys/gnu/dts/arm/tegra30-apalis.dtsi +++ sys/gnu/dts/arm/tegra30-apalis.dtsi @@ -437,7 +437,7 @@ }; hdmiddc: i2c@7000c700 { - clock-frequency = <100000>; + clock-frequency = <10000>; }; /* @@ -597,7 +597,6 @@ stmpe_touchscreen@0 { compatible = "st,stmpe-ts"; - reg = <0>; /* 3.25 MHz ADC clock speed */ st,adc-freq = <1>; /* 8 sample average control */ @@ -657,7 +656,7 @@ reg = <1>; clocks = <&clk16m>; interrupt-parent = <&gpio>; - interrupts = ; + interrupts = ; spi-max-frequency = <10000000>; }; }; @@ -672,7 +671,7 @@ reg = <0>; clocks = <&clk16m>; interrupt-parent = <&gpio>; - interrupts = ; + interrupts = ; spi-max-frequency = <10000000>; }; }; Index: sys/gnu/dts/arm/tegra30-beaver.dts =================================================================== --- sys/gnu/dts/arm/tegra30-beaver.dts +++ sys/gnu/dts/arm/tegra30-beaver.dts @@ -260,14 +260,14 @@ }; sdmmc3_dat6_pd3 { nvidia,pins = "sdmmc3_dat6_pd3"; - nvidia,function = "rsvd1"; + nvidia,function = "spdif"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; sdmmc3_dat7_pd4 { nvidia,pins = "sdmmc3_dat7_pd4"; - nvidia,function = "rsvd1"; + nvidia,function = "spdif"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -281,14 +281,14 @@ }; vi_vsync_pd6 { nvidia,pins = "vi_vsync_pd6"; - nvidia,function = "rsvd1"; + nvidia,function = "ddr"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; vi_hsync_pd7 { nvidia,pins = "vi_hsync_pd7"; - nvidia,function = "rsvd1"; + nvidia,function = "ddr"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -806,7 +806,7 @@ }; hdmi_int_pn7 { nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "rsvd1"; + nvidia,function = "hdmi"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -841,7 +841,7 @@ }; ulpi_data3_po4 { nvidia,pins = "ulpi_data3_po4"; - nvidia,function = "rsvd1"; + nvidia,function = "uarta"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -1107,21 +1107,21 @@ }; vi_d10_pt2 { nvidia,pins = "vi_d10_pt2"; - nvidia,function = "rsvd1"; + nvidia,function = "ddr"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; vi_d11_pt3 { nvidia,pins = "vi_d11_pt3"; - nvidia,function = "rsvd1"; + nvidia,function = "ddr"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; vi_d0_pt4 { nvidia,pins = "vi_d0_pt4"; - nvidia,function = "rsvd1"; + nvidia,function = "ddr"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -1151,7 +1151,7 @@ }; pu0 { nvidia,pins = "pu0"; - nvidia,function = "rsvd1"; + nvidia,function = "owr"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -1172,7 +1172,7 @@ }; pu3 { nvidia,pins = "pu3"; - nvidia,function = "rsvd1"; + nvidia,function = "pwm0"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -1193,7 +1193,7 @@ }; pu6 { nvidia,pins = "pu6"; - nvidia,function = "rsvd1"; + nvidia,function = "pwm3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -1221,7 +1221,7 @@ }; pv3 { nvidia,pins = "pv3"; - nvidia,function = "rsvd1"; + nvidia,function = "clk_12m_out"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -1510,7 +1510,7 @@ }; pbb0 { nvidia,pins = "pbb0"; - nvidia,function = "rsvd1"; + nvidia,function = "i2s4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -1575,7 +1575,7 @@ }; pcc1 { nvidia,pins = "pcc1"; - nvidia,function = "rsvd1"; + nvidia,function = "i2s4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -1762,7 +1762,7 @@ compatible = "realtek,rt5640"; reg = <0x1c>; interrupt-parent = <&gpio>; - interrupts = ; + interrupts = ; realtek,ldo1-en-gpios = <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>; }; Index: sys/gnu/dts/arm/tegra30-colibri-eval-v3.dts =================================================================== --- sys/gnu/dts/arm/tegra30-colibri-eval-v3.dts +++ sys/gnu/dts/arm/tegra30-colibri-eval-v3.dts @@ -56,11 +56,11 @@ */ i2c@7000c000 { status = "okay"; - clock-frequency = <100000>; + clock-frequency = <400000>; /* M41T0M6 real time clock on carrier board */ rtc@68 { - compatible = "st,m41t00"; + compatible = "st,m41t0"; reg = <0x68>; }; }; @@ -79,7 +79,7 @@ reg = <0>; clocks = <&clk16m>; interrupt-parent = <&gpio>; - interrupts = ; + interrupts = ; spi-max-frequency = <10000000>; }; spidev0: spi@1 { Index: sys/gnu/dts/arm/tegra30-colibri.dtsi =================================================================== --- sys/gnu/dts/arm/tegra30-colibri.dtsi +++ sys/gnu/dts/arm/tegra30-colibri.dtsi @@ -215,7 +215,7 @@ }; hdmiddc: i2c@7000c700 { - clock-frequency = <100000>; + clock-frequency = <10000>; }; /* @@ -363,7 +363,6 @@ stmpe_touchscreen { compatible = "st,stmpe-ts"; - reg = <0>; /* 3.25 MHz ADC clock speed */ st,adc-freq = <1>; /* 8 sample average control */ Index: sys/gnu/dts/arm/tegra30.dtsi =================================================================== --- sys/gnu/dts/arm/tegra30.dtsi +++ sys/gnu/dts/arm/tegra30.dtsi @@ -91,6 +91,19 @@ }; }; + iram@40000000 { + compatible = "mmio-sram"; + reg = <0x40000000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40000000 0x40000>; + + vde_pool: vde@400 { + reg = <0x400 0x3fc00>; + pool; + }; + }; + host1x@50000000 { compatible = "nvidia,tegra30-host1x", "simple-bus"; reg = <0x50000000 0x00024000>; @@ -358,6 +371,28 @@ */ }; + vde@6001a000 { + compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde"; + reg = <0x6001a000 0x1000 /* Syntax Engine */ + 0x6001b000 0x1000 /* Video Bitstream Engine */ + 0x6001c000 0x100 /* Macroblock Engine */ + 0x6001c200 0x100 /* Post-processing Engine */ + 0x6001c400 0x100 /* Motion Compensation Engine */ + 0x6001c600 0x100 /* Transform Engine */ + 0x6001c800 0x100 /* Pixel prediction block */ + 0x6001ca00 0x100 /* Video DMA */ + 0x6001d800 0x400>; /* Video frame controls */ + reg-names = "sxe", "bsev", "mbe", "ppe", "mce", + "tfe", "ppb", "vdma", "frameid"; + iram = <&vde_pool>; /* IRAM region */ + interrupts = , /* Sync token interrupt */ + , /* BSE-V interrupt */ + ; /* SXE interrupt */ + interrupt-names = "sync-token", "bsev", "sxe"; + clocks = <&tegra_car TEGRA30_CLK_VDE>; + resets = <&tegra_car 61>; + }; + apbmisc@70000800 { compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"; reg = <0x70000800 0x64 /* Chip revision */ Index: sys/gnu/dts/arm/uniphier-ld4-ref.dts =================================================================== --- sys/gnu/dts/arm/uniphier-ld4-ref.dts +++ sys/gnu/dts/arm/uniphier-ld4-ref.dts @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier LD4 Reference Board - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier LD4 Reference Board +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada /dts-v1/; #include "uniphier-ld4.dtsi" Index: sys/gnu/dts/arm/uniphier-ld4.dtsi =================================================================== --- sys/gnu/dts/arm/uniphier-ld4.dtsi +++ sys/gnu/dts/arm/uniphier-ld4.dtsi @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier LD4 SoC - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier LD4 SoC +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada #include Index: sys/gnu/dts/arm/uniphier-ld6b-ref.dts =================================================================== --- sys/gnu/dts/arm/uniphier-ld6b-ref.dts +++ sys/gnu/dts/arm/uniphier-ld6b-ref.dts @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier LD6b Reference Board - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier LD6b Reference Board +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada /dts-v1/; #include "uniphier-ld6b.dtsi" @@ -67,6 +65,17 @@ status = "okay"; }; +ð { + status = "okay"; + phy-handle = <ðphy>; +}; + +&mdio { + ethphy: ethphy@0 { + reg = <0>; + }; +}; + &nand { status = "okay"; }; Index: sys/gnu/dts/arm/uniphier-ld6b.dtsi =================================================================== --- sys/gnu/dts/arm/uniphier-ld6b.dtsi +++ sys/gnu/dts/arm/uniphier-ld6b.dtsi @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier LD6b SoC - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier LD6b SoC +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada /* * LD6b consists of two silicon dies: D-chip and A-chip. Index: sys/gnu/dts/arm/uniphier-pinctrl.dtsi =================================================================== --- sys/gnu/dts/arm/uniphier-pinctrl.dtsi +++ sys/gnu/dts/arm/uniphier-pinctrl.dtsi @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier SoCs default pinctrl settings - * - * Copyright (C) 2015-2017 Socionext Inc. - * Author: Masahiro Yamada - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier SoCs default pinctrl settings +// +// Copyright (C) 2015-2017 Socionext Inc. +// Author: Masahiro Yamada &pinctrl { pinctrl_aout: aout { @@ -13,6 +11,46 @@ function = "aout"; }; + pinctrl_ain1: ain1 { + groups = "ain1"; + function = "ain1"; + }; + + pinctrl_ain2: ain2 { + groups = "ain2"; + function = "ain2"; + }; + + pinctrl_ainiec1: ainiec1 { + groups = "ainiec1"; + function = "ainiec1"; + }; + + pinctrl_aout1: aout1 { + groups = "aout1"; + function = "aout1"; + }; + + pinctrl_aout2: aout2 { + groups = "aout2"; + function = "aout2"; + }; + + pinctrl_aout3: aout3 { + groups = "aout3"; + function = "aout3"; + }; + + pinctrl_aoutiec1: aoutiec1 { + groups = "aoutiec1"; + function = "aoutiec1"; + }; + + pinctrl_aoutiec2: aoutiec2 { + groups = "aoutiec2"; + function = "aoutiec2"; + }; + pinctrl_emmc: emmc { groups = "emmc", "emmc_dat8"; function = "emmc"; @@ -33,6 +71,16 @@ function = "ether_rmii"; }; + pinctrl_ether1_rgmii: ether1-rgmii { + groups = "ether1_rgmii"; + function = "ether1_rgmii"; + }; + + pinctrl_ether1_rmii: ether1-rmii { + groups = "ether1_rmii"; + function = "ether1_rmii"; + }; + pinctrl_i2c0: i2c0 { groups = "i2c0"; function = "i2c0"; Index: sys/gnu/dts/arm/uniphier-pro4-ace.dts =================================================================== --- sys/gnu/dts/arm/uniphier-pro4-ace.dts +++ sys/gnu/dts/arm/uniphier-pro4-ace.dts @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier Pro4 Ace Board - * - * Copyright (C) 2016 Socionext Inc. - * Author: Masahiro Yamada - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier Pro4 Ace Board +// +// Copyright (C) 2016 Socionext Inc. +// Author: Masahiro Yamada /dts-v1/; #include "uniphier-pro4.dtsi" @@ -77,3 +75,14 @@ &usb3 { status = "okay"; }; + +ð { + status = "okay"; + phy-handle = <ðphy>; +}; + +&mdio { + ethphy: ethphy@1 { + reg = <1>; + }; +}; Index: sys/gnu/dts/arm/uniphier-pro4-ref.dts =================================================================== --- sys/gnu/dts/arm/uniphier-pro4-ref.dts +++ sys/gnu/dts/arm/uniphier-pro4-ref.dts @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier Pro4 Reference Board - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier Pro4 Reference Board +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada /dts-v1/; #include "uniphier-pro4.dtsi" @@ -75,6 +73,17 @@ status = "okay"; }; +ð { + status = "okay"; + phy-handle = <ðphy>; +}; + +&mdio { + ethphy: ethphy@0 { + reg = <0>; + }; +}; + &nand { status = "okay"; }; Index: sys/gnu/dts/arm/uniphier-pro4-sanji.dts =================================================================== --- sys/gnu/dts/arm/uniphier-pro4-sanji.dts +++ sys/gnu/dts/arm/uniphier-pro4-sanji.dts @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier Pro4 Sanji Board - * - * Copyright (C) 2016 Socionext Inc. - * Author: Masahiro Yamada - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier Pro4 Sanji Board +// +// Copyright (C) 2016 Socionext Inc. +// Author: Masahiro Yamada /dts-v1/; #include "uniphier-pro4.dtsi" @@ -72,3 +70,14 @@ &usb3 { status = "okay"; }; + +ð { + status = "okay"; + phy-handle = <ðphy>; +}; + +&mdio { + ethphy: ethphy@1 { + reg = <1>; + }; +}; Index: sys/gnu/dts/arm/uniphier-pro4.dtsi =================================================================== --- sys/gnu/dts/arm/uniphier-pro4.dtsi +++ sys/gnu/dts/arm/uniphier-pro4.dtsi @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier Pro4 SoC - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier Pro4 SoC +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada #include @@ -366,6 +364,24 @@ }; }; + eth: ethernet@65000000 { + compatible = "socionext,uniphier-pro4-ave4"; + status = "disabled"; + reg = <0x65000000 0x8500>; + interrupts = <0 66 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ether_rgmii>; + clocks = <&sys_clk 6>; + resets = <&sys_rst 6>; + phy-mode = "rgmii"; + local-mac-address = [00 00 00 00 00 00]; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + nand: nand@68000000 { compatible = "socionext,uniphier-denali-nand-v5a"; status = "disabled"; Index: sys/gnu/dts/arm/uniphier-pro5.dtsi =================================================================== --- sys/gnu/dts/arm/uniphier-pro5.dtsi +++ sys/gnu/dts/arm/uniphier-pro5.dtsi @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier Pro5 SoC - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier Pro5 SoC +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada / { compatible = "socionext,uniphier-pro5"; Index: sys/gnu/dts/arm/uniphier-pxs2-gentil.dts =================================================================== --- sys/gnu/dts/arm/uniphier-pxs2-gentil.dts +++ sys/gnu/dts/arm/uniphier-pxs2-gentil.dts @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier PXs2 Gentil Board - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier PXs2 Gentil Board +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada /dts-v1/; #include "uniphier-pxs2.dtsi" @@ -34,6 +32,12 @@ device_type = "memory"; reg = <0x80000000 0x80000000>; }; + + sound { + compatible = "audio-graph-card"; + label = "UniPhier PXs2"; + dais = <&i2s_port2>; + }; }; &serial2 { @@ -50,6 +54,35 @@ }; }; +&i2s_aux { + dai-format = "i2s"; + remote-endpoint = <&wm_speaker>; +}; + &i2c2 { status = "okay"; + + wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + #sound-dai-cells = <0>; + + port@0 { + wm_speaker: endpoint { + dai-format = "i2s"; + remote-endpoint = <&i2s_aux>; + }; + }; + }; +}; + +ð { + status = "okay"; + phy-handle = <ðphy>; +}; + +&mdio { + ethphy: ethphy@1 { + reg = <1>; + }; }; Index: sys/gnu/dts/arm/uniphier-pxs2-vodka.dts =================================================================== --- sys/gnu/dts/arm/uniphier-pxs2-vodka.dts +++ sys/gnu/dts/arm/uniphier-pxs2-vodka.dts @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier PXs2 Vodka Board - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier PXs2 Vodka Board +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada /dts-v1/; #include "uniphier-pxs2.dtsi" @@ -32,12 +30,60 @@ device_type = "memory"; reg = <0x80000000 0x80000000>; }; + + sound { + compatible = "audio-graph-card"; + label = "UniPhier PXs2"; + dais = <&spdif_port0 + &comp_spdif_port0>; + }; + + spdif-out { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + + port@0 { + spdif_tx: endpoint { + remote-endpoint = <&spdif_hiecout1>; + }; + }; + }; + + comp-spdif-out { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + + port@0 { + comp_spdif_tx: endpoint { + remote-endpoint = <&comp_spdif_hiecout1>; + }; + }; + }; }; &serial2 { status = "okay"; }; +&spdif_hiecout1 { + remote-endpoint = <&spdif_tx>; +}; + +&comp_spdif_hiecout1 { + remote-endpoint = <&comp_spdif_tx>; +}; + &i2c0 { status = "okay"; }; + +ð { + status = "okay"; + phy-handle = <ðphy>; +}; + +&mdio { + ethphy: ethphy@1 { + reg = <1>; + }; +}; Index: sys/gnu/dts/arm/uniphier-pxs2.dtsi =================================================================== --- sys/gnu/dts/arm/uniphier-pxs2.dtsi +++ sys/gnu/dts/arm/uniphier-pxs2.dtsi @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier PXs2 SoC - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier PXs2 SoC +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada #include #include @@ -227,6 +225,61 @@ <21 217 3>; }; + audio@56000000 { + compatible = "socionext,uniphier-pxs2-aio"; + reg = <0x56000000 0x80000>; + interrupts = <0 144 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ain1>, + <&pinctrl_ain2>, + <&pinctrl_ainiec1>, + <&pinctrl_aout2>, + <&pinctrl_aout3>, + <&pinctrl_aoutiec1>, + <&pinctrl_aoutiec2>; + clock-names = "aio"; + clocks = <&sys_clk 40>; + reset-names = "aio"; + resets = <&sys_rst 40>; + #sound-dai-cells = <1>; + socionext,syscon = <&soc_glue>; + + i2s_port0: port@0 { + i2s_hdmi: endpoint { + }; + }; + + i2s_port1: port@1 { + i2s_line: endpoint { + }; + }; + + i2s_port2: port@2 { + i2s_aux: endpoint { + }; + }; + + spdif_port0: port@3 { + spdif_hiecout1: endpoint { + }; + }; + + spdif_port1: port@4 { + spdif_iecout1: endpoint { + }; + }; + + comp_spdif_port0: port@5 { + comp_spdif_hiecout1: endpoint { + }; + }; + + comp_spdif_port1: port@6 { + comp_spdif_iecout1: endpoint { + }; + }; + }; + i2c0: i2c@58780000 { compatible = "socionext,uniphier-fi2c"; status = "disabled"; @@ -366,7 +419,7 @@ }; }; - soc-glue@5f800000 { + soc_glue: soc-glue@5f800000 { compatible = "socionext,uniphier-pxs2-soc-glue", "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; @@ -446,6 +499,24 @@ }; }; + eth: ethernet@65000000 { + compatible = "socionext,uniphier-pxs2-ave4"; + status = "disabled"; + reg = <0x65000000 0x8500>; + interrupts = <0 66 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ether_rgmii>; + clocks = <&sys_clk 6>; + resets = <&sys_rst 6>; + phy-mode = "rgmii"; + local-mac-address = [00 00 00 00 00 00]; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + nand: nand@68000000 { compatible = "socionext,uniphier-denali-nand-v5b"; status = "disabled"; Index: sys/gnu/dts/arm/uniphier-ref-daughter.dtsi =================================================================== --- sys/gnu/dts/arm/uniphier-ref-daughter.dtsi +++ sys/gnu/dts/arm/uniphier-ref-daughter.dtsi @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier Reference Daughter Board - * - * Copyright (C) 2015-2017 Socionext Inc. - * Author: Masahiro Yamada - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier Reference Daughter Board +// +// Copyright (C) 2015-2017 Socionext Inc. +// Author: Masahiro Yamada &i2c0 { eeprom@50 { Index: sys/gnu/dts/arm/uniphier-sld8-ref.dts =================================================================== --- sys/gnu/dts/arm/uniphier-sld8-ref.dts +++ sys/gnu/dts/arm/uniphier-sld8-ref.dts @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier sLD8 Reference Board - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier sLD8 Reference Board +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada /dts-v1/; #include "uniphier-sld8.dtsi" Index: sys/gnu/dts/arm/uniphier-sld8.dtsi =================================================================== --- sys/gnu/dts/arm/uniphier-sld8.dtsi +++ sys/gnu/dts/arm/uniphier-sld8.dtsi @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier sLD8 SoC - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier sLD8 SoC +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada #include Index: sys/gnu/dts/arm/uniphier-support-card.dtsi =================================================================== --- sys/gnu/dts/arm/uniphier-support-card.dtsi +++ sys/gnu/dts/arm/uniphier-support-card.dtsi @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier Support Card (Expansion Board) - * - * Copyright (C) 2015-2017 Socionext Inc. - * Author: Masahiro Yamada - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier Support Card (Expansion Board) +// +// Copyright (C) 2015-2017 Socionext Inc. +// Author: Masahiro Yamada &system_bus { status = "okay"; Index: sys/gnu/dts/arm/versatile-ab-ib2.dts =================================================================== --- /dev/null +++ sys/gnu/dts/arm/versatile-ab-ib2.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * The Versatile AB with the IB2 expansion board mounted. + * This works as a superset of the Versatile AB. + */ + +#include "versatile-ab.dts" + +/ { + model = "ARM Versatile AB + IB2 board"; + + /* Special IB2 control register */ + ib2_syscon@27000000 { + compatible = "arm,versatile-ib2-syscon", "syscon", "simple-mfd"; + reg = <0x27000000 0x4>; + + led@00.4 { + compatible = "register-bit-led"; + offset = <0x00>; + mask = <0x10>; + label = "versatile-ib2:0"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + }; +}; Index: sys/gnu/dts/arm/versatile-ab.dts =================================================================== --- sys/gnu/dts/arm/versatile-ab.dts +++ sys/gnu/dts/arm/versatile-ab.dts @@ -30,6 +30,43 @@ clock-frequency = <24000000>; }; + bridge { + compatible = "ti,ths8134b", "ti,ths8134"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vga_bridge_in: endpoint { + remote-endpoint = <&clcd_pads_vga_dac>; + }; + }; + + port@1 { + reg = <1>; + + vga_bridge_out: endpoint { + remote-endpoint = <&vga_con_in>; + }; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + port { + vga_con_in: endpoint { + remote-endpoint = <&vga_bridge_out>; + }; + }; + }; + core-module@10000000 { compatible = "arm,core-module-versatile", "syscon", "simple-mfd"; reg = <0x10000000 0x200>; @@ -230,7 +267,39 @@ reg = <0x10120000 0x1000>; interrupts = <16>; clocks = <&osc1>, <&pclk>; - clock-names = "clcd", "apb_pclk"; + clock-names = "clcdclk", "apb_pclk"; + /* 800x600 16bpp @ 36MHz works fine */ + max-memory-bandwidth = <54000000>; + + /* + * This port is routed through a PLD (Programmable + * Logic Device) that routes the output from the CLCD + * (after transformations) to the VGA DAC and also an + * external panel connector. The PLD is essential for + * supporting RGB565/BGR565. + * + * The signals from the port thus reaches two endpoints. + * The PLD is managed through a few special bits in the + * FPGA "sysreg". + * + * This arrangement can be clearly seen in + * ARM DUI 0225D, page 3-41, figure 3-19. + */ + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + clcd_pads_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + clcd_pads_vga_dac: endpoint@1 { + reg = <1>; + remote-endpoint = <&vga_bridge_in>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; }; sctl@101e0000 { @@ -319,8 +388,18 @@ ranges = <0 0x10000000 0x10000>; sysreg@0 { - compatible = "arm,versatile-sysreg", "syscon"; + compatible = "arm,versatile-sysreg", "syscon", "simple-mfd"; reg = <0x00000 0x1000>; + + panel: display@0 { + compatible = "arm,versatile-tft-panel"; + + port { + panel_in: endpoint { + remote-endpoint = <&clcd_pads_panel>; + }; + }; + }; }; aaci@4000 { Index: sys/gnu/dts/arm/vf500-colibri.dtsi =================================================================== --- sys/gnu/dts/arm/vf500-colibri.dtsi +++ sys/gnu/dts/arm/vf500-colibri.dtsi @@ -46,7 +46,7 @@ model = "Toradex Colibri VF50 COM"; compatible = "toradex,vf610-colibri_vf50", "fsl,vf500"; - memory { + memory@80000000 { reg = <0x80000000 0x8000000>; }; Index: sys/gnu/dts/arm/vf500.dtsi =================================================================== --- sys/gnu/dts/arm/vf500.dtsi +++ sys/gnu/dts/arm/vf500.dtsi @@ -39,11 +39,16 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" #include "vfxxx.dtsi" #include / { + #address-cells = <1>; + #size-cells = <1>; + chosen { }; + aliases { }; + memory { device_type = "memory"; }; + cpus { #address-cells = <1>; #size-cells = <0>; Index: sys/gnu/dts/arm/vf610-colibri.dtsi =================================================================== --- sys/gnu/dts/arm/vf610-colibri.dtsi +++ sys/gnu/dts/arm/vf610-colibri.dtsi @@ -46,7 +46,7 @@ model = "Toradex Colibri VF61 COM"; compatible = "toradex,vf610-colibri_vf61", "fsl,vf610"; - memory { + memory@80000000 { reg = <0x80000000 0x10000000>; }; }; Index: sys/gnu/dts/arm/vf610-cosmic.dts =================================================================== --- sys/gnu/dts/arm/vf610-cosmic.dts +++ sys/gnu/dts/arm/vf610-cosmic.dts @@ -19,7 +19,7 @@ bootargs = "console=ttyLP1,115200"; }; - memory { + memory@80000000 { reg = <0x80000000 0x10000000>; }; Index: sys/gnu/dts/arm/vf610-twr.dts =================================================================== --- sys/gnu/dts/arm/vf610-twr.dts +++ sys/gnu/dts/arm/vf610-twr.dts @@ -50,7 +50,7 @@ bootargs = "console=ttyLP1,115200"; }; - memory { + memory@80000000 { reg = <0x80000000 0x8000000>; }; Index: sys/gnu/dts/arm/vf610-zii-dev.dtsi =================================================================== --- sys/gnu/dts/arm/vf610-zii-dev.dtsi +++ sys/gnu/dts/arm/vf610-zii-dev.dtsi @@ -49,7 +49,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@80000000 { reg = <0x80000000 0x20000000>; }; Index: sys/gnu/dts/arm/vf610m4-colibri.dts =================================================================== --- sys/gnu/dts/arm/vf610m4-colibri.dts +++ sys/gnu/dts/arm/vf610m4-colibri.dts @@ -51,10 +51,10 @@ chosen { bootargs = "console=ttyLP2,115200 clk_ignore_unused init=/linuxrc rw"; - linux,stdout-path = "&uart2"; + stdout-path = "&uart2"; }; - memory { + memory@8c000000 { reg = <0x8c000000 0x3000000>; }; }; Index: sys/gnu/dts/arm/vf610m4.dtsi =================================================================== --- sys/gnu/dts/arm/vf610m4.dtsi +++ sys/gnu/dts/arm/vf610m4.dtsi @@ -42,10 +42,17 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" #include "armv7-m.dtsi" #include "vfxxx.dtsi" +/ { + #address-cells = <1>; + #size-cells = <1>; + chosen { }; + aliases { }; + memory { device_type = "memory"; }; +}; + &mscm_ir { interrupt-parent = <&nvic>; }; Index: sys/gnu/dts/arm/zynq-7000.dtsi =================================================================== --- sys/gnu/dts/arm/zynq-7000.dtsi +++ sys/gnu/dts/arm/zynq-7000.dtsi @@ -1,14 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2011 - 2014 Xilinx - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * Copyright (C) 2011 - 2014 Xilinx */ / { Index: sys/gnu/dts/arm/zynq-cc108.dts =================================================================== --- /dev/null +++ sys/gnu/dts/arm/zynq-cc108.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx CC108 board DTS + * + * (C) Copyright 2007-2018 Xilinx, Inc. + * (C) Copyright 2007-2013 Michal Simek + * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd + * + * Michal SIMEK + */ +/dts-v1/; +/include/ "zynq-7000.dtsi" + +/ { + compatible = "xlnx,zynq-cc108", "xlnx,zynq-7000"; + model = "Xilinx Zynq"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart0; + }; + + chosen { + bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x20000000>; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + + usb_phy1: phy1 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@1 { + reg = <1>; + device_type = "ethernet-phy"; + }; +}; + +&sdhci1 { + status = "okay"; + broken-cd ; + wp-inverted ; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy1>; +}; Index: sys/gnu/dts/arm/zynq-microzed.dts =================================================================== --- sys/gnu/dts/arm/zynq-microzed.dts +++ sys/gnu/dts/arm/zynq-microzed.dts @@ -1,15 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2011 - 2014 Xilinx * Copyright (C) 2016 Jagan Teki - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ /dts-v1/; /include/ "zynq-7000.dtsi" @@ -23,7 +15,7 @@ serial0 = &uart1; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x40000000>; }; Index: sys/gnu/dts/arm/zynq-parallella.dts =================================================================== --- sys/gnu/dts/arm/zynq-parallella.dts +++ sys/gnu/dts/arm/zynq-parallella.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2014 SUSE LINUX Products GmbH * @@ -6,15 +7,6 @@ * Copyright (C) 2011 Xilinx * Copyright (C) 2012 National Instruments Corp. * Copyright (C) 2013 Xilinx - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ /dts-v1/; /include/ "zynq-7000.dtsi" Index: sys/gnu/dts/arm/zynq-zc702.dts =================================================================== --- sys/gnu/dts/arm/zynq-zc702.dts +++ sys/gnu/dts/arm/zynq-zc702.dts @@ -1,15 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2011 - 2014 Xilinx * Copyright (C) 2012 National Instruments Corp. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ /dts-v1/; #include "zynq-7000.dtsi" @@ -112,7 +104,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0_default>; - i2cswitch@74 { + i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; Index: sys/gnu/dts/arm/zynq-zc706.dts =================================================================== --- sys/gnu/dts/arm/zynq-zc706.dts +++ sys/gnu/dts/arm/zynq-zc706.dts @@ -1,15 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2011 - 2014 Xilinx * Copyright (C) 2012 National Instruments Corp. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ /dts-v1/; #include "zynq-7000.dtsi" @@ -68,7 +60,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0_default>; - i2cswitch@74 { + i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; Index: sys/gnu/dts/arm/zynq-zc770-xm010.dts =================================================================== --- /dev/null +++ sys/gnu/dts/arm/zynq-zc770-xm010.dts @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx ZC770 XM010 board DTS + * + * Copyright (C) 2013-2018 Xilinx, Inc. + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000"; + model = "Xilinx Zynq"; + + aliases { + ethernet0 = &gem0; + i2c0 = &i2c0; + serial0 = &uart1; + spi1 = &spi1; + }; + + chosen { + bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; + +&can0 { + status = "okay"; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@7 { + reg = <7>; + device_type = "ethernet-phy"; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + eeprom: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + }; + +}; + +&sdhci0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; + num-cs = <4>; + is-decoded-cs = <0>; + flash@0 { + compatible = "sst25wf080", "jedec,spi-nor"; + reg = <1>; + spi-max-frequency = <1000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "data"; + reg = <0x0 0x100000>; + }; + }; + }; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; Index: sys/gnu/dts/arm/zynq-zc770-xm011.dts =================================================================== --- /dev/null +++ sys/gnu/dts/arm/zynq-zc770-xm011.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx ZC770 XM013 board DTS + * + * Copyright (C) 2013-2018 Xilinx, Inc. + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000"; + model = "Xilinx Zynq"; + + aliases { + i2c0 = &i2c1; + serial0 = &uart1; + spi0 = &spi0; + }; + + chosen { + bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + usb_phy1: phy1 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; + +&can0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + eeprom: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + }; +}; + +&spi0 { + status = "okay"; + num-cs = <4>; + is-decoded-cs = <0>; +}; + +&uart1 { + status = "okay"; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy1>; +}; Index: sys/gnu/dts/arm/zynq-zc770-xm012.dts =================================================================== --- /dev/null +++ sys/gnu/dts/arm/zynq-zc770-xm012.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx ZC770 XM012 board DTS + * + * Copyright (C) 2013-2018 Xilinx, Inc. + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000"; + model = "Xilinx Zynq"; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + serial0 = &uart1; + spi0 = &spi1; + }; + + chosen { + bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; +}; + +&can1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + eeprom0: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + eeprom1: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + }; +}; + +&spi1 { + status = "okay"; + num-cs = <4>; + is-decoded-cs = <0>; +}; + +&uart1 { + status = "okay"; +}; Index: sys/gnu/dts/arm/zynq-zc770-xm013.dts =================================================================== --- /dev/null +++ sys/gnu/dts/arm/zynq-zc770-xm013.dts @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx ZC770 XM013 board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000"; + model = "Xilinx Zynq"; + + aliases { + ethernet0 = &gem1; + i2c0 = &i2c1; + serial0 = &uart0; + spi1 = &spi0; + }; + + chosen { + bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; +}; + +&can1 { + status = "okay"; +}; + +&gem1 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@7 { + reg = <7>; + device_type = "ethernet-phy"; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + si570: clock-generator@55 { + #clock-cells = <0>; + compatible = "silabs,si570"; + temperature-stability = <50>; + reg = <0x55>; + factory-fout = <156250000>; + clock-frequency = <148500000>; + }; +}; + +&spi0 { + status = "okay"; + num-cs = <4>; + is-decoded-cs = <0>; + eeprom: eeprom@0 { + at25,byte-len = <8192>; + at25,addr-mode = <2>; + at25,page-size = <32>; + + compatible = "atmel,at25"; + reg = <2>; + spi-max-frequency = <1000000>; + }; +}; + +&uart0 { + status = "okay"; +}; Index: sys/gnu/dts/arm/zynq-zed.dts =================================================================== --- sys/gnu/dts/arm/zynq-zed.dts +++ sys/gnu/dts/arm/zynq-zed.dts @@ -1,15 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2011 - 2014 Xilinx * Copyright (C) 2012 National Instruments Corp. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ /dts-v1/; #include "zynq-7000.dtsi" Index: sys/gnu/dts/arm/zynq-zybo-z7.dts =================================================================== --- sys/gnu/dts/arm/zynq-zybo-z7.dts +++ sys/gnu/dts/arm/zynq-zybo-z7.dts @@ -1,22 +1,10 @@ -/* - * Copyright (C) 2011 - 2014 Xilinx - * Copyright (C) 2012 National Instruments Corp. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0+ /dts-v1/; #include "zynq-7000.dtsi" / { - model = "Zynq Zed Development Board"; - compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; + model = "Zynq ZYBO Z7 Development Board"; + compatible = "digilent,zynq-zybo-z7", "xlnx,zynq-7000"; aliases { ethernet0 = &gem0; @@ -34,8 +22,9 @@ }; usb_phy0: phy0 { - compatible = "usb-nop-xceiv"; #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio0 46 1>; }; }; Index: sys/gnu/dts/arm/zynq-zybo.dts =================================================================== --- sys/gnu/dts/arm/zynq-zybo.dts +++ sys/gnu/dts/arm/zynq-zybo.dts @@ -1,15 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2011 - 2014 Xilinx * Copyright (C) 2012 National Instruments Corp. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ /dts-v1/; #include "zynq-7000.dtsi" Index: sys/gnu/dts/include/dt-bindings/clock/axg-clkc.h =================================================================== --- sys/gnu/dts/include/dt-bindings/clock/axg-clkc.h +++ sys/gnu/dts/include/dt-bindings/clock/axg-clkc.h @@ -67,5 +67,6 @@ #define CLKID_AO_I2C 58 #define CLKID_SD_EMMC_B_CLK0 59 #define CLKID_SD_EMMC_C_CLK0 60 +#define CLKID_HIFI_PLL 69 #endif /* __AXG_CLKC_H */ Index: sys/gnu/dts/include/dt-bindings/clock/histb-clock.h =================================================================== --- sys/gnu/dts/include/dt-bindings/clock/histb-clock.h +++ sys/gnu/dts/include/dt-bindings/clock/histb-clock.h @@ -22,18 +22,18 @@ #define HISTB_OSC_CLK 0 #define HISTB_APB_CLK 1 #define HISTB_AHB_CLK 2 -#define HISTB_UART1_CLK 3 -#define HISTB_UART2_CLK 4 -#define HISTB_UART3_CLK 5 -#define HISTB_I2C0_CLK 6 -#define HISTB_I2C1_CLK 7 -#define HISTB_I2C2_CLK 8 -#define HISTB_I2C3_CLK 9 -#define HISTB_I2C4_CLK 10 -#define HISTB_I2C5_CLK 11 -#define HISTB_SPI0_CLK 12 -#define HISTB_SPI1_CLK 13 -#define HISTB_SPI2_CLK 14 +#define HISTB_UART1_CLK 3 +#define HISTB_UART2_CLK 4 +#define HISTB_UART3_CLK 5 +#define HISTB_I2C0_CLK 6 +#define HISTB_I2C1_CLK 7 +#define HISTB_I2C2_CLK 8 +#define HISTB_I2C3_CLK 9 +#define HISTB_I2C4_CLK 10 +#define HISTB_I2C5_CLK 11 +#define HISTB_SPI0_CLK 12 +#define HISTB_SPI1_CLK 13 +#define HISTB_SPI2_CLK 14 #define HISTB_SCI_CLK 15 #define HISTB_FMC_CLK 16 #define HISTB_MMC_BIU_CLK 17 @@ -43,7 +43,7 @@ #define HISTB_SDIO0_BIU_CLK 21 #define HISTB_SDIO0_CIU_CLK 22 #define HISTB_SDIO0_DRV_CLK 23 -#define HISTB_SDIO0_SAMPLE_CLK 24 +#define HISTB_SDIO0_SAMPLE_CLK 24 #define HISTB_PCIE_AUX_CLK 25 #define HISTB_PCIE_PIPE_CLK 26 #define HISTB_PCIE_SYS_CLK 27 @@ -53,21 +53,22 @@ #define HISTB_ETH1_MAC_CLK 31 #define HISTB_ETH1_MACIF_CLK 32 #define HISTB_COMBPHY1_CLK 33 -#define HISTB_USB2_BUS_CLK 34 -#define HISTB_USB2_PHY_CLK 35 -#define HISTB_USB2_UTMI_CLK 36 -#define HISTB_USB2_12M_CLK 37 -#define HISTB_USB2_48M_CLK 38 -#define HISTB_USB2_OTG_UTMI_CLK 39 -#define HISTB_USB2_PHY1_REF_CLK 40 -#define HISTB_USB2_PHY2_REF_CLK 41 +#define HISTB_USB2_BUS_CLK 34 +#define HISTB_USB2_PHY_CLK 35 +#define HISTB_USB2_UTMI_CLK 36 +#define HISTB_USB2_12M_CLK 37 +#define HISTB_USB2_48M_CLK 38 +#define HISTB_USB2_OTG_UTMI_CLK 39 +#define HISTB_USB2_PHY1_REF_CLK 40 +#define HISTB_USB2_PHY2_REF_CLK 41 +#define HISTB_COMBPHY0_CLK 42 /* clocks provided by mcu CRG */ -#define HISTB_MCE_CLK 1 -#define HISTB_IR_CLK 2 -#define HISTB_TIMER01_CLK 3 -#define HISTB_LEDC_CLK 4 -#define HISTB_UART0_CLK 5 -#define HISTB_LSADC_CLK 6 +#define HISTB_MCE_CLK 1 +#define HISTB_IR_CLK 2 +#define HISTB_TIMER01_CLK 3 +#define HISTB_LEDC_CLK 4 +#define HISTB_UART0_CLK 5 +#define HISTB_LSADC_CLK 6 #endif /* __DTS_HISTB_CLOCK_H */ Index: sys/gnu/dts/include/dt-bindings/clock/imx6sll-clock.h =================================================================== --- /dev/null +++ sys/gnu/dts/include/dt-bindings/clock/imx6sll-clock.h @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP. + * + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX6SLL_H +#define __DT_BINDINGS_CLOCK_IMX6SLL_H + +#define IMX6SLL_CLK_DUMMY 0 +#define IMX6SLL_CLK_CKIL 1 +#define IMX6SLL_CLK_OSC 2 +#define IMX6SLL_PLL1_BYPASS_SRC 3 +#define IMX6SLL_PLL2_BYPASS_SRC 4 +#define IMX6SLL_PLL3_BYPASS_SRC 5 +#define IMX6SLL_PLL4_BYPASS_SRC 6 +#define IMX6SLL_PLL5_BYPASS_SRC 7 +#define IMX6SLL_PLL6_BYPASS_SRC 8 +#define IMX6SLL_PLL7_BYPASS_SRC 9 +#define IMX6SLL_CLK_PLL1 10 +#define IMX6SLL_CLK_PLL2 11 +#define IMX6SLL_CLK_PLL3 12 +#define IMX6SLL_CLK_PLL4 13 +#define IMX6SLL_CLK_PLL5 14 +#define IMX6SLL_CLK_PLL6 15 +#define IMX6SLL_CLK_PLL7 16 +#define IMX6SLL_PLL1_BYPASS 17 +#define IMX6SLL_PLL2_BYPASS 18 +#define IMX6SLL_PLL3_BYPASS 19 +#define IMX6SLL_PLL4_BYPASS 20 +#define IMX6SLL_PLL5_BYPASS 21 +#define IMX6SLL_PLL6_BYPASS 22 +#define IMX6SLL_PLL7_BYPASS 23 +#define IMX6SLL_CLK_PLL1_SYS 24 +#define IMX6SLL_CLK_PLL2_BUS 25 +#define IMX6SLL_CLK_PLL3_USB_OTG 26 +#define IMX6SLL_CLK_PLL4_AUDIO 27 +#define IMX6SLL_CLK_PLL5_VIDEO 28 +#define IMX6SLL_CLK_PLL6_ENET 29 +#define IMX6SLL_CLK_PLL7_USB_HOST 30 +#define IMX6SLL_CLK_USBPHY1 31 +#define IMX6SLL_CLK_USBPHY2 32 +#define IMX6SLL_CLK_USBPHY1_GATE 33 +#define IMX6SLL_CLK_USBPHY2_GATE 34 +#define IMX6SLL_CLK_PLL2_PFD0 35 +#define IMX6SLL_CLK_PLL2_PFD1 36 +#define IMX6SLL_CLK_PLL2_PFD2 37 +#define IMX6SLL_CLK_PLL2_PFD3 38 +#define IMX6SLL_CLK_PLL3_PFD0 39 +#define IMX6SLL_CLK_PLL3_PFD1 40 +#define IMX6SLL_CLK_PLL3_PFD2 41 +#define IMX6SLL_CLK_PLL3_PFD3 42 +#define IMX6SLL_CLK_PLL4_POST_DIV 43 +#define IMX6SLL_CLK_PLL4_AUDIO_DIV 44 +#define IMX6SLL_CLK_PLL5_POST_DIV 45 +#define IMX6SLL_CLK_PLL5_VIDEO_DIV 46 +#define IMX6SLL_CLK_PLL2_198M 47 +#define IMX6SLL_CLK_PLL3_120M 48 +#define IMX6SLL_CLK_PLL3_80M 49 +#define IMX6SLL_CLK_PLL3_60M 50 +#define IMX6SLL_CLK_STEP 51 +#define IMX6SLL_CLK_PLL1_SW 52 +#define IMX6SLL_CLK_AXI_ALT_SEL 53 +#define IMX6SLL_CLK_AXI_SEL 54 +#define IMX6SLL_CLK_PERIPH_PRE 55 +#define IMX6SLL_CLK_PERIPH2_PRE 56 +#define IMX6SLL_CLK_PERIPH_CLK2_SEL 57 +#define IMX6SLL_CLK_PERIPH2_CLK2_SEL 58 +#define IMX6SLL_CLK_PERCLK_SEL 59 +#define IMX6SLL_CLK_USDHC1_SEL 60 +#define IMX6SLL_CLK_USDHC2_SEL 61 +#define IMX6SLL_CLK_USDHC3_SEL 62 +#define IMX6SLL_CLK_SSI1_SEL 63 +#define IMX6SLL_CLK_SSI2_SEL 64 +#define IMX6SLL_CLK_SSI3_SEL 65 +#define IMX6SLL_CLK_PXP_SEL 66 +#define IMX6SLL_CLK_LCDIF_PRE_SEL 67 +#define IMX6SLL_CLK_LCDIF_SEL 68 +#define IMX6SLL_CLK_EPDC_PRE_SEL 69 +#define IMX6SLL_CLK_SPDIF_SEL 70 +#define IMX6SLL_CLK_ECSPI_SEL 71 +#define IMX6SLL_CLK_UART_SEL 72 +#define IMX6SLL_CLK_ARM 73 +#define IMX6SLL_CLK_PERIPH 74 +#define IMX6SLL_CLK_PERIPH2 75 +#define IMX6SLL_CLK_PERIPH2_CLK2 76 +#define IMX6SLL_CLK_PERIPH_CLK2 77 +#define IMX6SLL_CLK_MMDC_PODF 78 +#define IMX6SLL_CLK_AXI_PODF 79 +#define IMX6SLL_CLK_AHB 80 +#define IMX6SLL_CLK_IPG 81 +#define IMX6SLL_CLK_PERCLK 82 +#define IMX6SLL_CLK_USDHC1_PODF 83 +#define IMX6SLL_CLK_USDHC2_PODF 84 +#define IMX6SLL_CLK_USDHC3_PODF 85 +#define IMX6SLL_CLK_SSI1_PRED 86 +#define IMX6SLL_CLK_SSI2_PRED 87 +#define IMX6SLL_CLK_SSI3_PRED 88 +#define IMX6SLL_CLK_SSI1_PODF 89 +#define IMX6SLL_CLK_SSI2_PODF 90 +#define IMX6SLL_CLK_SSI3_PODF 91 +#define IMX6SLL_CLK_PXP_PODF 92 +#define IMX6SLL_CLK_LCDIF_PRED 93 +#define IMX6SLL_CLK_LCDIF_PODF 94 +#define IMX6SLL_CLK_EPDC_SEL 95 +#define IMX6SLL_CLK_EPDC_PODF 96 +#define IMX6SLL_CLK_SPDIF_PRED 97 +#define IMX6SLL_CLK_SPDIF_PODF 98 +#define IMX6SLL_CLK_ECSPI_PODF 99 +#define IMX6SLL_CLK_UART_PODF 100 + +/* CCGR 0 */ +#define IMX6SLL_CLK_AIPSTZ1 101 +#define IMX6SLL_CLK_AIPSTZ2 102 +#define IMX6SLL_CLK_DCP 103 +#define IMX6SLL_CLK_UART2_IPG 104 +#define IMX6SLL_CLK_UART2_SERIAL 105 + +/* CCGR 1 */ +#define IMX6SLL_CLK_ECSPI1 106 +#define IMX6SLL_CLK_ECSPI2 107 +#define IMX6SLL_CLK_ECSPI3 108 +#define IMX6SLL_CLK_ECSPI4 109 +#define IMX6SLL_CLK_UART3_IPG 110 +#define IMX6SLL_CLK_UART3_SERIAL 111 +#define IMX6SLL_CLK_UART4_IPG 112 +#define IMX6SLL_CLK_UART4_SERIAL 113 +#define IMX6SLL_CLK_EPIT1 114 +#define IMX6SLL_CLK_EPIT2 115 +#define IMX6SLL_CLK_GPT_BUS 116 +#define IMX6SLL_CLK_GPT_SERIAL 117 + +/* CCGR2 */ +#define IMX6SLL_CLK_CSI 118 +#define IMX6SLL_CLK_I2C1 119 +#define IMX6SLL_CLK_I2C2 120 +#define IMX6SLL_CLK_I2C3 121 +#define IMX6SLL_CLK_OCOTP 122 +#define IMX6SLL_CLK_LCDIF_APB 123 +#define IMX6SLL_CLK_PXP 124 + +/* CCGR3 */ +#define IMX6SLL_CLK_UART5_IPG 125 +#define IMX6SLL_CLK_UART5_SERIAL 126 +#define IMX6SLL_CLK_EPDC_AXI 127 +#define IMX6SLL_CLK_EPDC_PIX 128 +#define IMX6SLL_CLK_LCDIF_PIX 129 +#define IMX6SLL_CLK_WDOG1 130 +#define IMX6SLL_CLK_MMDC_P0_FAST 131 +#define IMX6SLL_CLK_MMDC_P0_IPG 132 +#define IMX6SLL_CLK_OCRAM 133 + +/* CCGR4 */ +#define IMX6SLL_CLK_PWM1 134 +#define IMX6SLL_CLK_PWM2 135 +#define IMX6SLL_CLK_PWM3 136 +#define IMX6SLL_CLK_PWM4 137 + +/* CCGR 5 */ +#define IMX6SLL_CLK_ROM 138 +#define IMX6SLL_CLK_SDMA 139 +#define IMX6SLL_CLK_KPP 140 +#define IMX6SLL_CLK_WDOG2 141 +#define IMX6SLL_CLK_SPBA 142 +#define IMX6SLL_CLK_SPDIF 143 +#define IMX6SLL_CLK_SPDIF_GCLK 144 +#define IMX6SLL_CLK_SSI1 145 +#define IMX6SLL_CLK_SSI1_IPG 146 +#define IMX6SLL_CLK_SSI2 147 +#define IMX6SLL_CLK_SSI2_IPG 148 +#define IMX6SLL_CLK_SSI3 149 +#define IMX6SLL_CLK_SSI3_IPG 150 +#define IMX6SLL_CLK_UART1_IPG 151 +#define IMX6SLL_CLK_UART1_SERIAL 152 + +/* CCGR 6 */ +#define IMX6SLL_CLK_USBOH3 153 +#define IMX6SLL_CLK_USDHC1 154 +#define IMX6SLL_CLK_USDHC2 155 +#define IMX6SLL_CLK_USDHC3 156 + +#define IMX6SLL_CLK_IPP_DI0 157 +#define IMX6SLL_CLK_IPP_DI1 158 +#define IMX6SLL_CLK_LDB_DI0_SEL 159 +#define IMX6SLL_CLK_LDB_DI0_DIV_3_5 160 +#define IMX6SLL_CLK_LDB_DI0_DIV_7 161 +#define IMX6SLL_CLK_LDB_DI0_DIV_SEL 162 +#define IMX6SLL_CLK_LDB_DI0 163 +#define IMX6SLL_CLK_LDB_DI1_SEL 164 +#define IMX6SLL_CLK_LDB_DI1_DIV_3_5 165 +#define IMX6SLL_CLK_LDB_DI1_DIV_7 166 +#define IMX6SLL_CLK_LDB_DI1_DIV_SEL 167 +#define IMX6SLL_CLK_LDB_DI1 168 +#define IMX6SLL_CLK_EXTERN_AUDIO_SEL 169 +#define IMX6SLL_CLK_EXTERN_AUDIO_PRED 170 +#define IMX6SLL_CLK_EXTERN_AUDIO_PODF 171 +#define IMX6SLL_CLK_EXTERN_AUDIO 172 + +#define IMX6SLL_CLK_END 173 + +#endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */ Index: sys/gnu/dts/include/dt-bindings/clock/imx7d-clock.h =================================================================== --- sys/gnu/dts/include/dt-bindings/clock/imx7d-clock.h +++ sys/gnu/dts/include/dt-bindings/clock/imx7d-clock.h @@ -452,5 +452,8 @@ #define IMX7D_OCOTP_CLK 439 #define IMX7D_NAND_RAWNAND_CLK 440 #define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441 -#define IMX7D_CLK_END 442 +#define IMX7D_SNVS_CLK 442 +#define IMX7D_CAAM_CLK 443 +#define IMX7D_KPP_ROOT_CLK 444 +#define IMX7D_CLK_END 445 #endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ Index: sys/gnu/dts/include/dt-bindings/clock/mt2701-clk.h =================================================================== --- sys/gnu/dts/include/dt-bindings/clock/mt2701-clk.h +++ sys/gnu/dts/include/dt-bindings/clock/mt2701-clk.h @@ -176,7 +176,8 @@ #define CLK_TOP_AUD_EXT1 156 #define CLK_TOP_AUD_EXT2 157 #define CLK_TOP_NFI1X_PAD 158 -#define CLK_TOP_NR 159 +#define CLK_TOP_AXISEL_D4 159 +#define CLK_TOP_NR 160 /* APMIXEDSYS */ Index: sys/gnu/dts/include/dt-bindings/clock/mt2712-clk.h =================================================================== --- sys/gnu/dts/include/dt-bindings/clock/mt2712-clk.h +++ sys/gnu/dts/include/dt-bindings/clock/mt2712-clk.h @@ -222,7 +222,13 @@ #define CLK_TOP_APLL_DIV_PDN5 183 #define CLK_TOP_APLL_DIV_PDN6 184 #define CLK_TOP_APLL_DIV_PDN7 185 -#define CLK_TOP_NR_CLK 186 +#define CLK_TOP_APLL1_D3 186 +#define CLK_TOP_APLL1_REF_SEL 187 +#define CLK_TOP_APLL2_REF_SEL 188 +#define CLK_TOP_NFI2X_EN 189 +#define CLK_TOP_NFIECC_EN 190 +#define CLK_TOP_NFI1X_CK_EN 191 +#define CLK_TOP_NR_CLK 192 /* INFRACFG */ @@ -281,7 +287,9 @@ #define CLK_PERI_MSDC30_3_EN 41 #define CLK_PERI_MSDC50_0_HCLK_EN 42 #define CLK_PERI_MSDC50_3_HCLK_EN 43 -#define CLK_PERI_NR_CLK 44 +#define CLK_PERI_MSDC30_0_QTR_EN 44 +#define CLK_PERI_MSDC30_3_QTR_EN 45 +#define CLK_PERI_NR_CLK 46 /* MCUCFG */ Index: sys/gnu/dts/include/dt-bindings/clock/mt7622-clk.h =================================================================== --- sys/gnu/dts/include/dt-bindings/clock/mt7622-clk.h +++ sys/gnu/dts/include/dt-bindings/clock/mt7622-clk.h @@ -235,7 +235,8 @@ #define CLK_AUDIO_MEM_ASRC3 43 #define CLK_AUDIO_MEM_ASRC4 44 #define CLK_AUDIO_MEM_ASRC5 45 -#define CLK_AUDIO_NR_CLK 46 +#define CLK_AUDIO_AFE_CONN 46 +#define CLK_AUDIO_NR_CLK 47 /* SSUSBSYS */ Index: sys/gnu/dts/include/dt-bindings/clock/qcom,rpmcc.h =================================================================== --- sys/gnu/dts/include/dt-bindings/clock/qcom,rpmcc.h +++ sys/gnu/dts/include/dt-bindings/clock/qcom,rpmcc.h @@ -40,6 +40,11 @@ #define RPM_SMI_CLK 22 #define RPM_SMI_A_CLK 23 #define RPM_PLL4_CLK 24 +#define RPM_XO_D0 25 +#define RPM_XO_D1 26 +#define RPM_XO_A0 27 +#define RPM_XO_A1 28 +#define RPM_XO_A2 29 /* SMD RPM clocks */ #define RPM_SMD_XO_CLK_SRC 0 Index: sys/gnu/dts/include/dt-bindings/clock/r8a77965-cpg-mssr.h =================================================================== --- /dev/null +++ sys/gnu/dts/include/dt-bindings/clock/r8a77965-cpg-mssr.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Jacopo Mondi + */ +#ifndef __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__ + +#include + +/* r8a77965 CPG Core Clocks */ +#define R8A77965_CLK_Z 0 +#define R8A77965_CLK_ZR 1 +#define R8A77965_CLK_ZG 2 +#define R8A77965_CLK_ZTR 3 +#define R8A77965_CLK_ZTRD2 4 +#define R8A77965_CLK_ZT 5 +#define R8A77965_CLK_ZX 6 +#define R8A77965_CLK_S0D1 7 +#define R8A77965_CLK_S0D2 8 +#define R8A77965_CLK_S0D3 9 +#define R8A77965_CLK_S0D4 10 +#define R8A77965_CLK_S0D6 11 +#define R8A77965_CLK_S0D8 12 +#define R8A77965_CLK_S0D12 13 +#define R8A77965_CLK_S1D1 14 +#define R8A77965_CLK_S1D2 15 +#define R8A77965_CLK_S1D4 16 +#define R8A77965_CLK_S2D1 17 +#define R8A77965_CLK_S2D2 18 +#define R8A77965_CLK_S2D4 19 +#define R8A77965_CLK_S3D1 20 +#define R8A77965_CLK_S3D2 21 +#define R8A77965_CLK_S3D4 22 +#define R8A77965_CLK_LB 23 +#define R8A77965_CLK_CL 24 +#define R8A77965_CLK_ZB3 25 +#define R8A77965_CLK_ZB3D2 26 +#define R8A77965_CLK_CR 27 +#define R8A77965_CLK_CRD2 28 +#define R8A77965_CLK_SD0H 29 +#define R8A77965_CLK_SD0 30 +#define R8A77965_CLK_SD1H 31 +#define R8A77965_CLK_SD1 32 +#define R8A77965_CLK_SD2H 33 +#define R8A77965_CLK_SD2 34 +#define R8A77965_CLK_SD3H 35 +#define R8A77965_CLK_SD3 36 +#define R8A77965_CLK_SSP2 37 +#define R8A77965_CLK_SSP1 38 +#define R8A77965_CLK_SSPRS 39 +#define R8A77965_CLK_RPC 40 +#define R8A77965_CLK_RPCD2 41 +#define R8A77965_CLK_MSO 42 +#define R8A77965_CLK_CANFD 43 +#define R8A77965_CLK_HDMI 44 +#define R8A77965_CLK_CSI0 45 +#define R8A77965_CLK_CP 46 +#define R8A77965_CLK_CPEX 47 +#define R8A77965_CLK_R 48 +#define R8A77965_CLK_OSC 49 + +#endif /* __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__ */ Index: sys/gnu/dts/include/dt-bindings/clock/r8a77980-cpg-mssr.h =================================================================== --- /dev/null +++ sys/gnu/dts/include/dt-bindings/clock/r8a77980-cpg-mssr.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018 Cogent Embedded, Inc. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ + +#include + +/* r8a77980 CPG Core Clocks */ +#define R8A77980_CLK_Z2 0 +#define R8A77980_CLK_ZR 1 +#define R8A77980_CLK_ZTR 2 +#define R8A77980_CLK_ZTRD2 3 +#define R8A77980_CLK_ZT 4 +#define R8A77980_CLK_ZX 5 +#define R8A77980_CLK_S0D1 6 +#define R8A77980_CLK_S0D2 7 +#define R8A77980_CLK_S0D3 8 +#define R8A77980_CLK_S0D4 9 +#define R8A77980_CLK_S0D6 10 +#define R8A77980_CLK_S0D12 11 +#define R8A77980_CLK_S0D24 12 +#define R8A77980_CLK_S1D1 13 +#define R8A77980_CLK_S1D2 14 +#define R8A77980_CLK_S1D4 15 +#define R8A77980_CLK_S2D1 16 +#define R8A77980_CLK_S2D2 17 +#define R8A77980_CLK_S2D4 18 +#define R8A77980_CLK_S3D1 19 +#define R8A77980_CLK_S3D2 20 +#define R8A77980_CLK_S3D4 21 +#define R8A77980_CLK_LB 22 +#define R8A77980_CLK_CL 23 +#define R8A77980_CLK_ZB3 24 +#define R8A77980_CLK_ZB3D2 25 +#define R8A77980_CLK_ZB3D4 26 +#define R8A77980_CLK_SD0H 27 +#define R8A77980_CLK_SD0 28 +#define R8A77980_CLK_RPC 29 +#define R8A77980_CLK_RPCD2 30 +#define R8A77980_CLK_MSO 31 +#define R8A77980_CLK_CANFD 32 +#define R8A77980_CLK_CSI0 33 +#define R8A77980_CLK_CP 34 +#define R8A77980_CLK_CPEX 35 +#define R8A77980_CLK_R 36 +#define R8A77980_CLK_OSC 37 + +#endif /* __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ */ Index: sys/gnu/dts/include/dt-bindings/clock/rk3328-cru.h =================================================================== --- sys/gnu/dts/include/dt-bindings/clock/rk3328-cru.h +++ sys/gnu/dts/include/dt-bindings/clock/rk3328-cru.h @@ -193,7 +193,6 @@ #define HCLK_VPU_PRE 324 #define HCLK_VIO_PRE 325 #define HCLK_VPU 326 -#define HCLK_VIO 327 #define HCLK_BUS_PRE 328 #define HCLK_PERI_PRE 329 #define HCLK_H264 330 Index: sys/gnu/dts/include/dt-bindings/clock/sprd,sc9860-clk.h =================================================================== --- sys/gnu/dts/include/dt-bindings/clock/sprd,sc9860-clk.h +++ sys/gnu/dts/include/dt-bindings/clock/sprd,sc9860-clk.h @@ -229,7 +229,26 @@ #define CLK_SDIO1_2X_EN 65 #define CLK_SDIO2_2X_EN 66 #define CLK_EMMC_2X_EN 67 -#define CLK_AON_GATE_NUM (CLK_EMMC_2X_EN + 1) +#define CLK_ARCH_RTC_EB 68 +#define CLK_KPB_RTC_EB 69 +#define CLK_AON_SYST_RTC_EB 70 +#define CLK_AP_SYST_RTC_EB 71 +#define CLK_AON_TMR_RTC_EB 72 +#define CLK_AP_TMR0_RTC_EB 73 +#define CLK_EIC_RTC_EB 74 +#define CLK_EIC_RTCDV5_EB 75 +#define CLK_AP_WDG_RTC_EB 76 +#define CLK_AP_TMR1_RTC_EB 77 +#define CLK_AP_TMR2_RTC_EB 78 +#define CLK_DCXO_TMR_RTC_EB 79 +#define CLK_BB_CAL_RTC_EB 80 +#define CLK_AVS_BIG_RTC_EB 81 +#define CLK_AVS_LIT_RTC_EB 82 +#define CLK_AVS_GPU0_RTC_EB 83 +#define CLK_AVS_GPU1_RTC_EB 84 +#define CLK_GPU_TS_EB 85 +#define CLK_RTCDV10_EB 86 +#define CLK_AON_GATE_NUM (CLK_RTCDV10_EB + 1) #define CLK_LIT_MCU 0 #define CLK_BIG_MCU 1 Index: sys/gnu/dts/include/dt-bindings/clock/stm32fx-clock.h =================================================================== --- sys/gnu/dts/include/dt-bindings/clock/stm32fx-clock.h +++ sys/gnu/dts/include/dt-bindings/clock/stm32fx-clock.h @@ -33,11 +33,12 @@ #define CLK_SAI2 11 #define CLK_I2SQ_PDIV 12 #define CLK_SAIQ_PDIV 13 - -#define END_PRIMARY_CLK 14 - #define CLK_HSI 14 #define CLK_SYSCLK 15 +#define CLK_F469_DSI 16 + +#define END_PRIMARY_CLK 17 + #define CLK_HDMI_CEC 16 #define CLK_SPDIF 17 #define CLK_USART1 18 Index: sys/gnu/dts/include/dt-bindings/clock/stm32mp1-clks.h =================================================================== --- /dev/null +++ sys/gnu/dts/include/dt-bindings/clock/stm32mp1-clks.h @@ -0,0 +1,254 @@ +/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ +/* + * Copyright (C) STMicroelectronics 2018 - All Rights Reserved + * Author: Gabriel Fernandez for STMicroelectronics. + */ + +#ifndef _DT_BINDINGS_STM32MP1_CLKS_H_ +#define _DT_BINDINGS_STM32MP1_CLKS_H_ + +/* OSCILLATOR clocks */ +#define CK_HSE 0 +#define CK_CSI 1 +#define CK_LSI 2 +#define CK_LSE 3 +#define CK_HSI 4 +#define CK_HSE_DIV2 5 + +/* Bus clocks */ +#define TIM2 6 +#define TIM3 7 +#define TIM4 8 +#define TIM5 9 +#define TIM6 10 +#define TIM7 11 +#define TIM12 12 +#define TIM13 13 +#define TIM14 14 +#define LPTIM1 15 +#define SPI2 16 +#define SPI3 17 +#define USART2 18 +#define USART3 19 +#define UART4 20 +#define UART5 21 +#define UART7 22 +#define UART8 23 +#define I2C1 24 +#define I2C2 25 +#define I2C3 26 +#define I2C5 27 +#define SPDIF 28 +#define CEC 29 +#define DAC12 30 +#define MDIO 31 +#define TIM1 32 +#define TIM8 33 +#define TIM15 34 +#define TIM16 35 +#define TIM17 36 +#define SPI1 37 +#define SPI4 38 +#define SPI5 39 +#define USART6 40 +#define SAI1 41 +#define SAI2 42 +#define SAI3 43 +#define DFSDM 44 +#define FDCAN 45 +#define LPTIM2 46 +#define LPTIM3 47 +#define LPTIM4 48 +#define LPTIM5 49 +#define SAI4 50 +#define SYSCFG 51 +#define VREF 52 +#define TMPSENS 53 +#define PMBCTRL 54 +#define HDP 55 +#define LTDC 56 +#define DSI 57 +#define IWDG2 58 +#define USBPHY 59 +#define STGENRO 60 +#define SPI6 61 +#define I2C4 62 +#define I2C6 63 +#define USART1 64 +#define RTCAPB 65 +#define TZC1 66 +#define TZPC 67 +#define IWDG1 68 +#define BSEC 69 +#define STGEN 70 +#define DMA1 71 +#define DMA2 72 +#define DMAMUX 73 +#define ADC12 74 +#define USBO 75 +#define SDMMC3 76 +#define DCMI 77 +#define CRYP2 78 +#define HASH2 79 +#define RNG2 80 +#define CRC2 81 +#define HSEM 82 +#define IPCC 83 +#define GPIOA 84 +#define GPIOB 85 +#define GPIOC 86 +#define GPIOD 87 +#define GPIOE 88 +#define GPIOF 89 +#define GPIOG 90 +#define GPIOH 91 +#define GPIOI 92 +#define GPIOJ 93 +#define GPIOK 94 +#define GPIOZ 95 +#define CRYP1 96 +#define HASH1 97 +#define RNG1 98 +#define BKPSRAM 99 +#define MDMA 100 +#define GPU 101 +#define ETHCK 102 +#define ETHTX 103 +#define ETHRX 104 +#define ETHMAC 105 +#define FMC 106 +#define QSPI 107 +#define SDMMC1 108 +#define SDMMC2 109 +#define CRC1 110 +#define USBH 111 +#define ETHSTP 112 +#define TZC2 113 + +/* Kernel clocks */ +#define SDMMC1_K 118 +#define SDMMC2_K 119 +#define SDMMC3_K 120 +#define FMC_K 121 +#define QSPI_K 122 +#define ETHCK_K 123 +#define RNG1_K 124 +#define RNG2_K 125 +#define GPU_K 126 +#define USBPHY_K 127 +#define STGEN_K 128 +#define SPDIF_K 129 +#define SPI1_K 130 +#define SPI2_K 131 +#define SPI3_K 132 +#define SPI4_K 133 +#define SPI5_K 134 +#define SPI6_K 135 +#define CEC_K 136 +#define I2C1_K 137 +#define I2C2_K 138 +#define I2C3_K 139 +#define I2C4_K 140 +#define I2C5_K 141 +#define I2C6_K 142 +#define LPTIM1_K 143 +#define LPTIM2_K 144 +#define LPTIM3_K 145 +#define LPTIM4_K 146 +#define LPTIM5_K 147 +#define USART1_K 148 +#define USART2_K 149 +#define USART3_K 150 +#define UART4_K 151 +#define UART5_K 152 +#define USART6_K 153 +#define UART7_K 154 +#define UART8_K 155 +#define DFSDM_K 156 +#define FDCAN_K 157 +#define SAI1_K 158 +#define SAI2_K 159 +#define SAI3_K 160 +#define SAI4_K 161 +#define ADC12_K 162 +#define DSI_K 163 +#define DSI_PX 164 +#define ADFSDM_K 165 +#define USBO_K 166 +#define LTDC_PX 167 +#define DAC12_K 168 +#define ETHPTP_K 169 + +/* PLL */ +#define PLL1 176 +#define PLL2 177 +#define PLL3 178 +#define PLL4 179 + +/* ODF */ +#define PLL1_P 180 +#define PLL1_Q 181 +#define PLL1_R 182 +#define PLL2_P 183 +#define PLL2_Q 184 +#define PLL2_R 185 +#define PLL3_P 186 +#define PLL3_Q 187 +#define PLL3_R 188 +#define PLL4_P 189 +#define PLL4_Q 190 +#define PLL4_R 191 + +/* AUX */ +#define RTC 192 + +/* MCLK */ +#define CK_PER 193 +#define CK_MPU 194 +#define CK_AXI 195 +#define CK_MCU 196 + +/* Time base */ +#define TIM2_K 197 +#define TIM3_K 198 +#define TIM4_K 199 +#define TIM5_K 200 +#define TIM6_K 201 +#define TIM7_K 202 +#define TIM12_K 203 +#define TIM13_K 204 +#define TIM14_K 205 +#define TIM1_K 206 +#define TIM8_K 207 +#define TIM15_K 208 +#define TIM16_K 209 +#define TIM17_K 210 + +/* MCO clocks */ +#define CK_MCO1 211 +#define CK_MCO2 212 + +/* TRACE & DEBUG clocks */ +#define CK_DBG 214 +#define CK_TRACE 215 + +/* DDR */ +#define DDRC1 220 +#define DDRC1LP 221 +#define DDRC2 222 +#define DDRC2LP 223 +#define DDRPHYC 224 +#define DDRPHYCLP 225 +#define DDRCAPB 226 +#define DDRCAPBLP 227 +#define AXIDCG 228 +#define DDRPHYCAPB 229 +#define DDRPHYCAPBLP 230 +#define DDRPERFM 231 + +#define STM32MP1_LAST_CLK 232 + +#define LTDC_K LTDC_PX +#define ETHMAC_K ETHCK_K + +#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */ Index: sys/gnu/dts/include/dt-bindings/clock/stratix10-clock.h =================================================================== --- /dev/null +++ sys/gnu/dts/include/dt-bindings/clock/stratix10-clock.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017, Intel Corporation + */ + +#ifndef __STRATIX10_CLOCK_H +#define __STRATIX10_CLOCK_H + +/* fixed rate clocks */ +#define STRATIX10_OSC1 0 +#define STRATIX10_CB_INTOSC_HS_DIV2_CLK 1 +#define STRATIX10_CB_INTOSC_LS_CLK 2 +#define STRATIX10_F2S_FREE_CLK 3 + +/* fixed factor clocks */ +#define STRATIX10_L4_SYS_FREE_CLK 4 +#define STRATIX10_MPU_PERIPH_CLK 5 +#define STRATIX10_MPU_L2RAM_CLK 6 +#define STRATIX10_SDMMC_CIU_CLK 7 + +/* PLL clocks */ +#define STRATIX10_MAIN_PLL_CLK 8 +#define STRATIX10_PERIPH_PLL_CLK 9 +#define STRATIX10_BOOT_CLK 10 + +/* Periph clocks */ +#define STRATIX10_MAIN_MPU_BASE_CLK 11 +#define STRATIX10_MAIN_NOC_BASE_CLK 12 +#define STRATIX10_MAIN_EMACA_CLK 13 +#define STRATIX10_MAIN_EMACB_CLK 14 +#define STRATIX10_MAIN_EMAC_PTP_CLK 15 +#define STRATIX10_MAIN_GPIO_DB_CLK 16 +#define STRATIX10_MAIN_SDMMC_CLK 17 +#define STRATIX10_MAIN_S2F_USR0_CLK 18 +#define STRATIX10_MAIN_S2F_USR1_CLK 19 +#define STRATIX10_MAIN_PSI_REF_CLK 20 + +#define STRATIX10_PERI_MPU_BASE_CLK 21 +#define STRATIX10_PERI_NOC_BASE_CLK 22 +#define STRATIX10_PERI_EMACA_CLK 23 +#define STRATIX10_PERI_EMACB_CLK 24 +#define STRATIX10_PERI_EMAC_PTP_CLK 25 +#define STRATIX10_PERI_GPIO_DB_CLK 26 +#define STRATIX10_PERI_SDMMC_CLK 27 +#define STRATIX10_PERI_S2F_USR0_CLK 28 +#define STRATIX10_PERI_S2F_USR1_CLK 29 +#define STRATIX10_PERI_PSI_REF_CLK 30 + +#define STRATIX10_MPU_FREE_CLK 31 +#define STRATIX10_NOC_FREE_CLK 32 +#define STRATIX10_S2F_USR0_CLK 33 +#define STRATIX10_NOC_CLK 34 +#define STRATIX10_EMAC_A_FREE_CLK 35 +#define STRATIX10_EMAC_B_FREE_CLK 36 +#define STRATIX10_EMAC_PTP_FREE_CLK 37 +#define STRATIX10_GPIO_DB_FREE_CLK 38 +#define STRATIX10_SDMMC_FREE_CLK 39 +#define STRATIX10_S2F_USER1_FREE_CLK 40 +#define STRATIX10_PSI_REF_FREE_CLK 41 + +/* Gate clocks */ +#define STRATIX10_MPU_CLK 42 +#define STRATIX10_L4_MAIN_CLK 43 +#define STRATIX10_L4_MP_CLK 44 +#define STRATIX10_L4_SP_CLK 45 +#define STRATIX10_CS_AT_CLK 46 +#define STRATIX10_CS_TRACE_CLK 47 +#define STRATIX10_CS_PDBG_CLK 48 +#define STRATIX10_CS_TIMER_CLK 49 +#define STRATIX10_S2F_USER0_CLK 50 +#define STRATIX10_S2F_USER1_CLK 51 +#define STRATIX10_EMAC0_CLK 52 +#define STRATIX10_EMAC1_CLK 53 +#define STRATIX10_EMAC2_CLK 54 +#define STRATIX10_EMAC_PTP_CLK 55 +#define STRATIX10_GPIO_DB_CLK 56 +#define STRATIX10_SDMMC_CLK 57 +#define STRATIX10_PSI_REF_CLK 58 +#define STRATIX10_USB_CLK 59 +#define STRATIX10_SPI_M_CLK 60 +#define STRATIX10_NAND_CLK 61 +#define STRATIX10_NUM_CLKS 62 + +#endif /* __STRATIX10_CLOCK_H */ Index: sys/gnu/dts/include/dt-bindings/clock/sun50i-h6-ccu.h =================================================================== --- /dev/null +++ sys/gnu/dts/include/dt-bindings/clock/sun50i-h6-ccu.h @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2017 Icenowy Zheng + */ + +#ifndef _DT_BINDINGS_CLK_SUN50I_H6_H_ +#define _DT_BINDINGS_CLK_SUN50I_H6_H_ + +#define CLK_PLL_PERIPH0 3 + +#define CLK_CPUX 21 + +#define CLK_APB1 26 + +#define CLK_DE 29 +#define CLK_BUS_DE 30 +#define CLK_DEINTERLACE 31 +#define CLK_BUS_DEINTERLACE 32 +#define CLK_GPU 33 +#define CLK_BUS_GPU 34 +#define CLK_CE 35 +#define CLK_BUS_CE 36 +#define CLK_VE 37 +#define CLK_BUS_VE 38 +#define CLK_EMCE 39 +#define CLK_BUS_EMCE 40 +#define CLK_VP9 41 +#define CLK_BUS_VP9 42 +#define CLK_BUS_DMA 43 +#define CLK_BUS_MSGBOX 44 +#define CLK_BUS_SPINLOCK 45 +#define CLK_BUS_HSTIMER 46 +#define CLK_AVS 47 +#define CLK_BUS_DBG 48 +#define CLK_BUS_PSI 49 +#define CLK_BUS_PWM 50 +#define CLK_BUS_IOMMU 51 + +#define CLK_MBUS_DMA 53 +#define CLK_MBUS_VE 54 +#define CLK_MBUS_CE 55 +#define CLK_MBUS_TS 56 +#define CLK_MBUS_NAND 57 +#define CLK_MBUS_CSI 58 +#define CLK_MBUS_DEINTERLACE 59 + +#define CLK_NAND0 61 +#define CLK_NAND1 62 +#define CLK_BUS_NAND 63 +#define CLK_MMC0 64 +#define CLK_MMC1 65 +#define CLK_MMC2 66 +#define CLK_BUS_MMC0 67 +#define CLK_BUS_MMC1 68 +#define CLK_BUS_MMC2 69 +#define CLK_BUS_UART0 70 +#define CLK_BUS_UART1 71 +#define CLK_BUS_UART2 72 +#define CLK_BUS_UART3 73 +#define CLK_BUS_I2C0 74 +#define CLK_BUS_I2C1 75 +#define CLK_BUS_I2C2 76 +#define CLK_BUS_I2C3 77 +#define CLK_BUS_SCR0 78 +#define CLK_BUS_SCR1 79 +#define CLK_SPI0 80 +#define CLK_SPI1 81 +#define CLK_BUS_SPI0 82 +#define CLK_BUS_SPI1 83 +#define CLK_BUS_EMAC 84 +#define CLK_TS 85 +#define CLK_BUS_TS 86 +#define CLK_IR_TX 87 +#define CLK_BUS_IR_TX 88 +#define CLK_BUS_THS 89 +#define CLK_I2S3 90 +#define CLK_I2S0 91 +#define CLK_I2S1 92 +#define CLK_I2S2 93 +#define CLK_BUS_I2S0 94 +#define CLK_BUS_I2S1 95 +#define CLK_BUS_I2S2 96 +#define CLK_BUS_I2S3 97 +#define CLK_SPDIF 98 +#define CLK_BUS_SPDIF 99 +#define CLK_DMIC 100 +#define CLK_BUS_DMIC 101 +#define CLK_AUDIO_HUB 102 +#define CLK_BUS_AUDIO_HUB 103 +#define CLK_USB_OHCI0 104 +#define CLK_USB_PHY0 105 +#define CLK_USB_PHY1 106 +#define CLK_USB_OHCI3 107 +#define CLK_USB_PHY3 108 +#define CLK_USB_HSIC_12M 109 +#define CLK_USB_HSIC 110 +#define CLK_BUS_OHCI0 111 +#define CLK_BUS_OHCI3 112 +#define CLK_BUS_EHCI0 113 +#define CLK_BUS_XHCI 114 +#define CLK_BUS_EHCI3 115 +#define CLK_BUS_OTG 116 +#define CLK_PCIE_REF_100M 117 +#define CLK_PCIE_REF 118 +#define CLK_PCIE_REF_OUT 119 +#define CLK_PCIE_MAXI 120 +#define CLK_PCIE_AUX 121 +#define CLK_BUS_PCIE 122 +#define CLK_HDMI 123 +#define CLK_HDMI_SLOW 124 +#define CLK_HDMI_CEC 125 +#define CLK_BUS_HDMI 126 +#define CLK_BUS_TCON_TOP 127 +#define CLK_TCON_LCD0 128 +#define CLK_BUS_TCON_LCD0 129 +#define CLK_TCON_TV0 130 +#define CLK_BUS_TCON_TV0 131 +#define CLK_CSI_CCI 132 +#define CLK_CSI_TOP 133 +#define CLK_CSI_MCLK 134 +#define CLK_BUS_CSI 135 +#define CLK_HDCP 136 +#define CLK_BUS_HDCP 137 + +#endif /* _DT_BINDINGS_CLK_SUN50I_H6_H_ */ Index: sys/gnu/dts/include/dt-bindings/clock/sun8i-h3-ccu.h =================================================================== --- sys/gnu/dts/include/dt-bindings/clock/sun8i-h3-ccu.h +++ sys/gnu/dts/include/dt-bindings/clock/sun8i-h3-ccu.h @@ -43,6 +43,8 @@ #ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_ #define _DT_BINDINGS_CLK_SUN8I_H3_H_ +#define CLK_PLL_VIDEO 6 + #define CLK_PLL_PERIPH0 9 #define CLK_CPUX 14 Index: sys/gnu/dts/include/dt-bindings/clock/tegra194-clock.h =================================================================== --- /dev/null +++ sys/gnu/dts/include/dt-bindings/clock/tegra194-clock.h @@ -0,0 +1,321 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */ + +#ifndef __ABI_MACH_T194_CLOCK_H +#define __ABI_MACH_T194_CLOCK_H + +#define TEGRA194_CLK_ACTMON 1 +#define TEGRA194_CLK_ADSP 2 +#define TEGRA194_CLK_ADSPNEON 3 +#define TEGRA194_CLK_AHUB 4 +#define TEGRA194_CLK_APB2APE 5 +#define TEGRA194_CLK_APE 6 +#define TEGRA194_CLK_AUD_MCLK 7 +#define TEGRA194_CLK_AXI_CBB 8 +#define TEGRA194_CLK_CAN1 9 +#define TEGRA194_CLK_CAN1_HOST 10 +#define TEGRA194_CLK_CAN2 11 +#define TEGRA194_CLK_CAN2_HOST 12 +#define TEGRA194_CLK_CEC 13 +#define TEGRA194_CLK_CLK_M 14 +#define TEGRA194_CLK_DMIC1 15 +#define TEGRA194_CLK_DMIC2 16 +#define TEGRA194_CLK_DMIC3 17 +#define TEGRA194_CLK_DMIC4 18 +#define TEGRA194_CLK_DPAUX 19 +#define TEGRA194_CLK_DPAUX1 20 +#define TEGRA194_CLK_ACLK 21 +#define TEGRA194_CLK_MSS_ENCRYPT 22 +#define TEGRA194_CLK_EQOS_RX_INPUT 23 +#define TEGRA194_CLK_IQC2 24 +#define TEGRA194_CLK_AON_APB 25 +#define TEGRA194_CLK_AON_NIC 26 +#define TEGRA194_CLK_AON_CPU_NIC 27 +#define TEGRA194_CLK_PLLA1 28 +#define TEGRA194_CLK_DSPK1 29 +#define TEGRA194_CLK_DSPK2 30 +#define TEGRA194_CLK_EMC 31 +#define TEGRA194_CLK_EQOS_AXI 32 +#define TEGRA194_CLK_EQOS_PTP_REF 33 +#define TEGRA194_CLK_EQOS_RX 34 +#define TEGRA194_CLK_EQOS_TX 35 +#define TEGRA194_CLK_EXTPERIPH1 36 +#define TEGRA194_CLK_EXTPERIPH2 37 +#define TEGRA194_CLK_EXTPERIPH3 38 +#define TEGRA194_CLK_EXTPERIPH4 39 +#define TEGRA194_CLK_FUSE 40 +#define TEGRA194_CLK_GPCCLK 41 +#define TEGRA194_CLK_GPU_PWR 42 +#define TEGRA194_CLK_HDA 43 +#define TEGRA194_CLK_HDA2CODEC_2X 44 +#define TEGRA194_CLK_HDA2HDMICODEC 45 +#define TEGRA194_CLK_HOST1X 46 +#define TEGRA194_CLK_HSIC_TRK 47 +#define TEGRA194_CLK_I2C1 48 +#define TEGRA194_CLK_I2C2 49 +#define TEGRA194_CLK_I2C3 50 +#define TEGRA194_CLK_I2C4 51 +#define TEGRA194_CLK_I2C6 52 +#define TEGRA194_CLK_I2C7 53 +#define TEGRA194_CLK_I2C8 54 +#define TEGRA194_CLK_I2C9 55 +#define TEGRA194_CLK_I2S1 56 +#define TEGRA194_CLK_I2S1_SYNC_INPUT 57 +#define TEGRA194_CLK_I2S2 58 +#define TEGRA194_CLK_I2S2_SYNC_INPUT 59 +#define TEGRA194_CLK_I2S3 60 +#define TEGRA194_CLK_I2S3_SYNC_INPUT 61 +#define TEGRA194_CLK_I2S4 62 +#define TEGRA194_CLK_I2S4_SYNC_INPUT 63 +#define TEGRA194_CLK_I2S5 64 +#define TEGRA194_CLK_I2S5_SYNC_INPUT 65 +#define TEGRA194_CLK_I2S6 66 +#define TEGRA194_CLK_I2S6_SYNC_INPUT 67 +#define TEGRA194_CLK_IQC1 68 +#define TEGRA194_CLK_ISP 69 +#define TEGRA194_CLK_KFUSE 70 +#define TEGRA194_CLK_MAUD 71 +#define TEGRA194_CLK_MIPI_CAL 72 +#define TEGRA194_CLK_MPHY_CORE_PLL_FIXED 73 +#define TEGRA194_CLK_MPHY_L0_RX_ANA 74 +#define TEGRA194_CLK_MPHY_L0_RX_LS_BIT 75 +#define TEGRA194_CLK_MPHY_L0_RX_SYMB 76 +#define TEGRA194_CLK_MPHY_L0_TX_LS_3XBIT 77 +#define TEGRA194_CLK_MPHY_L0_TX_SYMB 78 +#define TEGRA194_CLK_MPHY_L1_RX_ANA 79 +#define TEGRA194_CLK_MPHY_TX_1MHZ_REF 80 +#define TEGRA194_CLK_NVCSI 81 +#define TEGRA194_CLK_NVCSILP 82 +#define TEGRA194_CLK_NVDEC 83 +#define TEGRA194_CLK_NVDISPLAYHUB 84 +#define TEGRA194_CLK_NVDISPLAY_DISP 85 +#define TEGRA194_CLK_NVDISPLAY_P0 86 +#define TEGRA194_CLK_NVDISPLAY_P1 87 +#define TEGRA194_CLK_NVDISPLAY_P2 88 +#define TEGRA194_CLK_NVENC 89 +#define TEGRA194_CLK_NVJPG 90 +#define TEGRA194_CLK_OSC 91 +#define TEGRA194_CLK_AON_TOUCH 92 +#define TEGRA194_CLK_PLLA 93 +#define TEGRA194_CLK_PLLAON 94 +#define TEGRA194_CLK_PLLD 95 +#define TEGRA194_CLK_PLLD2 96 +#define TEGRA194_CLK_PLLD3 97 +#define TEGRA194_CLK_PLLDP 98 +#define TEGRA194_CLK_PLLD4 99 +#define TEGRA194_CLK_PLLE 100 +#define TEGRA194_CLK_PLLP 101 +#define TEGRA194_CLK_PLLP_OUT0 102 +#define TEGRA194_CLK_UTMIPLL 103 +#define TEGRA194_CLK_PLLA_OUT0 104 +#define TEGRA194_CLK_PWM1 105 +#define TEGRA194_CLK_PWM2 106 +#define TEGRA194_CLK_PWM3 107 +#define TEGRA194_CLK_PWM4 108 +#define TEGRA194_CLK_PWM5 109 +#define TEGRA194_CLK_PWM6 110 +#define TEGRA194_CLK_PWM7 111 +#define TEGRA194_CLK_PWM8 112 +#define TEGRA194_CLK_RCE_CPU_NIC 113 +#define TEGRA194_CLK_RCE_NIC 114 +#define TEGRA194_CLK_SATA 115 +#define TEGRA194_CLK_SATA_OOB 116 +#define TEGRA194_CLK_AON_I2C_SLOW 117 +#define TEGRA194_CLK_SCE_CPU_NIC 118 +#define TEGRA194_CLK_SCE_NIC 119 +#define TEGRA194_CLK_SDMMC1 120 +#define TEGRA194_CLK_UPHY_PLL3 121 +#define TEGRA194_CLK_SDMMC3 122 +#define TEGRA194_CLK_SDMMC4 123 +#define TEGRA194_CLK_SE 124 +#define TEGRA194_CLK_SOR0_OUT 125 +#define TEGRA194_CLK_SOR0_REF 126 +#define TEGRA194_CLK_SOR0_PAD_CLKOUT 127 +#define TEGRA194_CLK_SOR1_OUT 128 +#define TEGRA194_CLK_SOR1_REF 129 +#define TEGRA194_CLK_SOR1_PAD_CLKOUT 130 +#define TEGRA194_CLK_SOR_SAFE 131 +#define TEGRA194_CLK_IQC1_IN 132 +#define TEGRA194_CLK_IQC2_IN 133 +#define TEGRA194_CLK_DMIC5 134 +#define TEGRA194_CLK_SPI1 135 +#define TEGRA194_CLK_SPI2 136 +#define TEGRA194_CLK_SPI3 137 +#define TEGRA194_CLK_I2C_SLOW 138 +#define TEGRA194_CLK_SYNC_DMIC1 139 +#define TEGRA194_CLK_SYNC_DMIC2 140 +#define TEGRA194_CLK_SYNC_DMIC3 141 +#define TEGRA194_CLK_SYNC_DMIC4 142 +#define TEGRA194_CLK_SYNC_DSPK1 143 +#define TEGRA194_CLK_SYNC_DSPK2 144 +#define TEGRA194_CLK_SYNC_I2S1 145 +#define TEGRA194_CLK_SYNC_I2S2 146 +#define TEGRA194_CLK_SYNC_I2S3 147 +#define TEGRA194_CLK_SYNC_I2S4 148 +#define TEGRA194_CLK_SYNC_I2S5 149 +#define TEGRA194_CLK_SYNC_I2S6 150 +#define TEGRA194_CLK_MPHY_FORCE_LS_MODE 151 +#define TEGRA194_CLK_TACH 152 +#define TEGRA194_CLK_TSEC 153 +#define TEGRA194_CLK_TSECB 154 +#define TEGRA194_CLK_UARTA 155 +#define TEGRA194_CLK_UARTB 156 +#define TEGRA194_CLK_UARTC 157 +#define TEGRA194_CLK_UARTD 158 +#define TEGRA194_CLK_UARTE 159 +#define TEGRA194_CLK_UARTF 160 +#define TEGRA194_CLK_UARTG 161 +#define TEGRA194_CLK_UART_FST_MIPI_CAL 162 +#define TEGRA194_CLK_UFSDEV_REF 163 +#define TEGRA194_CLK_UFSHC 164 +#define TEGRA194_CLK_USB2_TRK 165 +#define TEGRA194_CLK_VI 166 +#define TEGRA194_CLK_VIC 167 +#define TEGRA194_CLK_PVA0_AXI 168 +#define TEGRA194_CLK_PVA0_VPS0 169 +#define TEGRA194_CLK_PVA0_VPS1 170 +#define TEGRA194_CLK_PVA1_AXI 171 +#define TEGRA194_CLK_PVA1_VPS0 172 +#define TEGRA194_CLK_PVA1_VPS1 173 +#define TEGRA194_CLK_DLA0_FALCON 174 +#define TEGRA194_CLK_DLA0_CORE 175 +#define TEGRA194_CLK_DLA1_FALCON 176 +#define TEGRA194_CLK_DLA1_CORE 177 +#define TEGRA194_CLK_SOR2_OUT 178 +#define TEGRA194_CLK_SOR2_REF 179 +#define TEGRA194_CLK_SOR2_PAD_CLKOUT 180 +#define TEGRA194_CLK_SOR3_OUT 181 +#define TEGRA194_CLK_SOR3_REF 182 +#define TEGRA194_CLK_SOR3_PAD_CLKOUT 183 +#define TEGRA194_CLK_NVDISPLAY_P3 184 +#define TEGRA194_CLK_DPAUX2 185 +#define TEGRA194_CLK_DPAUX3 186 +#define TEGRA194_CLK_NVDEC1 187 +#define TEGRA194_CLK_NVENC1 188 +#define TEGRA194_CLK_SE_FREE 189 +#define TEGRA194_CLK_UARTH 190 +#define TEGRA194_CLK_FUSE_SERIAL 191 +#define TEGRA194_CLK_QSPI0 192 +#define TEGRA194_CLK_QSPI1 193 +#define TEGRA194_CLK_QSPI0_PM 194 +#define TEGRA194_CLK_QSPI1_PM 195 +#define TEGRA194_CLK_VI_CONST 196 +#define TEGRA194_CLK_NAFLL_BPMP 197 +#define TEGRA194_CLK_NAFLL_SCE 198 +#define TEGRA194_CLK_NAFLL_NVDEC 199 +#define TEGRA194_CLK_NAFLL_NVJPG 200 +#define TEGRA194_CLK_NAFLL_TSEC 201 +#define TEGRA194_CLK_NAFLL_TSECB 202 +#define TEGRA194_CLK_NAFLL_VI 203 +#define TEGRA194_CLK_NAFLL_SE 204 +#define TEGRA194_CLK_NAFLL_NVENC 205 +#define TEGRA194_CLK_NAFLL_ISP 206 +#define TEGRA194_CLK_NAFLL_VIC 207 +#define TEGRA194_CLK_NAFLL_NVDISPLAYHUB 208 +#define TEGRA194_CLK_NAFLL_AXICBB 209 +#define TEGRA194_CLK_NAFLL_DLA 210 +#define TEGRA194_CLK_NAFLL_PVA_CORE 211 +#define TEGRA194_CLK_NAFLL_PVA_VPS 212 +#define TEGRA194_CLK_NAFLL_CVNAS 213 +#define TEGRA194_CLK_NAFLL_RCE 214 +#define TEGRA194_CLK_NAFLL_NVENC1 215 +#define TEGRA194_CLK_NAFLL_DLA_FALCON 216 +#define TEGRA194_CLK_NAFLL_NVDEC1 217 +#define TEGRA194_CLK_NAFLL_GPU 218 +#define TEGRA194_CLK_SDMMC_LEGACY_TM 219 +#define TEGRA194_CLK_PEX0_CORE_0 220 +#define TEGRA194_CLK_PEX0_CORE_1 221 +#define TEGRA194_CLK_PEX0_CORE_2 222 +#define TEGRA194_CLK_PEX0_CORE_3 223 +#define TEGRA194_CLK_PEX0_CORE_4 224 +#define TEGRA194_CLK_PEX1_CORE_5 225 +#define TEGRA194_CLK_PEX_REF1 226 +#define TEGRA194_CLK_PEX_REF2 227 +#define TEGRA194_CLK_CSI_A 229 +#define TEGRA194_CLK_CSI_B 230 +#define TEGRA194_CLK_CSI_C 231 +#define TEGRA194_CLK_CSI_D 232 +#define TEGRA194_CLK_CSI_E 233 +#define TEGRA194_CLK_CSI_F 234 +#define TEGRA194_CLK_CSI_G 235 +#define TEGRA194_CLK_CSI_H 236 +#define TEGRA194_CLK_PLLC4 237 +#define TEGRA194_CLK_PLLC4_OUT 238 +#define TEGRA194_CLK_PLLC4_OUT1 239 +#define TEGRA194_CLK_PLLC4_OUT2 240 +#define TEGRA194_CLK_PLLC4_MUXED 241 +#define TEGRA194_CLK_PLLC4_VCO_DIV2 242 +#define TEGRA194_CLK_CSI_A_PAD 244 +#define TEGRA194_CLK_CSI_B_PAD 245 +#define TEGRA194_CLK_CSI_C_PAD 246 +#define TEGRA194_CLK_CSI_D_PAD 247 +#define TEGRA194_CLK_CSI_E_PAD 248 +#define TEGRA194_CLK_CSI_F_PAD 249 +#define TEGRA194_CLK_CSI_G_PAD 250 +#define TEGRA194_CLK_CSI_H_PAD 251 +#define TEGRA194_CLK_PEX_SATA_USB_RX_BYP 254 +#define TEGRA194_CLK_PEX_USB_PAD_PLL0_MGMT 255 +#define TEGRA194_CLK_PEX_USB_PAD_PLL1_MGMT 256 +#define TEGRA194_CLK_PEX_USB_PAD_PLL2_MGMT 257 +#define TEGRA194_CLK_PEX_USB_PAD_PLL3_MGMT 258 +#define TEGRA194_CLK_XUSB_CORE_DEV 265 +#define TEGRA194_CLK_XUSB_CORE_MUX 266 +#define TEGRA194_CLK_XUSB_CORE_HOST 267 +#define TEGRA194_CLK_XUSB_CORE_SS 268 +#define TEGRA194_CLK_XUSB_FALCON 269 +#define TEGRA194_CLK_XUSB_FALCON_HOST 270 +#define TEGRA194_CLK_XUSB_FALCON_SS 271 +#define TEGRA194_CLK_XUSB_FS 272 +#define TEGRA194_CLK_XUSB_FS_HOST 273 +#define TEGRA194_CLK_XUSB_FS_DEV 274 +#define TEGRA194_CLK_XUSB_SS 275 +#define TEGRA194_CLK_XUSB_SS_DEV 276 +#define TEGRA194_CLK_XUSB_SS_SUPERSPEED 277 +#define TEGRA194_CLK_PLLDISPHUB 278 +#define TEGRA194_CLK_PLLDISPHUB_DIV 279 +#define TEGRA194_CLK_NAFLL_CLUSTER0 280 +#define TEGRA194_CLK_NAFLL_CLUSTER1 281 +#define TEGRA194_CLK_NAFLL_CLUSTER2 282 +#define TEGRA194_CLK_NAFLL_CLUSTER3 283 +#define TEGRA194_CLK_CAN1_CORE 284 +#define TEGRA194_CLK_CAN2_CORE 285 +#define TEGRA194_CLK_PLLA1_OUT1 286 +#define TEGRA194_CLK_PLLREFE_VCOOUT 288 +#define TEGRA194_CLK_CLK_32K 289 +#define TEGRA194_CLK_SPDIFIN_SYNC_INPUT 290 +#define TEGRA194_CLK_UTMIPLL_CLKOUT48 291 +#define TEGRA194_CLK_UTMIPLL_CLKOUT480 292 +#define TEGRA194_CLK_CVNAS 293 +#define TEGRA194_CLK_PLLNVCSI 294 +#define TEGRA194_CLK_PVA0_CPU_AXI 295 +#define TEGRA194_CLK_PVA1_CPU_AXI 296 +#define TEGRA194_CLK_PVA0_VPS 297 +#define TEGRA194_CLK_PVA1_VPS 298 +#define TEGRA194_CLK_DLA0_FALCON_MUX 299 +#define TEGRA194_CLK_DLA1_FALCON_MUX 300 +#define TEGRA194_CLK_DLA0_CORE_MUX 301 +#define TEGRA194_CLK_DLA1_CORE_MUX 302 +#define TEGRA194_CLK_UTMIPLL_HPS 304 +#define TEGRA194_CLK_I2C5 305 +#define TEGRA194_CLK_I2C10 306 +#define TEGRA194_CLK_BPMP_CPU_NIC 307 +#define TEGRA194_CLK_BPMP_APB 308 +#define TEGRA194_CLK_TSC 309 +#define TEGRA194_CLK_EMCSA 310 +#define TEGRA194_CLK_EMCSB 311 +#define TEGRA194_CLK_EMCSC 312 +#define TEGRA194_CLK_EMCSD 313 +#define TEGRA194_CLK_PLLC 314 +#define TEGRA194_CLK_PLLC2 315 +#define TEGRA194_CLK_PLLC3 316 +#define TEGRA194_CLK_TSC_REF 317 +#define TEGRA194_CLK_FUSE_BURN 318 +#define TEGRA194_CLK_PEX0_CORE_0M 319 +#define TEGRA194_CLK_PEX0_CORE_1M 320 +#define TEGRA194_CLK_PEX0_CORE_2M 321 +#define TEGRA194_CLK_PEX0_CORE_3M 322 +#define TEGRA194_CLK_PEX0_CORE_4M 323 +#define TEGRA194_CLK_PEX1_CORE_5M 324 +#define TEGRA194_CLK_PLLE_HPS 326 + +#endif Index: sys/gnu/dts/include/dt-bindings/clock/tegra210-car.h =================================================================== --- sys/gnu/dts/include/dt-bindings/clock/tegra210-car.h +++ sys/gnu/dts/include/dt-bindings/clock/tegra210-car.h @@ -95,7 +95,7 @@ #define TEGRA210_CLK_CSITE 73 /* 74 */ /* 75 */ -/* 76 */ +#define TEGRA210_CLK_LA 76 /* 77 */ #define TEGRA210_CLK_SOC_THERM 78 #define TEGRA210_CLK_DTV 79 Index: sys/gnu/dts/include/dt-bindings/gpio/meson8b-gpio.h =================================================================== --- sys/gnu/dts/include/dt-bindings/gpio/meson8b-gpio.h +++ sys/gnu/dts/include/dt-bindings/gpio/meson8b-gpio.h @@ -15,18 +15,113 @@ #ifndef _DT_BINDINGS_MESON8B_GPIO_H #define _DT_BINDINGS_MESON8B_GPIO_H -#include - -/* GPIO Bank DIF */ -#define DIF_0_P 120 -#define DIF_0_N 121 -#define DIF_1_P 122 -#define DIF_1_N 123 -#define DIF_2_P 124 -#define DIF_2_N 125 -#define DIF_3_P 126 -#define DIF_3_N 127 -#define DIF_4_P 128 -#define DIF_4_N 129 +/* EE (CBUS) GPIO chip */ +#define GPIOX_0 0 +#define GPIOX_1 1 +#define GPIOX_2 2 +#define GPIOX_3 3 +#define GPIOX_4 4 +#define GPIOX_5 5 +#define GPIOX_6 6 +#define GPIOX_7 7 +#define GPIOX_8 8 +#define GPIOX_9 9 +#define GPIOX_10 10 +#define GPIOX_11 11 +#define GPIOX_16 12 +#define GPIOX_17 13 +#define GPIOX_18 14 +#define GPIOX_19 15 +#define GPIOX_20 16 +#define GPIOX_21 17 + +#define GPIOY_0 18 +#define GPIOY_1 19 +#define GPIOY_3 20 +#define GPIOY_6 21 +#define GPIOY_7 22 +#define GPIOY_8 23 +#define GPIOY_9 24 +#define GPIOY_10 25 +#define GPIOY_11 26 +#define GPIOY_12 27 +#define GPIOY_13 28 +#define GPIOY_14 29 + +#define GPIODV_9 30 +#define GPIODV_24 31 +#define GPIODV_25 32 +#define GPIODV_26 33 +#define GPIODV_27 34 +#define GPIODV_28 35 +#define GPIODV_29 36 + +#define GPIOH_0 37 +#define GPIOH_1 38 +#define GPIOH_2 39 +#define GPIOH_3 40 +#define GPIOH_4 41 +#define GPIOH_5 42 +#define GPIOH_6 43 +#define GPIOH_7 44 +#define GPIOH_8 45 +#define GPIOH_9 46 + +#define CARD_0 47 +#define CARD_1 48 +#define CARD_2 49 +#define CARD_3 50 +#define CARD_4 51 +#define CARD_5 52 +#define CARD_6 53 + +#define BOOT_0 54 +#define BOOT_1 55 +#define BOOT_2 56 +#define BOOT_3 57 +#define BOOT_4 58 +#define BOOT_5 59 +#define BOOT_6 60 +#define BOOT_7 61 +#define BOOT_8 62 +#define BOOT_9 63 +#define BOOT_10 64 +#define BOOT_11 65 +#define BOOT_12 66 +#define BOOT_13 67 +#define BOOT_14 68 +#define BOOT_15 69 +#define BOOT_16 70 +#define BOOT_17 71 +#define BOOT_18 72 + +#define DIF_0_P 73 +#define DIF_0_N 74 +#define DIF_1_P 75 +#define DIF_1_N 76 +#define DIF_2_P 77 +#define DIF_2_N 78 +#define DIF_3_P 79 +#define DIF_3_N 80 +#define DIF_4_P 81 +#define DIF_4_N 82 + +/* AO GPIO chip */ +#define GPIOAO_0 0 +#define GPIOAO_1 1 +#define GPIOAO_2 2 +#define GPIOAO_3 3 +#define GPIOAO_4 4 +#define GPIOAO_5 5 +#define GPIOAO_6 6 +#define GPIOAO_7 7 +#define GPIOAO_8 8 +#define GPIOAO_9 9 +#define GPIOAO_10 10 +#define GPIOAO_11 11 +#define GPIOAO_12 12 +#define GPIOAO_13 13 +#define GPIO_BSD_EN 14 +#define GPIO_TEST_N 15 #endif /* _DT_BINDINGS_MESON8B_GPIO_H */ Index: sys/gnu/dts/include/dt-bindings/gpio/tegra194-gpio.h =================================================================== --- /dev/null +++ sys/gnu/dts/include/dt-bindings/gpio/tegra194-gpio.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */ + +/* + * This header provides constants for binding nvidia,tegra194-gpio*. + * + * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below + * provide names for this. + * + * The second cell contains standard flag values specified in gpio.h. + */ + +#ifndef _DT_BINDINGS_GPIO_TEGRA194_GPIO_H +#define _DT_BINDINGS_GPIO_TEGRA194_GPIO_H + +#include + +/* GPIOs implemented by main GPIO controller */ +#define TEGRA194_MAIN_GPIO_PORT_A 0 +#define TEGRA194_MAIN_GPIO_PORT_B 1 +#define TEGRA194_MAIN_GPIO_PORT_C 2 +#define TEGRA194_MAIN_GPIO_PORT_D 3 +#define TEGRA194_MAIN_GPIO_PORT_E 4 +#define TEGRA194_MAIN_GPIO_PORT_F 5 +#define TEGRA194_MAIN_GPIO_PORT_G 6 +#define TEGRA194_MAIN_GPIO_PORT_H 7 +#define TEGRA194_MAIN_GPIO_PORT_I 8 +#define TEGRA194_MAIN_GPIO_PORT_J 9 +#define TEGRA194_MAIN_GPIO_PORT_K 10 +#define TEGRA194_MAIN_GPIO_PORT_L 11 +#define TEGRA194_MAIN_GPIO_PORT_M 12 +#define TEGRA194_MAIN_GPIO_PORT_N 13 +#define TEGRA194_MAIN_GPIO_PORT_O 14 +#define TEGRA194_MAIN_GPIO_PORT_P 15 +#define TEGRA194_MAIN_GPIO_PORT_Q 16 +#define TEGRA194_MAIN_GPIO_PORT_R 17 +#define TEGRA194_MAIN_GPIO_PORT_S 18 +#define TEGRA194_MAIN_GPIO_PORT_T 19 +#define TEGRA194_MAIN_GPIO_PORT_U 20 +#define TEGRA194_MAIN_GPIO_PORT_V 21 +#define TEGRA194_MAIN_GPIO_PORT_W 22 +#define TEGRA194_MAIN_GPIO_PORT_X 23 +#define TEGRA194_MAIN_GPIO_PORT_Y 24 +#define TEGRA194_MAIN_GPIO_PORT_Z 25 +#define TEGRA194_MAIN_GPIO_PORT_FF 26 +#define TEGRA194_MAIN_GPIO_PORT_GG 27 + +#define TEGRA194_MAIN_GPIO(port, offset) \ + ((TEGRA194_MAIN_GPIO_PORT_##port * 8) + offset) + +/* GPIOs implemented by AON GPIO controller */ +#define TEGRA194_AON_GPIO_PORT_AA 0 +#define TEGRA194_AON_GPIO_PORT_BB 1 +#define TEGRA194_AON_GPIO_PORT_CC 2 +#define TEGRA194_AON_GPIO_PORT_DD 3 +#define TEGRA194_AON_GPIO_PORT_EE 4 + +#define TEGRA194_AON_GPIO(port, offset) \ + ((TEGRA194_AON_GPIO_PORT_##port * 8) + offset) + +#endif Index: sys/gnu/dts/include/dt-bindings/input/gpio-keys.h =================================================================== --- /dev/null +++ sys/gnu/dts/include/dt-bindings/input/gpio-keys.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for gpio keys bindings. + */ + +#ifndef _DT_BINDINGS_GPIO_KEYS_H +#define _DT_BINDINGS_GPIO_KEYS_H + +#define EV_ACT_ANY 0x00 /* asserted or deasserted */ +#define EV_ACT_ASSERTED 0x01 /* asserted */ +#define EV_ACT_DEASSERTED 0x02 /* deasserted */ + +#endif /* _DT_BINDINGS_GPIO_KEYS_H */ Index: sys/gnu/dts/include/dt-bindings/media/tda1997x.h =================================================================== --- /dev/null +++ sys/gnu/dts/include/dt-bindings/media/tda1997x.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017 Gateworks Corporation + */ +#ifndef _DT_BINDINGS_MEDIA_TDA1997X_H +#define _DT_BINDINGS_MEDIA_TDA1997X_H + +/* TDA19973 36bit Video Port control registers */ +#define TDA1997X_VP36_35_32 0 +#define TDA1997X_VP36_31_28 1 +#define TDA1997X_VP36_27_24 2 +#define TDA1997X_VP36_23_20 3 +#define TDA1997X_VP36_19_16 4 +#define TDA1997X_VP36_15_12 5 +#define TDA1997X_VP36_11_08 6 +#define TDA1997X_VP36_07_04 7 +#define TDA1997X_VP36_03_00 8 + +/* TDA19971 24bit Video Port control registers */ +#define TDA1997X_VP24_V23_20 0 +#define TDA1997X_VP24_V19_16 1 +#define TDA1997X_VP24_V15_12 3 +#define TDA1997X_VP24_V11_08 4 +#define TDA1997X_VP24_V07_04 6 +#define TDA1997X_VP24_V03_00 7 + +/* Pin groups */ +#define TDA1997X_VP_OUT_EN 0x80 /* enable output group */ +#define TDA1997X_VP_HIZ 0x40 /* hi-Z output group when not used */ +#define TDA1997X_VP_SWP 0x10 /* pin-swap output group */ +#define TDA1997X_R_CR_CBCR_3_0 (0 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_R_CR_CBCR_7_4 (1 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_R_CR_CBCR_11_8 (2 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_B_CB_3_0 (3 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_B_CB_7_4 (4 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_B_CB_11_8 (5 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_G_Y_3_0 (6 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_G_Y_7_4 (7 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_G_Y_11_8 (8 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +/* pinswapped groups */ +#define TDA1997X_R_CR_CBCR_3_0_S (TDA1997X_R_CR_CBCR_3_0 | TDA1997X_VP_SWAP) +#define TDA1997X_R_CR_CBCR_7_4_S (TDA1997X_R_CR_CBCR_7_4 | TDA1997X_VP_SWAP) +#define TDA1997X_R_CR_CBCR_11_8_S (TDA1997X_R_CR_CBCR_11_8 | TDA1997X_VP_SWAP) +#define TDA1997X_B_CB_3_0_S (TDA1997X_B_CB_3_0 | TDA1997X_VP_SWAP) +#define TDA1997X_B_CB_7_4_S (TDA1997X_B_CB_7_4 | TDA1997X_VP_SWAP) +#define TDA1997X_B_CB_11_8_S (TDA1997X_B_CB_11_8 | TDA1997X_VP_SWAP) +#define TDA1997X_G_Y_3_0_S (TDA1997X_G_Y_3_0 | TDA1997X_VP_SWAP) +#define TDA1997X_G_Y_7_4_S (TDA1997X_G_Y_7_4 | TDA1997X_VP_SWAP) +#define TDA1997X_G_Y_11_8_S (TDA1997X_G_Y_11_8 | TDA1997X_VP_SWAP) + +/* Audio bus DAI format */ +#define TDA1997X_I2S16 1 /* I2S 16bit */ +#define TDA1997X_I2S32 2 /* I2S 32bit */ +#define TDA1997X_SPDIF 3 /* SPDIF */ +#define TDA1997X_OBA 4 /* One Bit Audio */ +#define TDA1997X_DST 5 /* Direct Stream Transfer */ +#define TDA1997X_I2S16_HBR 6 /* HBR straight in I2S 16bit mode */ +#define TDA1997X_I2S16_HBR_DEMUX 7 /* HBR demux in I2S 16bit mode */ +#define TDA1997X_I2S32_HBR_DEMUX 8 /* HBR demux in I2S 32bit mode */ +#define TDA1997X_SPDIF_HBR_DEMUX 9 /* HBR demux in SPDIF mode */ + +/* Audio bus channel layout */ +#define TDA1997X_LAYOUT0 0 /* 2-channel */ +#define TDA1997X_LAYOUT1 1 /* 8-channel */ + +/* Audio bus clock */ +#define TDA1997X_ACLK_16FS 0 +#define TDA1997X_ACLK_32FS 1 +#define TDA1997X_ACLK_64FS 2 +#define TDA1997X_ACLK_128FS 3 +#define TDA1997X_ACLK_256FS 4 +#define TDA1997X_ACLK_512FS 5 + +#endif /* _DT_BINDINGS_MEDIA_TDA1997X_H */ Index: sys/gnu/dts/include/dt-bindings/mfd/stm32f7-rcc.h =================================================================== --- sys/gnu/dts/include/dt-bindings/mfd/stm32f7-rcc.h +++ sys/gnu/dts/include/dt-bindings/mfd/stm32f7-rcc.h @@ -91,6 +91,7 @@ #define STM32F7_RCC_APB2_TIM8 1 #define STM32F7_RCC_APB2_USART1 4 #define STM32F7_RCC_APB2_USART6 5 +#define STM32F7_RCC_APB2_SDMMC2 7 #define STM32F7_RCC_APB2_ADC1 8 #define STM32F7_RCC_APB2_ADC2 9 #define STM32F7_RCC_APB2_ADC3 10 Index: sys/gnu/dts/include/dt-bindings/net/ti-dp83867.h =================================================================== --- sys/gnu/dts/include/dt-bindings/net/ti-dp83867.h +++ sys/gnu/dts/include/dt-bindings/net/ti-dp83867.h @@ -42,4 +42,18 @@ #define DP83867_RGMIIDCTL_3_75_NS 0xe #define DP83867_RGMIIDCTL_4_00_NS 0xf +/* IO_MUX_CFG - Clock output selection */ +#define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0 +#define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1 +#define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2 +#define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3 +#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 +#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 +#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 +#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 +#define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8 +#define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9 +#define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA +#define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB +#define DP83867_CLK_O_SEL_REF_CLK 0xC #endif Index: sys/gnu/dts/include/dt-bindings/pinctrl/mt7623-pinfunc.h =================================================================== --- sys/gnu/dts/include/dt-bindings/pinctrl/mt7623-pinfunc.h +++ sys/gnu/dts/include/dt-bindings/pinctrl/mt7623-pinfunc.h @@ -251,6 +251,12 @@ #define MT7623_PIN_76_SCL0_FUNC_GPIO76 (MTK_PIN_NO(76) | 0) #define MT7623_PIN_76_SCL0_FUNC_SCL0 (MTK_PIN_NO(76) | 1) +#define MT7623_PIN_77_SDA2_FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define MT7623_PIN_77_SDA2_FUNC_SDA2 (MTK_PIN_NO(77) | 1) + +#define MT7623_PIN_78_SCL2_FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define MT7623_PIN_78_SCL2_FUNC_SCL2 (MTK_PIN_NO(78) | 1) + #define MT7623_PIN_79_URXD0_FUNC_GPIO79 (MTK_PIN_NO(79) | 0) #define MT7623_PIN_79_URXD0_FUNC_URXD0 (MTK_PIN_NO(79) | 1) #define MT7623_PIN_79_URXD0_FUNC_UTXD0 (MTK_PIN_NO(79) | 2) @@ -291,6 +297,24 @@ #define MT7623_PIN_100_MIPI_TDP0_FUNC_GPIO100 (MTK_PIN_NO(100) | 0) #define MT7623_PIN_100_MIPI_TDP0_FUNC_TDP0 (MTK_PIN_NO(100) | 1) +#define MT7623_PIN_101_SPI2_CSN_FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define MT7623_PIN_101_SPI2_CSN_FUNC_SPI2_CS (MTK_PIN_NO(101) | 1) +#define MT7623_PIN_101_SPI2_CSN_FUNC_SCL3 (MTK_PIN_NO(101) | 3) + +#define MT7623_PIN_102_SPI2_MI_FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define MT7623_PIN_102_SPI2_MI_FUNC_SPI2_MI (MTK_PIN_NO(102) | 1) +#define MT7623_PIN_102_SPI2_MI_FUNC_SPI2_MO (MTK_PIN_NO(102) | 2) +#define MT7623_PIN_102_SPI2_MI_FUNC_SDA3 (MTK_PIN_NO(102) | 3) + +#define MT7623_PIN_103_SPI2_MO_FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define MT7623_PIN_103_SPI2_MO_FUNC_SPI2_MO (MTK_PIN_NO(103) | 1) +#define MT7623_PIN_103_SPI2_MO_FUNC_SPI2_MI (MTK_PIN_NO(103) | 2) +#define MT7623_PIN_103_SPI2_MO_FUNC_SCL3 (MTK_PIN_NO(103) | 3) + +#define MT7623_PIN_104_SPI2_CK_FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define MT7623_PIN_104_SPI2_CK_FUNC_SPI2_CK (MTK_PIN_NO(104) | 1) +#define MT7623_PIN_104_SPI2_CK_FUNC_SDA3 (MTK_PIN_NO(104) | 3) + #define MT7623_PIN_105_MSDC1_CMD_FUNC_GPIO105 (MTK_PIN_NO(105) | 0) #define MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD (MTK_PIN_NO(105) | 1) #define MT7623_PIN_105_MSDC1_CMD_FUNC_SDA1 (MTK_PIN_NO(105) | 3) Index: sys/gnu/dts/include/dt-bindings/power/mt2712-power.h =================================================================== --- sys/gnu/dts/include/dt-bindings/power/mt2712-power.h +++ sys/gnu/dts/include/dt-bindings/power/mt2712-power.h @@ -22,5 +22,8 @@ #define MT2712_POWER_DOMAIN_USB 5 #define MT2712_POWER_DOMAIN_USB2 6 #define MT2712_POWER_DOMAIN_MFG 7 +#define MT2712_POWER_DOMAIN_MFG_SC1 8 +#define MT2712_POWER_DOMAIN_MFG_SC2 9 +#define MT2712_POWER_DOMAIN_MFG_SC3 10 #endif /* _DT_BINDINGS_POWER_MT2712_POWER_H */ Index: sys/gnu/dts/include/dt-bindings/power/mt7623a-power.h =================================================================== --- /dev/null +++ sys/gnu/dts/include/dt-bindings/power/mt7623a-power.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _DT_BINDINGS_POWER_MT7623A_POWER_H +#define _DT_BINDINGS_POWER_MT7623A_POWER_H + +#define MT7623A_POWER_DOMAIN_CONN 0 +#define MT7623A_POWER_DOMAIN_ETH 1 +#define MT7623A_POWER_DOMAIN_HIF 2 +#define MT7623A_POWER_DOMAIN_IFR_MSC 3 + +#endif /* _DT_BINDINGS_POWER_MT7623A_POWER_H */ Index: sys/gnu/dts/include/dt-bindings/power/r8a77965-sysc.h =================================================================== --- /dev/null +++ sys/gnu/dts/include/dt-bindings/power/r8a77965-sysc.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Jacopo Mondi + * Copyright (C) 2016 Glider bvba + */ + +#ifndef __DT_BINDINGS_POWER_R8A77965_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A77965_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A77965_PD_CA57_CPU0 0 +#define R8A77965_PD_CA57_CPU1 1 +#define R8A77965_PD_A3VP 9 +#define R8A77965_PD_CA57_SCU 12 +#define R8A77965_PD_CR7 13 +#define R8A77965_PD_A3VC 14 +#define R8A77965_PD_3DG_A 17 +#define R8A77965_PD_3DG_B 18 +#define R8A77965_PD_A3IR 24 +#define R8A77965_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A77965_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A77965_SYSC_H__ */ Index: sys/gnu/dts/include/dt-bindings/power/r8a77980-sysc.h =================================================================== --- /dev/null +++ sys/gnu/dts/include/dt-bindings/power/r8a77980-sysc.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018 Cogent Embedded, Inc. + */ +#ifndef __DT_BINDINGS_POWER_R8A77980_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A77980_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A77980_PD_A2SC2 0 +#define R8A77980_PD_A2SC3 1 +#define R8A77980_PD_A2SC4 2 +#define R8A77980_PD_A2PD0 3 +#define R8A77980_PD_A2PD1 4 +#define R8A77980_PD_CA53_CPU0 5 +#define R8A77980_PD_CA53_CPU1 6 +#define R8A77980_PD_CA53_CPU2 7 +#define R8A77980_PD_CA53_CPU3 8 +#define R8A77980_PD_A2CN 10 +#define R8A77980_PD_A3VIP 11 +#define R8A77980_PD_A2IR5 12 +#define R8A77980_PD_CR7 13 +#define R8A77980_PD_A2IR4 15 +#define R8A77980_PD_CA53_SCU 21 +#define R8A77980_PD_A2IR0 23 +#define R8A77980_PD_A3IR 24 +#define R8A77980_PD_A3VIP1 25 +#define R8A77980_PD_A3VIP2 26 +#define R8A77980_PD_A2IR1 27 +#define R8A77980_PD_A2IR2 28 +#define R8A77980_PD_A2IR3 29 +#define R8A77980_PD_A2SC0 30 +#define R8A77980_PD_A2SC1 31 + +/* Always-on power area */ +#define R8A77980_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A77980_SYSC_H__ */ Index: sys/gnu/dts/include/dt-bindings/power/tegra194-powergate.h =================================================================== --- /dev/null +++ sys/gnu/dts/include/dt-bindings/power/tegra194-powergate.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */ + +#ifndef __ABI_MACH_T194_POWERGATE_T194_H_ +#define __ABI_MACH_T194_POWERGATE_T194_H_ + +#define TEGRA194_POWER_DOMAIN_AUD 1 +#define TEGRA194_POWER_DOMAIN_DISP 2 +#define TEGRA194_POWER_DOMAIN_DISPB 3 +#define TEGRA194_POWER_DOMAIN_DISPC 4 +#define TEGRA194_POWER_DOMAIN_ISPA 5 +#define TEGRA194_POWER_DOMAIN_NVDECA 6 +#define TEGRA194_POWER_DOMAIN_NVJPG 7 +#define TEGRA194_POWER_DOMAIN_NVENCA 8 +#define TEGRA194_POWER_DOMAIN_NVENCB 9 +#define TEGRA194_POWER_DOMAIN_NVDECB 10 +#define TEGRA194_POWER_DOMAIN_SAX 11 +#define TEGRA194_POWER_DOMAIN_VE 12 +#define TEGRA194_POWER_DOMAIN_VIC 13 +#define TEGRA194_POWER_DOMAIN_XUSBA 14 +#define TEGRA194_POWER_DOMAIN_XUSBB 15 +#define TEGRA194_POWER_DOMAIN_XUSBC 16 +#define TEGRA194_POWER_DOMAIN_PCIEX8A 17 +#define TEGRA194_POWER_DOMAIN_PCIEX4A 18 +#define TEGRA194_POWER_DOMAIN_PCIEX1A 19 +#define TEGRA194_POWER_DOMAIN_PCIEX8B 21 +#define TEGRA194_POWER_DOMAIN_PVAA 22 +#define TEGRA194_POWER_DOMAIN_PVAB 23 +#define TEGRA194_POWER_DOMAIN_DLAA 24 +#define TEGRA194_POWER_DOMAIN_DLAB 25 +#define TEGRA194_POWER_DOMAIN_CV 26 +#define TEGRA194_POWER_DOMAIN_GPU 27 +#define TEGRA194_POWER_DOMAIN_MAX 27 + +#endif Index: sys/gnu/dts/include/dt-bindings/reset/stm32mp1-resets.h =================================================================== --- /dev/null +++ sys/gnu/dts/include/dt-bindings/reset/stm32mp1-resets.h @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ +/* + * Copyright (C) STMicroelectronics 2018 - All Rights Reserved + * Author: Gabriel Fernandez for STMicroelectronics. + */ + +#ifndef _DT_BINDINGS_STM32MP1_RESET_H_ +#define _DT_BINDINGS_STM32MP1_RESET_H_ + +#define LTDC_R 3072 +#define DSI_R 3076 +#define DDRPERFM_R 3080 +#define USBPHY_R 3088 +#define SPI6_R 3136 +#define I2C4_R 3138 +#define I2C6_R 3139 +#define USART1_R 3140 +#define STGEN_R 3156 +#define GPIOZ_R 3200 +#define CRYP1_R 3204 +#define HASH1_R 3205 +#define RNG1_R 3206 +#define AXIM_R 3216 +#define GPU_R 3269 +#define ETHMAC_R 3274 +#define FMC_R 3276 +#define QSPI_R 3278 +#define SDMMC1_R 3280 +#define SDMMC2_R 3281 +#define CRC1_R 3284 +#define USBH_R 3288 +#define MDMA_R 3328 +#define MCU_R 8225 +#define TIM2_R 19456 +#define TIM3_R 19457 +#define TIM4_R 19458 +#define TIM5_R 19459 +#define TIM6_R 19460 +#define TIM7_R 19461 +#define TIM12_R 16462 +#define TIM13_R 16463 +#define TIM14_R 16464 +#define LPTIM1_R 19465 +#define SPI2_R 19467 +#define SPI3_R 19468 +#define USART2_R 19470 +#define USART3_R 19471 +#define UART4_R 19472 +#define UART5_R 19473 +#define UART7_R 19474 +#define UART8_R 19475 +#define I2C1_R 19477 +#define I2C2_R 19478 +#define I2C3_R 19479 +#define I2C5_R 19480 +#define SPDIF_R 19482 +#define CEC_R 19483 +#define DAC12_R 19485 +#define MDIO_R 19847 +#define TIM1_R 19520 +#define TIM8_R 19521 +#define TIM15_R 19522 +#define TIM16_R 19523 +#define TIM17_R 19524 +#define SPI1_R 19528 +#define SPI4_R 19529 +#define SPI5_R 19530 +#define USART6_R 19533 +#define SAI1_R 19536 +#define SAI2_R 19537 +#define SAI3_R 19538 +#define DFSDM_R 19540 +#define FDCAN_R 19544 +#define LPTIM2_R 19584 +#define LPTIM3_R 19585 +#define LPTIM4_R 19586 +#define LPTIM5_R 19587 +#define SAI4_R 19592 +#define SYSCFG_R 19595 +#define VREF_R 19597 +#define TMPSENS_R 19600 +#define PMBCTRL_R 19601 +#define DMA1_R 19648 +#define DMA2_R 19649 +#define DMAMUX_R 19650 +#define ADC12_R 19653 +#define USBO_R 19656 +#define SDMMC3_R 19664 +#define CAMITF_R 19712 +#define CRYP2_R 19716 +#define HASH2_R 19717 +#define RNG2_R 19718 +#define CRC2_R 19719 +#define HSEM_R 19723 +#define MBOX_R 19724 +#define GPIOA_R 19776 +#define GPIOB_R 19777 +#define GPIOC_R 19778 +#define GPIOD_R 19779 +#define GPIOE_R 19780 +#define GPIOF_R 19781 +#define GPIOG_R 19782 +#define GPIOH_R 19783 +#define GPIOI_R 19784 +#define GPIOJ_R 19785 +#define GPIOK_R 19786 + +#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */ Index: sys/gnu/dts/include/dt-bindings/reset/sun50i-h6-ccu.h =================================================================== --- /dev/null +++ sys/gnu/dts/include/dt-bindings/reset/sun50i-h6-ccu.h @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2017 Icenowy Zheng + */ + +#ifndef _DT_BINDINGS_RESET_SUN50I_H6_H_ +#define _DT_BINDINGS_RESET_SUN50I_H6_H_ + +#define RST_MBUS 0 +#define RST_BUS_DE 1 +#define RST_BUS_DEINTERLACE 2 +#define RST_BUS_GPU 3 +#define RST_BUS_CE 4 +#define RST_BUS_VE 5 +#define RST_BUS_EMCE 6 +#define RST_BUS_VP9 7 +#define RST_BUS_DMA 8 +#define RST_BUS_MSGBOX 9 +#define RST_BUS_SPINLOCK 10 +#define RST_BUS_HSTIMER 11 +#define RST_BUS_DBG 12 +#define RST_BUS_PSI 13 +#define RST_BUS_PWM 14 +#define RST_BUS_IOMMU 15 +#define RST_BUS_DRAM 16 +#define RST_BUS_NAND 17 +#define RST_BUS_MMC0 18 +#define RST_BUS_MMC1 19 +#define RST_BUS_MMC2 20 +#define RST_BUS_UART0 21 +#define RST_BUS_UART1 22 +#define RST_BUS_UART2 23 +#define RST_BUS_UART3 24 +#define RST_BUS_I2C0 25 +#define RST_BUS_I2C1 26 +#define RST_BUS_I2C2 27 +#define RST_BUS_I2C3 28 +#define RST_BUS_SCR0 29 +#define RST_BUS_SCR1 30 +#define RST_BUS_SPI0 31 +#define RST_BUS_SPI1 32 +#define RST_BUS_EMAC 33 +#define RST_BUS_TS 34 +#define RST_BUS_IR_TX 35 +#define RST_BUS_THS 36 +#define RST_BUS_I2S0 37 +#define RST_BUS_I2S1 38 +#define RST_BUS_I2S2 39 +#define RST_BUS_I2S3 40 +#define RST_BUS_SPDIF 41 +#define RST_BUS_DMIC 42 +#define RST_BUS_AUDIO_HUB 43 +#define RST_USB_PHY0 44 +#define RST_USB_PHY1 45 +#define RST_USB_PHY3 46 +#define RST_USB_HSIC 47 +#define RST_BUS_OHCI0 48 +#define RST_BUS_OHCI3 49 +#define RST_BUS_EHCI0 50 +#define RST_BUS_XHCI 51 +#define RST_BUS_EHCI3 52 +#define RST_BUS_OTG 53 +#define RST_BUS_PCIE 54 +#define RST_PCIE_POWERUP 55 +#define RST_BUS_HDMI 56 +#define RST_BUS_HDMI_SUB 57 +#define RST_BUS_TCON_TOP 58 +#define RST_BUS_TCON_LCD0 59 +#define RST_BUS_TCON_TV0 60 +#define RST_BUS_CSI 61 +#define RST_BUS_HDCP 62 + +#endif /* _DT_BINDINGS_RESET_SUN50I_H6_H_ */ Index: sys/gnu/dts/include/dt-bindings/reset/tegra194-reset.h =================================================================== --- /dev/null +++ sys/gnu/dts/include/dt-bindings/reset/tegra194-reset.h @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */ + +#ifndef __ABI_MACH_T194_RESET_H +#define __ABI_MACH_T194_RESET_H + +#define TEGRA194_RESET_ACTMON 1 +#define TEGRA194_RESET_ADSP_ALL 2 +#define TEGRA194_RESET_AFI 3 +#define TEGRA194_RESET_CAN1 4 +#define TEGRA194_RESET_CAN2 5 +#define TEGRA194_RESET_DLA0 6 +#define TEGRA194_RESET_DLA1 7 +#define TEGRA194_RESET_DPAUX 8 +#define TEGRA194_RESET_DPAUX1 9 +#define TEGRA194_RESET_DPAUX2 10 +#define TEGRA194_RESET_DPAUX3 11 +#define TEGRA194_RESET_EQOS 17 +#define TEGRA194_RESET_GPCDMA 18 +#define TEGRA194_RESET_GPU 19 +#define TEGRA194_RESET_HDA 20 +#define TEGRA194_RESET_HDA2CODEC_2X 21 +#define TEGRA194_RESET_HDA2HDMICODEC 22 +#define TEGRA194_RESET_HOST1X 23 +#define TEGRA194_RESET_I2C1 24 +#define TEGRA194_RESET_I2C10 25 +#define TEGRA194_RESET_RSVD_26 26 +#define TEGRA194_RESET_RSVD_27 27 +#define TEGRA194_RESET_RSVD_28 28 +#define TEGRA194_RESET_I2C2 29 +#define TEGRA194_RESET_I2C3 30 +#define TEGRA194_RESET_I2C4 31 +#define TEGRA194_RESET_I2C6 32 +#define TEGRA194_RESET_I2C7 33 +#define TEGRA194_RESET_I2C8 34 +#define TEGRA194_RESET_I2C9 35 +#define TEGRA194_RESET_ISP 36 +#define TEGRA194_RESET_MIPI_CAL 37 +#define TEGRA194_RESET_MPHY_CLK_CTL 38 +#define TEGRA194_RESET_MPHY_L0_RX 39 +#define TEGRA194_RESET_MPHY_L0_TX 40 +#define TEGRA194_RESET_MPHY_L1_RX 41 +#define TEGRA194_RESET_MPHY_L1_TX 42 +#define TEGRA194_RESET_NVCSI 43 +#define TEGRA194_RESET_NVDEC 44 +#define TEGRA194_RESET_NVDISPLAY0_HEAD0 45 +#define TEGRA194_RESET_NVDISPLAY0_HEAD1 46 +#define TEGRA194_RESET_NVDISPLAY0_HEAD2 47 +#define TEGRA194_RESET_NVDISPLAY0_HEAD3 48 +#define TEGRA194_RESET_NVDISPLAY0_MISC 49 +#define TEGRA194_RESET_NVDISPLAY0_WGRP0 50 +#define TEGRA194_RESET_NVDISPLAY0_WGRP1 51 +#define TEGRA194_RESET_NVDISPLAY0_WGRP2 52 +#define TEGRA194_RESET_NVDISPLAY0_WGRP3 53 +#define TEGRA194_RESET_NVDISPLAY0_WGRP4 54 +#define TEGRA194_RESET_NVDISPLAY0_WGRP5 55 +#define TEGRA194_RESET_RSVD_56 56 +#define TEGRA194_RESET_RSVD_57 57 +#define TEGRA194_RESET_RSVD_58 58 +#define TEGRA194_RESET_NVENC 59 +#define TEGRA194_RESET_NVENC1 60 +#define TEGRA194_RESET_NVJPG 61 +#define TEGRA194_RESET_PCIE 62 +#define TEGRA194_RESET_PCIEXCLK 63 +#define TEGRA194_RESET_RSVD_64 64 +#define TEGRA194_RESET_RSVD_65 65 +#define TEGRA194_RESET_PVA0_ALL 66 +#define TEGRA194_RESET_PVA1_ALL 67 +#define TEGRA194_RESET_PWM1 68 +#define TEGRA194_RESET_PWM2 69 +#define TEGRA194_RESET_PWM3 70 +#define TEGRA194_RESET_PWM4 71 +#define TEGRA194_RESET_PWM5 72 +#define TEGRA194_RESET_PWM6 73 +#define TEGRA194_RESET_PWM7 74 +#define TEGRA194_RESET_PWM8 75 +#define TEGRA194_RESET_QSPI0 76 +#define TEGRA194_RESET_QSPI1 77 +#define TEGRA194_RESET_SATA 78 +#define TEGRA194_RESET_SATACOLD 79 +#define TEGRA194_RESET_SCE_ALL 80 +#define TEGRA194_RESET_RCE_ALL 81 +#define TEGRA194_RESET_SDMMC1 82 +#define TEGRA194_RESET_RSVD_83 83 +#define TEGRA194_RESET_SDMMC3 84 +#define TEGRA194_RESET_SDMMC4 85 +#define TEGRA194_RESET_SE 86 +#define TEGRA194_RESET_SOR0 87 +#define TEGRA194_RESET_SOR1 88 +#define TEGRA194_RESET_SOR2 89 +#define TEGRA194_RESET_SOR3 90 +#define TEGRA194_RESET_SPI1 91 +#define TEGRA194_RESET_SPI2 92 +#define TEGRA194_RESET_SPI3 93 +#define TEGRA194_RESET_SPI4 94 +#define TEGRA194_RESET_TACH 95 +#define TEGRA194_RESET_RSVD_96 96 +#define TEGRA194_RESET_TSCTNVI 97 +#define TEGRA194_RESET_TSEC 98 +#define TEGRA194_RESET_TSECB 99 +#define TEGRA194_RESET_UARTA 100 +#define TEGRA194_RESET_UARTB 101 +#define TEGRA194_RESET_UARTC 102 +#define TEGRA194_RESET_UARTD 103 +#define TEGRA194_RESET_UARTE 104 +#define TEGRA194_RESET_UARTF 105 +#define TEGRA194_RESET_UARTG 106 +#define TEGRA194_RESET_UARTH 107 +#define TEGRA194_RESET_UFSHC 108 +#define TEGRA194_RESET_UFSHC_AXI_M 109 +#define TEGRA194_RESET_UFSHC_LP_SEQ 110 +#define TEGRA194_RESET_RSVD_111 111 +#define TEGRA194_RESET_VI 112 +#define TEGRA194_RESET_VIC 113 +#define TEGRA194_RESET_XUSB_PADCTL 114 +#define TEGRA194_RESET_NVDEC1 115 +#define TEGRA194_RESET_PEX0_CORE_0 116 +#define TEGRA194_RESET_PEX0_CORE_1 117 +#define TEGRA194_RESET_PEX0_CORE_2 118 +#define TEGRA194_RESET_PEX0_CORE_3 119 +#define TEGRA194_RESET_PEX0_CORE_4 120 +#define TEGRA194_RESET_PEX0_CORE_0_APB 121 +#define TEGRA194_RESET_PEX0_CORE_1_APB 122 +#define TEGRA194_RESET_PEX0_CORE_2_APB 123 +#define TEGRA194_RESET_PEX0_CORE_3_APB 124 +#define TEGRA194_RESET_PEX0_CORE_4_APB 125 +#define TEGRA194_RESET_PEX0_COMMON_APB 126 +#define TEGRA194_RESET_PEX1_CORE_5 129 +#define TEGRA194_RESET_PEX1_CORE_5_APB 130 +#define TEGRA194_RESET_CVNAS 131 +#define TEGRA194_RESET_CVNAS_FCM 132 +#define TEGRA194_RESET_DMIC5 144 +#define TEGRA194_RESET_APE 145 +#define TEGRA194_RESET_PEX_USB_UPHY 146 +#define TEGRA194_RESET_PEX_USB_UPHY_L0 147 +#define TEGRA194_RESET_PEX_USB_UPHY_L1 148 +#define TEGRA194_RESET_PEX_USB_UPHY_L2 149 +#define TEGRA194_RESET_PEX_USB_UPHY_L3 150 +#define TEGRA194_RESET_PEX_USB_UPHY_L4 151 +#define TEGRA194_RESET_PEX_USB_UPHY_L5 152 +#define TEGRA194_RESET_PEX_USB_UPHY_L6 153 +#define TEGRA194_RESET_PEX_USB_UPHY_L7 154 +#define TEGRA194_RESET_PEX_USB_UPHY_L8 155 +#define TEGRA194_RESET_PEX_USB_UPHY_L9 156 +#define TEGRA194_RESET_PEX_USB_UPHY_L10 157 +#define TEGRA194_RESET_PEX_USB_UPHY_L11 158 +#define TEGRA194_RESET_PEX_USB_UPHY_PLL0 159 +#define TEGRA194_RESET_PEX_USB_UPHY_PLL1 160 +#define TEGRA194_RESET_PEX_USB_UPHY_PLL2 161 +#define TEGRA194_RESET_PEX_USB_UPHY_PLL3 162 + +#endif Index: sys/gnu/dts/include/dt-bindings/sound/rt5651.h =================================================================== --- /dev/null +++ sys/gnu/dts/include/dt-bindings/sound/rt5651.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_RT5651_H +#define __DT_RT5651_H + +#define RT5651_JD_NULL 0 +#define RT5651_JD1_1 1 +#define RT5651_JD1_2 2 +#define RT5651_JD2 3 + +#define RT5651_OVCD_SF_0P5 0 +#define RT5651_OVCD_SF_0P75 1 +#define RT5651_OVCD_SF_1P0 2 +#define RT5651_OVCD_SF_1P5 3 + +#endif /* __DT_RT5651_H */ Index: sys/i386/i386/bpf_jit_machdep.c =================================================================== --- sys/i386/i386/bpf_jit_machdep.c +++ sys/i386/i386/bpf_jit_machdep.c @@ -632,7 +632,7 @@ *size = stream.cur_ip; #ifdef _KERNEL - stream.ibuf = malloc(*size, M_BPFJIT, M_NOWAIT); + stream.ibuf = malloc(*size, M_BPFJIT, M_EXEC | M_NOWAIT); if (stream.ibuf == NULL) break; #else @@ -681,14 +681,3 @@ return ((bpf_filter_func)(void *)stream.ibuf); } - -void -bpf_jit_free(void *func, size_t size) -{ - -#ifdef _KERNEL - free(func, M_BPFJIT); -#else - munmap(func, size); -#endif -} Index: sys/i386/i386/copyout.c =================================================================== --- sys/i386/i386/copyout.c +++ sys/i386/i386/copyout.c @@ -226,7 +226,7 @@ if ((uintptr_t)udaddr + len < (uintptr_t)udaddr || (uintptr_t)udaddr + len > VM_MAXUSER_ADDRESS) - return (-1); + return (EFAULT); if (len == 0 || (fast_copyout && len <= TRAMP_COPYOUT_SZ && copyin_fast_tramp(udaddr, kaddr, len, KCR3) == 0)) return (0); @@ -261,7 +261,7 @@ if ((uintptr_t)udaddr + len < (uintptr_t)udaddr || (uintptr_t)udaddr + len > VM_MAXUSER_ADDRESS) - return (-1); + return (EFAULT); if (len == 0 || (fast_copyout && len <= TRAMP_COPYOUT_SZ && copyout_fast_tramp(kaddr, udaddr, len, KCR3) == 0)) return (0); Index: sys/i386/i386/npx.c =================================================================== --- sys/i386/i386/npx.c +++ sys/i386/i386/npx.c @@ -191,6 +191,11 @@ SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD, &hw_float, 0, "Floating point instructions executed in hardware"); +int lazy_fpu_switch = 0; +SYSCTL_INT(_hw, OID_AUTO, lazy_fpu_switch, CTLFLAG_RWTUN | CTLFLAG_NOFETCH, + &lazy_fpu_switch, 0, + "Lazily load FPU context after context switch"); + int use_xsave; uint64_t xsave_mask; static uma_zone_t fpu_save_area_zone; @@ -319,6 +324,7 @@ u_int cp[4]; uint64_t xsave_mask_user; + TUNABLE_INT_FETCH("hw.lazy_fpu_switch", &lazy_fpu_switch); if (cpu_fxsr && (cpu_feature2 & CPUID2_XSAVE) != 0) { use_xsave = 1; TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave); @@ -777,47 +783,20 @@ return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]); } -/* - * Implement device not available (DNA) exception - * - * It would be better to switch FP context here (if curthread != fpcurthread) - * and not necessarily for every context switch, but it is too hard to - * access foreign pcb's. - */ - -static int err_count = 0; - -int -npxdna(void) +static void +restore_npx_curthread(struct thread *td, struct pcb *pcb) { - if (!hw_float) - return (0); - critical_enter(); - if (PCPU_GET(fpcurthread) == curthread) { - printf("npxdna: fpcurthread == curthread %d times\n", - ++err_count); - stop_emulating(); - critical_exit(); - return (1); - } - if (PCPU_GET(fpcurthread) != NULL) { - printf("npxdna: fpcurthread = %p (%d), curthread = %p (%d)\n", - PCPU_GET(fpcurthread), - PCPU_GET(fpcurthread)->td_proc->p_pid, - curthread, curthread->td_proc->p_pid); - panic("npxdna"); - } - stop_emulating(); /* * Record new context early in case frstor causes a trap. */ - PCPU_SET(fpcurthread, curthread); + PCPU_SET(fpcurthread, td); + stop_emulating(); if (cpu_fxsr) fpu_clean_state(); - if ((curpcb->pcb_flags & PCB_NPXINITDONE) == 0) { + if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) { /* * This is the first time this thread has used the FPU or * the PCB doesn't contain a clean FPU state. Explicitly @@ -828,18 +807,54 @@ * npx_initialstate, to ignite the XSAVEOPT * tracking engine. */ - bcopy(npx_initialstate, curpcb->pcb_save, cpu_max_ext_state_size); - fpurstor(curpcb->pcb_save); - if (curpcb->pcb_initial_npxcw != __INITIAL_NPXCW__) - fldcw(curpcb->pcb_initial_npxcw); - curpcb->pcb_flags |= PCB_NPXINITDONE; - if (PCB_USER_FPU(curpcb)) - curpcb->pcb_flags |= PCB_NPXUSERINITDONE; + bcopy(npx_initialstate, pcb->pcb_save, cpu_max_ext_state_size); + fpurstor(pcb->pcb_save); + if (pcb->pcb_initial_npxcw != __INITIAL_NPXCW__) + fldcw(pcb->pcb_initial_npxcw); + pcb->pcb_flags |= PCB_NPXINITDONE; + if (PCB_USER_FPU(pcb)) + pcb->pcb_flags |= PCB_NPXUSERINITDONE; } else { - fpurstor(curpcb->pcb_save); + fpurstor(pcb->pcb_save); } - critical_exit(); +} +/* + * Implement device not available (DNA) exception + * + * It would be better to switch FP context here (if curthread != fpcurthread) + * and not necessarily for every context switch, but it is too hard to + * access foreign pcb's. + */ +int +npxdna(void) +{ + struct thread *td; + + if (!hw_float) + return (0); + td = curthread; + critical_enter(); + if (__predict_false(PCPU_GET(fpcurthread) == td)) { + /* + * Some virtual machines seems to set %cr0.TS at + * arbitrary moments. Silently clear the TS bit + * regardless of the eager/lazy FPU context switch + * mode. + */ + stop_emulating(); + } else { + if (__predict_false(PCPU_GET(fpcurthread) != NULL)) { + printf( + "npxdna: fpcurthread = %p (%d), curthread = %p (%d)\n", + PCPU_GET(fpcurthread), + PCPU_GET(fpcurthread)->td_proc->p_pid, + td, td->td_proc->p_pid); + panic("npxdna"); + } + restore_npx_curthread(td, td->td_pcb); + } + critical_exit(); return (1); } @@ -861,8 +876,20 @@ xsaveopt((char *)addr, xsave_mask); else fpusave(addr); - start_emulating(); - PCPU_SET(fpcurthread, NULL); +} + +void npxswitch(struct thread *td, struct pcb *pcb); +void +npxswitch(struct thread *td, struct pcb *pcb) +{ + + if (lazy_fpu_switch || (td->td_pflags & TDP_KTHREAD) != 0 || + !PCB_USER_FPU(pcb)) { + start_emulating(); + PCPU_SET(fpcurthread, NULL); + } else if (PCPU_GET(fpcurthread) != td) { + restore_npx_curthread(td, pcb); + } } /* Index: sys/i386/i386/swtch.s =================================================================== --- sys/i386/i386/swtch.s +++ sys/i386/i386/swtch.s @@ -283,6 +283,12 @@ cpu_switch_load_gs: mov PCB_GS(%edx),%gs + pushl %edx + pushl PCPU(CURTHREAD) + call npxswitch + popl %edx + popl %edx + /* Test if debug registers should be restored. */ testl $PCB_DBREGS,PCB_FLAGS(%edx) jz 1f Index: sys/kern/kern_malloc.c =================================================================== --- sys/kern/kern_malloc.c +++ sys/kern/kern_malloc.c @@ -564,7 +564,7 @@ return (va); #endif - if (size <= kmem_zmax) { + if (size <= kmem_zmax && (flags & M_EXEC) == 0) { if (size & KMEM_ZMASK) size = (size & ~KMEM_ZMASK) + KMEM_ZBASE; indx = kmemsize[size >> KMEM_ZSHIFT]; @@ -609,7 +609,7 @@ if (malloc_dbg(&va, &size, mtp, flags) != 0) return (va); #endif - if (size <= kmem_zmax) { + if (size <= kmem_zmax && (flags & M_EXEC) == 0) { if (size & KMEM_ZMASK) size = (size & ~KMEM_ZMASK) + KMEM_ZBASE; indx = kmemsize[size >> KMEM_ZSHIFT]; Index: sys/kern/subr_disk.c =================================================================== --- sys/kern/subr_disk.c +++ sys/kern/subr_disk.c @@ -23,8 +23,13 @@ #include #include #include +#include #include +static int bioq_batchsize = 0; +SYSCTL_INT(_debug, OID_AUTO, bioq_batchsize, CTLFLAG_RW, + &bioq_batchsize, 0, "BIOQ batch size"); + /*- * Disk error is the preface to plaintive error messages * about failing disk transfers. It prints messages of the form @@ -152,6 +157,8 @@ TAILQ_INIT(&head->queue); head->last_offset = 0; head->insert_point = NULL; + head->total = 0; + head->batched = 0; } void @@ -165,6 +172,7 @@ head->insert_point = NULL; TAILQ_REMOVE(&head->queue, bp, bio_queue); + head->total--; } void @@ -183,6 +191,8 @@ if (head->insert_point == NULL) head->last_offset = bp->bio_offset; TAILQ_INSERT_HEAD(&head->queue, bp, bio_queue); + head->total++; + head->batched = 0; } void @@ -190,6 +200,7 @@ { TAILQ_INSERT_TAIL(&head->queue, bp, bio_queue); + head->total++; head->insert_point = bp; head->last_offset = bp->bio_offset; } @@ -248,6 +259,11 @@ return; } + if (bioq_batchsize > 0 && head->batched > bioq_batchsize) { + bioq_insert_tail(head, bp); + return; + } + prev = NULL; key = bioq_bio_key(head, bp); cur = TAILQ_FIRST(&head->queue); @@ -266,4 +282,6 @@ TAILQ_INSERT_HEAD(&head->queue, bp, bio_queue); else TAILQ_INSERT_AFTER(&head->queue, prev, bp, bio_queue); + head->total++; + head->batched++; } Index: sys/kern/subr_vmem.c =================================================================== --- sys/kern/subr_vmem.c +++ sys/kern/subr_vmem.c @@ -241,6 +241,9 @@ static struct vmem transient_arena_storage; /* kernel and kmem arenas are aliased for backwards KPI compat. */ vmem_t *kernel_arena = &kernel_arena_storage; +#if VM_NRESERVLEVEL > 0 +vmem_t *kernel_rwx_arena = NULL; +#endif vmem_t *kmem_arena = &kernel_arena_storage; vmem_t *buffer_arena = &buffer_arena_storage; vmem_t *transient_arena = &transient_arena_storage; Index: sys/kern/vfs_syscalls.c =================================================================== --- sys/kern/vfs_syscalls.c +++ sys/kern/vfs_syscalls.c @@ -2094,12 +2094,25 @@ int ino64_trunc_error; SYSCTL_INT(_vfs, OID_AUTO, ino64_trunc_error, CTLFLAG_RW, &ino64_trunc_error, 0, - "Error on truncation of inode number, device id or link count"); + "Error on truncation of device, file or inode number, or link count"); + int freebsd11_cvtstat(struct stat *st, struct freebsd11_stat *ost) { ost->st_dev = st->st_dev; + if (ost->st_dev != st->st_dev) { + switch (ino64_trunc_error) { + default: + /* + * Since dev_t is almost raw, don't clamp to the + * maximum for case 2, but ignore the error. + */ + break; + case 1: + return (EOVERFLOW); + } + } ost->st_ino = st->st_ino; if (ost->st_ino != st->st_ino) { switch (ino64_trunc_error) { @@ -2130,6 +2143,14 @@ ost->st_uid = st->st_uid; ost->st_gid = st->st_gid; ost->st_rdev = st->st_rdev; + if (ost->st_rdev != st->st_rdev) { + switch (ino64_trunc_error) { + default: + break; + case 1: + return (EOVERFLOW); + } + } ost->st_atim = st->st_atim; ost->st_mtim = st->st_mtim; ost->st_ctim = st->st_ctim; Index: sys/modules/Makefile =================================================================== --- sys/modules/Makefile +++ sys/modules/Makefile @@ -331,6 +331,7 @@ ${_rdrand_rng} \ re \ rl \ + ${_rockchip} \ rtwn \ rtwn_pci \ rtwn_usb \ @@ -563,6 +564,7 @@ _armv8crypto= armv8crypto _efirt= efirt _em= em +_rockchip= rockchip .endif .if ${MACHINE_CPUARCH} == "i386" || ${MACHINE_CPUARCH} == "amd64" Index: sys/modules/rockchip/Makefile =================================================================== --- /dev/null +++ sys/modules/rockchip/Makefile @@ -0,0 +1,7 @@ +# $FreeBSD$ +# Build modules specific to RockChip. + +SUBDIR = \ + rk_i2c \ + +.include Index: sys/modules/rockchip/rk_i2c/Makefile =================================================================== --- /dev/null +++ sys/modules/rockchip/rk_i2c/Makefile @@ -0,0 +1,16 @@ +# $FreeBSD$ + +.PATH: ${SRCTOP}/sys/arm64/rockchip + +KMOD= rk_i2c +SRCS= rk_i2c.c + +SRCS+= \ + bus_if.h \ + clknode_if.h \ + device_if.h \ + iicbus_if.h \ + ofw_bus_if.h \ + opt_platform.h \ + +.include Index: sys/net/bpf_jitter.h =================================================================== --- sys/net/bpf_jitter.h +++ sys/net/bpf_jitter.h @@ -88,6 +88,5 @@ struct bpf_insn; bpf_filter_func bpf_jit_compile(struct bpf_insn *, u_int, size_t *); -void bpf_jit_free(void *, size_t); #endif /* _NET_BPF_JITTER_H_ */ Index: sys/net/bpf_jitter.c =================================================================== --- sys/net/bpf_jitter.c +++ sys/net/bpf_jitter.c @@ -101,11 +101,13 @@ bpf_destroy_jit_filter(bpf_jit_filter *filter) { - if (filter->func != bpf_jit_accept_all) - bpf_jit_free(filter->func, filter->size); #ifdef _KERNEL + if (filter->func != bpf_jit_accept_all) + free(filter->func, M_BPFJIT); free(filter, M_BPFJIT); #else + if (filter->func != bpf_jit_accept_all) + munmap(filter->func, filter->size); free(filter); #endif } Index: sys/net/if_gre.h =================================================================== --- sys/net/if_gre.h +++ sys/net/if_gre.h @@ -64,8 +64,6 @@ struct gre_softc { struct ifnet *gre_ifp; - LIST_ENTRY(gre_softc) gre_list; - struct rmlock gre_lock; int gre_family; /* AF of delivery header */ uint32_t gre_iseq; uint32_t gre_oseq; @@ -82,18 +80,20 @@ struct greip6 *gi6hdr; #endif } gre_uhdr; - const struct encaptab *gre_ecookie; + + CK_LIST_ENTRY(gre_softc) chain; }; +CK_LIST_HEAD(gre_list, gre_softc); +MALLOC_DECLARE(M_GRE); + +#ifndef GRE_HASH_SIZE +#define GRE_HASH_SIZE (1 << 4) +#endif + #define GRE2IFP(sc) ((sc)->gre_ifp) -#define GRE_LOCK_INIT(sc) rm_init(&(sc)->gre_lock, "gre softc") -#define GRE_LOCK_DESTROY(sc) rm_destroy(&(sc)->gre_lock) -#define GRE_RLOCK_TRACKER struct rm_priotracker gre_tracker -#define GRE_RLOCK(sc) rm_rlock(&(sc)->gre_lock, &gre_tracker) -#define GRE_RUNLOCK(sc) rm_runlock(&(sc)->gre_lock, &gre_tracker) -#define GRE_RLOCK_ASSERT(sc) rm_assert(&(sc)->gre_lock, RA_RLOCKED) -#define GRE_WLOCK(sc) rm_wlock(&(sc)->gre_lock) -#define GRE_WUNLOCK(sc) rm_wunlock(&(sc)->gre_lock) -#define GRE_WLOCK_ASSERT(sc) rm_assert(&(sc)->gre_lock, RA_WLOCKED) +#define GRE_RLOCK() epoch_enter_preempt(net_epoch_preempt) +#define GRE_RUNLOCK() epoch_exit_preempt(net_epoch_preempt) +#define GRE_WAIT() epoch_wait_preempt(net_epoch_preempt) #define gre_hdr gre_uhdr.hdr #define gre_gihdr gre_uhdr.gihdr @@ -101,15 +101,23 @@ #define gre_oip gre_gihdr->gi_ip #define gre_oip6 gre_gi6hdr->gi6_ip6 +struct gre_list *gre_hashinit(void); +void gre_hashdestroy(struct gre_list *); + int gre_input(struct mbuf *, int, int, void *); -#ifdef INET -int in_gre_attach(struct gre_softc *); +void gre_updatehdr(struct gre_softc *, struct grehdr *); + +void in_gre_init(void); +void in_gre_uninit(void); +void in_gre_setopts(struct gre_softc *, u_long, uint32_t); +int in_gre_ioctl(struct gre_softc *, u_long, caddr_t); int in_gre_output(struct mbuf *, int, int); -#endif -#ifdef INET6 -int in6_gre_attach(struct gre_softc *); + +void in6_gre_init(void); +void in6_gre_uninit(void); +void in6_gre_setopts(struct gre_softc *, u_long, uint32_t); +int in6_gre_ioctl(struct gre_softc *, u_long, caddr_t); int in6_gre_output(struct mbuf *, int, int); -#endif /* * CISCO uses special type for GRE tunnel created as part of WCCP * connection, while in fact those packets are just IPv4 encapsulated Index: sys/net/if_gre.c =================================================================== --- sys/net/if_gre.c +++ sys/net/if_gre.c @@ -2,7 +2,7 @@ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 1998 The NetBSD Foundation, Inc. - * Copyright (c) 2014 Andrey V. Elsukov + * Copyright (c) 2014, 2018 Andrey V. Elsukov * All rights reserved. * * This code is derived from software contributed to The NetBSD Foundation @@ -41,17 +41,13 @@ #include "opt_inet6.h" #include -#include #include #include -#include #include #include #include #include #include -#include -#include #include #include #include @@ -70,7 +66,6 @@ #include #ifdef INET -#include #include #include #include @@ -80,7 +75,6 @@ #include #include #include -#include #endif #include @@ -91,18 +85,10 @@ #include #define GREMTU 1476 + static const char grename[] = "gre"; -static MALLOC_DEFINE(M_GRE, grename, "Generic Routing Encapsulation"); -static VNET_DEFINE(struct mtx, gre_mtx); -#define V_gre_mtx VNET(gre_mtx) -#define GRE_LIST_LOCK_INIT(x) mtx_init(&V_gre_mtx, "gre_mtx", NULL, \ - MTX_DEF) -#define GRE_LIST_LOCK_DESTROY(x) mtx_destroy(&V_gre_mtx) -#define GRE_LIST_LOCK(x) mtx_lock(&V_gre_mtx) -#define GRE_LIST_UNLOCK(x) mtx_unlock(&V_gre_mtx) - -static VNET_DEFINE(LIST_HEAD(, gre_softc), gre_softc_list); -#define V_gre_softc_list VNET(gre_softc_list) +MALLOC_DEFINE(M_GRE, grename, "Generic Routing Encapsulation"); + static struct sx gre_ioctl_sx; SX_SYSINIT(gre_ioctl_sx, &gre_ioctl_sx, "gre_ioctl"); @@ -116,11 +102,7 @@ static int gre_ioctl(struct ifnet *, u_long, caddr_t); static int gre_output(struct ifnet *, struct mbuf *, const struct sockaddr *, struct route *); - -static void gre_updatehdr(struct gre_softc *); -static int gre_set_tunnel(struct ifnet *, struct sockaddr *, - struct sockaddr *); -static void gre_delete_tunnel(struct ifnet *); +static void gre_delete_tunnel(struct gre_softc *); SYSCTL_DECL(_net_link); static SYSCTL_NODE(_net_link, IFT_TUNNEL, gre, CTLFLAG_RW, 0, @@ -145,10 +127,15 @@ static void vnet_gre_init(const void *unused __unused) { - LIST_INIT(&V_gre_softc_list); - GRE_LIST_LOCK_INIT(); + V_gre_cloner = if_clone_simple(grename, gre_clone_create, gre_clone_destroy, 0); +#ifdef INET + in_gre_init(); +#endif +#ifdef INET6 + in6_gre_init(); +#endif } VNET_SYSINIT(vnet_gre_init, SI_SUB_PROTO_IFATTACHDOMAIN, SI_ORDER_ANY, vnet_gre_init, NULL); @@ -158,7 +145,12 @@ { if_clone_detach(V_gre_cloner); - GRE_LIST_LOCK_DESTROY(); +#ifdef INET + in_gre_uninit(); +#endif +#ifdef INET6 + in6_gre_uninit(); +#endif } VNET_SYSUNINIT(vnet_gre_uninit, SI_SUB_PROTO_IFATTACHDOMAIN, SI_ORDER_ANY, vnet_gre_uninit, NULL); @@ -171,7 +163,6 @@ sc = malloc(sizeof(struct gre_softc), M_GRE, M_WAITOK | M_ZERO); sc->gre_fibnum = curthread->td_proc->p_fibnum; GRE2IFP(sc) = if_alloc(IFT_TUNNEL); - GRE_LOCK_INIT(sc); GRE2IFP(sc)->if_softc = sc; if_initname(GRE2IFP(sc), grename, unit); @@ -185,9 +176,6 @@ GRE2IFP(sc)->if_capenable |= IFCAP_LINKSTATE; if_attach(GRE2IFP(sc)); bpfattach(GRE2IFP(sc), DLT_NULL, sizeof(u_int32_t)); - GRE_LIST_LOCK(); - LIST_INSERT_HEAD(&V_gre_softc_list, sc, gre_list); - GRE_LIST_UNLOCK(); return (0); } @@ -198,33 +186,22 @@ sx_xlock(&gre_ioctl_sx); sc = ifp->if_softc; - gre_delete_tunnel(ifp); - GRE_LIST_LOCK(); - LIST_REMOVE(sc, gre_list); - GRE_LIST_UNLOCK(); + gre_delete_tunnel(sc); bpfdetach(ifp); if_detach(ifp); ifp->if_softc = NULL; sx_xunlock(&gre_ioctl_sx); + GRE_WAIT(); if_free(ifp); - GRE_LOCK_DESTROY(sc); free(sc, M_GRE); } static int gre_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) { - GRE_RLOCK_TRACKER; struct ifreq *ifr = (struct ifreq *)data; - struct sockaddr *src, *dst; struct gre_softc *sc; -#ifdef INET - struct sockaddr_in *sin = NULL; -#endif -#ifdef INET6 - struct sockaddr_in6 *sin6 = NULL; -#endif uint32_t opt; int error; @@ -249,7 +226,6 @@ case GREGPROTO: return (EOPNOTSUPP); } - src = dst = NULL; sx_xlock(&gre_ioctl_sx); sc = ifp->if_softc; if (sc == NULL) { @@ -258,189 +234,25 @@ } error = 0; switch (cmd) { - case SIOCSIFPHYADDR: -#ifdef INET6 - case SIOCSIFPHYADDR_IN6: -#endif - error = EINVAL; - switch (cmd) { -#ifdef INET - case SIOCSIFPHYADDR: - src = (struct sockaddr *) - &(((struct in_aliasreq *)data)->ifra_addr); - dst = (struct sockaddr *) - &(((struct in_aliasreq *)data)->ifra_dstaddr); - break; -#endif -#ifdef INET6 - case SIOCSIFPHYADDR_IN6: - src = (struct sockaddr *) - &(((struct in6_aliasreq *)data)->ifra_addr); - dst = (struct sockaddr *) - &(((struct in6_aliasreq *)data)->ifra_dstaddr); - break; -#endif - default: - error = EAFNOSUPPORT; - goto end; - } - /* sa_family must be equal */ - if (src->sa_family != dst->sa_family || - src->sa_len != dst->sa_len) - goto end; - - /* validate sa_len */ - switch (src->sa_family) { -#ifdef INET - case AF_INET: - if (src->sa_len != sizeof(struct sockaddr_in)) - goto end; - break; -#endif -#ifdef INET6 - case AF_INET6: - if (src->sa_len != sizeof(struct sockaddr_in6)) - goto end; - break; -#endif - default: - error = EAFNOSUPPORT; - goto end; - } - /* check sa_family looks sane for the cmd */ - error = EAFNOSUPPORT; - switch (cmd) { -#ifdef INET - case SIOCSIFPHYADDR: - if (src->sa_family == AF_INET) - break; - goto end; -#endif -#ifdef INET6 - case SIOCSIFPHYADDR_IN6: - if (src->sa_family == AF_INET6) - break; - goto end; -#endif - } - error = EADDRNOTAVAIL; - switch (src->sa_family) { -#ifdef INET - case AF_INET: - if (satosin(src)->sin_addr.s_addr == INADDR_ANY || - satosin(dst)->sin_addr.s_addr == INADDR_ANY) - goto end; - break; -#endif -#ifdef INET6 - case AF_INET6: - if (IN6_IS_ADDR_UNSPECIFIED(&satosin6(src)->sin6_addr) - || - IN6_IS_ADDR_UNSPECIFIED(&satosin6(dst)->sin6_addr)) - goto end; - /* - * Check validity of the scope zone ID of the - * addresses, and convert it into the kernel - * internal form if necessary. - */ - error = sa6_embedscope(satosin6(src), 0); - if (error != 0) - goto end; - error = sa6_embedscope(satosin6(dst), 0); - if (error != 0) - goto end; -#endif - } - error = gre_set_tunnel(ifp, src, dst); - break; case SIOCDIFPHYADDR: - gre_delete_tunnel(ifp); + if (sc->gre_family == 0) + break; + gre_delete_tunnel(sc); break; +#ifdef INET + case SIOCSIFPHYADDR: case SIOCGIFPSRCADDR: case SIOCGIFPDSTADDR: + error = in_gre_ioctl(sc, cmd, data); + break; +#endif #ifdef INET6 + case SIOCSIFPHYADDR_IN6: case SIOCGIFPSRCADDR_IN6: case SIOCGIFPDSTADDR_IN6: -#endif - if (sc->gre_family == 0) { - error = EADDRNOTAVAIL; - break; - } - GRE_RLOCK(sc); - switch (cmd) { -#ifdef INET - case SIOCGIFPSRCADDR: - case SIOCGIFPDSTADDR: - if (sc->gre_family != AF_INET) { - error = EADDRNOTAVAIL; - break; - } - sin = (struct sockaddr_in *)&ifr->ifr_addr; - memset(sin, 0, sizeof(*sin)); - sin->sin_family = AF_INET; - sin->sin_len = sizeof(*sin); - break; -#endif -#ifdef INET6 - case SIOCGIFPSRCADDR_IN6: - case SIOCGIFPDSTADDR_IN6: - if (sc->gre_family != AF_INET6) { - error = EADDRNOTAVAIL; - break; - } - sin6 = (struct sockaddr_in6 *) - &(((struct in6_ifreq *)data)->ifr_addr); - memset(sin6, 0, sizeof(*sin6)); - sin6->sin6_family = AF_INET6; - sin6->sin6_len = sizeof(*sin6); - break; -#endif - } - if (error == 0) { - switch (cmd) { -#ifdef INET - case SIOCGIFPSRCADDR: - sin->sin_addr = sc->gre_oip.ip_src; - break; - case SIOCGIFPDSTADDR: - sin->sin_addr = sc->gre_oip.ip_dst; - break; -#endif -#ifdef INET6 - case SIOCGIFPSRCADDR_IN6: - sin6->sin6_addr = sc->gre_oip6.ip6_src; - break; - case SIOCGIFPDSTADDR_IN6: - sin6->sin6_addr = sc->gre_oip6.ip6_dst; - break; -#endif - } - } - GRE_RUNLOCK(sc); - if (error != 0) - break; - switch (cmd) { -#ifdef INET - case SIOCGIFPSRCADDR: - case SIOCGIFPDSTADDR: - error = prison_if(curthread->td_ucred, - (struct sockaddr *)sin); - if (error != 0) - memset(sin, 0, sizeof(*sin)); - break; -#endif -#ifdef INET6 - case SIOCGIFPSRCADDR_IN6: - case SIOCGIFPDSTADDR_IN6: - error = prison_if(curthread->td_ucred, - (struct sockaddr *)sin6); - if (error == 0) - error = sa6_recoverscope(sin6); - if (error != 0) - memset(sin6, 0, sizeof(*sin6)); -#endif - } + error = in6_gre_ioctl(sc, cmd, data); break; +#endif case SIOCGTUNFIB: ifr->ifr_fib = sc->gre_fibnum; break; @@ -453,40 +265,50 @@ sc->gre_fibnum = ifr->ifr_fib; break; case GRESKEY: + case GRESOPTS: if ((error = priv_check(curthread, PRIV_NET_GRE)) != 0) break; if ((error = copyin(ifr_data_get_ptr(ifr), &opt, sizeof(opt))) != 0) break; - if (sc->gre_key != opt) { - GRE_WLOCK(sc); - sc->gre_key = opt; - gre_updatehdr(sc); - GRE_WUNLOCK(sc); + if (cmd == GRESKEY) { + if (sc->gre_key == opt) + break; + } else if (cmd == GRESOPTS) { + if (opt & ~GRE_OPTMASK) { + error = EINVAL; + break; + } + if (sc->gre_options == opt) + break; + } + switch (sc->gre_family) { +#ifdef INET + case AF_INET: + in_gre_setopts(sc, cmd, opt); + break; +#endif +#ifdef INET6 + case AF_INET6: + in6_gre_setopts(sc, cmd, opt); + break; +#endif + default: + if (cmd == GRESKEY) + sc->gre_key = opt; + else + sc->gre_options = opt; + break; } + /* + * XXX: Do we need to initiate change of interface + * state here? + */ break; case GREGKEY: error = copyout(&sc->gre_key, ifr_data_get_ptr(ifr), sizeof(sc->gre_key)); break; - case GRESOPTS: - if ((error = priv_check(curthread, PRIV_NET_GRE)) != 0) - break; - if ((error = copyin(ifr_data_get_ptr(ifr), &opt, - sizeof(opt))) != 0) - break; - if (opt & ~GRE_OPTMASK) - error = EINVAL; - else { - if (sc->gre_options != opt) { - GRE_WLOCK(sc); - sc->gre_options = opt; - gre_updatehdr(sc); - GRE_WUNLOCK(sc); - } - } - break; - case GREGOPTS: error = copyout(&sc->gre_options, ifr_data_get_ptr(ifr), sizeof(sc->gre_options)); @@ -495,40 +317,68 @@ error = EINVAL; break; } + if (error == 0 && sc->gre_family != 0) { + if ( +#ifdef INET + cmd == SIOCSIFPHYADDR || +#endif +#ifdef INET6 + cmd == SIOCSIFPHYADDR_IN6 || +#endif + 0) { + ifp->if_drv_flags |= IFF_DRV_RUNNING; + if_link_state_change(ifp, LINK_STATE_UP); + } + } end: sx_xunlock(&gre_ioctl_sx); return (error); } static void -gre_updatehdr(struct gre_softc *sc) +gre_delete_tunnel(struct gre_softc *sc) +{ + + sx_assert(&gre_ioctl_sx, SA_XLOCKED); + if (sc->gre_family != 0) { + CK_LIST_REMOVE(sc, chain); + GRE_WAIT(); + free(sc->gre_hdr, M_GRE); + sc->gre_family = 0; + } + GRE2IFP(sc)->if_drv_flags &= ~IFF_DRV_RUNNING; + if_link_state_change(GRE2IFP(sc), LINK_STATE_DOWN); +} + +struct gre_list * +gre_hashinit(void) +{ + struct gre_list *hash; + int i; + + hash = malloc(sizeof(struct gre_list) * GRE_HASH_SIZE, + M_GRE, M_WAITOK); + for (i = 0; i < GRE_HASH_SIZE; i++) + CK_LIST_INIT(&hash[i]); + + return (hash); +} + +void +gre_hashdestroy(struct gre_list *hash) +{ + + free(hash, M_GRE); +} + +void +gre_updatehdr(struct gre_softc *sc, struct grehdr *gh) { - struct grehdr *gh = NULL; uint32_t *opts; uint16_t flags; - GRE_WLOCK_ASSERT(sc); - switch (sc->gre_family) { -#ifdef INET - case AF_INET: - sc->gre_hlen = sizeof(struct greip); - sc->gre_oip.ip_v = IPPROTO_IPV4; - sc->gre_oip.ip_hl = sizeof(struct ip) >> 2; - sc->gre_oip.ip_p = IPPROTO_GRE; - gh = &sc->gre_gihdr->gi_gre; - break; -#endif -#ifdef INET6 - case AF_INET6: - sc->gre_hlen = sizeof(struct greip6); - sc->gre_oip6.ip6_vfc = IPV6_VERSION; - sc->gre_oip6.ip6_nxt = IPPROTO_GRE; - gh = &sc->gre_gi6hdr->gi6_gre; - break; -#endif - default: - return; - } + sx_assert(&gre_ioctl_sx, SA_XLOCKED); + flags = 0; opts = gh->gre_opts; if (sc->gre_options & GRE_ENABLE_CSUM) { @@ -550,141 +400,6 @@ gh->gre_flags = htons(flags); } -static void -gre_detach(struct gre_softc *sc, int family) -{ - - sx_assert(&gre_ioctl_sx, SA_XLOCKED); - if (sc->gre_ecookie != NULL) { - switch (family) { -#ifdef INET - case AF_INET: - ip_encap_detach(sc->gre_ecookie); - break; -#endif -#ifdef INET6 - case AF_INET6: - ip6_encap_detach(sc->gre_ecookie); - break; -#endif - } - } - sc->gre_ecookie = NULL; -} - -static int -gre_set_tunnel(struct ifnet *ifp, struct sockaddr *src, - struct sockaddr *dst) -{ - struct gre_softc *sc, *tsc; -#ifdef INET6 - struct ip6_hdr *ip6; -#endif -#ifdef INET - struct ip *ip; -#endif - void *hdr; - int error; - - sx_assert(&gre_ioctl_sx, SA_XLOCKED); - GRE_LIST_LOCK(); - sc = ifp->if_softc; - LIST_FOREACH(tsc, &V_gre_softc_list, gre_list) { - if (tsc == sc || tsc->gre_family != src->sa_family) - continue; -#ifdef INET - if (tsc->gre_family == AF_INET && - tsc->gre_oip.ip_src.s_addr == - satosin(src)->sin_addr.s_addr && - tsc->gre_oip.ip_dst.s_addr == - satosin(dst)->sin_addr.s_addr) { - GRE_LIST_UNLOCK(); - return (EADDRNOTAVAIL); - } -#endif -#ifdef INET6 - if (tsc->gre_family == AF_INET6 && - IN6_ARE_ADDR_EQUAL(&tsc->gre_oip6.ip6_src, - &satosin6(src)->sin6_addr) && - IN6_ARE_ADDR_EQUAL(&tsc->gre_oip6.ip6_dst, - &satosin6(dst)->sin6_addr)) { - GRE_LIST_UNLOCK(); - return (EADDRNOTAVAIL); - } -#endif - } - GRE_LIST_UNLOCK(); - - switch (src->sa_family) { -#ifdef INET - case AF_INET: - hdr = ip = malloc(sizeof(struct greip) + - 3 * sizeof(uint32_t), M_GRE, M_WAITOK | M_ZERO); - ip->ip_src = satosin(src)->sin_addr; - ip->ip_dst = satosin(dst)->sin_addr; - break; -#endif -#ifdef INET6 - case AF_INET6: - hdr = ip6 = malloc(sizeof(struct greip6) + - 3 * sizeof(uint32_t), M_GRE, M_WAITOK | M_ZERO); - ip6->ip6_src = satosin6(src)->sin6_addr; - ip6->ip6_dst = satosin6(dst)->sin6_addr; - break; -#endif - default: - return (EAFNOSUPPORT); - } - if (sc->gre_family != 0) - gre_detach(sc, sc->gre_family); - GRE_WLOCK(sc); - if (sc->gre_family != 0) - free(sc->gre_hdr, M_GRE); - sc->gre_family = src->sa_family; - sc->gre_hdr = hdr; - sc->gre_oseq = 0; - sc->gre_iseq = UINT32_MAX; - gre_updatehdr(sc); - GRE_WUNLOCK(sc); - - error = 0; - switch (src->sa_family) { -#ifdef INET - case AF_INET: - error = in_gre_attach(sc); - break; -#endif -#ifdef INET6 - case AF_INET6: - error = in6_gre_attach(sc); - break; -#endif - } - if (error == 0) { - ifp->if_drv_flags |= IFF_DRV_RUNNING; - if_link_state_change(ifp, LINK_STATE_UP); - } - return (error); -} - -static void -gre_delete_tunnel(struct ifnet *ifp) -{ - struct gre_softc *sc = ifp->if_softc; - int family; - - GRE_WLOCK(sc); - family = sc->gre_family; - sc->gre_family = 0; - GRE_WUNLOCK(sc); - if (family != 0) { - gre_detach(sc, family); - free(sc->gre_hdr, M_GRE); - } - ifp->if_drv_flags &= ~IFF_DRV_RUNNING; - if_link_state_change(ifp, LINK_STATE_DOWN); -} - int gre_input(struct mbuf *m, int off, int proto, void *arg) { @@ -823,35 +538,18 @@ struct route *ro) { uint32_t af; - int error; - -#ifdef MAC - error = mac_ifnet_check_transmit(ifp, m); - if (error != 0) - goto drop; -#endif - if ((ifp->if_flags & IFF_MONITOR) != 0 || - (ifp->if_flags & IFF_UP) == 0) { - error = ENETDOWN; - goto drop; - } - - error = gre_check_nesting(ifp, m); - if (error != 0) - goto drop; - m->m_flags &= ~(M_BCAST|M_MCAST); if (dst->sa_family == AF_UNSPEC) bcopy(dst->sa_data, &af, sizeof(af)); else af = dst->sa_family; - BPF_MTAP2(ifp, &af, sizeof(af), m); - m->m_pkthdr.csum_data = af; /* save af for if_transmit */ + /* + * Now save the af in the inbound pkt csum data, this is a cheat since + * we are using the inbound csum_data field to carry the af over to + * the gre_transmit() routine, avoiding using yet another mtag. + */ + m->m_pkthdr.csum_data = af; return (ifp->if_transmit(ifp, m)); -drop: - m_freem(m); - if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); - return (error); } static void @@ -874,92 +572,90 @@ static int gre_transmit(struct ifnet *ifp, struct mbuf *m) { - GRE_RLOCK_TRACKER; struct gre_softc *sc; struct grehdr *gh; - uint32_t iaf, oaf, oseq; - int error, hlen, olen, plen; - int want_seq, want_csum; + uint32_t af; + int error, len; + uint16_t proto; - plen = 0; - sc = ifp->if_softc; - if (sc == NULL) { - error = ENETDOWN; + len = 0; +#ifdef MAC + error = mac_ifnet_check_transmit(ifp, m); + if (error) { m_freem(m); goto drop; } - GRE_RLOCK(sc); - if (sc->gre_family == 0) { - GRE_RUNLOCK(sc); - error = ENETDOWN; +#endif + error = ENETDOWN; + GRE_RLOCK(); + sc = ifp->if_softc; + if ((ifp->if_flags & IFF_MONITOR) != 0 || + (ifp->if_flags & IFF_UP) == 0 || + sc->gre_family == 0 || + (error = gre_check_nesting(ifp, m)) != 0) { m_freem(m); goto drop; } - iaf = m->m_pkthdr.csum_data; - oaf = sc->gre_family; - hlen = sc->gre_hlen; - want_seq = (sc->gre_options & GRE_ENABLE_SEQ) != 0; - if (want_seq) - oseq = sc->gre_oseq++; /* XXX */ - else - oseq = 0; /* Make compiler happy. */ - want_csum = (sc->gre_options & GRE_ENABLE_CSUM) != 0; + af = m->m_pkthdr.csum_data; M_SETFIB(m, sc->gre_fibnum); - M_PREPEND(m, hlen, M_NOWAIT); + M_PREPEND(m, sc->gre_hlen, M_NOWAIT); if (m == NULL) { - GRE_RUNLOCK(sc); error = ENOBUFS; goto drop; } - bcopy(sc->gre_hdr, mtod(m, void *), hlen); - GRE_RUNLOCK(sc); - switch (oaf) { + bcopy(sc->gre_hdr, mtod(m, void *), sc->gre_hlen); + /* Determine GRE proto */ + switch (af) { #ifdef INET case AF_INET: - olen = sizeof(struct ip); + proto = htons(ETHERTYPE_IP); break; #endif #ifdef INET6 case AF_INET6: - olen = sizeof(struct ip6_hdr); + proto = htons(ETHERTYPE_IPV6); break; #endif default: + m_freem(m); error = ENETDOWN; goto drop; } - gh = (struct grehdr *)mtodo(m, olen); - switch (iaf) { + /* Determine offset of GRE header */ + switch (sc->gre_family) { #ifdef INET case AF_INET: - gh->gre_proto = htons(ETHERTYPE_IP); + len = sizeof(struct ip); break; #endif #ifdef INET6 case AF_INET6: - gh->gre_proto = htons(ETHERTYPE_IPV6); + len = sizeof(struct ip6_hdr); break; #endif default: + m_freem(m); error = ENETDOWN; goto drop; } - if (want_seq) - gre_setseqn(gh, oseq); - if (want_csum) { + gh = (struct grehdr *)mtodo(m, len); + gh->gre_proto = proto; + if (sc->gre_options & GRE_ENABLE_SEQ) + gre_setseqn(gh, sc->gre_oseq++); + if (sc->gre_options & GRE_ENABLE_CSUM) { *(uint16_t *)gh->gre_opts = in_cksum_skip(m, - m->m_pkthdr.len, olen); + m->m_pkthdr.len, len); } - plen = m->m_pkthdr.len - hlen; - switch (oaf) { + len = m->m_pkthdr.len - len; + switch (sc->gre_family) { #ifdef INET case AF_INET: - error = in_gre_output(m, iaf, hlen); + error = in_gre_output(m, af, sc->gre_hlen); break; #endif #ifdef INET6 case AF_INET6: - error = in6_gre_output(m, iaf, hlen); + error = in6_gre_output(m, af, sc->gre_hlen); break; #endif default: @@ -971,8 +667,9 @@ if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); else { if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); - if_inc_counter(ifp, IFCOUNTER_OBYTES, plen); + if_inc_counter(ifp, IFCOUNTER_OBYTES, len); } + GRE_RUNLOCK(); return (error); } Index: sys/netinet/in_pcb.h =================================================================== --- sys/netinet/in_pcb.h +++ sys/netinet/in_pcb.h @@ -276,7 +276,7 @@ TAILQ_ENTRY(inpcb) inp_input; /* pacing in queue next lock(b) */ struct inpcbinfo *inp_pcbinfo; /* (c) PCB list info */ struct inpcbgroup *inp_pcbgroup; /* (g/i) PCB group list */ - LIST_ENTRY(inpcb) inp_pcbgroup_wild; /* (g/i/h) group wildcard entry */ + CK_LIST_ENTRY(inpcb) inp_pcbgroup_wild; /* (g/i/h) group wildcard entry */ struct ucred *inp_cred; /* (c) cache of socket cred */ u_int32_t inp_flow; /* (i) IPv6 flow information */ u_char inp_vflag; /* (i) IP version flag (v4/v6) */ Index: sys/netinet/in_pcb.c =================================================================== --- sys/netinet/in_pcb.c +++ sys/netinet/in_pcb.c @@ -2025,7 +2025,7 @@ INP_GROUP_LOCK(pcbgroup); head = &pcbgroup->ipg_hashbase[INP_PCBHASH(faddr.s_addr, lport, fport, pcbgroup->ipg_hashmask)]; - LIST_FOREACH(inp, head, inp_pcbgrouphash) { + CK_LIST_FOREACH(inp, head, inp_pcbgrouphash) { #ifdef INET6 /* XXX inp locking */ if ((inp->inp_vflag & INP_IPV4) == 0) @@ -2075,7 +2075,7 @@ head = &pcbgroup->ipg_hashbase[INP_PCBHASH(INADDR_ANY, lport, 0, pcbgroup->ipg_hashmask)]; - LIST_FOREACH(inp, head, inp_pcbgrouphash) { + CK_LIST_FOREACH(inp, head, inp_pcbgrouphash) { #ifdef INET6 /* XXX inp locking */ if ((inp->inp_vflag & INP_IPV4) == 0) @@ -2149,7 +2149,7 @@ */ head = &pcbinfo->ipi_wildbase[INP_PCBHASH(INADDR_ANY, lport, 0, pcbinfo->ipi_wildmask)]; - LIST_FOREACH(inp, head, inp_pcbgroup_wild) { + CK_LIST_FOREACH(inp, head, inp_pcbgroup_wild) { #ifdef INET6 /* XXX inp locking */ if ((inp->inp_vflag & INP_IPV4) == 0) Index: sys/netinet/in_pcbgroup.c =================================================================== --- sys/netinet/in_pcbgroup.c +++ sys/netinet/in_pcbgroup.c @@ -207,7 +207,7 @@ for (pgn = 0; pgn < pcbinfo->ipi_npcbgroups; pgn++) { pcbgroup = &pcbinfo->ipi_pcbgroups[pgn]; - KASSERT(LIST_EMPTY(pcbinfo->ipi_listhead), + KASSERT(CK_LIST_EMPTY(pcbinfo->ipi_listhead), ("in_pcbinfo_destroy: listhead not empty")); INP_GROUP_LOCK_DESTROY(pcbgroup); hashdestroy(pcbgroup->ipg_hashbase, M_PCB, @@ -338,7 +338,7 @@ INP_GROUP_LOCK(&pcbinfo->ipi_pcbgroups[pgn]); head = &pcbinfo->ipi_wildbase[INP_PCBHASH(INADDR_ANY, inp->inp_lport, 0, pcbinfo->ipi_wildmask)]; - LIST_INSERT_HEAD(head, inp, inp_pcbgroup_wild); + CK_LIST_INSERT_HEAD(head, inp, inp_pcbgroup_wild); inp->inp_flags2 |= INP_PCBGROUPWILD; for (pgn = 0; pgn < pcbinfo->ipi_npcbgroups; pgn++) INP_GROUP_UNLOCK(&pcbinfo->ipi_pcbgroups[pgn]); @@ -357,7 +357,7 @@ pcbinfo = inp->inp_pcbinfo; for (pgn = 0; pgn < pcbinfo->ipi_npcbgroups; pgn++) INP_GROUP_LOCK(&pcbinfo->ipi_pcbgroups[pgn]); - LIST_REMOVE(inp, inp_pcbgroup_wild); + CK_LIST_REMOVE(inp, inp_pcbgroup_wild); for (pgn = 0; pgn < pcbinfo->ipi_npcbgroups; pgn++) INP_GROUP_UNLOCK(&pcbinfo->ipi_pcbgroups[pgn]); inp->inp_flags2 &= ~INP_PCBGROUPWILD; @@ -415,7 +415,7 @@ oldpcbgroup = inp->inp_pcbgroup; if (oldpcbgroup != NULL && oldpcbgroup != newpcbgroup) { INP_GROUP_LOCK(oldpcbgroup); - LIST_REMOVE(inp, inp_pcbgrouphash); + CK_LIST_REMOVE(inp, inp_pcbgrouphash); inp->inp_pcbgroup = NULL; INP_GROUP_UNLOCK(oldpcbgroup); } @@ -445,7 +445,7 @@ inp->inp_fport, newpcbgroup->ipg_hashmask)]; } - LIST_INSERT_HEAD(pcbhash, inp, inp_pcbgrouphash); + CK_LIST_INSERT_HEAD(pcbhash, inp, inp_pcbgrouphash); inp->inp_pcbgroup = newpcbgroup; INP_GROUP_UNLOCK(newpcbgroup); } @@ -548,7 +548,7 @@ pcbgroup = inp->inp_pcbgroup; if (pcbgroup != NULL) { INP_GROUP_LOCK(pcbgroup); - LIST_REMOVE(inp, inp_pcbgrouphash); + CK_LIST_REMOVE(inp, inp_pcbgrouphash); inp->inp_pcbgroup = NULL; INP_GROUP_UNLOCK(pcbgroup); } Index: sys/netinet/ip_gre.c =================================================================== --- sys/netinet/ip_gre.c +++ sys/netinet/ip_gre.c @@ -2,7 +2,7 @@ * SPDX-License-Identifier: BSD-2-Clause-NetBSD * * Copyright (c) 1998 The NetBSD Foundation, Inc. - * Copyright (c) 2014 Andrey V. Elsukov + * Copyright (c) 2014, 2018 Andrey V. Elsukov * All rights reserved. * * This code is derived from software contributed to The NetBSD Foundation @@ -41,17 +41,16 @@ #include "opt_inet6.h" #include +#include #include -#include #include -#include +#include +#include #include -#include #include -#include -#include #include -#include +#include + #include #include #include @@ -74,36 +73,168 @@ SYSCTL_INT(_net_inet_ip, OID_AUTO, grettl, CTLFLAG_VNET | CTLFLAG_RW, &VNET_NAME(ip_gre_ttl), 0, "Default TTL value for encapsulated packets"); +static VNET_DEFINE(struct gre_list *, ipv4_hashtbl) = NULL; +#define V_ipv4_hashtbl VNET(ipv4_hashtbl) +#define GRE_HASH(src, dst) (V_ipv4_hashtbl[\ + in_gre_hashval((src), (dst)) & (GRE_HASH_SIZE - 1)]) +#define GRE_HASH_SC(sc) GRE_HASH((sc)->gre_oip.ip_src.s_addr,\ + (sc)->gre_oip.ip_dst.s_addr) + +static uint32_t +in_gre_hashval(in_addr_t src, in_addr_t dst) +{ + uint32_t ret; + + ret = fnv_32_buf(&src, sizeof(src), FNV1_32_INIT); + return (fnv_32_buf(&dst, sizeof(dst), ret)); +} + +static int +in_gre_checkdup(const struct gre_softc *sc, in_addr_t src, in_addr_t dst) +{ + struct gre_softc *tmp; + + if (sc->gre_family == AF_INET && + sc->gre_oip.ip_src.s_addr == src && + sc->gre_oip.ip_dst.s_addr == dst) + return (EEXIST); + + CK_LIST_FOREACH(tmp, &GRE_HASH(src, dst), chain) { + if (tmp == sc) + continue; + if (tmp->gre_oip.ip_src.s_addr == src && + tmp->gre_oip.ip_dst.s_addr == dst) + return (EADDRNOTAVAIL); + } + return (0); +} + static int -in_gre_encapcheck(const struct mbuf *m, int off, int proto, void *arg) +in_gre_lookup(const struct mbuf *m, int off, int proto, void **arg) { - GRE_RLOCK_TRACKER; + const struct ip *ip; struct gre_softc *sc; - struct ip *ip; - sc = (struct gre_softc *)arg; - if ((GRE2IFP(sc)->if_flags & IFF_UP) == 0) - return (0); + MPASS(in_epoch()); + ip = mtod(m, const struct ip *); + CK_LIST_FOREACH(sc, &GRE_HASH(ip->ip_dst.s_addr, + ip->ip_src.s_addr), chain) { + /* + * This is an inbound packet, its ip_dst is source address + * in softc. + */ + if (sc->gre_oip.ip_src.s_addr == ip->ip_dst.s_addr && + sc->gre_oip.ip_dst.s_addr == ip->ip_src.s_addr) { + if ((GRE2IFP(sc)->if_flags & IFF_UP) == 0) + return (0); + *arg = sc; + return (ENCAP_DRV_LOOKUP); + } + } + return (0); +} + +static void +in_gre_attach(struct gre_softc *sc) +{ - M_ASSERTPKTHDR(m); + sc->gre_hlen = sizeof(struct greip); + sc->gre_oip.ip_v = IPVERSION; + sc->gre_oip.ip_hl = sizeof(struct ip) >> 2; + sc->gre_oip.ip_p = IPPROTO_GRE; + gre_updatehdr(sc, &sc->gre_gihdr->gi_gre); + CK_LIST_INSERT_HEAD(&GRE_HASH_SC(sc), sc, chain); +} - GRE_RLOCK(sc); - if (sc->gre_family == 0) - goto bad; +void +in_gre_setopts(struct gre_softc *sc, u_long cmd, uint32_t value) +{ - KASSERT(sc->gre_family == AF_INET, - ("wrong gre_family: %d", sc->gre_family)); + MPASS(cmd == GRESKEY || cmd == GRESOPTS); - ip = mtod(m, struct ip *); - if (sc->gre_oip.ip_src.s_addr != ip->ip_dst.s_addr || - sc->gre_oip.ip_dst.s_addr != ip->ip_src.s_addr) - goto bad; + /* NOTE: we are protected with gre_ioctl_sx lock */ + MPASS(sc->gre_family == AF_INET); + CK_LIST_REMOVE(sc, chain); + GRE_WAIT(); + if (cmd == GRESKEY) + sc->gre_key = value; + else + sc->gre_options = value; + in_gre_attach(sc); +} - GRE_RUNLOCK(sc); - return (32 * 3); /* src + dst + gre_hdr */ -bad: - GRE_RUNLOCK(sc); - return (0); +int +in_gre_ioctl(struct gre_softc *sc, u_long cmd, caddr_t data) +{ + struct ifreq *ifr = (struct ifreq *)data; + struct sockaddr_in *dst, *src; + struct ip *ip; + int error; + + /* NOTE: we are protected with gre_ioctl_sx lock */ + error = EINVAL; + switch (cmd) { + case SIOCSIFPHYADDR: + src = &((struct in_aliasreq *)data)->ifra_addr; + dst = &((struct in_aliasreq *)data)->ifra_dstaddr; + + /* sanity checks */ + if (src->sin_family != dst->sin_family || + src->sin_family != AF_INET || + src->sin_len != dst->sin_len || + src->sin_len != sizeof(*src)) + break; + if (src->sin_addr.s_addr == INADDR_ANY || + dst->sin_addr.s_addr == INADDR_ANY) { + error = EADDRNOTAVAIL; + break; + } + if (V_ipv4_hashtbl == NULL) + V_ipv4_hashtbl = gre_hashinit(); + error = in_gre_checkdup(sc, src->sin_addr.s_addr, + dst->sin_addr.s_addr); + if (error == EADDRNOTAVAIL) + break; + if (error == EEXIST) { + /* Addresses are the same. Just return. */ + error = 0; + break; + } + ip = malloc(sizeof(struct greip) + 3 * sizeof(uint32_t), + M_GRE, M_WAITOK | M_ZERO); + ip->ip_src.s_addr = src->sin_addr.s_addr; + ip->ip_dst.s_addr = dst->sin_addr.s_addr; + if (sc->gre_family != 0) { + /* Detach existing tunnel first */ + CK_LIST_REMOVE(sc, chain); + GRE_WAIT(); + free(sc->gre_hdr, M_GRE); + /* XXX: should we notify about link state change? */ + } + sc->gre_family = AF_INET; + sc->gre_hdr = ip; + sc->gre_oseq = 0; + sc->gre_iseq = UINT32_MAX; + in_gre_attach(sc); + break; + case SIOCGIFPSRCADDR: + case SIOCGIFPDSTADDR: + if (sc->gre_family != AF_INET) { + error = EADDRNOTAVAIL; + break; + } + src = (struct sockaddr_in *)&ifr->ifr_addr; + memset(src, 0, sizeof(*src)); + src->sin_family = AF_INET; + src->sin_len = sizeof(*src); + src->sin_addr = (cmd == SIOCGIFPSRCADDR) ? + sc->gre_oip.ip_src: sc->gre_oip.ip_dst; + error = prison_if(curthread->td_ucred, (struct sockaddr *)src); + if (error != 0) + memset(src, 0, sizeof(*src)); + break; + } + return (error); } int @@ -136,19 +267,30 @@ return (ip_output(m, NULL, NULL, IP_FORWARDING, NULL, NULL)); } +static const struct encaptab *ecookie = NULL; static const struct encap_config ipv4_encap_cfg = { .proto = IPPROTO_GRE, .min_length = sizeof(struct greip) + sizeof(struct ip), - .exact_match = (sizeof(in_addr_t) << 4) + 32, - .check = in_gre_encapcheck, + .exact_match = ENCAP_DRV_LOOKUP, + .lookup = in_gre_lookup, .input = gre_input }; -int -in_gre_attach(struct gre_softc *sc) +void +in_gre_init(void) { - KASSERT(sc->gre_ecookie == NULL, ("gre_ecookie isn't NULL")); - sc->gre_ecookie = ip_encap_attach(&ipv4_encap_cfg, sc, M_WAITOK); - return (0); + if (!IS_DEFAULT_VNET(curvnet)) + return; + ecookie = ip_encap_attach(&ipv4_encap_cfg, NULL, M_WAITOK); +} + +void +in_gre_uninit(void) +{ + + if (IS_DEFAULT_VNET(curvnet)) + ip_encap_detach(ecookie); + if (V_ipv4_hashtbl != NULL) + gre_hashdestroy(V_ipv4_hashtbl); } Index: sys/netinet/libalias/alias.c =================================================================== --- sys/netinet/libalias/alias.c +++ sys/netinet/libalias/alias.c @@ -1751,7 +1751,8 @@ * the input packet, on failure NULL. The input packet is always consumed. */ struct mbuf * -m_megapullup(struct mbuf *m, int len) { +m_megapullup(struct mbuf *m, int len) +{ struct mbuf *mcl; if (len > m->m_pkthdr.len) @@ -1760,7 +1761,14 @@ if (m->m_next == NULL && M_WRITABLE(m)) return (m); - mcl = m_get2(len, M_NOWAIT, MT_DATA, M_PKTHDR); + if (len <= MJUMPAGESIZE) + mcl = m_get2(len, M_NOWAIT, MT_DATA, M_PKTHDR); + else if (len <= MJUM9BYTES) + mcl = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); + else if (len <= MJUM16BYTES) + mcl = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM16BYTES); + else + goto bad; if (mcl == NULL) goto bad; m_align(mcl, len); Index: sys/netinet/tcp_stacks/rack.c =================================================================== --- sys/netinet/tcp_stacks/rack.c +++ sys/netinet/tcp_stacks/rack.c @@ -2083,6 +2083,8 @@ /* We can't start any timer in persists */ return (rack_get_persists_timer_val(tp, rack)); } + if (tp->t_state < TCPS_ESTABLISHED) + goto activate_rxt; rsm = TAILQ_FIRST(&rack->r_ctl.rc_tmap); if (rsm == NULL) { /* Nothing on the send map */ @@ -3385,8 +3387,15 @@ rsm->r_tim_lastsent[0] = ts; rsm->r_rtr_cnt = 1; rsm->r_rtr_bytes = 0; - rsm->r_start = seq_out; - rsm->r_end = rsm->r_start + len; + if (th_flags & TH_SYN) { + /* The data space is one beyond snd_una */ + rsm->r_start = seq_out + 1; + rsm->r_end = rsm->r_start + (len - 1); + } else { + /* Normal case */ + rsm->r_start = seq_out; + rsm->r_end = rsm->r_start + len; + } rsm->r_sndcnt = 0; TAILQ_INSERT_TAIL(&rack->r_ctl.rc_map, rsm, r_next); TAILQ_INSERT_TAIL(&rack->r_ctl.rc_tmap, rsm, r_tnext); @@ -4657,11 +4666,7 @@ * send garbage on first SYN. */ int32_t nsegs; -#ifdef TCP_RFC7413 int32_t tfo_syn; -#else -#define tfo_syn (FALSE) -#endif struct tcp_rack *rack; rack = (struct tcp_rack *)tp->t_fb_ptr; @@ -4767,10 +4772,8 @@ * PRU_RCVD). If a FIN has already been received on this connection * then we just ignore the text. */ -#ifdef TCP_RFC7413 tfo_syn = ((tp->t_state == TCPS_SYN_RECEIVED) && - (tp->t_flags & TF_FASTOPEN)); -#endif + IS_FASTOPEN(tp->t_flags)); if ((tlen || (thflags & TH_FIN) || tfo_syn) && TCPS_HAVERCVDFIN(tp->t_state) == 0) { tcp_seq save_start = th->th_seq; @@ -5237,6 +5240,8 @@ tp->irs = th->th_seq; tcp_rcvseqinit(tp); if (thflags & TH_ACK) { + int tfo_partial = 0; + TCPSTAT_INC(tcps_connects); soisconnected(so); #ifdef MAC @@ -5250,10 +5255,19 @@ tp->rcv_adv += min(tp->rcv_wnd, TCP_MAXWIN << tp->rcv_scale); /* + * If not all the data that was sent in the TFO SYN + * has been acked, resend the remainder right away. + */ + if (IS_FASTOPEN(tp->t_flags) && + (tp->snd_una != tp->snd_max)) { + tp->snd_nxt = th->th_ack; + tfo_partial = 1; + } + /* * If there's data, delay ACK; if there's also a FIN ACKNOW * will be turned on later. */ - if (DELAY_ACK(tp, tlen) && tlen != 0) { + if (DELAY_ACK(tp, tlen) && tlen != 0 && (tfo_partial == 0)) { rack_timer_cancel(tp, (struct tcp_rack *)tp->t_fb_ptr, ((struct tcp_rack *)tp->t_fb_ptr)->r_ctl.rc_rcvtime, __LINE__); tp->t_flags |= TF_DELACK; @@ -5266,6 +5280,21 @@ tp->t_flags |= TF_ECN_PERMIT; TCPSTAT_INC(tcps_ecn_shs); } + if (SEQ_GT(th->th_ack, tp->snd_una)) { + /* + * We advance snd_una for the + * fast open case. If th_ack is + * acknowledging data beyond + * snd_una we can't just call + * ack-processing since the + * data stream in our send-map + * will start at snd_una + 1 (one + * beyond the SYN). If its just + * equal we don't need to do that + * and there is no send_map. + */ + tp->snd_una++; + } /* * Received in SYN_SENT[*] state. Transitions: * SYN_SENT --> ESTABLISHED SYN_SENT* --> FIN_WAIT_1 @@ -5375,13 +5404,13 @@ rack_do_dropwithreset(m, tp, th, ti_locked, BANDLIM_RST_OPENPORT, tlen); return (1); } -#ifdef TCP_RFC7413 - if (tp->t_flags & TF_FASTOPEN) { + if (IS_FASTOPEN(tp->t_flags)) { /* - * When a TFO connection is in SYN_RECEIVED, the only valid - * packets are the initial SYN, a retransmit/copy of the - * initial SYN (possibly with a subset of the original - * data), a valid ACK, a FIN, or a RST. + * When a TFO connection is in SYN_RECEIVED, the + * only valid packets are the initial SYN, a + * retransmit/copy of the initial SYN (possibly with + * a subset of the original data), a valid ACK, a + * FIN, or a RST. */ if ((thflags & (TH_SYN | TH_ACK)) == (TH_SYN | TH_ACK)) { rack_do_dropwithreset(m, tp, th, ti_locked, BANDLIM_RST_OPENPORT, tlen); @@ -5402,7 +5431,6 @@ return (0); } } -#endif if (thflags & TH_RST) return (rack_process_rst(m, th, so, tp, ti_locked)); /* @@ -5463,12 +5491,10 @@ * processing; else drop segment and return. */ if ((thflags & TH_ACK) == 0) { -#ifdef TCP_RFC7413 - if (tp->t_flags & TF_FASTOPEN) { + if (IS_FASTOPEN(tp->t_flags)) { tp->snd_wnd = tiwin; cc_conn_init(tp); } -#endif return (rack_process_data(m, th, so, tp, drop_hdrlen, tlen, ti_locked, tiwin, thflags, nxt_pkt)); } @@ -5492,8 +5518,7 @@ tcp_state_change(tp, TCPS_ESTABLISHED); TCP_PROBE5(accept__established, NULL, tp, mtod(m, const char *), tp, th); -#ifdef TCP_RFC7413 - if (tp->t_tfo_pending) { + if (IS_FASTOPEN(tp->t_flags) && tp->t_tfo_pending) { tcp_fastopen_decrement_counter(tp->t_tfo_pending); tp->t_tfo_pending = NULL; @@ -5509,8 +5534,7 @@ * is not harmless as it would undo the snd_cwnd reduction * that occurs when a TFO SYN|ACK is retransmitted. */ - if (!(tp->t_flags & TF_FASTOPEN)) -#endif + if (!IS_FASTOPEN(tp->t_flags)) cc_conn_init(tp); } /* @@ -6926,6 +6950,7 @@ struct tcp_rack *rack; struct tcphdr *th; uint8_t pass = 0; + uint8_t wanted_cookie = 0; u_char opt[TCP_MAXOLEN]; unsigned ipoptlen, optlen, hdrlen, ulen=0; uint32_t rack_seq; @@ -6967,17 +6992,15 @@ return (tcp_offload_output(tp)); #endif -#ifdef TCP_RFC7413 /* * For TFO connections in SYN_RECEIVED, only allow the initial * SYN|ACK and those sent by the retransmit timer. */ - if ((tp->t_flags & TF_FASTOPEN) && + if (IS_FASTOPEN(tp->t_flags) && (tp->t_state == TCPS_SYN_RECEIVED) && - SEQ_GT(tp->snd_max, tp->snd_una) && /* inital SYN|ACK sent */ - (tp->snd_nxt != tp->snd_una)) /* not a retransmit */ + SEQ_GT(tp->snd_max, tp->snd_una) && /* initial SYN|ACK sent */ + (rack->r_ctl.rc_resend == NULL)) /* not a retransmit */ return (0); -#endif #ifdef INET6 if (rack->r_state) { /* Use the cache line loaded if possible */ @@ -7267,7 +7290,7 @@ uint32_t avail; avail = sbavail(sb); - if (SEQ_GT(tp->snd_nxt, tp->snd_una)) + if (SEQ_GT(tp->snd_nxt, tp->snd_una) && avail) sb_offset = tp->snd_nxt - tp->snd_una; else sb_offset = 0; @@ -7359,22 +7382,18 @@ * SYN-SENT state and if segment contains data and if we don't know * that foreign host supports TAO, suppress sending segment. */ - if ((flags & TH_SYN) && SEQ_GT(tp->snd_nxt, tp->snd_una)) { - if ((tp->t_state != TCPS_SYN_RECEIVED) && - (tp->t_state != TCPS_SYN_SENT)) + if ((flags & TH_SYN) && SEQ_GT(tp->snd_nxt, tp->snd_una) && + ((sack_rxmit == 0) && (tp->t_rxtshift == 0))) { + if (tp->t_state != TCPS_SYN_RECEIVED) flags &= ~TH_SYN; -#ifdef TCP_RFC7413 /* * When sending additional segments following a TFO SYN|ACK, * do not include the SYN bit. */ - if ((tp->t_flags & TF_FASTOPEN) && + if (IS_FASTOPEN(tp->t_flags) && (tp->t_state == TCPS_SYN_RECEIVED)) flags &= ~TH_SYN; -#endif sb_offset--, len++; - if (sbavail(sb) == 0) - len = 0; } /* * Be careful not to send data and/or FIN on SYN segments. This @@ -7385,16 +7404,27 @@ len = 0; flags &= ~TH_FIN; } -#ifdef TCP_RFC7413 /* - * When retransmitting SYN|ACK on a passively-created TFO socket, - * don't include data, as the presence of data may have caused the - * original SYN|ACK to have been dropped by a middlebox. + * On TFO sockets, ensure no data is sent in the following cases: + * + * - When retransmitting SYN|ACK on a passively-created socket + * + * - When retransmitting SYN on an actively created socket + * + * - When sending a zero-length cookie (cookie request) on an + * actively created socket + * + * - When the socket is in the CLOSED state (RST is being sent) */ - if ((tp->t_flags & TF_FASTOPEN) && - ((tp->t_state == TCPS_SYN_RECEIVED) && (tp->t_rxtshift > 0))) + if (IS_FASTOPEN(tp->t_flags) && + (((flags & TH_SYN) && (tp->t_rxtshift > 0)) || + ((tp->t_state == TCPS_SYN_SENT) && + (tp->t_tfo_client_cookie_len == 0)) || + (flags & TH_RST))) + len = 0; + /* Without fast-open there should never be data sent on a SYN */ + if ((flags & TH_SYN) && (!IS_FASTOPEN(tp->t_flags))) len = 0; -#endif if (len <= 0) { /* * If FIN has been sent but not acked, but we haven't been @@ -7710,22 +7740,39 @@ to.to_mss -= V_tcp_udp_tunneling_overhead; #endif to.to_flags |= TOF_MSS; -#ifdef TCP_RFC7413 + /* - * Only include the TFO option on the first - * transmission of the SYN|ACK on a - * passively-created TFO socket, as the presence of - * the TFO option may have caused the original - * SYN|ACK to have been dropped by a middlebox. + * On SYN or SYN|ACK transmits on TFO connections, + * only include the TFO option if it is not a + * retransmit, as the presence of the TFO option may + * have caused the original SYN or SYN|ACK to have + * been dropped by a middlebox. */ - if ((tp->t_flags & TF_FASTOPEN) && - (tp->t_state == TCPS_SYN_RECEIVED) && + if (IS_FASTOPEN(tp->t_flags) && (tp->t_rxtshift == 0)) { - to.to_tfo_len = TCP_FASTOPEN_MAX_COOKIE_LEN; - to.to_tfo_cookie = (u_char *)&tp->t_tfo_cookie; - to.to_flags |= TOF_FASTOPEN; + if (tp->t_state == TCPS_SYN_RECEIVED) { + to.to_tfo_len = TCP_FASTOPEN_COOKIE_LEN; + to.to_tfo_cookie = + (u_int8_t *)&tp->t_tfo_cookie.server; + to.to_flags |= TOF_FASTOPEN; + wanted_cookie = 1; + } else if (tp->t_state == TCPS_SYN_SENT) { + to.to_tfo_len = + tp->t_tfo_client_cookie_len; + to.to_tfo_cookie = + tp->t_tfo_cookie.client; + to.to_flags |= TOF_FASTOPEN; + wanted_cookie = 1; + /* + * If we wind up having more data to + * send with the SYN than can fit in + * one segment, don't send any more + * until the SYN|ACK comes back from + * the other end. + */ + sendalot = 0; + } } -#endif } /* Window scaling. */ if ((flags & TH_SYN) && (tp->t_flags & TF_REQ_SCALE)) { @@ -7760,6 +7807,13 @@ /* Processing the options. */ hdrlen += optlen = tcp_addoptions(&to, opt); + /* + * If we wanted a TFO option to be added, but it was unable + * to fit, ensure no data is sent. + */ + if (IS_FASTOPEN(tp->t_flags) && wanted_cookie && + !(to.to_flags & TOF_FASTOPEN)) + len = 0; } #ifdef NETFLIX_TCPOUDP if (tp->t_port) { Index: sys/netinet6/in6_ifattach.c =================================================================== --- sys/netinet6/in6_ifattach.c +++ sys/netinet6/in6_ifattach.c @@ -749,7 +749,6 @@ /* * nuke any of IPv6 addresses we have - * XXX: all addresses should be already removed */ CK_STAILQ_FOREACH_SAFE(ifa, &ifp->if_addrhead, ifa_link, next) { if (ifa->ifa_addr->sa_family != AF_INET6) Index: sys/netinet6/in6_pcb.c =================================================================== --- sys/netinet6/in6_pcb.c +++ sys/netinet6/in6_pcb.c @@ -946,7 +946,7 @@ INP_GROUP_LOCK(pcbgroup); head = &pcbgroup->ipg_hashbase[INP_PCBHASH( INP6_PCBHASHKEY(faddr), lport, fport, pcbgroup->ipg_hashmask)]; - LIST_FOREACH(inp, head, inp_pcbgrouphash) { + CK_LIST_FOREACH(inp, head, inp_pcbgrouphash) { /* XXX inp locking */ if ((inp->inp_vflag & INP_IPV6) == 0) continue; @@ -987,7 +987,7 @@ */ head = &pcbgroup->ipg_hashbase[ INP_PCBHASH(INADDR_ANY, lport, 0, pcbgroup->ipg_hashmask)]; - LIST_FOREACH(inp, head, inp_pcbgrouphash) { + CK_LIST_FOREACH(inp, head, inp_pcbgrouphash) { /* XXX inp locking */ if ((inp->inp_vflag & INP_IPV6) == 0) continue; @@ -1049,7 +1049,7 @@ head = &pcbinfo->ipi_wildbase[INP_PCBHASH( INP6_PCBHASHKEY(&in6addr_any), lport, 0, pcbinfo->ipi_wildmask)]; - LIST_FOREACH(inp, head, inp_pcbgroup_wild) { + CK_LIST_FOREACH(inp, head, inp_pcbgroup_wild) { /* XXX inp locking */ if ((inp->inp_vflag & INP_IPV6) == 0) continue; Index: sys/netinet6/ip6_gre.c =================================================================== --- sys/netinet6/ip6_gre.c +++ sys/netinet6/ip6_gre.c @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2014 Andrey V. Elsukov + * Copyright (c) 2014, 2018 Andrey V. Elsukov * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -31,16 +31,13 @@ #include "opt_inet6.h" #include -#include -#include +#include #include #include #include #include #include #include -#include -#include #include #include @@ -49,7 +46,6 @@ #include #include -#include #ifdef INET #include #include @@ -58,6 +54,7 @@ #include #include #include +#include #include VNET_DEFINE(int, ip6_gre_hlim) = IPV6_DEFHLIM; @@ -67,40 +64,184 @@ SYSCTL_INT(_net_inet6_ip6, OID_AUTO, grehlim, CTLFLAG_VNET | CTLFLAG_RW, &VNET_NAME(ip6_gre_hlim), 0, "Default hop limit for encapsulated packets"); +static VNET_DEFINE(struct gre_list *, ipv6_hashtbl) = NULL; +#define V_ipv6_hashtbl VNET(ipv6_hashtbl) +#define GRE_HASH(src, dst) (V_ipv6_hashtbl[\ + in6_gre_hashval((src), (dst)) & (GRE_HASH_SIZE - 1)]) +#define GRE_HASH_SC(sc) GRE_HASH(&(sc)->gre_oip6.ip6_src,\ + &(sc)->gre_oip6.ip6_dst) + +static uint32_t +in6_gre_hashval(const struct in6_addr *src, const struct in6_addr *dst) +{ + uint32_t ret; + + ret = fnv_32_buf(src, sizeof(*src), FNV1_32_INIT); + return (fnv_32_buf(dst, sizeof(*dst), ret)); +} + +static int +in6_gre_checkdup(const struct gre_softc *sc, const struct in6_addr *src, + const struct in6_addr *dst) +{ + struct gre_softc *tmp; + + if (sc->gre_family == AF_INET6 && + IN6_ARE_ADDR_EQUAL(&sc->gre_oip6.ip6_src, src) && + IN6_ARE_ADDR_EQUAL(&sc->gre_oip6.ip6_dst, dst)) + return (EEXIST); + + CK_LIST_FOREACH(tmp, &GRE_HASH(src, dst), chain) { + if (tmp == sc) + continue; + if (IN6_ARE_ADDR_EQUAL(&tmp->gre_oip6.ip6_src, src) && + IN6_ARE_ADDR_EQUAL(&tmp->gre_oip6.ip6_dst, dst)) + return (EADDRNOTAVAIL); + } + return (0); +} + static int -in6_gre_encapcheck(const struct mbuf *m, int off, int proto, void *arg) +in6_gre_lookup(const struct mbuf *m, int off, int proto, void **arg) { - GRE_RLOCK_TRACKER; + const struct ip6_hdr *ip6; struct gre_softc *sc; - struct ip6_hdr *ip6; - sc = (struct gre_softc *)arg; - if ((GRE2IFP(sc)->if_flags & IFF_UP) == 0) - return (0); + MPASS(in_epoch()); + ip6 = mtod(m, const struct ip6_hdr *); + CK_LIST_FOREACH(sc, &GRE_HASH(&ip6->ip6_dst, &ip6->ip6_src), chain) { + /* + * This is an inbound packet, its ip6_dst is source address + * in softc. + */ + if (IN6_ARE_ADDR_EQUAL(&sc->gre_oip6.ip6_src, + &ip6->ip6_dst) && + IN6_ARE_ADDR_EQUAL(&sc->gre_oip6.ip6_dst, + &ip6->ip6_src)) { + if ((GRE2IFP(sc)->if_flags & IFF_UP) == 0) + return (0); + *arg = sc; + return (ENCAP_DRV_LOOKUP); + } + } + return (0); +} - M_ASSERTPKTHDR(m); +static void +in6_gre_attach(struct gre_softc *sc) +{ - GRE_RLOCK(sc); - if (sc->gre_family == 0) - goto bad; + sc->gre_hlen = sizeof(struct greip6); + sc->gre_oip6.ip6_vfc = IPV6_VERSION; + sc->gre_oip6.ip6_nxt = IPPROTO_GRE; + gre_updatehdr(sc, &sc->gre_gi6hdr->gi6_gre); + CK_LIST_INSERT_HEAD(&GRE_HASH_SC(sc), sc, chain); +} - KASSERT(sc->gre_family == AF_INET6, - ("wrong gre_family: %d", sc->gre_family)); +void +in6_gre_setopts(struct gre_softc *sc, u_long cmd, uint32_t value) +{ - ip6 = mtod(m, struct ip6_hdr *); - if (!IN6_ARE_ADDR_EQUAL(&sc->gre_oip6.ip6_src, &ip6->ip6_dst) || - !IN6_ARE_ADDR_EQUAL(&sc->gre_oip6.ip6_dst, &ip6->ip6_src)) - goto bad; + MPASS(cmd == GRESKEY || cmd == GRESOPTS); - GRE_RUNLOCK(sc); - return (128 * 2 + 32); -bad: - GRE_RUNLOCK(sc); - return (0); + /* NOTE: we are protected with gre_ioctl_sx lock */ + MPASS(sc->gre_family == AF_INET6); + CK_LIST_REMOVE(sc, chain); + GRE_WAIT(); + if (cmd == GRESKEY) + sc->gre_key = value; + else + sc->gre_options = value; + in6_gre_attach(sc); } int -in6_gre_output(struct mbuf *m, int af, int hlen) +in6_gre_ioctl(struct gre_softc *sc, u_long cmd, caddr_t data) +{ + struct in6_ifreq *ifr = (struct in6_ifreq *)data; + struct sockaddr_in6 *dst, *src; + struct ip6_hdr *ip6; + int error; + + /* NOTE: we are protected with gre_ioctl_sx lock */ + error = EINVAL; + switch (cmd) { + case SIOCSIFPHYADDR_IN6: + src = &((struct in6_aliasreq *)data)->ifra_addr; + dst = &((struct in6_aliasreq *)data)->ifra_dstaddr; + + /* sanity checks */ + if (src->sin6_family != dst->sin6_family || + src->sin6_family != AF_INET6 || + src->sin6_len != dst->sin6_len || + src->sin6_len != sizeof(*src)) + break; + if (IN6_IS_ADDR_UNSPECIFIED(&src->sin6_addr) || + IN6_IS_ADDR_UNSPECIFIED(&dst->sin6_addr)) { + error = EADDRNOTAVAIL; + break; + } + /* + * Check validity of the scope zone ID of the + * addresses, and convert it into the kernel + * internal form if necessary. + */ + if ((error = sa6_embedscope(src, 0)) != 0 || + (error = sa6_embedscope(dst, 0)) != 0) + break; + + if (V_ipv6_hashtbl == NULL) + V_ipv6_hashtbl = gre_hashinit(); + error = in6_gre_checkdup(sc, &src->sin6_addr, + &dst->sin6_addr); + if (error == EADDRNOTAVAIL) + break; + if (error == EEXIST) { + /* Addresses are the same. Just return. */ + error = 0; + break; + } + ip6 = malloc(sizeof(struct greip6) + 3 * sizeof(uint32_t), + M_GRE, M_WAITOK | M_ZERO); + ip6->ip6_src = src->sin6_addr; + ip6->ip6_dst = dst->sin6_addr; + if (sc->gre_family != 0) { + /* Detach existing tunnel first */ + CK_LIST_REMOVE(sc, chain); + GRE_WAIT(); + free(sc->gre_hdr, M_GRE); + /* XXX: should we notify about link state change? */ + } + sc->gre_family = AF_INET6; + sc->gre_hdr = ip6; + sc->gre_oseq = 0; + sc->gre_iseq = UINT32_MAX; + in6_gre_attach(sc); + break; + case SIOCGIFPSRCADDR_IN6: + case SIOCGIFPDSTADDR_IN6: + if (sc->gre_family != AF_INET6) { + error = EADDRNOTAVAIL; + break; + } + src = (struct sockaddr_in6 *)&ifr->ifr_addr; + memset(src, 0, sizeof(*src)); + src->sin6_family = AF_INET6; + src->sin6_len = sizeof(*src); + src->sin6_addr = (cmd == SIOCGIFPSRCADDR_IN6) ? + sc->gre_oip6.ip6_src: sc->gre_oip6.ip6_dst; + error = prison_if(curthread->td_ucred, (struct sockaddr *)src); + if (error == 0) + error = sa6_recoverscope(src); + if (error != 0) + memset(src, 0, sizeof(*src)); + break; + } + return (error); +} + +int +in6_gre_output(struct mbuf *m, int af __unused, int hlen __unused) { struct greip6 *gi6; @@ -109,6 +250,7 @@ return (ip6_output(m, NULL, NULL, IPV6_MINMTU, NULL, NULL, NULL)); } +static const struct encaptab *ecookie = NULL; static const struct encap_config ipv6_encap_cfg = { .proto = IPPROTO_GRE, .min_length = sizeof(struct greip6) + @@ -117,16 +259,26 @@ #else sizeof(struct ip6_hdr), #endif - .exact_match = (sizeof(struct in6_addr) << 4) + 32, - .check = in6_gre_encapcheck, + .exact_match = ENCAP_DRV_LOOKUP, + .lookup = in6_gre_lookup, .input = gre_input }; -int -in6_gre_attach(struct gre_softc *sc) +void +in6_gre_init(void) { - KASSERT(sc->gre_ecookie == NULL, ("gre_ecookie isn't NULL")); - sc->gre_ecookie = ip6_encap_attach(&ipv6_encap_cfg, sc, M_WAITOK); - return (0); + if (!IS_DEFAULT_VNET(curvnet)) + return; + ecookie = ip6_encap_attach(&ipv6_encap_cfg, NULL, M_WAITOK); +} + +void +in6_gre_uninit(void) +{ + + if (IS_DEFAULT_VNET(curvnet)) + ip6_encap_detach(ecookie); + if (V_ipv6_hashtbl != NULL) + gre_hashdestroy(V_ipv6_hashtbl); } Index: sys/netinet6/mld6.c =================================================================== --- sys/netinet6/mld6.c +++ sys/netinet6/mld6.c @@ -1679,7 +1679,8 @@ IF_ADDR_WLOCK(ifp); restart: CK_STAILQ_FOREACH_SAFE(ifma, &ifp->if_multiaddrs, ifma_link, next) { - if (ifma->ifma_addr->sa_family != AF_INET6) + if (ifma->ifma_addr->sa_family != AF_INET6 || + ifma->ifma_protospec == NULL) continue; inm = (struct in6_multi *)ifma->ifma_protospec; switch (inm->in6m_state) { Index: sys/ofed/drivers/infiniband/core/ib_user_mad.c =================================================================== --- sys/ofed/drivers/infiniband/core/ib_user_mad.c +++ sys/ofed/drivers/infiniband/core/ib_user_mad.c @@ -130,7 +130,7 @@ static struct class *umad_class; -static const dev_t base_dev = MKDEV(IB_UMAD_MAJOR, IB_UMAD_MINOR_BASE); +#define base_dev MKDEV(IB_UMAD_MAJOR, IB_UMAD_MINOR_BASE) static DEFINE_SPINLOCK(port_lock); static DECLARE_BITMAP(dev_map, IB_UMAD_MAX_PORTS); Index: sys/riscv/riscv/locore.S =================================================================== --- sys/riscv/riscv/locore.S +++ sys/riscv/riscv/locore.S @@ -263,6 +263,21 @@ * Called by a core when it is being brought online. */ ENTRY(mpentry) + /* + * Calculate the offset to __riscv_boot_ap + * for the current core, cpuid is in a0. + */ + li t1, 4 + mulw t1, t1, a0 + /* Get the pointer */ + la t0, __riscv_boot_ap + add t0, t0, t1 + +1: + /* Wait the kernel to be ready */ + lw t1, 0(t0) + beqz t1, 1b + /* Setup stack pointer */ la t0, secondary_stacks li t1, (PAGE_SIZE * KSTACK_PAGES) @@ -296,20 +311,6 @@ /* Ensure sscratch is zero */ li t0, 0 csrw sscratch, t0 - /* - * Calculate the offset to __riscv_boot_ap - * for current core, cpuid in a0. - */ - li t1, 4 - mulw t1, t1, a0 - /* Get pointer */ - la t0, __riscv_boot_ap - add t0, t0, t1 - -1: - /* Wait the kernel to be ready */ - lw t1, 0(t0) - beqz t1, 1b call init_secondary END(mpentry) Index: sys/security/audit/audit_private.h =================================================================== --- sys/security/audit/audit_private.h +++ sys/security/audit/audit_private.h @@ -275,7 +275,7 @@ #define ARG_SADDRINET 0x0000000000100000ULL #define ARG_SADDRINET6 0x0000000000200000ULL #define ARG_SADDRUNIX 0x0000000000400000ULL -#define ARG_TERMID_ADDR 0x0000000000400000ULL +#define ARG_TERMID_ADDR 0x0000000000800000ULL #define ARG_UNUSED2 0x0000000001000000ULL #define ARG_UPATH1 0x0000000002000000ULL #define ARG_UPATH2 0x0000000004000000ULL Index: sys/sys/bio.h =================================================================== --- sys/sys/bio.h +++ sys/sys/bio.h @@ -138,6 +138,8 @@ TAILQ_HEAD(bio_queue, bio) queue; off_t last_offset; struct bio *insert_point; + int total; + int batched; }; extern struct vm_map *bio_transient_map; Index: sys/sys/malloc.h =================================================================== --- sys/sys/malloc.h +++ sys/sys/malloc.h @@ -49,7 +49,7 @@ #define MINALLOCSIZE UMA_SMALLEST_UNIT /* - * flags to malloc. + * Flags to memory allocation functions. */ #define M_NOWAIT 0x0001 /* do not block */ #define M_WAITOK 0x0002 /* ok to block */ @@ -59,6 +59,7 @@ #define M_NODUMP 0x0800 /* don't dump pages in this allocation */ #define M_FIRSTFIT 0x1000 /* Only for vmem, fast fit. */ #define M_BESTFIT 0x2000 /* Only for vmem, low fragmentation. */ +#define M_EXEC 0x4000 /* allocate executable space. */ #define M_MAGIC 877983977 /* time when first defined :-) */ Index: sys/sys/types.h =================================================================== --- sys/sys/types.h +++ sys/sys/types.h @@ -366,9 +366,36 @@ #include -#define major(x) ((int)((dev_t)(x) >> 32)) -#define minor(x) ((int)(x)) -#define makedev(x, y) (((dev_t)(x) << 32) | (unsigned)(y)) +/* + * The major and minor numbers are encoded in dev_t as MMMmmmMm (where + * letters correspond to bytes). The encoding of the lower 4 bytes is + * constrained by compatibility with 16-bit and 32-bit dev_t's. The + * encoding of of the upper 4 bytes is the least unnatural one consistent + * with this and other constraints. Also, the decoding of the m bytes by + * minor() is unnatural to maximize compatibility subject to not discarding + * bits. The upper m byte is shifted into the position of the lower M byte + * instead of shifting 3 upper m bytes to close the gap. Compatibility for + * minor() is achieved iff the upper m byte is 0. + */ +#define major(d) __major(d) +static __inline int +__major(dev_t _d) +{ + return (((_d >> 32) & 0xffffff00) | ((_d >> 8) & 0xff)); +} +#define minor(d) __minor(d) +static __inline int +__minor(dev_t _d) +{ + return (((_d >> 24) & 0xff00) | (_d & 0xffff00ff)); +} +#define makedev(M, m) __makedev((M), (m)) +static __inline dev_t +__makedev(int _M, int _m) +{ + return (((dev_t)(_M & 0xffffff00) << 32) | ((_M & 0xff) << 8) | + ((dev_t)(_m & 0xff00) << 24) | (_m & 0xffff00ff)); +} /* * These declarations belong elsewhere, but are repeated here and in Index: sys/vm/uma.h =================================================================== --- sys/vm/uma.h +++ sys/vm/uma.h @@ -617,11 +617,12 @@ * These flags are setable in the allocf and visible in the freef. */ #define UMA_SLAB_BOOT 0x01 /* Slab alloced from boot pages */ +#define UMA_SLAB_KRWX 0x02 /* Slab alloced from kernel_rwx_arena */ #define UMA_SLAB_KERNEL 0x04 /* Slab alloced from kernel_map */ #define UMA_SLAB_PRIV 0x08 /* Slab alloced from priv allocator */ #define UMA_SLAB_OFFP 0x10 /* Slab is managed separately */ #define UMA_SLAB_MALLOC 0x20 /* Slab is a large malloc slab */ -/* 0x02, 0x40 and 0x80 are available */ +/* 0x40 and 0x80 are available */ /* * Used to pre-fill a zone with some number of items Index: sys/vm/uma_core.c =================================================================== --- sys/vm/uma_core.c +++ sys/vm/uma_core.c @@ -1167,7 +1167,7 @@ void *p; /* Returned page */ *pflag = UMA_SLAB_KERNEL; - p = (void *) kmem_malloc_domain(domain, bytes, wait); + p = (void *) kmem_malloc_domain(kernel_arena, domain, bytes, wait); return (p); } @@ -2280,6 +2280,7 @@ WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL, "uma_zalloc_arg: zone \"%s\"", zone->uz_name); } + KASSERT((flags & M_EXEC) == 0, ("uma_zalloc_arg: called with M_EXEC")); KASSERT(curthread->td_critnest == 0 || SCHEDULER_STOPPED(), ("uma_zalloc_arg: called with spinlock or critical section held")); if (zone->uz_flags & UMA_ZONE_PCPU) @@ -3587,20 +3588,34 @@ void * uma_large_malloc_domain(vm_size_t size, int domain, int wait) { + struct vmem *arena; vm_offset_t addr; uma_slab_t slab; +#if VM_NRESERVLEVEL > 0 + if (__predict_true((wait & M_EXEC) == 0)) + arena = kernel_arena; + else + arena = kernel_rwx_arena; +#else + arena = kernel_arena; +#endif + slab = zone_alloc_item(slabzone, NULL, domain, wait); if (slab == NULL) return (NULL); if (domain == UMA_ANYDOMAIN) - addr = kmem_malloc(kernel_arena, size, wait); + addr = kmem_malloc(arena, size, wait); else - addr = kmem_malloc_domain(domain, size, wait); + addr = kmem_malloc_domain(arena, domain, size, wait); if (addr != 0) { vsetslab(addr, slab); slab->us_data = (void *)addr; slab->us_flags = UMA_SLAB_KERNEL | UMA_SLAB_MALLOC; +#if VM_NRESERVLEVEL > 0 + if (__predict_false(arena == kernel_rwx_arena)) + slab->us_flags |= UMA_SLAB_KRWX; +#endif slab->us_size = size; slab->us_domain = vm_phys_domain(PHYS_TO_VM_PAGE( pmap_kextract(addr))); @@ -3622,10 +3637,19 @@ void uma_large_free(uma_slab_t slab) { + struct vmem *arena; KASSERT((slab->us_flags & UMA_SLAB_KERNEL) != 0, ("uma_large_free: Memory not allocated with uma_large_malloc.")); - kmem_free(kernel_arena, (vm_offset_t)slab->us_data, slab->us_size); +#if VM_NRESERVLEVEL > 0 + if (__predict_true((slab->us_flags & UMA_SLAB_KRWX) == 0)) + arena = kernel_arena; + else + arena = kernel_rwx_arena; +#else + arena = kernel_arena; +#endif + kmem_free(arena, (vm_offset_t)slab->us_data, slab->us_size); uma_total_dec(slab->us_size); zone_free_item(slabzone, slab, NULL, SKIP_NONE); } Index: sys/vm/vm_extern.h =================================================================== --- sys/vm/vm_extern.h +++ sys/vm/vm_extern.h @@ -65,7 +65,8 @@ vm_paddr_t low, vm_paddr_t high, u_long alignment, vm_paddr_t boundary, vm_memattr_t memattr); vm_offset_t kmem_malloc(struct vmem *, vm_size_t size, int flags); -vm_offset_t kmem_malloc_domain(int domain, vm_size_t size, int flags); +vm_offset_t kmem_malloc_domain(struct vmem *, int domain, vm_size_t size, + int flags); void kmem_free(struct vmem *, vm_offset_t, vm_size_t); /* This provides memory for previously allocated address space. */ Index: sys/vm/vm_init.c =================================================================== --- sys/vm/vm_init.c +++ sys/vm/vm_init.c @@ -135,6 +135,23 @@ return (0); } +#if VM_NRESERVLEVEL > 0 +/* + * Import a superpage from the normal kernel arena into the special + * arena for allocations with different permissions. + */ +static int +kernel_rwx_alloc(void *arena, vmem_size_t size, int flags, vmem_addr_t *addrp) +{ + + KASSERT((size % KVA_QUANTUM) == 0, + ("kernel_rwx_alloc: Size %jd is not a multiple of %d", + (intmax_t)size, (int)KVA_QUANTUM)); + return (vmem_xalloc(arena, size, KVA_QUANTUM, 0, 0, VMEM_ADDR_MIN, + VMEM_ADDR_MAX, flags, addrp)); +} +#endif + /* * vm_init initializes the virtual memory system. * This is done only by the first cpu up. @@ -173,12 +190,31 @@ vmem_init(kernel_arena, "kernel arena", 0, 0, PAGE_SIZE, 0, 0); vmem_set_import(kernel_arena, kva_import, NULL, NULL, KVA_QUANTUM); +#if VM_NRESERVLEVEL > 0 + /* + * In an architecture with superpages, maintain a separate arena + * for allocations with permissions that differ from the "standard" + * read/write permissions used for memory in the kernel_arena. + */ + kernel_rwx_arena = vmem_create("kernel rwx arena", 0, 0, PAGE_SIZE, + 0, M_WAITOK); + vmem_set_import(kernel_rwx_arena, kernel_rwx_alloc, + (vmem_release_t *)vmem_xfree, kernel_arena, KVA_QUANTUM); +#endif + for (domain = 0; domain < vm_ndomains; domain++) { vm_dom[domain].vmd_kernel_arena = vmem_create( "kernel arena domain", 0, 0, PAGE_SIZE, 0, M_WAITOK); vmem_set_import(vm_dom[domain].vmd_kernel_arena, (vmem_import_t *)vmem_alloc, NULL, kernel_arena, KVA_QUANTUM); +#if VM_NRESERVLEVEL > 0 + vm_dom[domain].vmd_kernel_rwx_arena = vmem_create( + "kernel rwx arena domain", 0, 0, PAGE_SIZE, 0, M_WAITOK); + vmem_set_import(vm_dom[domain].vmd_kernel_rwx_arena, + kernel_rwx_alloc, (vmem_release_t *)vmem_xfree, + vm_dom[domain].vmd_kernel_arena, KVA_QUANTUM); +#endif } #ifndef UMA_MD_SMALL_ALLOC Index: sys/vm/vm_kern.h =================================================================== --- sys/vm/vm_kern.h +++ sys/vm/vm_kern.h @@ -70,6 +70,7 @@ extern vm_map_t exec_map; extern vm_map_t pipe_map; extern struct vmem *kernel_arena; +extern struct vmem *kernel_rwx_arena; extern struct vmem *kmem_arena; extern struct vmem *buffer_arena; extern struct vmem *transient_arena; Index: sys/vm/vm_kern.c =================================================================== --- sys/vm/vm_kern.c +++ sys/vm/vm_kern.c @@ -212,8 +212,8 @@ if ((flags & M_ZERO) && (m->flags & PG_ZERO) == 0) pmap_zero_page(m); m->valid = VM_PAGE_BITS_ALL; - pmap_enter(kernel_pmap, addr + i, m, VM_PROT_ALL, - VM_PROT_ALL | PMAP_ENTER_WIRED, 0); + pmap_enter(kernel_pmap, addr + i, m, VM_PROT_RW, + VM_PROT_RW | PMAP_ENTER_WIRED, 0); } VM_OBJECT_WUNLOCK(object); return (addr); @@ -298,8 +298,8 @@ if ((flags & M_ZERO) && (m->flags & PG_ZERO) == 0) pmap_zero_page(m); m->valid = VM_PAGE_BITS_ALL; - pmap_enter(kernel_pmap, tmp, m, VM_PROT_ALL, - VM_PROT_ALL | PMAP_ENTER_WIRED, 0); + pmap_enter(kernel_pmap, tmp, m, VM_PROT_RW, + VM_PROT_RW | PMAP_ENTER_WIRED, 0); tmp += PAGE_SIZE; } VM_OBJECT_WUNLOCK(object); @@ -372,20 +372,32 @@ * Allocate wired-down pages in the kernel's address space. */ vm_offset_t -kmem_malloc_domain(int domain, vm_size_t size, int flags) +kmem_malloc_domain(struct vmem *vmem, int domain, vm_size_t size, int flags) { - vmem_t *vmem; + vmem_t *arena; vm_offset_t addr; int rv; - vmem = vm_dom[domain].vmd_kernel_arena; +#if VM_NRESERVLEVEL > 0 + KASSERT(vmem == kernel_arena || vmem == kernel_rwx_arena, + ("kmem_malloc_domain: Only kernel_arena or kernel_rwx_arena " + "are supported.")); + if (__predict_true(vmem == kernel_arena)) + arena = vm_dom[domain].vmd_kernel_arena; + else + arena = vm_dom[domain].vmd_kernel_rwx_arena; +#else + KASSERT(vmem == kernel_arena, + ("kmem_malloc_domain: Only kernel_arena is supported.")); + arena = vm_dom[domain].vmd_kernel_arena; +#endif size = round_page(size); - if (vmem_alloc(vmem, size, flags | M_BESTFIT, &addr)) + if (vmem_alloc(arena, size, flags | M_BESTFIT, &addr)) return (0); rv = kmem_back_domain(domain, kernel_object, addr, size, flags); if (rv != KERN_SUCCESS) { - vmem_free(vmem, addr, size); + vmem_free(arena, addr, size); return (0); } return (addr); @@ -398,12 +410,9 @@ vm_offset_t addr; int domain; - KASSERT(vmem == kernel_arena, - ("kmem_malloc: Only kernel_arena is supported.")); - vm_domainset_iter_malloc_init(&di, kernel_object, &domain, &flags); do { - addr = kmem_malloc_domain(domain, size, flags); + addr = kmem_malloc_domain(vmem, domain, size, flags); if (addr != 0) break; } while (vm_domainset_iter_malloc(&di, &domain, &flags) == 0); @@ -422,6 +431,7 @@ { vm_offset_t offset, i; vm_page_t m, mpred; + vm_prot_t prot; int pflags; KASSERT(object == kernel_object, @@ -432,6 +442,7 @@ pflags &= ~(VM_ALLOC_NOWAIT | VM_ALLOC_WAITOK | VM_ALLOC_WAITFAIL); if (flags & M_WAITOK) pflags |= VM_ALLOC_WAITFAIL; + prot = (flags & M_EXEC) != 0 ? VM_PROT_ALL : VM_PROT_RW; i = 0; VM_OBJECT_WLOCK(object); @@ -461,8 +472,8 @@ KASSERT((m->oflags & VPO_UNMANAGED) != 0, ("kmem_malloc: page %p is managed", m)); m->valid = VM_PAGE_BITS_ALL; - pmap_enter(kernel_pmap, addr + i, m, VM_PROT_ALL, - VM_PROT_ALL | PMAP_ENTER_WIRED, 0); + pmap_enter(kernel_pmap, addr + i, m, prot, + prot | PMAP_ENTER_WIRED, 0); } VM_OBJECT_WUNLOCK(object); @@ -542,13 +553,28 @@ void kmem_free(struct vmem *vmem, vm_offset_t addr, vm_size_t size) { + struct vmem *arena; int domain; +#if VM_NRESERVLEVEL > 0 + KASSERT(vmem == kernel_arena || vmem == kernel_rwx_arena, + ("kmem_free: Only kernel_arena or kernel_rwx_arena are supported.")); +#else KASSERT(vmem == kernel_arena, ("kmem_free: Only kernel_arena is supported.")); +#endif + size = round_page(size); domain = _kmem_unback(kernel_object, addr, size); - vmem_free(vm_dom[domain].vmd_kernel_arena, addr, size); +#if VM_NRESERVLEVEL > 0 + if (__predict_true(vmem == kernel_arena)) + arena = vm_dom[domain].vmd_kernel_arena; + else + arena = vm_dom[domain].vmd_kernel_rwx_arena; +#else + arena = vm_dom[domain].vmd_kernel_arena; +#endif + vmem_free(arena, addr, size); } /* Index: sys/vm/vm_pagequeue.h =================================================================== --- sys/vm/vm_pagequeue.h +++ sys/vm/vm_pagequeue.h @@ -103,7 +103,8 @@ struct mtx_padalign vmd_free_mtx; struct mtx_padalign vmd_pageout_mtx; uma_zone_t vmd_pgcache; /* (c) page free cache. */ - struct vmem *vmd_kernel_arena; /* (c) per-domain kva arena. */ + struct vmem *vmd_kernel_arena; /* (c) per-domain kva R/W arena. */ + struct vmem *vmd_kernel_rwx_arena; /* (c) per-domain kva R/W/X arena. */ u_int vmd_domain; /* (c) Domain number. */ u_int vmd_page_count; /* (c) Total page count. */ long vmd_segs; /* (c) bitmask of the segments */ Index: tests/sys/audit/file-attribute-access.c =================================================================== --- tests/sys/audit/file-attribute-access.c +++ tests/sys/audit/file-attribute-access.c @@ -25,6 +25,9 @@ * $FreeBSD$ */ +#include +#include +#include #include #include @@ -36,8 +39,11 @@ static struct pollfd fds[1]; static mode_t mode = 0777; +static pid_t pid; +static int filedesc; static char extregex[80]; static struct stat statbuff; +static struct statfs statfsbuff; static const char *auclass = "fa"; static const char *path = "fileforaudit"; static const char *errpath = "dirdoesnotexist/fileforaudit"; @@ -55,10 +61,11 @@ ATF_TC_BODY(stat_success, tc) { /* File needs to exist to call stat(2) */ - ATF_REQUIRE(open(path, O_CREAT, mode) != -1); + ATF_REQUIRE((filedesc = open(path, O_CREAT, mode)) != -1); FILE *pipefd = setup(fds, auclass); ATF_REQUIRE_EQ(0, stat(path, &statbuff)); check_audit(fds, successreg, pipefd); + close(filedesc); } ATF_TC_CLEANUP(stat_success, tc) @@ -140,7 +147,6 @@ ATF_TC_BODY(fstat_success, tc) { - int filedesc; /* File needs to exist to call fstat(2) */ ATF_REQUIRE((filedesc = open(path, O_CREAT | O_RDWR, mode)) != -1); FILE *pipefd = setup(fds, auclass); @@ -149,6 +155,7 @@ snprintf(extregex, sizeof(extregex), "fstat.*%jd.*return,success", (intmax_t)statbuff.st_ino); check_audit(fds, extregex, pipefd); + close(filedesc); } ATF_TC_CLEANUP(fstat_success, tc) @@ -224,6 +231,145 @@ } +ATF_TC_WITH_CLEANUP(statfs_success); +ATF_TC_HEAD(statfs_success, tc) +{ + atf_tc_set_md_var(tc, "descr", "Tests the audit of a successful " + "statfs(2) call"); +} + +ATF_TC_BODY(statfs_success, tc) +{ + /* File needs to exist to call statfs(2) */ + ATF_REQUIRE((filedesc = open(path, O_CREAT, mode)) != -1); + FILE *pipefd = setup(fds, auclass); + ATF_REQUIRE_EQ(0, statfs(path, &statfsbuff)); + check_audit(fds, successreg, pipefd); + close(filedesc); +} + +ATF_TC_CLEANUP(statfs_success, tc) +{ + cleanup(); +} + + +ATF_TC_WITH_CLEANUP(statfs_failure); +ATF_TC_HEAD(statfs_failure, tc) +{ + atf_tc_set_md_var(tc, "descr", "Tests the audit of an unsuccessful " + "statfs(2) call"); +} + +ATF_TC_BODY(statfs_failure, tc) +{ + FILE *pipefd = setup(fds, auclass); + /* Failure reason: file does not exist */ + ATF_REQUIRE_EQ(-1, statfs(errpath, &statfsbuff)); + check_audit(fds, failurereg, pipefd); +} + +ATF_TC_CLEANUP(statfs_failure, tc) +{ + cleanup(); +} + + +ATF_TC_WITH_CLEANUP(fstatfs_success); +ATF_TC_HEAD(fstatfs_success, tc) +{ + atf_tc_set_md_var(tc, "descr", "Tests the audit of a successful " + "fstatfs(2) call"); +} + +ATF_TC_BODY(fstatfs_success, tc) +{ + /* File needs to exist to call fstat(2) */ + ATF_REQUIRE((filedesc = open(path, O_CREAT | O_RDWR, mode)) != -1); + /* Call stat(2) to store the Inode number of 'path' */ + ATF_REQUIRE_EQ(0, stat(path, &statbuff)); + FILE *pipefd = setup(fds, auclass); + ATF_REQUIRE_EQ(0, fstatfs(filedesc, &statfsbuff)); + + snprintf(extregex, sizeof(extregex), "fstatfs.*%jd.*return,success", + (intmax_t)statbuff.st_ino); + check_audit(fds, extregex, pipefd); + close(filedesc); +} + +ATF_TC_CLEANUP(fstatfs_success, tc) +{ + cleanup(); +} + + +ATF_TC_WITH_CLEANUP(fstatfs_failure); +ATF_TC_HEAD(fstatfs_failure, tc) +{ + atf_tc_set_md_var(tc, "descr", "Tests the audit of an unsuccessful " + "fstatfs(2) call"); +} + +ATF_TC_BODY(fstatfs_failure, tc) +{ + FILE *pipefd = setup(fds, auclass); + const char *regex = "fstatfs.*return,failure : Bad file descriptor"; + /* Failure reason: bad file descriptor */ + ATF_REQUIRE_EQ(-1, fstatfs(-1, &statfsbuff)); + check_audit(fds, regex, pipefd); +} + +ATF_TC_CLEANUP(fstatfs_failure, tc) +{ + cleanup(); +} + + +ATF_TC_WITH_CLEANUP(getfsstat_success); +ATF_TC_HEAD(getfsstat_success, tc) +{ + atf_tc_set_md_var(tc, "descr", "Tests the audit of a successful " + "getfsstat(2) call"); +} + +ATF_TC_BODY(getfsstat_success, tc) +{ + pid = getpid(); + snprintf(extregex, sizeof(extregex), "getfsstat.*%d.*success", pid); + + FILE *pipefd = setup(fds, auclass); + ATF_REQUIRE(getfsstat(NULL, 0, MNT_NOWAIT) != -1); + check_audit(fds, extregex, pipefd); +} + +ATF_TC_CLEANUP(getfsstat_success, tc) +{ + cleanup(); +} + + +ATF_TC_WITH_CLEANUP(getfsstat_failure); +ATF_TC_HEAD(getfsstat_failure, tc) +{ + atf_tc_set_md_var(tc, "descr", "Tests the audit of an unsuccessful " + "getfsstat(2) call"); +} + +ATF_TC_BODY(getfsstat_failure, tc) +{ + const char *regex = "getfsstat.*return,failure : Invalid argument"; + FILE *pipefd = setup(fds, auclass); + /* Failure reason: Invalid value for mode */ + ATF_REQUIRE_EQ(-1, getfsstat(NULL, 0, -1)); + check_audit(fds, regex, pipefd); +} + +ATF_TC_CLEANUP(getfsstat_failure, tc) +{ + cleanup(); +} + + ATF_TP_ADD_TCS(tp) { ATF_TP_ADD_TC(tp, stat_success); @@ -235,5 +381,13 @@ ATF_TP_ADD_TC(tp, fstatat_success); ATF_TP_ADD_TC(tp, fstatat_failure); + ATF_TP_ADD_TC(tp, statfs_success); + ATF_TP_ADD_TC(tp, statfs_failure); + ATF_TP_ADD_TC(tp, fstatfs_success); + ATF_TP_ADD_TC(tp, fstatfs_failure); + + ATF_TP_ADD_TC(tp, getfsstat_success); + ATF_TP_ADD_TC(tp, getfsstat_failure); + return (atf_no_error()); } Index: tests/sys/audit/file-close.c =================================================================== --- tests/sys/audit/file-close.c +++ tests/sys/audit/file-close.c @@ -40,6 +40,7 @@ static pid_t pid; static struct pollfd fds[1]; static mode_t mode = 0777; +static int filedesc; static char extregex[80]; static struct stat statbuff; static const char *auclass = "cl"; @@ -103,7 +104,6 @@ ATF_TC_BODY(close_success, tc) { - int filedesc; /* File needs to exist to call close(2) */ ATF_REQUIRE((filedesc = open(path, O_CREAT | O_RDWR, mode)) != -1); /* Call stat(2) to store the Inode number of 'path' */ @@ -176,7 +176,6 @@ ATF_TC_BODY(revoke_success, tc) { - int filedesc; char *ptyname; pid = getpid(); snprintf(extregex, sizeof(extregex), "revoke.*%d.*return,success", pid); @@ -188,9 +187,7 @@ FILE *pipefd = setup(fds, auclass); ATF_REQUIRE_EQ(0, revoke(ptyname)); check_audit(fds, extregex, pipefd); - - /* Close the file descriptor to pseudo terminal */ - ATF_REQUIRE_EQ(0, close(filedesc)); + close(filedesc); } ATF_TC_CLEANUP(revoke_success, tc) Index: tests/sys/audit/file-create.c =================================================================== --- tests/sys/audit/file-create.c +++ tests/sys/audit/file-create.c @@ -37,6 +37,7 @@ static struct pollfd fds[1]; static mode_t mode = 0777; +static int filedesc; static dev_t dev = 0; static const char *auclass = "fc"; static const char *path = "fileforaudit"; @@ -305,10 +306,11 @@ ATF_TC_BODY(rename_success, tc) { - ATF_REQUIRE(open(path, O_CREAT, mode) != -1); + ATF_REQUIRE((filedesc = open(path, O_CREAT, mode)) != -1); FILE *pipefd = setup(fds, auclass); ATF_REQUIRE_EQ(0, rename(path, "renamed")); check_audit(fds, successreg, pipefd); + close(filedesc); } ATF_TC_CLEANUP(rename_success, tc) @@ -347,10 +349,11 @@ ATF_TC_BODY(renameat_success, tc) { - ATF_REQUIRE(open(path, O_CREAT, mode) != -1); + ATF_REQUIRE((filedesc = open(path, O_CREAT, mode)) != -1); FILE *pipefd = setup(fds, auclass); ATF_REQUIRE_EQ(0, renameat(AT_FDCWD, path, AT_FDCWD, "renamed")); check_audit(fds, successreg, pipefd); + close(filedesc); } ATF_TC_CLEANUP(renameat_success, tc) @@ -389,10 +392,11 @@ ATF_TC_BODY(link_success, tc) { - ATF_REQUIRE(open(path, O_CREAT, mode) != -1); + ATF_REQUIRE((filedesc = open(path, O_CREAT, mode)) != -1); FILE *pipefd = setup(fds, auclass); ATF_REQUIRE_EQ(0, link(path, "hardlink")); check_audit(fds, successreg, pipefd); + close(filedesc); } ATF_TC_CLEANUP(link_success, tc) @@ -431,10 +435,11 @@ ATF_TC_BODY(linkat_success, tc) { - ATF_REQUIRE(open(path, O_CREAT, mode) != -1); + ATF_REQUIRE((filedesc = open(path, O_CREAT, mode)) != -1); FILE *pipefd = setup(fds, auclass); ATF_REQUIRE_EQ(0, linkat(AT_FDCWD, path, AT_FDCWD, "hardlink", 0)); check_audit(fds, successreg, pipefd); + close(filedesc); } ATF_TC_CLEANUP(linkat_success, tc) Index: tests/sys/audit/file-delete.c =================================================================== --- tests/sys/audit/file-delete.c +++ tests/sys/audit/file-delete.c @@ -35,6 +35,7 @@ static struct pollfd fds[1]; static mode_t mode = 0777; +static int filedesc; static const char *path = "fileforaudit"; static const char *errpath = "dirdoesnotexist/fileforaudit"; static const char *successreg = "fileforaudit.*return,success"; @@ -92,10 +93,11 @@ ATF_TC_BODY(rename_success, tc) { - ATF_REQUIRE(open(path, O_CREAT, mode) != -1); + ATF_REQUIRE((filedesc = open(path, O_CREAT, mode)) != -1); FILE *pipefd = setup(fds, "fd"); ATF_REQUIRE_EQ(0, rename(path, "renamed")); check_audit(fds, successreg, pipefd); + close(filedesc); } ATF_TC_CLEANUP(rename_success, tc) @@ -134,10 +136,11 @@ ATF_TC_BODY(renameat_success, tc) { - ATF_REQUIRE(open(path, O_CREAT, mode) != -1); + ATF_REQUIRE((filedesc = open(path, O_CREAT, mode)) != -1); FILE *pipefd = setup(fds, "fd"); ATF_REQUIRE_EQ(0, renameat(AT_FDCWD, path, AT_FDCWD, "renamed")); check_audit(fds, successreg, pipefd); + close(filedesc); } ATF_TC_CLEANUP(renameat_success, tc) @@ -176,10 +179,11 @@ ATF_TC_BODY(unlink_success, tc) { - ATF_REQUIRE(open(path, O_CREAT, mode) != -1); + ATF_REQUIRE((filedesc = open(path, O_CREAT, mode)) != -1); FILE *pipefd = setup(fds, "fd"); ATF_REQUIRE_EQ(0, unlink(path)); check_audit(fds, successreg, pipefd); + close(filedesc); } ATF_TC_CLEANUP(unlink_success, tc) Index: tests/sys/audit/file-write.c =================================================================== --- tests/sys/audit/file-write.c +++ tests/sys/audit/file-write.c @@ -32,6 +32,7 @@ static struct pollfd fds[1]; static mode_t mode = 0777; +static int filedesc; static off_t offlen = 0; static const char *path = "fileforaudit"; static const char *errpath = "dirdoesnotexist/fileforaudit"; @@ -49,10 +50,11 @@ ATF_TC_BODY(truncate_success, tc) { /* File needs to exist to call truncate(2) */ - ATF_REQUIRE(open(path, O_CREAT, mode) != -1); + ATF_REQUIRE((filedesc = open(path, O_CREAT, mode)) != -1); FILE *pipefd = setup(fds, "fw"); ATF_REQUIRE_EQ(0, truncate(path, offlen)); check_audit(fds, successreg, pipefd); + close(filedesc); } ATF_TC_CLEANUP(truncate_success, tc) @@ -91,13 +93,13 @@ ATF_TC_BODY(ftruncate_success, tc) { - int filedesc; const char *regex = "ftruncate.*return,success"; /* Valid file descriptor needs to exist to call ftruncate(2) */ ATF_REQUIRE((filedesc = open(path, O_CREAT | O_RDWR)) != -1); FILE *pipefd = setup(fds, "fw"); ATF_REQUIRE_EQ(0, ftruncate(filedesc, offlen)); check_audit(fds, regex, pipefd); + close(filedesc); } ATF_TC_CLEANUP(ftruncate_success, tc) Index: tests/sys/audit/open.c =================================================================== --- tests/sys/audit/open.c +++ tests/sys/audit/open.c @@ -52,6 +52,7 @@ static struct pollfd fds[1]; static mode_t o_mode = 0777; +static int filedesc; static char extregex[80]; static const char *path = "fileforaudit"; static const char *errpath = "adirhasnoname/fileforaudit"; @@ -71,10 +72,11 @@ snprintf(extregex, sizeof(extregex), \ "open.*%s.*fileforaudit.*return,success", regex); \ /* File needs to exist for successful open(2) invocation */ \ - ATF_REQUIRE(open(path, O_CREAT, o_mode) != -1); \ + ATF_REQUIRE((filedesc = open(path, O_CREAT, o_mode)) != -1); \ FILE *pipefd = setup(fds, class); \ ATF_REQUIRE(syscall(SYS_open, path, flag) != -1); \ check_audit(fds, extregex, pipefd); \ + close(filedesc); \ } \ ATF_TC_CLEANUP(open_ ## mode ## _success, tc) \ { \ @@ -106,13 +108,16 @@ } \ ATF_TC_BODY(openat_ ## mode ## _success, tc) \ { \ + int filedesc2; \ snprintf(extregex, sizeof(extregex), \ "openat.*%s.*fileforaudit.*return,success", regex); \ /* File needs to exist for successful openat(2) invocation */ \ - ATF_REQUIRE(open(path, O_CREAT, o_mode) != -1); \ + ATF_REQUIRE((filedesc = open(path, O_CREAT, o_mode)) != -1); \ FILE *pipefd = setup(fds, class); \ - ATF_REQUIRE(openat(AT_FDCWD, path, flag) != -1); \ + ATF_REQUIRE((filedesc2 = openat(AT_FDCWD, path, flag)) != -1); \ check_audit(fds, extregex, pipefd); \ + close(filedesc2); \ + close(filedesc); \ } \ ATF_TC_CLEANUP(openat_ ## mode ## _success, tc) \ { \ Index: tests/sys/audit/utils.c =================================================================== --- tests/sys/audit/utils.c +++ tests/sys/audit/utils.c @@ -27,15 +27,16 @@ #include -#include +#include +#include + +#include #include #include -#include -#include #include +#include +#include #include -#include -#include #include "utils.h" @@ -79,7 +80,7 @@ } free(buff); - fclose(memstream); + ATF_REQUIRE_EQ(0, fclose(memstream)); return (atf_utils_grep_string("%s", membuff, auditregex)); } @@ -194,9 +195,8 @@ check_audit(struct pollfd fd[], const char *auditrgx, FILE *pipestream) { check_auditpipe(fd, auditrgx, pipestream); - /* Cleanup */ - fclose(pipestream); - close(fd[0].fd); + /* Teardown: /dev/auditpipe's instance opened for this test-suite */ + ATF_REQUIRE_EQ(0, fclose(pipestream)); } FILE @@ -207,9 +207,9 @@ nomask = get_audit_mask("no"); FILE *pipestream; - fd[0].fd = open("/dev/auditpipe", O_RDONLY); + ATF_REQUIRE((fd[0].fd = open("/dev/auditpipe", O_RDONLY)) != -1); + ATF_REQUIRE((pipestream = fdopen(fd[0].fd, "r")) != NULL); fd[0].events = POLLIN; - pipestream = fdopen(fd[0].fd, "r"); /* Set local preselection audit_class as "no" for audit startup */ set_preselect_mode(fd[0].fd, &nomask); Index: usr.bin/top/machine.c =================================================================== --- usr.bin/top/machine.c +++ usr.bin/top/machine.c @@ -304,7 +304,7 @@ { int i, j, empty, pagesize; uint64_t arc_size; - bool carc_en; + int carc_en; size_t size; size = sizeof(smpmode); Index: usr.bin/top/top.1 =================================================================== --- usr.bin/top/top.1 +++ usr.bin/top/top.1 @@ -360,7 +360,6 @@ Lock names are prefixed with an asterisk \*(lq*\*(rq while sleep events are not. .Sh AUTHORS -.An Eitan Adler Aq Mt eadler@FreeBSD.org .An William LeFebvre, EECS Department, Northwestern University .Sh BUGS The command name for swapped processes should be tracked down, but this Index: usr.bin/top/utils.c =================================================================== --- usr.bin/top/utils.c +++ usr.bin/top/utils.c @@ -122,7 +122,7 @@ * string_index(string, array) - find string in array and return index */ -int __pure +int string_index(const char *string, const char * const *array) { size_t i = 0; @@ -175,7 +175,7 @@ * useful on for calculating cpu state percentages. */ -long __pure +long percentages(int cnt, int *out, long *new, long *old, long *diffs) { int i; @@ -210,13 +210,10 @@ /* calculate percentages based on overall change, rounding up */ half_total = total_change / 2l; - /* Do not divide by 0. Causes Floating point exception */ - if(total_change) { - for (i = 0; i < cnt; i++) - { - *out++ = (int)((*diffs++ * 1000 + half_total) / total_change); - } - } + for (i = 0; i < cnt; i++) + { + *out++ = (int)((*diffs++ * 1000 + half_total) / total_change); + } /* return the total in case the caller wants to use it */ return(total_change); Index: usr.sbin/bhyve/acpi.c =================================================================== --- usr.sbin/bhyve/acpi.c +++ usr.sbin/bhyve/acpi.c @@ -885,7 +885,7 @@ int len; err = 0; - + /* * */ Index: usr.sbin/bhyve/ahci.h =================================================================== --- usr.sbin/bhyve/ahci.h +++ usr.sbin/bhyve/ahci.h @@ -33,292 +33,292 @@ #define _AHCI_H_ /* ATA register defines */ -#define ATA_DATA 0 /* (RW) data */ - -#define ATA_FEATURE 1 /* (W) feature */ -#define ATA_F_DMA 0x01 /* enable DMA */ -#define ATA_F_OVL 0x02 /* enable overlap */ - -#define ATA_COUNT 2 /* (W) sector count */ - -#define ATA_SECTOR 3 /* (RW) sector # */ -#define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ -#define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */ -#define ATA_DRIVE 6 /* (W) Sector/Drive/Head */ -#define ATA_D_LBA 0x40 /* use LBA addressing */ -#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ - -#define ATA_COMMAND 7 /* (W) command */ - -#define ATA_ERROR 8 /* (R) error */ -#define ATA_E_ILI 0x01 /* illegal length */ -#define ATA_E_NM 0x02 /* no media */ -#define ATA_E_ABORT 0x04 /* command aborted */ -#define ATA_E_MCR 0x08 /* media change request */ -#define ATA_E_IDNF 0x10 /* ID not found */ -#define ATA_E_MC 0x20 /* media changed */ -#define ATA_E_UNC 0x40 /* uncorrectable data */ -#define ATA_E_ICRC 0x80 /* UDMA crc error */ -#define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */ - -#define ATA_IREASON 9 /* (R) interrupt reason */ -#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ -#define ATA_I_IN 0x02 /* read (1) | write (0) */ -#define ATA_I_RELEASE 0x04 /* released bus (1) */ -#define ATA_I_TAGMASK 0xf8 /* tag mask */ - -#define ATA_STATUS 10 /* (R) status */ -#define ATA_ALTSTAT 11 /* (R) alternate status */ -#define ATA_S_ERROR 0x01 /* error */ -#define ATA_S_INDEX 0x02 /* index */ -#define ATA_S_CORR 0x04 /* data corrected */ -#define ATA_S_DRQ 0x08 /* data request */ -#define ATA_S_DSC 0x10 /* drive seek completed */ -#define ATA_S_SERVICE 0x10 /* drive needs service */ -#define ATA_S_DWF 0x20 /* drive write fault */ -#define ATA_S_DMA 0x20 /* DMA ready */ -#define ATA_S_READY 0x40 /* drive ready */ -#define ATA_S_BUSY 0x80 /* busy */ - -#define ATA_CONTROL 12 /* (W) control */ -#define ATA_A_IDS 0x02 /* disable interrupts */ -#define ATA_A_RESET 0x04 /* RESET controller */ -#define ATA_A_4BIT 0x08 /* 4 head bits */ -#define ATA_A_HOB 0x80 /* High Order Byte enable */ +#define ATA_DATA 0 /* (RW) data */ + +#define ATA_FEATURE 1 /* (W) feature */ +#define ATA_F_DMA 0x01 /* enable DMA */ +#define ATA_F_OVL 0x02 /* enable overlap */ + +#define ATA_COUNT 2 /* (W) sector count */ + +#define ATA_SECTOR 3 /* (RW) sector # */ +#define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ +#define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */ +#define ATA_DRIVE 6 /* (W) Sector/Drive/Head */ +#define ATA_D_LBA 0x40 /* use LBA addressing */ +#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ + +#define ATA_COMMAND 7 /* (W) command */ + +#define ATA_ERROR 8 /* (R) error */ +#define ATA_E_ILI 0x01 /* illegal length */ +#define ATA_E_NM 0x02 /* no media */ +#define ATA_E_ABORT 0x04 /* command aborted */ +#define ATA_E_MCR 0x08 /* media change request */ +#define ATA_E_IDNF 0x10 /* ID not found */ +#define ATA_E_MC 0x20 /* media changed */ +#define ATA_E_UNC 0x40 /* uncorrectable data */ +#define ATA_E_ICRC 0x80 /* UDMA crc error */ +#define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */ + +#define ATA_IREASON 9 /* (R) interrupt reason */ +#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ +#define ATA_I_IN 0x02 /* read (1) | write (0) */ +#define ATA_I_RELEASE 0x04 /* released bus (1) */ +#define ATA_I_TAGMASK 0xf8 /* tag mask */ + +#define ATA_STATUS 10 /* (R) status */ +#define ATA_ALTSTAT 11 /* (R) alternate status */ +#define ATA_S_ERROR 0x01 /* error */ +#define ATA_S_INDEX 0x02 /* index */ +#define ATA_S_CORR 0x04 /* data corrected */ +#define ATA_S_DRQ 0x08 /* data request */ +#define ATA_S_DSC 0x10 /* drive seek completed */ +#define ATA_S_SERVICE 0x10 /* drive needs service */ +#define ATA_S_DWF 0x20 /* drive write fault */ +#define ATA_S_DMA 0x20 /* DMA ready */ +#define ATA_S_READY 0x40 /* drive ready */ +#define ATA_S_BUSY 0x80 /* busy */ + +#define ATA_CONTROL 12 /* (W) control */ +#define ATA_A_IDS 0x02 /* disable interrupts */ +#define ATA_A_RESET 0x04 /* RESET controller */ +#define ATA_A_4BIT 0x08 /* 4 head bits */ +#define ATA_A_HOB 0x80 /* High Order Byte enable */ /* SATA register defines */ -#define ATA_SSTATUS 13 -#define ATA_SS_DET_MASK 0x0000000f -#define ATA_SS_DET_NO_DEVICE 0x00000000 -#define ATA_SS_DET_DEV_PRESENT 0x00000001 -#define ATA_SS_DET_PHY_ONLINE 0x00000003 -#define ATA_SS_DET_PHY_OFFLINE 0x00000004 - -#define ATA_SS_SPD_MASK 0x000000f0 -#define ATA_SS_SPD_NO_SPEED 0x00000000 -#define ATA_SS_SPD_GEN1 0x00000010 -#define ATA_SS_SPD_GEN2 0x00000020 -#define ATA_SS_SPD_GEN3 0x00000030 - -#define ATA_SS_IPM_MASK 0x00000f00 -#define ATA_SS_IPM_NO_DEVICE 0x00000000 -#define ATA_SS_IPM_ACTIVE 0x00000100 -#define ATA_SS_IPM_PARTIAL 0x00000200 -#define ATA_SS_IPM_SLUMBER 0x00000600 -#define ATA_SS_IPM_DEVSLEEP 0x00000800 - -#define ATA_SERROR 14 -#define ATA_SE_DATA_CORRECTED 0x00000001 -#define ATA_SE_COMM_CORRECTED 0x00000002 -#define ATA_SE_DATA_ERR 0x00000100 -#define ATA_SE_COMM_ERR 0x00000200 -#define ATA_SE_PROT_ERR 0x00000400 -#define ATA_SE_HOST_ERR 0x00000800 -#define ATA_SE_PHY_CHANGED 0x00010000 -#define ATA_SE_PHY_IERROR 0x00020000 -#define ATA_SE_COMM_WAKE 0x00040000 -#define ATA_SE_DECODE_ERR 0x00080000 -#define ATA_SE_PARITY_ERR 0x00100000 -#define ATA_SE_CRC_ERR 0x00200000 -#define ATA_SE_HANDSHAKE_ERR 0x00400000 -#define ATA_SE_LINKSEQ_ERR 0x00800000 -#define ATA_SE_TRANSPORT_ERR 0x01000000 -#define ATA_SE_UNKNOWN_FIS 0x02000000 -#define ATA_SE_EXCHANGED 0x04000000 - -#define ATA_SCONTROL 15 -#define ATA_SC_DET_MASK 0x0000000f -#define ATA_SC_DET_IDLE 0x00000000 -#define ATA_SC_DET_RESET 0x00000001 -#define ATA_SC_DET_DISABLE 0x00000004 - -#define ATA_SC_SPD_MASK 0x000000f0 -#define ATA_SC_SPD_NO_SPEED 0x00000000 -#define ATA_SC_SPD_SPEED_GEN1 0x00000010 -#define ATA_SC_SPD_SPEED_GEN2 0x00000020 -#define ATA_SC_SPD_SPEED_GEN3 0x00000030 - -#define ATA_SC_IPM_MASK 0x00000f00 -#define ATA_SC_IPM_NONE 0x00000000 -#define ATA_SC_IPM_DIS_PARTIAL 0x00000100 -#define ATA_SC_IPM_DIS_SLUMBER 0x00000200 -#define ATA_SC_IPM_DIS_DEVSLEEP 0x00000400 - -#define ATA_SACTIVE 16 - -#define AHCI_MAX_PORTS 32 -#define AHCI_MAX_SLOTS 32 -#define AHCI_MAX_IRQS 16 +#define ATA_SSTATUS 13 +#define ATA_SS_DET_MASK 0x0000000f +#define ATA_SS_DET_NO_DEVICE 0x00000000 +#define ATA_SS_DET_DEV_PRESENT 0x00000001 +#define ATA_SS_DET_PHY_ONLINE 0x00000003 +#define ATA_SS_DET_PHY_OFFLINE 0x00000004 + +#define ATA_SS_SPD_MASK 0x000000f0 +#define ATA_SS_SPD_NO_SPEED 0x00000000 +#define ATA_SS_SPD_GEN1 0x00000010 +#define ATA_SS_SPD_GEN2 0x00000020 +#define ATA_SS_SPD_GEN3 0x00000030 + +#define ATA_SS_IPM_MASK 0x00000f00 +#define ATA_SS_IPM_NO_DEVICE 0x00000000 +#define ATA_SS_IPM_ACTIVE 0x00000100 +#define ATA_SS_IPM_PARTIAL 0x00000200 +#define ATA_SS_IPM_SLUMBER 0x00000600 +#define ATA_SS_IPM_DEVSLEEP 0x00000800 + +#define ATA_SERROR 14 +#define ATA_SE_DATA_CORRECTED 0x00000001 +#define ATA_SE_COMM_CORRECTED 0x00000002 +#define ATA_SE_DATA_ERR 0x00000100 +#define ATA_SE_COMM_ERR 0x00000200 +#define ATA_SE_PROT_ERR 0x00000400 +#define ATA_SE_HOST_ERR 0x00000800 +#define ATA_SE_PHY_CHANGED 0x00010000 +#define ATA_SE_PHY_IERROR 0x00020000 +#define ATA_SE_COMM_WAKE 0x00040000 +#define ATA_SE_DECODE_ERR 0x00080000 +#define ATA_SE_PARITY_ERR 0x00100000 +#define ATA_SE_CRC_ERR 0x00200000 +#define ATA_SE_HANDSHAKE_ERR 0x00400000 +#define ATA_SE_LINKSEQ_ERR 0x00800000 +#define ATA_SE_TRANSPORT_ERR 0x01000000 +#define ATA_SE_UNKNOWN_FIS 0x02000000 +#define ATA_SE_EXCHANGED 0x04000000 + +#define ATA_SCONTROL 15 +#define ATA_SC_DET_MASK 0x0000000f +#define ATA_SC_DET_IDLE 0x00000000 +#define ATA_SC_DET_RESET 0x00000001 +#define ATA_SC_DET_DISABLE 0x00000004 + +#define ATA_SC_SPD_MASK 0x000000f0 +#define ATA_SC_SPD_NO_SPEED 0x00000000 +#define ATA_SC_SPD_SPEED_GEN1 0x00000010 +#define ATA_SC_SPD_SPEED_GEN2 0x00000020 +#define ATA_SC_SPD_SPEED_GEN3 0x00000030 + +#define ATA_SC_IPM_MASK 0x00000f00 +#define ATA_SC_IPM_NONE 0x00000000 +#define ATA_SC_IPM_DIS_PARTIAL 0x00000100 +#define ATA_SC_IPM_DIS_SLUMBER 0x00000200 +#define ATA_SC_IPM_DIS_DEVSLEEP 0x00000400 + +#define ATA_SACTIVE 16 + +#define AHCI_MAX_PORTS 32 +#define AHCI_MAX_SLOTS 32 +#define AHCI_MAX_IRQS 16 /* SATA AHCI v1.0 register defines */ -#define AHCI_CAP 0x00 -#define AHCI_CAP_NPMASK 0x0000001f -#define AHCI_CAP_SXS 0x00000020 -#define AHCI_CAP_EMS 0x00000040 -#define AHCI_CAP_CCCS 0x00000080 -#define AHCI_CAP_NCS 0x00001F00 -#define AHCI_CAP_NCS_SHIFT 8 -#define AHCI_CAP_PSC 0x00002000 -#define AHCI_CAP_SSC 0x00004000 -#define AHCI_CAP_PMD 0x00008000 -#define AHCI_CAP_FBSS 0x00010000 -#define AHCI_CAP_SPM 0x00020000 -#define AHCI_CAP_SAM 0x00080000 -#define AHCI_CAP_ISS 0x00F00000 -#define AHCI_CAP_ISS_SHIFT 20 -#define AHCI_CAP_SCLO 0x01000000 -#define AHCI_CAP_SAL 0x02000000 -#define AHCI_CAP_SALP 0x04000000 -#define AHCI_CAP_SSS 0x08000000 -#define AHCI_CAP_SMPS 0x10000000 -#define AHCI_CAP_SSNTF 0x20000000 -#define AHCI_CAP_SNCQ 0x40000000 -#define AHCI_CAP_64BIT 0x80000000 - -#define AHCI_GHC 0x04 -#define AHCI_GHC_AE 0x80000000 -#define AHCI_GHC_MRSM 0x00000004 -#define AHCI_GHC_IE 0x00000002 -#define AHCI_GHC_HR 0x00000001 - -#define AHCI_IS 0x08 -#define AHCI_PI 0x0c -#define AHCI_VS 0x10 - -#define AHCI_CCCC 0x14 -#define AHCI_CCCC_TV_MASK 0xffff0000 -#define AHCI_CCCC_TV_SHIFT 16 -#define AHCI_CCCC_CC_MASK 0x0000ff00 -#define AHCI_CCCC_CC_SHIFT 8 -#define AHCI_CCCC_INT_MASK 0x000000f8 -#define AHCI_CCCC_INT_SHIFT 3 -#define AHCI_CCCC_EN 0x00000001 -#define AHCI_CCCP 0x18 - -#define AHCI_EM_LOC 0x1C -#define AHCI_EM_CTL 0x20 -#define AHCI_EM_MR 0x00000001 -#define AHCI_EM_TM 0x00000100 -#define AHCI_EM_RST 0x00000200 -#define AHCI_EM_LED 0x00010000 -#define AHCI_EM_SAFTE 0x00020000 -#define AHCI_EM_SES2 0x00040000 -#define AHCI_EM_SGPIO 0x00080000 -#define AHCI_EM_SMB 0x01000000 -#define AHCI_EM_XMT 0x02000000 -#define AHCI_EM_ALHD 0x04000000 -#define AHCI_EM_PM 0x08000000 - -#define AHCI_CAP2 0x24 -#define AHCI_CAP2_BOH 0x00000001 -#define AHCI_CAP2_NVMP 0x00000002 -#define AHCI_CAP2_APST 0x00000004 -#define AHCI_CAP2_SDS 0x00000008 -#define AHCI_CAP2_SADM 0x00000010 -#define AHCI_CAP2_DESO 0x00000020 - -#define AHCI_OFFSET 0x100 -#define AHCI_STEP 0x80 - -#define AHCI_P_CLB 0x00 -#define AHCI_P_CLBU 0x04 -#define AHCI_P_FB 0x08 -#define AHCI_P_FBU 0x0c -#define AHCI_P_IS 0x10 -#define AHCI_P_IE 0x14 -#define AHCI_P_IX_DHR 0x00000001 -#define AHCI_P_IX_PS 0x00000002 -#define AHCI_P_IX_DS 0x00000004 -#define AHCI_P_IX_SDB 0x00000008 -#define AHCI_P_IX_UF 0x00000010 -#define AHCI_P_IX_DP 0x00000020 -#define AHCI_P_IX_PC 0x00000040 -#define AHCI_P_IX_MP 0x00000080 - -#define AHCI_P_IX_PRC 0x00400000 -#define AHCI_P_IX_IPM 0x00800000 -#define AHCI_P_IX_OF 0x01000000 -#define AHCI_P_IX_INF 0x04000000 -#define AHCI_P_IX_IF 0x08000000 -#define AHCI_P_IX_HBD 0x10000000 -#define AHCI_P_IX_HBF 0x20000000 -#define AHCI_P_IX_TFE 0x40000000 -#define AHCI_P_IX_CPD 0x80000000 - -#define AHCI_P_CMD 0x18 -#define AHCI_P_CMD_ST 0x00000001 -#define AHCI_P_CMD_SUD 0x00000002 -#define AHCI_P_CMD_POD 0x00000004 -#define AHCI_P_CMD_CLO 0x00000008 -#define AHCI_P_CMD_FRE 0x00000010 -#define AHCI_P_CMD_CCS_MASK 0x00001f00 -#define AHCI_P_CMD_CCS_SHIFT 8 -#define AHCI_P_CMD_ISS 0x00002000 -#define AHCI_P_CMD_FR 0x00004000 -#define AHCI_P_CMD_CR 0x00008000 -#define AHCI_P_CMD_CPS 0x00010000 -#define AHCI_P_CMD_PMA 0x00020000 -#define AHCI_P_CMD_HPCP 0x00040000 -#define AHCI_P_CMD_MPSP 0x00080000 -#define AHCI_P_CMD_CPD 0x00100000 -#define AHCI_P_CMD_ESP 0x00200000 -#define AHCI_P_CMD_FBSCP 0x00400000 -#define AHCI_P_CMD_APSTE 0x00800000 -#define AHCI_P_CMD_ATAPI 0x01000000 -#define AHCI_P_CMD_DLAE 0x02000000 -#define AHCI_P_CMD_ALPE 0x04000000 -#define AHCI_P_CMD_ASP 0x08000000 -#define AHCI_P_CMD_ICC_MASK 0xf0000000 -#define AHCI_P_CMD_NOOP 0x00000000 -#define AHCI_P_CMD_ACTIVE 0x10000000 -#define AHCI_P_CMD_PARTIAL 0x20000000 -#define AHCI_P_CMD_SLUMBER 0x60000000 -#define AHCI_P_CMD_DEVSLEEP 0x80000000 - -#define AHCI_P_TFD 0x20 -#define AHCI_P_SIG 0x24 -#define AHCI_P_SSTS 0x28 -#define AHCI_P_SCTL 0x2c -#define AHCI_P_SERR 0x30 -#define AHCI_P_SACT 0x34 -#define AHCI_P_CI 0x38 -#define AHCI_P_SNTF 0x3C -#define AHCI_P_FBS 0x40 -#define AHCI_P_FBS_EN 0x00000001 -#define AHCI_P_FBS_DEC 0x00000002 -#define AHCI_P_FBS_SDE 0x00000004 -#define AHCI_P_FBS_DEV 0x00000f00 -#define AHCI_P_FBS_DEV_SHIFT 8 -#define AHCI_P_FBS_ADO 0x0000f000 -#define AHCI_P_FBS_ADO_SHIFT 12 -#define AHCI_P_FBS_DWE 0x000f0000 -#define AHCI_P_FBS_DWE_SHIFT 16 -#define AHCI_P_DEVSLP 0x44 -#define AHCI_P_DEVSLP_ADSE 0x00000001 -#define AHCI_P_DEVSLP_DSP 0x00000002 -#define AHCI_P_DEVSLP_DETO 0x000003fc -#define AHCI_P_DEVSLP_DETO_SHIFT 2 -#define AHCI_P_DEVSLP_MDAT 0x00007c00 -#define AHCI_P_DEVSLP_MDAT_SHIFT 10 -#define AHCI_P_DEVSLP_DITO 0x01ff8000 -#define AHCI_P_DEVSLP_DITO_SHIFT 15 -#define AHCI_P_DEVSLP_DM 0x0e000000 -#define AHCI_P_DEVSLP_DM_SHIFT 25 +#define AHCI_CAP 0x00 +#define AHCI_CAP_NPMASK 0x0000001f +#define AHCI_CAP_SXS 0x00000020 +#define AHCI_CAP_EMS 0x00000040 +#define AHCI_CAP_CCCS 0x00000080 +#define AHCI_CAP_NCS 0x00001F00 +#define AHCI_CAP_NCS_SHIFT 8 +#define AHCI_CAP_PSC 0x00002000 +#define AHCI_CAP_SSC 0x00004000 +#define AHCI_CAP_PMD 0x00008000 +#define AHCI_CAP_FBSS 0x00010000 +#define AHCI_CAP_SPM 0x00020000 +#define AHCI_CAP_SAM 0x00080000 +#define AHCI_CAP_ISS 0x00F00000 +#define AHCI_CAP_ISS_SHIFT 20 +#define AHCI_CAP_SCLO 0x01000000 +#define AHCI_CAP_SAL 0x02000000 +#define AHCI_CAP_SALP 0x04000000 +#define AHCI_CAP_SSS 0x08000000 +#define AHCI_CAP_SMPS 0x10000000 +#define AHCI_CAP_SSNTF 0x20000000 +#define AHCI_CAP_SNCQ 0x40000000 +#define AHCI_CAP_64BIT 0x80000000 + +#define AHCI_GHC 0x04 +#define AHCI_GHC_AE 0x80000000 +#define AHCI_GHC_MRSM 0x00000004 +#define AHCI_GHC_IE 0x00000002 +#define AHCI_GHC_HR 0x00000001 + +#define AHCI_IS 0x08 +#define AHCI_PI 0x0c +#define AHCI_VS 0x10 + +#define AHCI_CCCC 0x14 +#define AHCI_CCCC_TV_MASK 0xffff0000 +#define AHCI_CCCC_TV_SHIFT 16 +#define AHCI_CCCC_CC_MASK 0x0000ff00 +#define AHCI_CCCC_CC_SHIFT 8 +#define AHCI_CCCC_INT_MASK 0x000000f8 +#define AHCI_CCCC_INT_SHIFT 3 +#define AHCI_CCCC_EN 0x00000001 +#define AHCI_CCCP 0x18 + +#define AHCI_EM_LOC 0x1C +#define AHCI_EM_CTL 0x20 +#define AHCI_EM_MR 0x00000001 +#define AHCI_EM_TM 0x00000100 +#define AHCI_EM_RST 0x00000200 +#define AHCI_EM_LED 0x00010000 +#define AHCI_EM_SAFTE 0x00020000 +#define AHCI_EM_SES2 0x00040000 +#define AHCI_EM_SGPIO 0x00080000 +#define AHCI_EM_SMB 0x01000000 +#define AHCI_EM_XMT 0x02000000 +#define AHCI_EM_ALHD 0x04000000 +#define AHCI_EM_PM 0x08000000 + +#define AHCI_CAP2 0x24 +#define AHCI_CAP2_BOH 0x00000001 +#define AHCI_CAP2_NVMP 0x00000002 +#define AHCI_CAP2_APST 0x00000004 +#define AHCI_CAP2_SDS 0x00000008 +#define AHCI_CAP2_SADM 0x00000010 +#define AHCI_CAP2_DESO 0x00000020 + +#define AHCI_OFFSET 0x100 +#define AHCI_STEP 0x80 + +#define AHCI_P_CLB 0x00 +#define AHCI_P_CLBU 0x04 +#define AHCI_P_FB 0x08 +#define AHCI_P_FBU 0x0c +#define AHCI_P_IS 0x10 +#define AHCI_P_IE 0x14 +#define AHCI_P_IX_DHR 0x00000001 +#define AHCI_P_IX_PS 0x00000002 +#define AHCI_P_IX_DS 0x00000004 +#define AHCI_P_IX_SDB 0x00000008 +#define AHCI_P_IX_UF 0x00000010 +#define AHCI_P_IX_DP 0x00000020 +#define AHCI_P_IX_PC 0x00000040 +#define AHCI_P_IX_MP 0x00000080 + +#define AHCI_P_IX_PRC 0x00400000 +#define AHCI_P_IX_IPM 0x00800000 +#define AHCI_P_IX_OF 0x01000000 +#define AHCI_P_IX_INF 0x04000000 +#define AHCI_P_IX_IF 0x08000000 +#define AHCI_P_IX_HBD 0x10000000 +#define AHCI_P_IX_HBF 0x20000000 +#define AHCI_P_IX_TFE 0x40000000 +#define AHCI_P_IX_CPD 0x80000000 + +#define AHCI_P_CMD 0x18 +#define AHCI_P_CMD_ST 0x00000001 +#define AHCI_P_CMD_SUD 0x00000002 +#define AHCI_P_CMD_POD 0x00000004 +#define AHCI_P_CMD_CLO 0x00000008 +#define AHCI_P_CMD_FRE 0x00000010 +#define AHCI_P_CMD_CCS_MASK 0x00001f00 +#define AHCI_P_CMD_CCS_SHIFT 8 +#define AHCI_P_CMD_ISS 0x00002000 +#define AHCI_P_CMD_FR 0x00004000 +#define AHCI_P_CMD_CR 0x00008000 +#define AHCI_P_CMD_CPS 0x00010000 +#define AHCI_P_CMD_PMA 0x00020000 +#define AHCI_P_CMD_HPCP 0x00040000 +#define AHCI_P_CMD_MPSP 0x00080000 +#define AHCI_P_CMD_CPD 0x00100000 +#define AHCI_P_CMD_ESP 0x00200000 +#define AHCI_P_CMD_FBSCP 0x00400000 +#define AHCI_P_CMD_APSTE 0x00800000 +#define AHCI_P_CMD_ATAPI 0x01000000 +#define AHCI_P_CMD_DLAE 0x02000000 +#define AHCI_P_CMD_ALPE 0x04000000 +#define AHCI_P_CMD_ASP 0x08000000 +#define AHCI_P_CMD_ICC_MASK 0xf0000000 +#define AHCI_P_CMD_NOOP 0x00000000 +#define AHCI_P_CMD_ACTIVE 0x10000000 +#define AHCI_P_CMD_PARTIAL 0x20000000 +#define AHCI_P_CMD_SLUMBER 0x60000000 +#define AHCI_P_CMD_DEVSLEEP 0x80000000 + +#define AHCI_P_TFD 0x20 +#define AHCI_P_SIG 0x24 +#define AHCI_P_SSTS 0x28 +#define AHCI_P_SCTL 0x2c +#define AHCI_P_SERR 0x30 +#define AHCI_P_SACT 0x34 +#define AHCI_P_CI 0x38 +#define AHCI_P_SNTF 0x3C +#define AHCI_P_FBS 0x40 +#define AHCI_P_FBS_EN 0x00000001 +#define AHCI_P_FBS_DEC 0x00000002 +#define AHCI_P_FBS_SDE 0x00000004 +#define AHCI_P_FBS_DEV 0x00000f00 +#define AHCI_P_FBS_DEV_SHIFT 8 +#define AHCI_P_FBS_ADO 0x0000f000 +#define AHCI_P_FBS_ADO_SHIFT 12 +#define AHCI_P_FBS_DWE 0x000f0000 +#define AHCI_P_FBS_DWE_SHIFT 16 +#define AHCI_P_DEVSLP 0x44 +#define AHCI_P_DEVSLP_ADSE 0x00000001 +#define AHCI_P_DEVSLP_DSP 0x00000002 +#define AHCI_P_DEVSLP_DETO 0x000003fc +#define AHCI_P_DEVSLP_DETO_SHIFT 2 +#define AHCI_P_DEVSLP_MDAT 0x00007c00 +#define AHCI_P_DEVSLP_MDAT_SHIFT 10 +#define AHCI_P_DEVSLP_DITO 0x01ff8000 +#define AHCI_P_DEVSLP_DITO_SHIFT 15 +#define AHCI_P_DEVSLP_DM 0x0e000000 +#define AHCI_P_DEVSLP_DM_SHIFT 25 /* Just to be sure, if building as module. */ #if MAXPHYS < 512 * 1024 #undef MAXPHYS -#define MAXPHYS 512 * 1024 +#define MAXPHYS 512 * 1024 #endif /* Pessimistic prognosis on number of required S/G entries */ -#define AHCI_SG_ENTRIES (roundup(btoc(MAXPHYS) + 1, 8)) +#define AHCI_SG_ENTRIES (roundup(btoc(MAXPHYS) + 1, 8)) /* Command list. 32 commands. First, 1Kbyte aligned. */ -#define AHCI_CL_OFFSET 0 -#define AHCI_CL_SIZE 32 +#define AHCI_CL_OFFSET 0 +#define AHCI_CL_SIZE 32 /* Command tables. Up to 32 commands, Each, 128byte aligned. */ -#define AHCI_CT_OFFSET (AHCI_CL_OFFSET + AHCI_CL_SIZE * AHCI_MAX_SLOTS) -#define AHCI_CT_SIZE (128 + AHCI_SG_ENTRIES * 16) +#define AHCI_CT_OFFSET (AHCI_CL_OFFSET + AHCI_CL_SIZE * AHCI_MAX_SLOTS) +#define AHCI_CT_SIZE (128 + AHCI_SG_ENTRIES * 16) /* Total main work area. */ -#define AHCI_WORK_SIZE (AHCI_CT_OFFSET + AHCI_CT_SIZE * ch->numslots) +#define AHCI_WORK_SIZE (AHCI_CT_OFFSET + AHCI_CT_SIZE * ch->numslots) #endif /* _AHCI_H_ */ Index: usr.sbin/bhyve/bhyverun.c =================================================================== --- usr.sbin/bhyve/bhyverun.c +++ usr.sbin/bhyve/bhyverun.c @@ -118,14 +118,14 @@ static struct vm_exit vmexit[VM_MAXCPU]; struct bhyvestats { - uint64_t vmexit_bogus; + uint64_t vmexit_bogus; uint64_t vmexit_reqidle; - uint64_t vmexit_hlt; - uint64_t vmexit_pause; - uint64_t vmexit_mtrap; - uint64_t vmexit_inst_emul; - uint64_t cpu_switch_rotate; - uint64_t cpu_switch_direct; + uint64_t vmexit_hlt; + uint64_t vmexit_pause; + uint64_t vmexit_mtrap; + uint64_t vmexit_inst_emul; + uint64_t cpu_switch_rotate; + uint64_t cpu_switch_direct; } stats; struct mt_vmm_info { @@ -413,7 +413,7 @@ * put guest-driven debug here */ #endif - return (VMEXIT_CONTINUE); + return (VMEXIT_CONTINUE); } static int Index: usr.sbin/bhyve/block_if.c =================================================================== --- usr.sbin/bhyve/block_if.c +++ usr.sbin/bhyve/block_if.c @@ -101,8 +101,8 @@ int bc_psectoff; int bc_closing; pthread_t bc_btid[BLOCKIF_NUMTHR]; - pthread_mutex_t bc_mtx; - pthread_cond_t bc_cond; + pthread_mutex_t bc_mtx; + pthread_cond_t bc_cond; /* Request elements and free/pending/busy queues */ TAILQ_HEAD(, blockif_elem) bc_freeq; Index: usr.sbin/bhyve/bootrom.h =================================================================== --- usr.sbin/bhyve/bootrom.h +++ usr.sbin/bhyve/bootrom.h @@ -35,6 +35,6 @@ struct vmctx; -int bootrom_init(struct vmctx *ctx, const char *romfile); +int bootrom_init(struct vmctx *ctx, const char *romfile); #endif Index: usr.sbin/bhyve/console.h =================================================================== --- usr.sbin/bhyve/console.h +++ usr.sbin/bhyve/console.h @@ -37,19 +37,19 @@ typedef void (*kbd_event_func_t)(int down, uint32_t keysym, void *arg); typedef void (*ptr_event_func_t)(uint8_t mask, int x, int y, void *arg); -void console_init(int w, int h, void *fbaddr); +void console_init(int w, int h, void *fbaddr); -void console_set_fbaddr(void *fbaddr); +void console_set_fbaddr(void *fbaddr); struct bhyvegc_image *console_get_image(void); -void console_fb_register(fb_render_func_t render_cb, void *arg); -void console_refresh(void); +void console_fb_register(fb_render_func_t render_cb, void *arg); +void console_refresh(void); -void console_kbd_register(kbd_event_func_t event_cb, void *arg, int pri); -void console_key_event(int down, uint32_t keysym); +void console_kbd_register(kbd_event_func_t event_cb, void *arg, int pri); +void console_key_event(int down, uint32_t keysym); -void console_ptr_register(ptr_event_func_t event_cb, void *arg, int pri); -void console_ptr_event(uint8_t button, int x, int y); +void console_ptr_register(ptr_event_func_t event_cb, void *arg, int pri); +void console_ptr_event(uint8_t button, int x, int y); #endif /* _CONSOLE_H_ */ Index: usr.sbin/bhyve/consport.c =================================================================== --- usr.sbin/bhyve/consport.c +++ usr.sbin/bhyve/consport.c @@ -74,14 +74,14 @@ static bool tty_char_available(void) { - fd_set rfds; - struct timeval tv; - - FD_ZERO(&rfds); - FD_SET(STDIN_FILENO, &rfds); - tv.tv_sec = 0; - tv.tv_usec = 0; - if (select(STDIN_FILENO + 1, &rfds, NULL, NULL, &tv) > 0) { + fd_set rfds; + struct timeval tv; + + FD_ZERO(&rfds); + FD_SET(STDIN_FILENO, &rfds); + tv.tv_sec = 0; + tv.tv_usec = 0; + if (select(STDIN_FILENO + 1, &rfds, NULL, NULL, &tv) > 0) { return (true); } else { return (false); Index: usr.sbin/bhyve/inout.c =================================================================== --- usr.sbin/bhyve/inout.c +++ usr.sbin/bhyve/inout.c @@ -68,21 +68,21 @@ default_inout(struct vmctx *ctx, int vcpu, int in, int port, int bytes, uint32_t *eax, void *arg) { - if (in) { - switch (bytes) { - case 4: - *eax = 0xffffffff; - break; - case 2: - *eax = 0xffff; - break; - case 1: - *eax = 0xff; - break; - } - } - - return (0); + if (in) { + switch (bytes) { + case 4: + *eax = 0xffffffff; + break; + case 2: + *eax = 0xffff; + break; + case 1: + *eax = 0xff; + break; + } + } + + return (0); } static void Index: usr.sbin/bhyve/mem.h =================================================================== --- usr.sbin/bhyve/mem.h +++ usr.sbin/bhyve/mem.h @@ -55,7 +55,7 @@ void init_mem(void); int emulate_mem(struct vmctx *, int vcpu, uint64_t paddr, struct vie *vie, struct vm_guest_paging *paging); - + int read_mem(struct vmctx *ctx, int vcpu, uint64_t gpa, uint64_t *rval, int size); int register_mem(struct mem_range *memp); Index: usr.sbin/bhyve/mem.c =================================================================== --- usr.sbin/bhyve/mem.c +++ usr.sbin/bhyve/mem.c @@ -38,15 +38,16 @@ __FBSDID("$FreeBSD$"); #include -#include #include +#include #include #include -#include -#include #include +#include #include +#include +#include #include "mem.h" @@ -285,8 +286,11 @@ err = 0; mrp = malloc(sizeof(struct mmio_rb_range)); - - if (mrp != NULL) { + if (mrp == NULL) { + warn("%s: couldn't allocate memory for mrp\n", + __func__); + err = ENOMEM; + } else { mrp->mr_param = *memp; mrp->mr_base = memp->base; mrp->mr_end = memp->base + memp->size - 1; @@ -297,8 +301,7 @@ assert(perror == 0); if (err) free(mrp); - } else - err = ENOMEM; + } return (err); } Index: usr.sbin/bhyve/mevent.c =================================================================== --- usr.sbin/bhyve/mevent.c +++ usr.sbin/bhyve/mevent.c @@ -71,7 +71,7 @@ static int mevent_pipefd[2]; static pthread_mutex_t mevent_lmutex = PTHREAD_MUTEX_INITIALIZER; -struct mevent { +struct mevent { void (*me_func)(int, enum ev_type, void *); #define me_msecs me_fd int me_fd; @@ -81,7 +81,7 @@ int me_cq; int me_state; int me_closefd; - LIST_ENTRY(mevent) me_list; + LIST_ENTRY(mevent) me_list; }; static LIST_HEAD(listhead, mevent) global_head, change_head; Index: usr.sbin/bhyve/mevent_test.c =================================================================== --- usr.sbin/bhyve/mevent_test.c +++ usr.sbin/bhyve/mevent_test.c @@ -199,25 +199,25 @@ int s; static int first; - if ((s = socket(AF_INET, SOCK_STREAM, 0)) < 0) { - perror("socket"); - exit(1); - } - - sin.sin_len = sizeof(sin); - sin.sin_family = AF_INET; - sin.sin_addr.s_addr = htonl(INADDR_ANY); - sin.sin_port = htons(TEST_PORT); - - if (bind(s, (struct sockaddr *)&sin, sizeof(sin)) < 0) { - perror("bind"); - exit(1); - } - - if (listen(s, 1) < 0) { - perror("listen"); - exit(1); - } + if ((s = socket(AF_INET, SOCK_STREAM, 0)) < 0) { + perror("socket"); + exit(1); + } + + sin.sin_len = sizeof(sin); + sin.sin_family = AF_INET; + sin.sin_addr.s_addr = htonl(INADDR_ANY); + sin.sin_port = htons(TEST_PORT); + + if (bind(s, (struct sockaddr *)&sin, sizeof(sin)) < 0) { + perror("bind"); + exit(1); + } + + if (listen(s, 1) < 0) { + perror("listen"); + exit(1); + } (void) mevent_add(s, EVF_READ, acceptor_callback, NULL); Index: usr.sbin/bhyve/pci_e82545.c =================================================================== --- usr.sbin/bhyve/pci_e82545.c +++ usr.sbin/bhyve/pci_e82545.c @@ -344,8 +344,8 @@ #define E82545_NVM_MODE_OPADDR 0x0 #define E82545_NVM_MODE_DATAIN 0x1 #define E82545_NVM_MODE_DATAOUT 0x2 - /* EEPROM data */ - uint16_t eeprom_data[E82545_NVM_EEPROM_SIZE]; + /* EEPROM data */ + uint16_t eeprom_data[E82545_NVM_EEPROM_SIZE]; }; static void e82545_reset(struct e82545_softc *sc, int dev); @@ -1472,7 +1472,7 @@ static void e82545_write_ra(struct e82545_softc *sc, int reg, uint32_t wval) { - struct eth_uni *eu; + struct eth_uni *eu; int idx; idx = reg >> 1; @@ -1498,7 +1498,7 @@ static uint32_t e82545_read_ra(struct e82545_softc *sc, int reg) { - struct eth_uni *eu; + struct eth_uni *eu; uint32_t retval; int idx; @@ -1742,12 +1742,12 @@ { uint32_t retval; int ridx; - + if (offset & 0x3) { DPRINTF("Unaligned register read offset:0x%x\r\n", offset); return 0; } - + DPRINTF("Register read: 0x%x\r\n", offset); switch (offset) { Index: usr.sbin/bhyve/pci_emul.c =================================================================== --- usr.sbin/bhyve/pci_emul.c +++ usr.sbin/bhyve/pci_emul.c @@ -863,7 +863,7 @@ { uint16_t msgctrl, rwmask; int off; - + off = offset - capoff; /* Message Control Register */ if (off == 2 && bytes == 2) { @@ -876,8 +876,8 @@ pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE; pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK; pci_lintr_update(pi); - } - + } + CFGWRITE(pi, offset, val, bytes); } @@ -1336,11 +1336,11 @@ dsdt_line("Name (PPRT, Package ()"); dsdt_line("{"); pci_walk_lintr(bus, pci_pirq_prt_entry, NULL); - dsdt_line("})"); + dsdt_line("})"); dsdt_line("Name (APRT, Package ()"); dsdt_line("{"); pci_walk_lintr(bus, pci_apic_prt_entry, NULL); - dsdt_line("})"); + dsdt_line("})"); dsdt_line("Method (_PRT, 0, NotSerialized)"); dsdt_line("{"); dsdt_line(" If (PICM)"); @@ -1726,7 +1726,7 @@ * interrupt. */ pci_lintr_update(pi); -} +} static void pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot, int func, Index: usr.sbin/bhyve/pci_virtio_net.c =================================================================== --- usr.sbin/bhyve/pci_virtio_net.c +++ usr.sbin/bhyve/pci_virtio_net.c @@ -726,24 +726,24 @@ static int pci_vtnet_parsemac(char *mac_str, uint8_t *mac_addr) { - struct ether_addr *ea; - char *tmpstr; - char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 }; + struct ether_addr *ea; + char *tmpstr; + char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 }; - tmpstr = strsep(&mac_str,"="); - - if ((mac_str != NULL) && (!strcmp(tmpstr,"mac"))) { - ea = ether_aton(mac_str); + tmpstr = strsep(&mac_str,"="); - if (ea == NULL || ETHER_IS_MULTICAST(ea->octet) || - memcmp(ea->octet, zero_addr, ETHER_ADDR_LEN) == 0) { + if ((mac_str != NULL) && (!strcmp(tmpstr,"mac"))) { + ea = ether_aton(mac_str); + + if (ea == NULL || ETHER_IS_MULTICAST(ea->octet) || + memcmp(ea->octet, zero_addr, ETHER_ADDR_LEN) == 0) { fprintf(stderr, "Invalid MAC %s\n", mac_str); - return (EINVAL); - } else - memcpy(mac_addr, ea->octet, ETHER_ADDR_LEN); - } + return (EINVAL); + } else + memcpy(mac_addr, ea->octet, ETHER_ADDR_LEN); + } - return (0); + return (0); } static void @@ -932,7 +932,7 @@ pthread_create(&sc->tx_tid, NULL, pci_vtnet_tx_thread, (void *)sc); snprintf(tname, sizeof(tname), "vtnet-%d:%d tx", pi->pi_slot, pi->pi_func); - pthread_set_name_np(sc->tx_tid, tname); + pthread_set_name_np(sc->tx_tid, tname); return (0); } Index: usr.sbin/bhyve/pci_xhci.c =================================================================== --- usr.sbin/bhyve/pci_xhci.c +++ usr.sbin/bhyve/pci_xhci.c @@ -2212,12 +2212,12 @@ sc = pi->pi_arg; - assert(baridx == 0); + assert(baridx == 0); - pthread_mutex_lock(&sc->mtx); + pthread_mutex_lock(&sc->mtx); if (offset < XHCI_CAPLEN) /* read only registers */ - WPRINTF(("pci_xhci: write RO-CAPs offset %ld\r\n", offset)); + WPRINTF(("pci_xhci: write RO-CAPs offset %ld\r\n", offset)); else if (offset < sc->dboff) pci_xhci_hostop_write(sc, offset, value); else if (offset < sc->rtsoff) @@ -2225,9 +2225,9 @@ else if (offset < sc->regsend) pci_xhci_rtsregs_write(sc, offset, value); else - WPRINTF(("pci_xhci: write invalid offset %ld\r\n", offset)); + WPRINTF(("pci_xhci: write invalid offset %ld\r\n", offset)); - pthread_mutex_unlock(&sc->mtx); + pthread_mutex_unlock(&sc->mtx); } static uint64_t @@ -2435,9 +2435,9 @@ sc = pi->pi_arg; - assert(baridx == 0); + assert(baridx == 0); - pthread_mutex_lock(&sc->mtx); + pthread_mutex_lock(&sc->mtx); if (offset < XHCI_CAPLEN) value = pci_xhci_hostcap_read(sc, offset); else if (offset < sc->dboff) @@ -2450,10 +2450,10 @@ value = pci_xhci_xecp_read(sc, offset); else { value = 0; - WPRINTF(("pci_xhci: read invalid offset %ld\r\n", offset)); + WPRINTF(("pci_xhci: read invalid offset %ld\r\n", offset)); } - pthread_mutex_unlock(&sc->mtx); + pthread_mutex_unlock(&sc->mtx); switch (size) { case 1: Index: usr.sbin/bhyve/rfb.c =================================================================== --- usr.sbin/bhyve/rfb.c +++ usr.sbin/bhyve/rfb.c @@ -74,11 +74,11 @@ #define AUTH_LENGTH 16 #define PASSWD_LENGTH 8 -#define SECURITY_TYPE_NONE 1 -#define SECURITY_TYPE_VNC_AUTH 2 +#define SECURITY_TYPE_NONE 1 +#define SECURITY_TYPE_VNC_AUTH 2 -#define AUTH_FAILED_UNAUTH 1 -#define AUTH_FAILED_ERROR 2 +#define AUTH_FAILED_UNAUTH 1 +#define AUTH_FAILED_ERROR 2 struct rfb_softc { int sfd; @@ -140,12 +140,12 @@ #define RFB_ENCODING_ZLIB 6 #define RFB_ENCODING_RESIZE -223 -#define RFB_MAX_WIDTH 2000 -#define RFB_MAX_HEIGHT 1200 +#define RFB_MAX_WIDTH 2000 +#define RFB_MAX_HEIGHT 1200 #define RFB_ZLIB_BUFSZ RFB_MAX_WIDTH*RFB_MAX_HEIGHT*4 /* percentage changes to screen before sending the entire screen */ -#define RFB_SEND_ALL_THRESH 25 +#define RFB_SEND_ALL_THRESH 25 struct rfb_enc_msg { uint8_t type; @@ -306,7 +306,7 @@ int x, int y, int w, int h) { struct rfb_srvr_updt_msg supdt_msg; - struct rfb_srvr_rect_hdr srect_hdr; + struct rfb_srvr_rect_hdr srect_hdr; unsigned long zlen; ssize_t nwrite, total; int err; @@ -466,9 +466,9 @@ return (nwrite); } -#define PIX_PER_CELL 32 +#define PIX_PER_CELL 32 #define PIXCELL_SHIFT 5 -#define PIXCELL_MASK 0x1F +#define PIXCELL_MASK 0x1F static int rfb_send_screen(struct rfb_softc *rc, int cfd, int all) @@ -714,7 +714,7 @@ tv.tv_usec = 10000; err = select(cfd+1, &rfds, NULL, NULL, &tv); - if (err < 0) + if (err < 0) return (NULL); /* Determine if its time to push screen; ~24hz */ Index: usr.sbin/bhyve/rtc.c =================================================================== --- usr.sbin/bhyve/rtc.c +++ usr.sbin/bhyve/rtc.c @@ -51,7 +51,7 @@ #define RTC_HMEM_SB 0x5c #define RTC_HMEM_MSB 0x5d -#define m_64KB (64*1024) +#define m_64KB (64*1024) #define m_16MB (16*1024*1024) #define m_4GB (4ULL*1024*1024*1024) Index: usr.sbin/bhyve/sockstream.c =================================================================== --- usr.sbin/bhyve/sockstream.c +++ usr.sbin/bhyve/sockstream.c @@ -84,5 +84,3 @@ } return (len); } - - Index: usr.sbin/bhyve/uart_emul.c =================================================================== --- usr.sbin/bhyve/uart_emul.c +++ usr.sbin/bhyve/uart_emul.c @@ -56,9 +56,9 @@ #include "uart_emul.h" #define COM1_BASE 0x3F8 -#define COM1_IRQ 4 +#define COM1_IRQ 4 #define COM2_BASE 0x2F8 -#define COM2_IRQ 3 +#define COM2_IRQ 3 #define DEFAULT_RCLK 1843200 #define DEFAULT_BAUD 9600 @@ -71,7 +71,7 @@ #define MSR_DELTA_MASK 0x0f #ifndef REG_SCR -#define REG_SCR com_scr +#define REG_SCR com_scr #endif #define FIFOSZ 16 Index: usr.sbin/bhyve/usb_mouse.c =================================================================== --- usr.sbin/bhyve/usb_mouse.c +++ usr.sbin/bhyve/usb_mouse.c @@ -222,16 +222,16 @@ HSETW(.wTotalLength, sizeof(umouse_bosd)), .bNumDeviceCaps = 1, }, - .usbssd = { - .bLength = sizeof(umouse_bosd.usbssd), - .bDescriptorType = UDESC_DEVICE_CAPABILITY, - .bDevCapabilityType = 3, - .bmAttributes = 0, - HSETW(.wSpeedsSupported, 0x08), - .bFunctionalitySupport = 3, - .bU1DevExitLat = 0xa, /* dummy - not used */ - .wU2DevExitLat = { 0x20, 0x00 }, - } + .usbssd = { + .bLength = sizeof(umouse_bosd.usbssd), + .bDescriptorType = UDESC_DEVICE_CAPABILITY, + .bDevCapabilityType = 3, + .bmAttributes = 0, + HSETW(.wSpeedsSupported, 0x08), + .bFunctionalitySupport = 3, + .bU1DevExitLat = 0xa, /* dummy - not used */ + .wU2DevExitLat = { 0x20, 0x00 }, + } }; Index: usr.sbin/bhyve/vga.h =================================================================== --- usr.sbin/bhyve/vga.h +++ usr.sbin/bhyve/vga.h @@ -40,8 +40,8 @@ #define GEN_MISC_OUTPUT_PORT 0x3cc #define GEN_INPUT_STS1_MONO_PORT 0x3ba #define GEN_INPUT_STS1_COLOR_PORT 0x3da -#define GEN_IS1_VR 0x08 /* Vertical retrace */ -#define GEN_IS1_DE 0x01 /* Display enable not */ +#define GEN_IS1_VR 0x08 /* Vertical retrace */ +#define GEN_IS1_DE 0x01 /* Display enable not */ /* Attribute controller registers. */ #define ATC_IDX_PORT 0x3c0 @@ -51,14 +51,14 @@ #define ATC_PALETTE0 0 #define ATC_PALETTE15 15 #define ATC_MODE_CONTROL 16 -#define ATC_MC_IPS 0x80 /* Internal palette size */ -#define ATC_MC_GA 0x01 /* Graphics/alphanumeric */ +#define ATC_MC_IPS 0x80 /* Internal palette size */ +#define ATC_MC_GA 0x01 /* Graphics/alphanumeric */ #define ATC_OVERSCAN_COLOR 17 #define ATC_COLOR_PLANE_ENABLE 18 #define ATC_HORIZ_PIXEL_PANNING 19 #define ATC_COLOR_SELECT 20 -#define ATC_CS_C67 0x0c /* Color select bits 6+7 */ -#define ATC_CS_C45 0x03 /* Color select bits 4+5 */ +#define ATC_CS_C67 0x0c /* Color select bits 6+7 */ +#define ATC_CS_C45 0x03 /* Color select bits 4+5 */ /* Sequencer registers. */ #define SEQ_IDX_PORT 0x3c4 @@ -68,22 +68,22 @@ #define SEQ_RESET_ASYNC 0x1 #define SEQ_RESET_SYNC 0x2 #define SEQ_CLOCKING_MODE 1 -#define SEQ_CM_SO 0x20 /* Screen off */ -#define SEQ_CM_89 0x01 /* 8/9 dot clock */ +#define SEQ_CM_SO 0x20 /* Screen off */ +#define SEQ_CM_89 0x01 /* 8/9 dot clock */ #define SEQ_MAP_MASK 2 #define SEQ_CHAR_MAP_SELECT 3 -#define SEQ_CMS_SAH 0x20 /* Char map A bit 2 */ -#define SEQ_CMS_SAH_SHIFT 5 -#define SEQ_CMS_SA 0x0c /* Char map A bits 0+1 */ -#define SEQ_CMS_SA_SHIFT 2 -#define SEQ_CMS_SBH 0x10 /* Char map B bit 2 */ -#define SEQ_CMS_SBH_SHIFT 4 -#define SEQ_CMS_SB 0x03 /* Char map B bits 0+1 */ -#define SEQ_CMS_SB_SHIFT 0 +#define SEQ_CMS_SAH 0x20 /* Char map A bit 2 */ +#define SEQ_CMS_SAH_SHIFT 5 +#define SEQ_CMS_SA 0x0c /* Char map A bits 0+1 */ +#define SEQ_CMS_SA_SHIFT 2 +#define SEQ_CMS_SBH 0x10 /* Char map B bit 2 */ +#define SEQ_CMS_SBH_SHIFT 4 +#define SEQ_CMS_SB 0x03 /* Char map B bits 0+1 */ +#define SEQ_CMS_SB_SHIFT 0 #define SEQ_MEMORY_MODE 4 -#define SEQ_MM_C4 0x08 /* Chain 4 */ -#define SEQ_MM_OE 0x04 /* Odd/even */ -#define SEQ_MM_EM 0x02 /* Extended memory */ +#define SEQ_MM_C4 0x08 /* Chain 4 */ +#define SEQ_MM_OE 0x04 /* Odd/even */ +#define SEQ_MM_EM 0x02 /* Extended memory */ /* Graphics controller registers. */ #define GC_IDX_PORT 0x3ce @@ -95,13 +95,13 @@ #define GC_DATA_ROTATE 3 #define GC_READ_MAP_SELECT 4 #define GC_MODE 5 -#define GC_MODE_OE 0x10 /* Odd/even */ -#define GC_MODE_C4 0x04 /* Chain 4 */ +#define GC_MODE_OE 0x10 /* Odd/even */ +#define GC_MODE_C4 0x04 /* Chain 4 */ #define GC_MISCELLANEOUS 6 -#define GC_MISC_GM 0x01 /* Graphics/alphanumeric */ -#define GC_MISC_MM 0x0c /* memory map */ -#define GC_MISC_MM_SHIFT 2 +#define GC_MISC_GM 0x01 /* Graphics/alphanumeric */ +#define GC_MISC_MM 0x0c /* memory map */ +#define GC_MISC_MM_SHIFT 2 #define GC_COLOR_DONT_CARE 7 #define GC_BIT_MASK 8 @@ -119,36 +119,36 @@ #define CRTC_END_HORIZ_RETRACE 5 #define CRTC_VERT_TOTAL 6 #define CRTC_OVERFLOW 7 -#define CRTC_OF_VRS9 0x80 /* VRS bit 9 */ -#define CRTC_OF_VRS9_SHIFT 7 -#define CRTC_OF_VDE9 0x40 /* VDE bit 9 */ -#define CRTC_OF_VDE9_SHIFT 6 -#define CRTC_OF_VRS8 0x04 /* VRS bit 8 */ -#define CRTC_OF_VRS8_SHIFT 2 -#define CRTC_OF_VDE8 0x02 /* VDE bit 8 */ -#define CRTC_OF_VDE8_SHIFT 1 +#define CRTC_OF_VRS9 0x80 /* VRS bit 9 */ +#define CRTC_OF_VRS9_SHIFT 7 +#define CRTC_OF_VDE9 0x40 /* VDE bit 9 */ +#define CRTC_OF_VDE9_SHIFT 6 +#define CRTC_OF_VRS8 0x04 /* VRS bit 8 */ +#define CRTC_OF_VRS8_SHIFT 2 +#define CRTC_OF_VDE8 0x02 /* VDE bit 8 */ +#define CRTC_OF_VDE8_SHIFT 1 #define CRTC_PRESET_ROW_SCAN 8 #define CRTC_MAX_SCAN_LINE 9 -#define CRTC_MSL_MSL 0x1f +#define CRTC_MSL_MSL 0x1f #define CRTC_CURSOR_START 10 -#define CRTC_CS_CO 0x20 /* Cursor off */ -#define CRTC_CS_CS 0x1f /* Cursor start */ +#define CRTC_CS_CO 0x20 /* Cursor off */ +#define CRTC_CS_CS 0x1f /* Cursor start */ #define CRTC_CURSOR_END 11 -#define CRTC_CE_CE 0x1f /* Cursor end */ +#define CRTC_CE_CE 0x1f /* Cursor end */ #define CRTC_START_ADDR_HIGH 12 #define CRTC_START_ADDR_LOW 13 #define CRTC_CURSOR_LOC_HIGH 14 #define CRTC_CURSOR_LOC_LOW 15 #define CRTC_VERT_RETRACE_START 16 #define CRTC_VERT_RETRACE_END 17 -#define CRTC_VRE_MASK 0xf +#define CRTC_VRE_MASK 0xf #define CRTC_VERT_DISP_END 18 #define CRTC_OFFSET 19 #define CRTC_UNDERLINE_LOC 20 #define CRTC_START_VERT_BLANK 21 #define CRTC_END_VERT_BLANK 22 #define CRTC_MODE_CONTROL 23 -#define CRTC_MC_TE 0x80 /* Timing enable */ +#define CRTC_MC_TE 0x80 /* Timing enable */ #define CRTC_LINE_COMPARE 24 /* DAC registers */ Index: usr.sbin/bhyve/virtio.h =================================================================== --- usr.sbin/bhyve/virtio.h +++ usr.sbin/bhyve/virtio.h @@ -186,7 +186,7 @@ /* * PFN register shift amount */ -#define VRING_PFN 12 +#define VRING_PFN 12 /* * Virtio device types @@ -224,19 +224,19 @@ * If MSI-X is not enabled, those two registers disappear and * the remaining configuration registers start at offset 20. */ -#define VTCFG_R_HOSTCAP 0 -#define VTCFG_R_GUESTCAP 4 -#define VTCFG_R_PFN 8 -#define VTCFG_R_QNUM 12 -#define VTCFG_R_QSEL 14 -#define VTCFG_R_QNOTIFY 16 -#define VTCFG_R_STATUS 18 -#define VTCFG_R_ISR 19 -#define VTCFG_R_CFGVEC 20 -#define VTCFG_R_QVEC 22 -#define VTCFG_R_CFG0 20 /* No MSI-X */ -#define VTCFG_R_CFG1 24 /* With MSI-X */ -#define VTCFG_R_MSIX 20 +#define VTCFG_R_HOSTCAP 0 +#define VTCFG_R_GUESTCAP 4 +#define VTCFG_R_PFN 8 +#define VTCFG_R_QNUM 12 +#define VTCFG_R_QSEL 14 +#define VTCFG_R_QNOTIFY 16 +#define VTCFG_R_STATUS 18 +#define VTCFG_R_ISR 19 +#define VTCFG_R_CFGVEC 20 +#define VTCFG_R_QVEC 22 +#define VTCFG_R_CFG0 20 /* No MSI-X */ +#define VTCFG_R_CFG1 24 /* With MSI-X */ +#define VTCFG_R_MSIX 20 /* * Bits in VTCFG_R_STATUS. Guests need not actually set any of these, @@ -255,7 +255,7 @@ #define VTCFG_ISR_QUEUES 0x01 /* re-scan queues */ #define VTCFG_ISR_CONF_CHANGED 0x80 /* configuration changed */ -#define VIRTIO_MSI_NO_VECTOR 0xFFFF +#define VIRTIO_MSI_NO_VECTOR 0xFFFF /* * Feature flags. Index: usr.sbin/bhyve/virtio.c =================================================================== --- usr.sbin/bhyve/virtio.c +++ usr.sbin/bhyve/virtio.c @@ -51,7 +51,7 @@ * front of virtio-based device softc" constraint, let's use * this to convert. */ -#define DEV_SOFTC(vs) ((void *)(vs)) +#define DEV_SOFTC(vs) ((void *)(vs)) /* * Link a virtio_softc to its constants, the device softc, and