Index: devel/yosys/Makefile
===================================================================
--- /dev/null
+++ devel/yosys/Makefile
@@ -0,0 +1,45 @@
+# Created by: Johnny Sorocil <propaliidealist@gmail.com>
+# $FreeBSD$
+
+PORTNAME=	yosys
+DISTVERSION=	0.7-783
+DISTVERSIONSUFFIX=	-gbab39eac
+CATEGORIES=	devel
+
+MAINTAINER=	propaliidealist@gmail.com
+COMMENT=	Yosys Open SYnthesis Suite
+
+LICENSE=		ISCL
+LICENSE_FILE=	${WRKSRC}/COPYING
+
+BUILD_DEPENDS=	gawk:lang/gawk \
+				pkgconf:devel/pkgconf \
+				tclsh:lang/tcl-wrapper \
+				bash:shells/bash \
+				abc:devel/abc
+
+USES=			gmake shebangfix readline tcl bison python:3.6+,build
+SHEBANG_FILES=	${WRKSRC}/misc/yosys-config.in
+
+USE_GITHUB=	yes
+GH_ACCOUNT=	YosysHQ
+GH_TAGNAME=	bab39eacce5c17c42d50a3a60a67cc8a9ee52d98
+
+LIB_DEPENDS+=	libffi.so:devel/libffi
+
+post-patch:
+	@${REINPLACE_CMD} -e 's/python3 /python${PYTHON3_DEFAULT} /g' \
+		${WRKSRC}/techlibs/ice40/Makefile.inc \
+		${WRKSRC}/techlibs/xilinx/Makefile.inc \
+		${WRKSRC}/techlibs/common/Makefile.inc \
+		${WRKSRC}/tests/fsm/run-test.sh \
+		${WRKSRC}/tests/realmath/run-test.sh \
+		${WRKSRC}/tests/share/run-test.sh \
+		${WRKSRC}/tests/bram/run-test.sh
+	@${SED} -i '' 's/ABCEXTERNAL ?=/ABCEXTERNAL ?= abc/g' ${WRKSRC}/Makefile
+
+post-install:
+	${STRIP_CMD} ${STAGEDIR}${PREFIX}/bin/yosys
+	${SED} -i '' 's/python3/python${PYTHON3_DEFAULT}/g' ${STAGEDIR}${LOCALBASE}/bin/yosys-smtbmc
+
+.include <bsd.port.mk>
Index: devel/yosys/distinfo
===================================================================
--- /dev/null
+++ devel/yosys/distinfo
@@ -0,0 +1,3 @@
+TIMESTAMP = 1527191683
+SHA256 (YosysHQ-yosys-0.7-783-gbab39eac-bab39eacce5c17c42d50a3a60a67cc8a9ee52d98_GH0.tar.gz) = 1c97050a19f653fc957550cb5a505e1ebcb5722eade487bd86e8a5f9681ae09c
+SIZE (YosysHQ-yosys-0.7-783-gbab39eac-bab39eacce5c17c42d50a3a60a67cc8a9ee52d98_GH0.tar.gz) = 1089933
Index: devel/yosys/pkg-descr
===================================================================
--- /dev/null
+++ devel/yosys/pkg-descr
@@ -0,0 +1,5 @@
+Yosys is a framework for Verilog RTL synthesis. It currently has extensive
+Verilog-2005 support and provides a basic set of synthesis algorithms for
+various application domains.
+
+WWW: http://www.clifford.at/yosys/
Index: devel/yosys/pkg-plist
===================================================================
--- /dev/null
+++ devel/yosys/pkg-plist
@@ -0,0 +1,86 @@
+%%DATADIR%%/achronix/speedster22i/cells_map.v
+%%DATADIR%%/achronix/speedster22i/cells_sim.v
+%%DATADIR%%/adff2dff.v
+%%DATADIR%%/cells.lib
+%%DATADIR%%/coolrunner2/cells_latch.v
+%%DATADIR%%/coolrunner2/cells_sim.v
+%%DATADIR%%/coolrunner2/tff_extract.v
+%%DATADIR%%/coolrunner2/xc2_dff.lib
+%%DATADIR%%/dff2ff.v
+%%DATADIR%%/gowin/cells_map.v
+%%DATADIR%%/gowin/cells_sim.v
+%%DATADIR%%/greenpak4/cells_blackbox.v
+%%DATADIR%%/greenpak4/cells_latch.v
+%%DATADIR%%/greenpak4/cells_map.v
+%%DATADIR%%/greenpak4/cells_sim_ams.v
+%%DATADIR%%/greenpak4/cells_sim_digital.v
+%%DATADIR%%/greenpak4/cells_sim_wip.v
+%%DATADIR%%/greenpak4/cells_sim.v
+%%DATADIR%%/greenpak4/gp_dff.lib
+%%DATADIR%%/ice40/arith_map.v
+%%DATADIR%%/ice40/brams_init1.vh
+%%DATADIR%%/ice40/brams_init2.vh
+%%DATADIR%%/ice40/brams_init3.vh
+%%DATADIR%%/ice40/brams_map.v
+%%DATADIR%%/ice40/brams.txt
+%%DATADIR%%/ice40/cells_map.v
+%%DATADIR%%/ice40/cells_sim.v
+%%DATADIR%%/ice40/latches_map.v
+%%DATADIR%%/include/backends/ilang/ilang_backend.h
+%%DATADIR%%/include/frontends/ast/ast.h
+%%DATADIR%%/include/kernel/celledges.h
+%%DATADIR%%/include/kernel/celltypes.h
+%%DATADIR%%/include/kernel/consteval.h
+%%DATADIR%%/include/kernel/hashlib.h
+%%DATADIR%%/include/kernel/log.h
+%%DATADIR%%/include/kernel/macc.h
+%%DATADIR%%/include/kernel/modtools.h
+%%DATADIR%%/include/kernel/register.h
+%%DATADIR%%/include/kernel/rtlil.h
+%%DATADIR%%/include/kernel/satgen.h
+%%DATADIR%%/include/kernel/sigtools.h
+%%DATADIR%%/include/kernel/utils.h
+%%DATADIR%%/include/kernel/yosys.h
+%%DATADIR%%/include/libs/ezsat/ezminisat.h
+%%DATADIR%%/include/libs/ezsat/ezsat.h
+%%DATADIR%%/include/libs/sha1/sha1.h
+%%DATADIR%%/include/passes/fsm/fsmdata.h
+%%DATADIR%%/intel/a10gx/cells_map.v
+%%DATADIR%%/intel/a10gx/cells_sim.v
+%%DATADIR%%/intel/common/altpll_bb.v
+%%DATADIR%%/intel/common/brams_map.v
+%%DATADIR%%/intel/common/brams.txt
+%%DATADIR%%/intel/common/m9k_bb.v
+%%DATADIR%%/intel/cyclone10/cells_map.v
+%%DATADIR%%/intel/cyclone10/cells_sim.v
+%%DATADIR%%/intel/cycloneiv/cells_map.v
+%%DATADIR%%/intel/cycloneiv/cells_sim.v
+%%DATADIR%%/intel/cycloneive/cells_map.v
+%%DATADIR%%/intel/cycloneive/cells_sim.v
+%%DATADIR%%/intel/cyclonev/cells_map.v
+%%DATADIR%%/intel/cyclonev/cells_sim.v
+%%DATADIR%%/intel/max10/cells_map.v
+%%DATADIR%%/intel/max10/cells_sim.v
+%%DATADIR%%/pmux2mux.v
+%%DATADIR%%/python3/smtio.py
+%%DATADIR%%/simcells.v
+%%DATADIR%%/simlib.v
+%%DATADIR%%/techmap.v
+%%DATADIR%%/xilinx/arith_map.v
+%%DATADIR%%/xilinx/brams_bb.v
+%%DATADIR%%/xilinx/brams_init_%%PYTHON_SUFFIX%%.vh
+%%DATADIR%%/xilinx/brams_init_16.vh
+%%DATADIR%%/xilinx/brams_init_18.vh
+%%DATADIR%%/xilinx/brams_init_32.vh
+%%DATADIR%%/xilinx/brams_map.v
+%%DATADIR%%/xilinx/brams.txt
+%%DATADIR%%/xilinx/cells_map.v
+%%DATADIR%%/xilinx/cells_sim.v
+%%DATADIR%%/xilinx/cells_xtra.v
+%%DATADIR%%/xilinx/drams_map.v
+%%DATADIR%%/xilinx/drams.txt
+%%DATADIR%%/xilinx/lut2lut.v
+bin/yosys
+bin/yosys-config
+bin/yosys-filterlib
+bin/yosys-smtbmc