Index: sys/x86/x86/mca.c
===================================================================
--- sys/x86/x86/mca.c
+++ sys/x86/x86/mca.c
@@ -1095,6 +1095,15 @@
 	if (!mca_enabled || !(cpu_feature & CPUID_MCE))
 		return;
 
+	/*
+	 * The cmci_monitor() must not be executed simultaneously by
+	 * several CPUs.  Provide mutual exclusion for boot on APs,
+	 * relying on the early initialization for BSP to be
+	 * single-threaded.
+	 */
+	if (!IS_BSP() && boot)
+		mtx_lock_spin(&mca_lock);
+
 	if (cpu_feature & CPUID_MCA) {
 		if (boot)
 			PCPU_SET(cmci_mask, 0);
@@ -1165,6 +1174,8 @@
 			lapic_enable_cmc();
 #endif
 	}
+	if (!IS_BSP() && boot)
+		mtx_unlock_spin(&mca_lock);
 
 	load_cr4(rcr4() | CR4_MCE);
 }
Index: sys/x86/x86/mp_x86.c
===================================================================
--- sys/x86/x86/mp_x86.c
+++ sys/x86/x86/mp_x86.c
@@ -1007,10 +1007,10 @@
 	KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
 	PCPU_SET(curthread, PCPU_GET(idlethread));
 
-	mca_init();
-
 	mtx_lock_spin(&ap_boot_mtx);
 
+	mca_init();
+
 	/* Init local apic for irq's */
 	lapic_setup(1);