Index: lib/libc/sparc64/fpu/fpu_div.c =================================================================== --- lib/libc/sparc64/fpu/fpu_div.c +++ lib/libc/sparc64/fpu/fpu_div.c @@ -133,7 +133,7 @@ * } while ((bit >>= 1) != 0); * Q[0] = q; * for (i = 1; i < 4; i++) { - * q = 0, bit = 1 << 31; + * q = 0, bit = 1U << 31; * do { * D = R - Y; * if (D >= 0) { @@ -234,7 +234,7 @@ #define WORD(r, i) /* calculate r->fp_mant[i] */ \ q = 0; \ - bit = 1 << 31; \ + bit = 1U << 31; \ LOOP; \ (x)->fp_mant[i] = q Index: lib/libc/sparc64/fpu/fpu_sqrt.c =================================================================== --- lib/libc/sparc64/fpu/fpu_sqrt.c +++ lib/libc/sparc64/fpu/fpu_sqrt.c @@ -295,7 +295,7 @@ #define t1 tt q = 0; y1 = 0; - bit = 1 << 31; + bit = 1U << 31; EVEN_DOUBLE; t1 = bit; FPU_SUBS(d1, x1, t1); @@ -326,7 +326,7 @@ #define t2 tt q = 0; y2 = 0; - bit = 1 << 31; + bit = 1U << 31; EVEN_DOUBLE; t2 = bit; FPU_SUBS(d2, x2, t2); @@ -359,7 +359,7 @@ #define t3 tt q = 0; y3 = 0; - bit = 1 << 31; + bit = 1U << 31; EVEN_DOUBLE; t3 = bit; FPU_SUBS(d3, x3, t3); Index: release/picobsd/tinyware/ns/ns.c =================================================================== --- release/picobsd/tinyware/ns/ns.c +++ release/picobsd/tinyware/ns/ns.c @@ -98,7 +98,7 @@ case 255: { int i = 0; u_long mask; - u_int index = 1 << 31; + u_int index = 1U << 31; u_short new_mask = 0; mask = ntohl(((struct sockaddr_in *)sa)->sin_addr.s_addr); Index: sbin/ipfw/tables.c =================================================================== --- sbin/ipfw/tables.c +++ sbin/ipfw/tables.c @@ -1502,7 +1502,7 @@ n = arg; etype = NULL; - for (i = 1; i < (1 << 31); i *= 2) { + for (i = 1; i < (1U << 31); i *= 2) { if ((flag = (vmask & i)) == 0) continue; vmask &= ~flag; @@ -1756,7 +1756,7 @@ return; } - for (i = 1; i < (1 << 31); i *= 2) { + for (i = 1; i < (1U << 31); i *= 2) { if ((flag = (vmask & i)) == 0) continue; l = 0; Index: stand/i386/libfirewire/fwohci.c =================================================================== --- stand/i386/libfirewire/fwohci.c +++ stand/i386/libfirewire/fwohci.c @@ -365,7 +365,7 @@ /* Enable bus reset interrupt */ OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); /* Allow async. request to us */ - OWRITE(sc, OHCI_AREQHI, 1 << 31); + OWRITE(sc, OHCI_AREQHI, 1U << 31); /* XXX insecure ?? */ OWRITE(sc, OHCI_PREQHI, 0x7fffffff); OWRITE(sc, OHCI_PREQLO, 0xffffffff); Index: stand/i386/libfirewire/fwohcireg.h =================================================================== --- stand/i386/libfirewire/fwohcireg.h +++ stand/i386/libfirewire/fwohcireg.h @@ -185,9 +185,9 @@ struct ohci_dma{ fwohcireg_t cntl; -#define OHCI_CNTL_CYCMATCH_S (0x1 << 31) +#define OHCI_CNTL_CYCMATCH_S (0x1U << 31) -#define OHCI_CNTL_BUFFIL (0x1 << 31) +#define OHCI_CNTL_BUFFIL (0x1U << 31) #define OHCI_CNTL_ISOHDR (0x1 << 30) #define OHCI_CNTL_CYCMATCH_R (0x1 << 29) #define OHCI_CNTL_MULTICH (0x1 << 28) @@ -358,7 +358,7 @@ #define OHCI_INT_CYC_LONG (0x1 << 25) #define OHCI_INT_PHY_REG (0x1 << 26) -#define OHCI_INT_EN (0x1 << 31) +#define OHCI_INT_EN (0x1U << 31) #define IP_CHANNELS 0x0234 #define FWOHCI_MAXREC 2048 Index: sys/arm/allwinner/a10_fb.c =================================================================== --- sys/arm/allwinner/a10_fb.c +++ sys/arm/allwinner/a10_fb.c @@ -107,14 +107,14 @@ /* Timing controller */ #define TCON_GCTL 0x000 -#define GCTL_TCON_EN (1 << 31) +#define GCTL_TCON_EN (1U << 31) #define GCTL_IO_MAP_SEL_TCON1 (1 << 0) #define TCON_GINT1 0x008 #define GINT1_TCON1_LINENO(n) (((n) + 2) << 0) #define TCON0_DCLK 0x044 #define DCLK_EN 0xf0000000 #define TCON1_CTL 0x090 -#define TCON1_EN (1 << 31) +#define TCON1_EN (1U << 31) #define INTERLACE_EN (1 << 20) #define TCON1_SRC_SEL(src) ((src) << 0) #define TCON1_SRC_CH1 0 Index: sys/arm/allwinner/a10_hdmi.c =================================================================== --- sys/arm/allwinner/a10_hdmi.c +++ sys/arm/allwinner/a10_hdmi.c @@ -54,12 +54,12 @@ #include "hdmi_if.h" #define HDMI_CTRL 0x004 -#define CTRL_MODULE_EN (1 << 31) +#define CTRL_MODULE_EN (1U << 31) #define HDMI_INT_STATUS 0x008 #define HDMI_HPD 0x00c #define HPD_DET (1 << 0) #define HDMI_VID_CTRL 0x010 -#define VID_CTRL_VIDEO_EN (1 << 31) +#define VID_CTRL_VIDEO_EN (1U << 31) #define VID_CTRL_HDMI_MODE (1 << 30) #define VID_CTRL_INTERLACE (1 << 4) #define VID_CTRL_REPEATER_2X (1 << 0) @@ -80,12 +80,12 @@ #define VID_VSYNC_ACTSEL (1 << 1) #define VID_HSYNC_ACTSEL (1 << 0) #define HDMI_AUD_CTRL 0x040 -#define AUD_CTRL_EN (1 << 31) +#define AUD_CTRL_EN (1U << 31) #define AUD_CTRL_RST (1 << 30) #define HDMI_ADMA_CTRL 0x044 -#define HDMI_ADMA_MODE (1 << 31) +#define HDMI_ADMA_MODE (1U << 31) #define HDMI_ADMA_MODE_DDMA (0 << 31) -#define HDMI_ADMA_MODE_NDMA (1 << 31) +#define HDMI_ADMA_MODE_NDMA (1U << 31) #define HDMI_AUD_FMT 0x048 #define AUD_FMT_CH(n) ((n) - 1) #define HDMI_PCM_CTRL 0x04c @@ -103,7 +103,7 @@ #define HDMI_AUDIO_N 6144 /* 48 kHz */ #define HDMI_AUDIO_CTS(r, n) ((((r) * 10) * ((n) / 128)) / 480) #define HDMI_PADCTRL0 0x200 -#define PADCTRL0_BIASEN (1 << 31) +#define PADCTRL0_BIASEN (1U << 31) #define PADCTRL0_LDOCEN (1 << 30) #define PADCTRL0_LDODEN (1 << 29) #define PADCTRL0_PWENC (1 << 28) @@ -134,7 +134,7 @@ #define PADCTRL1_REG_AMP_EN (0x6 << 3) #define PADCTRL1_REG_PLR (0x7 << 0) #define HDMI_PLLCTRL0 0x208 -#define PLLCTRL0_PLL_EN (1 << 31) +#define PLLCTRL0_PLL_EN (1U << 31) #define PLLCTRL0_BWS (1 << 30) #define PLLCTRL0_HV_IS_33 (1 << 29) #define PLLCTRL0_LDO1_EN (1 << 28) @@ -160,7 +160,7 @@ #define PKT_SPD 5 #define PKT_END 15 #define DDC_CTRL 0x500 -#define CTRL_DDC_EN (1 << 31) +#define CTRL_DDC_EN (1U << 31) #define CTRL_DDC_ACMD_START (1 << 30) #define CTRL_DDC_FIFO_DIR (1 << 8) #define CTRL_DDC_FIFO_DIR_READ (0 << 8) @@ -174,7 +174,7 @@ #define DDC_INT_STATUS 0x50c #define INT_STATUS_XFER_DONE (1 << 0) #define DDC_FIFO_CTRL 0x510 -#define FIFO_CTRL_CLEAR (1 << 31) +#define FIFO_CTRL_CLEAR (1U << 31) #define DDC_BYTE_COUNTER 0x51c #define DDC_COMMAND 0x520 #define COMMAND_EOREAD (4 << 0) Index: sys/arm/allwinner/clk/aw_debeclk.c =================================================================== --- sys/arm/allwinner/clk/aw_debeclk.c +++ sys/arm/allwinner/clk/aw_debeclk.c @@ -51,7 +51,7 @@ #include "clkdev_if.h" #include "hwreset_if.h" -#define SCLK_GATING (1 << 31) +#define SCLK_GATING (1U << 31) #define BE_RST (1 << 30) #define CLK_SRC_SEL (0x3 << 24) #define CLK_SRC_SEL_SHIFT 24 Index: sys/arm/allwinner/clk/aw_hdmiclk.c =================================================================== --- sys/arm/allwinner/clk/aw_hdmiclk.c +++ sys/arm/allwinner/clk/aw_hdmiclk.c @@ -50,7 +50,7 @@ #include "clkdev_if.h" -#define SCLK_GATING (1 << 31) +#define SCLK_GATING (1U << 31) #define CLK_SRC_SEL (0x3 << 24) #define CLK_SRC_SEL_SHIFT 24 #define CLK_SRC_SEL_MAX 0x3 Index: sys/arm/allwinner/clk/aw_lcdclk.c =================================================================== --- sys/arm/allwinner/clk/aw_lcdclk.c +++ sys/arm/allwinner/clk/aw_lcdclk.c @@ -52,7 +52,7 @@ #include "hwreset_if.h" /* CH0 */ -#define CH0_SCLK_GATING (1 << 31) +#define CH0_SCLK_GATING (1U << 31) #define CH0_LCD_RST (1 << 30) #define CH0_CLK_SRC_SEL (0x3 << 24) #define CH0_CLK_SRC_SEL_SHIFT 24 @@ -62,7 +62,7 @@ #define CH0_CLK_SRC_SEL_PLL6 3 /* CH1 */ -#define CH1_SCLK2_GATING (1 << 31) +#define CH1_SCLK2_GATING (1U << 31) #define CH1_SCLK2_SEL (0x3 << 24) #define CH1_SCLK2_SEL_SHIFT 24 #define CH1_SCLK2_SEL_PLL3_1X 0 Index: sys/arm/allwinner/clk/aw_mmcclk.c =================================================================== --- sys/arm/allwinner/clk/aw_mmcclk.c +++ sys/arm/allwinner/clk/aw_mmcclk.c @@ -50,7 +50,7 @@ #include "clkdev_if.h" -#define SCLK_GATING (1 << 31) +#define SCLK_GATING (1U << 31) #define CLK_SRC_SEL (0x3 << 24) #define CLK_SRC_SEL_SHIFT 24 #define CLK_SRC_SEL_MAX 0x3 Index: sys/arm/allwinner/clk/aw_modclk.c =================================================================== --- sys/arm/allwinner/clk/aw_modclk.c +++ sys/arm/allwinner/clk/aw_modclk.c @@ -50,7 +50,7 @@ #include "clkdev_if.h" -#define SCLK_GATING (1 << 31) +#define SCLK_GATING (1U << 31) #define CLK_SRC_SEL (0x3 << 24) #define CLK_SRC_SEL_SHIFT 24 #define CLK_RATIO_N (0x3 << 16) Index: sys/arm/allwinner/clk/aw_pll.c =================================================================== --- sys/arm/allwinner/clk/aw_pll.c +++ sys/arm/allwinner/clk/aw_pll.c @@ -56,7 +56,7 @@ #define SUN4I_A10_PLL2_4X 2 #define SUN4I_A10_PLL2_8X 3 -#define AW_PLL_ENABLE (1 << 31) +#define AW_PLL_ENABLE (1U << 31) #define A10_PLL1_OUT_EXT_DIVP (0x3 << 16) #define A10_PLL1_OUT_EXT_DIVP_SHIFT 16 Index: sys/arm/allwinner/clk/aw_thsclk.c =================================================================== --- sys/arm/allwinner/clk/aw_thsclk.c +++ sys/arm/allwinner/clk/aw_thsclk.c @@ -50,7 +50,7 @@ #include "clkdev_if.h" -#define SCLK_GATING (1 << 31) +#define SCLK_GATING (1U << 31) #define CLK_SRC_SEL (0x3 << 24) #define CLK_SRC_SEL_SHIFT 24 #define CLK_SRC_SEL_MAX 1 Index: sys/arm/allwinner/if_awgreg.h =================================================================== --- sys/arm/allwinner/if_awgreg.h +++ sys/arm/allwinner/if_awgreg.h @@ -61,9 +61,9 @@ #define TX_DMA_STOPPED_INT_EN (1 << 1) #define TX_INT_EN (1 << 0) #define EMAC_TX_CTL_0 0x10 -#define TX_EN (1 << 31) +#define TX_EN (1U << 31) #define EMAC_TX_CTL_1 0x14 -#define TX_DMA_START (1 << 31) +#define TX_DMA_START (1U << 31) #define TX_DMA_EN (1 << 30) #define TX_NEXT_FRAME (1 << 2) #define TX_MD (1 << 1) @@ -74,18 +74,18 @@ #define TX_FLOW_CTL_EN (1 << 0) #define EMAC_TX_DMA_LIST 0x20 #define EMAC_RX_CTL_0 0x24 -#define RX_EN (1 << 31) +#define RX_EN (1U << 31) #define JUMBO_FRM_EN (1 << 29) #define STRIP_FCS (1 << 28) #define CHECK_CRC (1 << 27) #define RX_FLOW_CTL_EN (1 << 16) #define EMAC_RX_CTL_1 0x28 -#define RX_DMA_START (1 << 31) +#define RX_DMA_START (1U << 31) #define RX_DMA_EN (1 << 30) #define RX_MD (1 << 1) #define EMAC_RX_DMA_LIST 0x34 #define EMAC_RX_FRM_FLT 0x38 -#define DIS_ADDR_FILTER (1 << 31) +#define DIS_ADDR_FILTER (1U << 31) #define DIS_BROADCAST (1 << 17) #define RX_ALL_MULTICAST (1 << 16) #define CTL_FRM_FILTER (0x3 << 12) @@ -126,7 +126,7 @@ struct emac_desc { uint32_t status; /* Transmit */ -#define TX_DESC_CTL (1 << 31) +#define TX_DESC_CTL (1U << 31) #define TX_HEADER_ERR (1 << 16) #define TX_LENGTH_ERR (1 << 14) #define TX_PAYLOAD_ERR (1 << 12) @@ -139,7 +139,7 @@ #define TX_UNDERFLOW_ERR (1 << 1) #define TX_DEFER (1 << 0) /* Receive */ -#define RX_DESC_CTL (1 << 31) +#define RX_DESC_CTL (1U << 31) #define RX_DAF_FAIL (1 << 30) #define RX_FRM_LEN (0x3fff << 16) #define RX_FRM_LEN_SHIFT 16 @@ -158,7 +158,7 @@ uint32_t size; /* Transmit */ -#define TX_INT_CTL (1 << 31) +#define TX_INT_CTL (1U << 31) #define TX_LAST_DESC (1 << 30) #define TX_FIR_DESC (1 << 29) #define TX_CHECKSUM_CTL (0x3 << 27) @@ -170,7 +170,7 @@ #define TX_BUF_SIZE (0xfff << 0) #define TX_BUF_SIZE_SHIFT 0 /* Receive */ -#define RX_INT_CTL (1 << 31) +#define RX_INT_CTL (1U << 31) #define RX_BUF_SIZE (0xfff << 0) #define RX_BUF_SIZE_SHIFT 0 Index: sys/arm/arm/identcpu-v6.c =================================================================== --- sys/arm/arm/identcpu-v6.c +++ sys/arm/arm/identcpu-v6.c @@ -302,7 +302,7 @@ hw_buf_newline = true; val = (cpuinfo.mpidr >> 4)& 0xF; - if (cpuinfo.mpidr & (1 << 31U)) + if (cpuinfo.mpidr & (1U << 31U)) add_cap("Multiprocessing"); val = (cpuinfo.id_pfr0 >> 4)& 0xF; if (val == 1) Index: sys/arm/at91/at91_pioreg.h =================================================================== --- sys/arm/at91/at91_pioreg.h +++ sys/arm/at91/at91_pioreg.h @@ -101,7 +101,7 @@ #define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 #define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 #define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 -#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) // Pin Controlled by PA31 +#define AT91C_PIO_PA31 ((unsigned int) 1U << 31) // Pin Controlled by PA31 #define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 #define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 #define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 @@ -133,7 +133,7 @@ #define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 #define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 #define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 -#define AT91C_PIO_PB31 ((unsigned int) 1 << 31) // Pin Controlled by PB31 +#define AT91C_PIO_PB31 ((unsigned int) 1U << 31) // Pin Controlled by PB31 #define AT91C_PIO_PC0 ((unsigned int) 1 << 0) // Pin Controlled by PC0 #define AT91C_PIO_PC1 ((unsigned int) 1 << 1) // Pin Controlled by PC1 #define AT91C_PIO_PC2 ((unsigned int) 1 << 2) // Pin Controlled by PC2 @@ -165,7 +165,7 @@ #define AT91C_PIO_PC28 ((unsigned int) 1 << 28) // Pin Controlled by PC28 #define AT91C_PIO_PC29 ((unsigned int) 1 << 29) // Pin Controlled by PC29 #define AT91C_PIO_PC30 ((unsigned int) 1 << 30) // Pin Controlled by PC30 -#define AT91C_PIO_PC31 ((unsigned int) 1 << 31) // Pin Controlled by PC31 +#define AT91C_PIO_PC31 ((unsigned int) 1U << 31) // Pin Controlled by PC31 #define AT91C_PIO_PD0 ((unsigned int) 1 << 0) // Pin Controlled by PD0 #define AT91C_PIO_PD1 ((unsigned int) 1 << 1) // Pin Controlled by PD1 #define AT91C_PIO_PD2 ((unsigned int) 1 << 2) // Pin Controlled by PD2 @@ -197,7 +197,7 @@ #define AT91C_PIO_PD28 ((unsigned int) 1 << 28) // Pin Controlled by PD28 #define AT91C_PIO_PD29 ((unsigned int) 1 << 29) // Pin Controlled by PD29 #define AT91C_PIO_PD30 ((unsigned int) 1 << 30) // Pin Controlled by PD30 -#define AT91C_PIO_PD31 ((unsigned int) 1 << 31) // Pin Controlled by PD31 +#define AT91C_PIO_PD31 ((unsigned int) 1U << 31) // Pin Controlled by PD31 #define AT91C_PIO_PE0 ((unsigned int) 1 << 0) // Pin Controlled by PE0 #define AT91C_PIO_PE1 ((unsigned int) 1 << 1) // Pin Controlled by PE1 #define AT91C_PIO_PE2 ((unsigned int) 1 << 2) // Pin Controlled by PE2 @@ -229,6 +229,6 @@ #define AT91C_PIO_PE28 ((unsigned int) 1 << 28) // Pin Controlled by PE28 #define AT91C_PIO_PE29 ((unsigned int) 1 << 29) // Pin Controlled by PE29 #define AT91C_PIO_PE30 ((unsigned int) 1 << 30) // Pin Controlled by PE30 -#define AT91C_PIO_PE31 ((unsigned int) 1 << 31) // Pin Controlled by PE31 +#define AT91C_PIO_PE31 ((unsigned int) 1U << 31) // Pin Controlled by PE31 #endif /* ARM_AT91_AT91_PIOREG_H */ Index: sys/arm/freescale/imx/imx6_audmux.c =================================================================== --- sys/arm/freescale/imx/imx6_audmux.c +++ sys/arm/freescale/imx/imx6_audmux.c @@ -58,7 +58,7 @@ bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val) #define AUDMUX_PTCR(n) (0x8 * (n - 1)) /* Port Timing Control Register */ -#define PTCR_TFS_DIR (1 << 31) /* Transmit Frame Sync Direction Control */ +#define PTCR_TFS_DIR (1U << 31) /* Transmit Frame Sync Direction Control */ #define PTCR_TFSEL_S 27 /* Transmit Frame Sync Select */ #define PTCR_TFSEL_M 0xf #define PTCR_TCLKDIR (1 << 26) /* Transmit Clock Direction Control */ Index: sys/arm/freescale/imx/imx6_ipu.c =================================================================== --- sys/arm/freescale/imx/imx6_ipu.c +++ sys/arm/freescale/imx/imx6_ipu.c @@ -123,7 +123,7 @@ #define DISP_GEN_MCU_MAX_BURST_STOP (1 << 22) #define DISP_GEN_MCU_T_SHIFT 18 #define IPU_MEM_RST 0x2000DC -#define IPU_MEM_RST_START (1 << 31) +#define IPU_MEM_RST_START (1U << 31) #define IPU_MEM_RST_ALL 0x807FFFFF #define IPU_CH_DB_MODE_SEL_0 0x200150 #define IPU_CH_DB_MODE_SEL_1 0x200154 Index: sys/arm/freescale/vybrid/vf_dcu4.c =================================================================== --- sys/arm/freescale/vybrid/vf_dcu4.c +++ sys/arm/freescale/vybrid/vf_dcu4.c @@ -145,7 +145,7 @@ #define DCU_COMP_IMSIZE 0x0C8 /* Compression Image Size */ #define DCU_UPDATE_MODE 0x0CC /* Update Mode */ #define READREG (1 << 30) -#define MODE (1 << 31) +#define MODE (1U << 31) #define DCU_UNDERRUN 0x0D0 /* Underrun */ #define DCU_GLBL_PROTECT 0x100 /* Global Protection */ #define DCU_SFT_LCK_BIT_L0 0x104 /* Soft Lock Bit Layer 0 */ @@ -166,7 +166,7 @@ #define BPP_MASK 0xf /* Bit per pixel Mask */ #define BPP_SHIFT 16 /* Bit per pixel Shift */ #define BPP24 0x5 -#define EN_LAYER (1 << 31) /* Enable the layer */ +#define EN_LAYER (1U << 31) /* Enable the layer */ #define DCU_CTRLDESCLn_5(n) DCU_CTRLDESCL(n, 5) #define DCU_CTRLDESCLn_6(n) DCU_CTRLDESCL(n, 6) #define DCU_CTRLDESCLn_7(n) DCU_CTRLDESCL(n, 7) Index: sys/arm/freescale/vybrid/vf_sai.c =================================================================== --- sys/arm/freescale/vybrid/vf_sai.c +++ sys/arm/freescale/vybrid/vf_sai.c @@ -101,7 +101,7 @@ #define TCR5_W0W_S 16 /* Word 0 Width */ #define TCR5_WNW_M 0x1f /* Word N Width */ #define TCR5_WNW_S 24 /* Word N Width */ -#define TCSR_TE (1 << 31) /* Transmitter Enable */ +#define TCSR_TE (1U << 31) /* Transmitter Enable */ #define TCSR_BCE (1 << 28) /* Bit Clock Enable */ #define TCSR_FRDE (1 << 0) /* FIFO Request DMA Enable */ Index: sys/arm/freescale/vybrid/vf_spi.c =================================================================== --- sys/arm/freescale/vybrid/vf_spi.c +++ sys/arm/freescale/vybrid/vf_spi.c @@ -61,7 +61,7 @@ #define SPI_FIFO_SIZE 4 #define SPI_MCR 0x00 /* Module Configuration */ -#define MCR_MSTR (1 << 31) /* Master/Slave Mode Select */ +#define MCR_MSTR (1U << 31) /* Master/Slave Mode Select */ #define MCR_CONT_SCKE (1 << 30) /* Continuous SCK Enable */ #define MCR_FRZ (1 << 27) /* Freeze */ #define MCR_PCSIS_S 16 /* Peripheral Chip Select */ @@ -92,14 +92,14 @@ #define CTAR_BR_M 0xf #define CTAR_BR_S 0 /* Baud Rate Scaler */ #define SPI_SR 0x2C /* Status Register */ -#define SR_TCF (1 << 31) /* Transfer Complete Flag */ +#define SR_TCF (1U << 31) /* Transfer Complete Flag */ #define SR_EOQF (1 << 28) /* End of Queue Flag */ #define SR_TFFF (1 << 25) /* Transmit FIFO Fill Flag */ #define SR_RFDF (1 << 17) /* Receive FIFO Drain Flag */ #define SPI_RSER 0x30 /* DMA/Interrupt Select */ #define RSER_EOQF_RE (1 << 28) /* Finished Request Enable */ #define SPI_PUSHR 0x34 /* PUSH TX FIFO In Master Mode */ -#define PUSHR_CONT (1 << 31) /* Continuous Peripheral CS */ +#define PUSHR_CONT (1U << 31) /* Continuous Peripheral CS */ #define PUSHR_EOQ (1 << 27) /* End Of Queue */ #define PUSHR_CTCNT (1 << 26) /* Clear Transfer Counter */ #define PUSHR_PCS_M 0x3f Index: sys/arm/nvidia/tegra124/tegra124_machdep.c =================================================================== --- sys/arm/nvidia/tegra124/tegra124_machdep.c +++ sys/arm/nvidia/tegra124/tegra124_machdep.c @@ -53,7 +53,7 @@ #define PMC_SIZE 0x400 #define PMC_CONTROL_REG 0x0 #define PMC_SCRATCH0 0x50 -#define PMC_SCRATCH0_MODE_RECOVERY (1 << 31) +#define PMC_SCRATCH0_MODE_RECOVERY (1U << 31) #define PMC_SCRATCH0_MODE_BOOTLOADER (1 << 30) #define PMC_SCRATCH0_MODE_RCM (1 << 1) #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ Index: sys/arm/nvidia/tegra124/tegra124_pmc.c =================================================================== --- sys/arm/nvidia/tegra124/tegra124_pmc.c +++ sys/arm/nvidia/tegra124/tegra124_pmc.c @@ -83,7 +83,7 @@ #define PMC_PWRGATE_STATUS_PARTID(x) (1 << ((x) & 0x1F)) #define PMC_SCRATCH0 0x050 -#define PMC_SCRATCH0_MODE_RECOVERY (1 << 31) +#define PMC_SCRATCH0_MODE_RECOVERY (1U << 31) #define PMC_SCRATCH0_MODE_BOOTLOADER (1 << 30) #define PMC_SCRATCH0_MODE_RCM (1 << 1) #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ @@ -118,7 +118,7 @@ #define PMC_SCRATCH54_ADDR_SHIFT 0 #define PMC_SCRATCH55 0x25c -#define PMC_SCRATCH55_RST_ENABLE (1 << 31) +#define PMC_SCRATCH55_RST_ENABLE (1U << 31) #define PMC_SCRATCH55_CNTRL_TYPE (1 << 30) #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27 #define PMC_SCRATCH55_CNTRL_ID_MASK 0x07 Index: sys/arm/nvidia/tegra_ahci.c =================================================================== --- sys/arm/nvidia/tegra_ahci.c +++ sys/arm/nvidia/tegra_ahci.c @@ -159,7 +159,7 @@ #define T_AHCI_HBA_CCC_PORTS 0x0018 #define T_AHCI_HBA_CAP_BKDR 0x00A0 -#define T_AHCI_HBA_CAP_BKDR_S64A (1 << 31) +#define T_AHCI_HBA_CAP_BKDR_S64A (1U << 31) #define T_AHCI_HBA_CAP_BKDR_SNCQ (1 << 30) #define T_AHCI_HBA_CAP_BKDR_SSNTF (1 << 29) #define T_AHCI_HBA_CAP_BKDR_SMPS (1 << 28) Index: sys/arm/samsung/exynos/exynos5_usb_phy.c =================================================================== --- sys/arm/samsung/exynos/exynos5_usb_phy.c +++ sys/arm/samsung/exynos/exynos5_usb_phy.c @@ -68,7 +68,7 @@ #define USB_DRD_PHYCLKRST 0x10 #define PHYCLKRST_PORTRESET (1 << 1) #define PHYCLKRST_COMMONONN (1 << 0) -#define PHYCLKRST_EN_UTMISUSPEND (1 << 31) +#define PHYCLKRST_EN_UTMISUSPEND (1U << 31) #define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23) #define PHYCLKRST_SSC_REFCLKSEL(x) ((x) << 23) #define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21) @@ -99,7 +99,7 @@ #define USB_DRD_PHYREG0 0x14 #define USB_DRD_PHYREG1 0x18 #define USB_DRD_PHYPARAM0 0x1c -#define PHYPARAM0_REF_USE_PAD (1 << 31) +#define PHYPARAM0_REF_USE_PAD (1U << 31) #define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26) #define PHYPARAM0_REF_LOSLEVEL (0x9 << 26) #define USB_DRD_PHYPARAM1 0x20 Index: sys/arm/samsung/exynos/exynos5_xhci.c =================================================================== --- sys/arm/samsung/exynos/exynos5_xhci.c +++ sys/arm/samsung/exynos/exynos5_xhci.c @@ -82,10 +82,10 @@ #define GHWPARAMS1_EN_PWROPT_NO 0 #define GHWPARAMS1_EN_PWROPT_CLK 1 #define GUSB2PHYCFG(n) (0x100 + (n * 0x04)) -#define GUSB2PHYCFG_PHYSOFTRST (1 << 31) +#define GUSB2PHYCFG_PHYSOFTRST (1U << 31) #define GUSB2PHYCFG_SUSPHY (1 << 6) #define GUSB3PIPECTL(n) (0x1c0 + (n * 0x04)) -#define GUSB3PIPECTL_PHYSOFTRST (1 << 31) +#define GUSB3PIPECTL_PHYSOFTRST (1U << 31) #define GUSB3PIPECTL_SUSPHY (1 << 17) /* Forward declarations */ Index: sys/arm/ti/cpsw/if_cpsw.c =================================================================== --- sys/arm/ti/cpsw/if_cpsw.c +++ sys/arm/ti/cpsw/if_cpsw.c @@ -2303,7 +2303,7 @@ cpsw_write_4(sc, CPSW_ALE_TBLW0, ale_entry[0]); cpsw_write_4(sc, CPSW_ALE_TBLW1, ale_entry[1]); cpsw_write_4(sc, CPSW_ALE_TBLW2, ale_entry[2]); - cpsw_write_4(sc, CPSW_ALE_TBLCTL, 1 << 31 | (idx & 1023)); + cpsw_write_4(sc, CPSW_ALE_TBLCTL, 1U << 31 | (idx & 1023)); } static void Index: sys/arm64/arm64/gic_v3_reg.h =================================================================== --- sys/arm64/arm64/gic_v3_reg.h +++ sys/arm64/arm64/gic_v3_reg.h @@ -63,7 +63,7 @@ #define GICD_CTLR_G1 (1 << 0) #define GICD_CTLR_G1A (1 << 1) #define GICD_CTLR_ARE_NS (1 << 4) -#define GICD_CTLR_RWP (1 << 31) +#define GICD_CTLR_RWP (1U << 31) /* GICD_TYPER */ #define GICD_TYPER_IDBITS(n) ((((n) >> 19) & 0x1F) + 1) Index: sys/dev/acpi_support/acpi_ibm.c =================================================================== --- sys/dev/acpi_support/acpi_ibm.c +++ sys/dev/acpi_support/acpi_ibm.c @@ -273,7 +273,7 @@ #define ACPI_IBM_HKEY_MICMUTE_MASK (1 << 26) #define ACPI_IBM_HKEY_SETTINGS_MASK (1 << 28) #define ACPI_IBM_HKEY_VIEWOPEN_MASK (1 << 30) -#define ACPI_IBM_HKEY_VIEWALL_MASK (1 << 31) +#define ACPI_IBM_HKEY_VIEWALL_MASK (1U << 31) struct acpi_ibm_models { const char *maker; Index: sys/dev/ata/chipsets/ata-intel.c =================================================================== --- sys/dev/ata/chipsets/ata-intel.c +++ sys/dev/ata/chipsets/ata-intel.c @@ -556,12 +556,12 @@ mode = min(mode, ctlr->chip->max_dma); if (mode >= ATA_UDMA0) { - tim |= (0x1 << 31); + tim |= (0x1U << 31); tim &= ~(0x7 << 16); tim |= ((mode & ATA_MODE_MASK) << 16); piomode = ATA_PIO4; } else if (mode >= ATA_WDMA0) { - tim &= ~(0x1 << 31); + tim &= ~(0x1U << 31); tim &= ~(0x3 << 8); tim |= ((mode & ATA_MODE_MASK) << 8); piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : Index: sys/dev/bxe/ecore_hsi.h =================================================================== --- sys/dev/bxe/ecore_hsi.h +++ sys/dev/bxe/ecore_hsi.h @@ -2564,7 +2564,7 @@ uint32_t flags; #define ENABLE_ALL_TRIGGERS (0x7fffffff) - #define TRIGGER_MDUMP_ONCE (1 << 31) + #define TRIGGER_MDUMP_ONCE (1U << 31) }; struct shmem2_region { Index: sys/dev/cesa/cesa.h =================================================================== --- sys/dev/cesa/cesa.h +++ sys/dev/cesa/cesa.h @@ -355,7 +355,7 @@ /* CESA SA registers definitions */ #define CESA_SA_CMD 0x0E00 #define CESA_SA_CMD_ACTVATE (1 << 0) -#define CESA_SA_CMD_SHA2 (1 << 31) +#define CESA_SA_CMD_SHA2 (1U << 31) #define CESA_SA_DPR 0x0E04 Index: sys/dev/cxgb/common/cxgb_t3_hw.c =================================================================== --- sys/dev/cxgb/common/cxgb_t3_hw.c +++ sys/dev/cxgb/common/cxgb_t3_hw.c @@ -3587,7 +3587,7 @@ t3_write_reg(adap, A_TP_EMBED_OP_FIELD2, cpu_to_be32(*buf++)); t3_write_reg(adap, A_TP_EMBED_OP_FIELD1, cpu_to_be32(*buf++)); - t3_write_reg(adap, A_TP_EMBED_OP_FIELD0, i << 1 | 1 << 31); + t3_write_reg(adap, A_TP_EMBED_OP_FIELD0, i << 1 | 1U << 31); if (t3_wait_op_done(adap, A_TP_EMBED_OP_FIELD0, 1, 1, 5, 1)) return -EIO; } Index: sys/dev/cxgbe/firmware/t4fw_interface.h =================================================================== --- sys/dev/cxgbe/firmware/t4fw_interface.h +++ sys/dev/cxgbe/firmware/t4fw_interface.h @@ -2021,7 +2021,7 @@ }; enum fw_ri_init_rqeqid_srq { - FW_RI_INIT_RQEQID_SRQ = 1 << 31, + FW_RI_INIT_RQEQID_SRQ = 1U << 31, }; struct fw_ri_wr { Index: sys/dev/drm2/i915/i915_reg.h =================================================================== --- sys/dev/drm2/i915/i915_reg.h +++ sys/dev/drm2/i915/i915_reg.h @@ -927,7 +927,7 @@ #define _DPLL_A 0x06014 #define _DPLL_B 0x06018 #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B) -#define DPLL_VCO_ENABLE (1 << 31) +#define DPLL_VCO_ENABLE (1U << 31) #define DPLL_DVO_HIGH_SPEED (1 << 30) #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) #define DPLL_SYNCLOCK_ENABLE (1 << 29) @@ -1694,7 +1694,7 @@ /* SDVO port control */ #define SDVOB 0x61140 #define SDVOC 0x61160 -#define SDVO_ENABLE (1 << 31) +#define SDVO_ENABLE (1U << 31) #define SDVO_PIPE_B_SELECT (1 << 30) #define SDVO_STALL_SELECT (1 << 29) #define SDVO_INTERRUPT_ENABLE (1 << 26) @@ -1732,7 +1732,7 @@ #define DVOA 0x61120 #define DVOB 0x61140 #define DVOC 0x61160 -#define DVO_ENABLE (1 << 31) +#define DVO_ENABLE (1U << 31) #define DVO_PIPE_B_SELECT (1 << 30) #define DVO_PIPE_STALL_UNUSED (0 << 28) #define DVO_PIPE_STALL (1 << 28) @@ -1768,7 +1768,7 @@ * Enables the LVDS port. This bit must be set before DPLLs are enabled, as * the DPLL semantics change when the LVDS is assigned to that pipe. */ -#define LVDS_PORT_EN (1 << 31) +#define LVDS_PORT_EN (1U << 31) /* Selects pipe B for LVDS data. Must be set on pre-965. */ #define LVDS_PIPEB_SELECT (1 << 30) #define LVDS_PIPE_MASK (1 << 30) @@ -1820,7 +1820,7 @@ #define VIDEO_DIP_DATA_SIZE 32 #define VIDEO_DIP_CTL 0x61170 /* Pre HSW: */ -#define VIDEO_DIP_ENABLE (1 << 31) +#define VIDEO_DIP_ENABLE (1U << 31) #define VIDEO_DIP_PORT_B (1 << 29) #define VIDEO_DIP_PORT_C (2 << 29) #define VIDEO_DIP_PORT_D (3 << 29) @@ -1848,7 +1848,7 @@ /* Panel power sequencing */ #define PP_STATUS 0x61200 -#define PP_ON (1 << 31) +#define PP_ON (1U << 31) /* * Indicates that all dependencies of the panel are on: * @@ -1881,7 +1881,7 @@ /* Panel fitting */ #define PFIT_CONTROL 0x61230 -#define PFIT_ENABLE (1 << 31) +#define PFIT_ENABLE (1U << 31) #define PFIT_PIPE_MASK (3 << 29) #define PFIT_PIPE_SHIFT 29 #define VERT_INTERP_DISABLE (0 << 10) @@ -1916,7 +1916,7 @@ /* Backlight control */ #define BLC_PWM_CTL2 0x61250 /* 965+ only */ -#define BLM_PWM_ENABLE (1 << 31) +#define BLM_PWM_ENABLE (1U << 31) #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ #define BLM_PIPE_SELECT (1 << 29) #define BLM_PIPE_SELECT_IVB (3 << 29) @@ -1966,7 +1966,7 @@ /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ #define BLC_PWM_PCH_CTL1 0xc8250 -#define BLM_PCH_PWM_ENABLE (1 << 31) +#define BLM_PCH_PWM_ENABLE (1U << 31) #define BLM_PCH_OVERRIDE_ENABLE (1 << 30) #define BLM_PCH_POLARITY (1 << 29) #define BLC_PWM_PCH_CTL2 0xc8254 @@ -1974,7 +1974,7 @@ /* TV port control */ #define TV_CTL 0x68000 /** Enables the TV encoder */ -# define TV_ENC_ENABLE (1 << 31) +# define TV_ENC_ENABLE (1U << 31) /** Sources the TV encoder input from pipe B instead of A. */ # define TV_ENC_PIPEB_SELECT (1 << 30) /** Outputs composite video (DAC A only) */ @@ -2046,7 +2046,7 @@ * * This gets cleared when TV_DAC_STATE_EN is cleared */ -# define TVDAC_STATE_CHG (1 << 31) +# define TVDAC_STATE_CHG (1U << 31) # define TVDAC_SENSE_MASK (7 << 28) /** Reports that DAC A voltage is above the detect threshold */ # define TVDAC_A_SENSE (1 << 30) @@ -2173,7 +2173,7 @@ #define TV_H_CTL_2 0x68034 /** Enables the colorburst (needed for non-component color) */ -# define TV_BURST_ENA (1 << 31) +# define TV_BURST_ENA (1U << 31) /** Offset of the colorburst from the start of hsync, in pixels minus one. */ # define TV_HBURST_START_SHIFT 16 # define TV_HBURST_START_MASK 0x1fff0000 @@ -2218,7 +2218,7 @@ #define TV_V_CTL_3 0x68044 /** Enables generation of the equalization signal */ -# define TV_EQUAL_ENA (1 << 31) +# define TV_EQUAL_ENA (1U << 31) /** Length of vsync, in half lines */ # define TV_VEQ_LEN_MASK 0x007f0000 # define TV_VEQ_LEN_SHIFT 16 @@ -2292,7 +2292,7 @@ #define TV_SC_CTL_1 0x68060 /** Turns on the first subcarrier phase generation DDA */ -# define TV_SC_DDA1_EN (1 << 31) +# define TV_SC_DDA1_EN (1U << 31) /** Turns on the first subcarrier phase generation DDA */ # define TV_SC_DDA2_EN (1 << 30) /** Turns on the first subcarrier phase generation DDA */ @@ -2355,7 +2355,7 @@ * If set, the rest of the registers are ignored, and the calculated values can * be read back from the register. */ -# define TV_AUTO_SCALE (1 << 31) +# define TV_AUTO_SCALE (1U << 31) /** * Disables the vertical filter. * @@ -2418,7 +2418,7 @@ # define TV_VSCALE_IP_FRAC_SHIFT 0 #define TV_CC_CONTROL 0x68090 -# define TV_CC_ENABLE (1 << 31) +# define TV_CC_ENABLE (1U << 31) /** * Specifies which field to send the CC data in. * @@ -2434,7 +2434,7 @@ # define TV_CC_LINE_SHIFT 0 #define TV_CC_DATA 0x68094 -# define TV_CC_RDY (1 << 31) +# define TV_CC_RDY (1U << 31) /** Second word of CC data to be transmitted. */ # define TV_CC_DATA_2_MASK 0x007f0000 # define TV_CC_DATA_2_SHIFT 16 @@ -2457,7 +2457,7 @@ #define DP_C 0x64200 #define DP_D 0x64300 -#define DP_PORT_EN (1 << 31) +#define DP_PORT_EN (1U << 31) #define DP_PIPEB_SELECT (1 << 30) #define DP_PIPE_MASK (1 << 30) @@ -2567,7 +2567,7 @@ #define DPD_AUX_CH_DATA4 0x64320 #define DPD_AUX_CH_DATA5 0x64324 -#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) +#define DP_AUX_CH_CTL_SEND_BUSY (1U << 31) #define DP_AUX_CH_CTL_DONE (1 << 30) #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) @@ -3253,7 +3253,7 @@ /* VBIOS regs */ #define VGACNTRL 0x71400 -# define VGA_DISP_DISABLE (1 << 31) +# define VGA_DISP_DISABLE (1U << 31) # define VGA_2X_MODE (1 << 30) # define VGA_PIPE_B_SELECT (1 << 29) @@ -3375,7 +3375,7 @@ #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) /* interrupts */ -#define DE_MASTER_IRQ_CONTROL (1 << 31) +#define DE_MASTER_IRQ_CONTROL (1U << 31) #define DE_SPRITEB_FLIP_DONE (1 << 29) #define DE_SPRITEA_FLIP_DONE (1 << 28) #define DE_PLANEB_FLIP_DONE (1 << 27) @@ -3534,7 +3534,7 @@ #define SDE_TRANS_MASK (0x3f) /* south display engine interrupt: CPT/PPT */ -#define SDE_AUDIO_POWER_D_CPT (1 << 31) +#define SDE_AUDIO_POWER_D_CPT (1U << 31) #define SDE_AUDIO_POWER_C_CPT (1 << 30) #define SDE_AUDIO_POWER_B_CPT (1 << 29) #define SDE_AUDIO_POWER_SHIFT_CPT 29 @@ -3993,7 +3993,7 @@ /* or SDVOB */ #define HDMIB 0xe1140 -#define PORT_ENABLE (1 << 31) +#define PORT_ENABLE (1U << 31) #define TRANSCODER(pipe) ((pipe) << 30) #define TRANSCODER_CPT(pipe) ((pipe) << 29) #define TRANSCODER_MASK (1 << 30) Index: sys/dev/drm2/i915/intel_pm.c =================================================================== --- sys/dev/drm2/i915/intel_pm.c +++ sys/dev/drm2/i915/intel_pm.c @@ -2483,7 +2483,7 @@ struct drm_i915_private *dev_priv = dev->dev_private; I915_WRITE(GEN6_RC_CONTROL, 0); - I915_WRITE(GEN6_RPNSWREQ, 1 << 31); + I915_WRITE(GEN6_RPNSWREQ, 1U << 31); I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); I915_WRITE(GEN6_PMIER, 0); /* Complete PM interrupt masking here doesn't race with the rps work Index: sys/dev/e1000/e1000_82575.h =================================================================== --- sys/dev/e1000/e1000_82575.h +++ sys/dev/e1000/e1000_82575.h @@ -385,7 +385,7 @@ #define E1000_ETQF_FILTER_ENABLE (1 << 26) #define E1000_ETQF_IMM_INT (1 << 29) #define E1000_ETQF_1588 (1 << 30) -#define E1000_ETQF_QUEUE_ENABLE (1 << 31) +#define E1000_ETQF_QUEUE_ENABLE (1U << 31) /* * ETQF filter list: one static filter per filter consumer. This is * to avoid filter collisions later. Add new filters @@ -412,7 +412,7 @@ #define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */ #define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8 #define E1000_DTXSWC_LLE_SHIFT 16 -#define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31) /* global VF LB enable */ +#define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1U << 31) /* global VF LB enable */ /* Easy defines for setting default pool, would normally be left a zero */ #define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7 Index: sys/dev/e1000/e1000_ich8lan.c =================================================================== --- sys/dev/e1000/e1000_ich8lan.c +++ sys/dev/e1000/e1000_ich8lan.c @@ -5202,7 +5202,7 @@ /* Device Status */ if (hw->mac.type == e1000_ich8lan) { reg = E1000_READ_REG(hw, E1000_STATUS); - reg &= ~(1 << 31); + reg &= ~(1U << 31); E1000_WRITE_REG(hw, E1000_STATUS, reg); } Index: sys/dev/e1000/e1000_regs.h =================================================================== --- sys/dev/e1000/e1000_regs.h +++ sys/dev/e1000/e1000_regs.h @@ -215,7 +215,7 @@ /* QAV Tx mode control register bitfields masks */ #define E1000_TQAVCC_IDLE_SLOPE 0xFFFF /* Idle slope */ #define E1000_TQAVCC_KEEP_CREDITS (1 << 30) /* Keep credits opt enable */ -#define E1000_TQAVCC_QUEUE_MODE (1 << 31) /* SP vs. SR Tx mode */ +#define E1000_TQAVCC_QUEUE_MODE (1U << 31) /* SP vs. SR Tx mode */ /* Good transmitted packets counter registers */ #define E1000_PQGPTC(_n) (0x010014 + (0x100 * (_n))) Index: sys/dev/firewire/firewire.c =================================================================== --- sys/dev/firewire/firewire.c +++ sys/dev/firewire/firewire.c @@ -630,7 +630,7 @@ CSRARC(fc, CONF_ROM) = 0x04 << 24; CSRARC(fc, CONF_ROM + 4) = 0x31333934; /* means strings 1394 */ - CSRARC(fc, CONF_ROM + 8) = 1 << 31 | 1 << 30 | 1 << 29 | + CSRARC(fc, CONF_ROM + 8) = 1U << 31 | 1 << 30 | 1 << 29 | 1 << 28 | 0xff << 16 | 0x09 << 8; CSRARC(fc, CONF_ROM + 0xc) = 0; Index: sys/dev/firewire/fwohci.c =================================================================== --- sys/dev/firewire/fwohci.c +++ sys/dev/firewire/fwohci.c @@ -87,7 +87,7 @@ #define MAX_SPEED 3 extern char *linkspeed[]; -uint32_t tagbit[4] = {1 << 28, 1 << 29, 1 << 30, 1 << 31}; +uint32_t tagbit[4] = {1 << 28, 1 << 29, 1 << 30, 1U << 31}; static struct tcode_info tinfo[] = { /* hdr_len block flag valid_response */ @@ -1846,7 +1846,7 @@ OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); /* Allow async. request to us */ - OWRITE(sc, OHCI_AREQHI, 1 << 31); + OWRITE(sc, OHCI_AREQHI, 1U << 31); if (firewire_phydma_enable) { /* allow from all nodes */ OWRITE(sc, OHCI_PREQHI, 0x7fffffff); Index: sys/dev/firewire/fwohcireg.h =================================================================== --- sys/dev/firewire/fwohcireg.h +++ sys/dev/firewire/fwohcireg.h @@ -189,9 +189,9 @@ struct ohci_dma { fwohcireg_t cntl; -#define OHCI_CNTL_CYCMATCH_S (0x1 << 31) +#define OHCI_CNTL_CYCMATCH_S (0x1U << 31) -#define OHCI_CNTL_BUFFIL (0x1 << 31) +#define OHCI_CNTL_BUFFIL (0x1U << 31) #define OHCI_CNTL_ISOHDR (0x1 << 30) #define OHCI_CNTL_CYCMATCH_R (0x1 << 29) #define OHCI_CNTL_MULTICH (0x1 << 28) @@ -439,7 +439,7 @@ #define OHCI_INT_ERR (0x1 << 24) #define OHCI_INT_CYC_LONG (0x1 << 25) #define OHCI_INT_PHY_REG (0x1 << 26) -#define OHCI_INT_EN (0x1 << 31) +#define OHCI_INT_EN (0x1U << 31) #define IP_CHANNELS 0x0234 #define FWOHCI_MAXREC 2048 Index: sys/dev/hwpmc/hwpmc_armv7.c =================================================================== --- sys/dev/hwpmc/hwpmc_armv7.c +++ sys/dev/hwpmc/hwpmc_armv7.c @@ -328,7 +328,7 @@ /* Check if counter has overflowed */ if (pm->pm_md.pm_armv7.pm_armv7_evsel == PMC_EV_CPU_CYCLES) - reg = (1 << 31); + reg = (1U << 31); else reg = (1 << ri); Index: sys/dev/hwpmc/hwpmc_e500.c =================================================================== --- sys/dev/hwpmc/hwpmc_e500.c +++ sys/dev/hwpmc/hwpmc_e500.c @@ -47,7 +47,7 @@ PMC_CAP_WRITE | PMC_CAP_INVERT | \ PMC_CAP_QUALIFIER) -#define E500_PMC_HAS_OVERFLOWED(x) (e500_pmcn_read(x) & (0x1 << 31)) +#define E500_PMC_HAS_OVERFLOWED(x) (e500_pmcn_read(x) & (0x1U << 31)) struct e500_event_code_map { enum pmc_event pe_ev; /* enum value */ Index: sys/dev/hwpmc/hwpmc_mpc7xxx.c =================================================================== --- sys/dev/hwpmc/hwpmc_mpc7xxx.c +++ sys/dev/hwpmc/hwpmc_mpc7xxx.c @@ -58,7 +58,7 @@ /* Change this when we support more than just the 7450. */ #define MPC7XXX_MAX_PMCS 6 -#define MPC7XXX_PMC_HAS_OVERFLOWED(x) (mpc7xxx_pmcn_read(x) & (0x1 << 31)) +#define MPC7XXX_PMC_HAS_OVERFLOWED(x) (mpc7xxx_pmcn_read(x) & (0x1U << 31)) /* * Things to improve on this: Index: sys/dev/hwpmc/hwpmc_powerpc.h =================================================================== --- sys/dev/hwpmc/hwpmc_powerpc.h +++ sys/dev/hwpmc/hwpmc_powerpc.h @@ -40,7 +40,7 @@ PMC_CAP_QUALIFIER) #define POWERPC_PMC_KERNEL_ENABLE (0x1 << 30) -#define POWERPC_PMC_USER_ENABLE (0x1 << 31) +#define POWERPC_PMC_USER_ENABLE (0x1U << 31) #define POWERPC_PMC_ENABLE (POWERPC_PMC_KERNEL_ENABLE | POWERPC_PMC_USER_ENABLE) #define POWERPC_RELOAD_COUNT_TO_PERFCTR_VALUE(V) (0x80000000-(V)) Index: sys/dev/hwpmc/hwpmc_ppc970.c =================================================================== --- sys/dev/hwpmc/hwpmc_ppc970.c +++ sys/dev/hwpmc/hwpmc_ppc970.c @@ -50,7 +50,7 @@ #define PPC970_SET_MMCR1_PMCSEL(r, x, i) \ ((r & ~(0x1f << (5 * (7 - i) + 2))) | (x << (5 * (7 - i) + 2))) -#define PPC970_PMC_HAS_OVERFLOWED(x) (ppc970_pmcn_read(x) & (0x1 << 31)) +#define PPC970_PMC_HAS_OVERFLOWED(x) (ppc970_pmcn_read(x) & (0x1U << 31)) /* How PMC works on PPC970: * Index: sys/dev/if_ndis/if_ndis.c =================================================================== --- sys/dev/if_ndis/if_ndis.c +++ sys/dev/if_ndis/if_ndis.c @@ -3108,7 +3108,7 @@ rkey.nk_keyidx = 0; if (key->wk_flags & IEEE80211_KEY_XMIT) - rkey.nk_keyidx |= 1 << 31; + rkey.nk_keyidx |= 1U << 31; if (key->wk_flags & IEEE80211_KEY_GROUP) { bcopy(ieee80211broadcastaddr, Index: sys/dev/iwm/if_iwmreg.h =================================================================== --- sys/dev/iwm/if_iwmreg.h +++ sys/dev/iwm/if_iwmreg.h @@ -193,7 +193,7 @@ /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), * acknowledged (reset) by host writing "1" to flagged bits. */ -#define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ +#define IWM_CSR_INT_BIT_FH_RX (1U << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ #define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ #define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ #define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ @@ -216,7 +216,7 @@ IWM_CSR_INT_BIT_RX_PERIODIC) /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ -#define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ +#define IWM_CSR_FH_INT_BIT_ERR (1U << 31) /* Error */ #define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ #define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ #define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ @@ -417,7 +417,7 @@ #define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) /* DRAM INT TABLE */ -#define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31) +#define IWM_CSR_DRAM_INT_TBL_ENABLE (1U << 31) #define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) #define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) @@ -558,7 +558,7 @@ #define IWM_HOST_INT_TIMEOUT_MAX (0xFF) #define IWM_HOST_INT_TIMEOUT_DEF (0x40) #define IWM_HOST_INT_TIMEOUT_MIN (0x0) -#define IWM_HOST_INT_OPER_MODE (1 << 31) +#define IWM_HOST_INT_OPER_MODE (1U << 31) /***************************************************************************** * 7000/3000 series SHR DTS addresses * @@ -4201,7 +4201,7 @@ IWM_TX_CMD_FLG_FW_DROP = (1 << 26), IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27), IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28), - IWM_TX_CMD_FLG_HCCA_CHUNK = (1 << 31) + IWM_TX_CMD_FLG_HCCA_CHUNK = (1U << 31) }; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */ /** Index: sys/dev/ixgbe/ixgbe_type.h =================================================================== --- sys/dev/ixgbe/ixgbe_type.h +++ sys/dev/ixgbe/ixgbe_type.h @@ -4329,7 +4329,7 @@ #define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR (1 << 26) #define IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE (1 << 28) #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE (1 << 29) -#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART (1 << 31) +#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART (1U << 31) #define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE (1 << 28) #define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE (1 << 29) @@ -4359,7 +4359,7 @@ #define IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN (1 << 1) #define IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN (1 << 2) #define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN (1 << 3) -#define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN (1 << 31) +#define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN (1U << 31) #define IXGBE_SB_IOSF_INDIRECT_CTRL 0x00011144 #define IXGBE_SB_IOSF_INDIRECT_DATA 0x00011148 Index: sys/dev/mlx4/cq.h =================================================================== --- sys/dev/mlx4/cq.h +++ sys/dev/mlx4/cq.h @@ -86,7 +86,7 @@ } __packed; enum { - MLX4_CQE_L2_TUNNEL_IPOK = 1 << 31, + MLX4_CQE_L2_TUNNEL_IPOK = 1U << 31, MLX4_CQE_CVLAN_PRESENT_MASK = 1 << 29, MLX4_CQE_SVLAN_PRESENT_MASK = 1 << 30, MLX4_CQE_L2_TUNNEL = 1 << 27, Index: sys/dev/mlx4/mlx4_core/mlx4_fw.c =================================================================== --- sys/dev/mlx4/mlx4_core/mlx4_fw.c +++ sys/dev/mlx4/mlx4_core/mlx4_fw.c @@ -1944,7 +1944,7 @@ #endif if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT) - *(inbox + INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET / 4) |= cpu_to_be32(1 << 31); + *(inbox + INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET / 4) |= cpu_to_be32(1U << 31); /* QPC/EEC/CQC/EQC/RDMARC attributes */ Index: sys/dev/mlx4/mlx4_core/mlx4_mcg.c =================================================================== --- sys/dev/mlx4/mlx4_core/mlx4_mcg.c +++ sys/dev/mlx4/mlx4_core/mlx4_mcg.c @@ -1352,7 +1352,7 @@ qpn = qp->qpn; qpn |= (prot << 28); if (attach && block_loopback) - qpn |= (1 << 31); + qpn |= (1U << 31); err = mlx4_cmd(dev, mailbox->dma, qpn, attach, MLX4_CMD_QP_ATTACH, MLX4_CMD_TIME_CLASS_A, Index: sys/dev/mlx4/mlx4_en/mlx4_en_tx.c =================================================================== --- sys/dev/mlx4/mlx4_en/mlx4_en_tx.c +++ sys/dev/mlx4/mlx4_en/mlx4_en_tx.c @@ -600,16 +600,16 @@ if (unlikely(len < MIN_PKT_LEN)) { *(volatile uint32_t *)inl = - SET_BYTE_COUNT((1 << 31) | MIN_PKT_LEN); + SET_BYTE_COUNT((1U << 31) | MIN_PKT_LEN); } else if (len <= spc) { *(volatile uint32_t *)inl = - SET_BYTE_COUNT((1 << 31) | len); + SET_BYTE_COUNT((1U << 31) | len); } else { *(volatile uint32_t *)(inl + 4 + spc) = - SET_BYTE_COUNT((1 << 31) | (len - spc)); + SET_BYTE_COUNT((1U << 31) | (len - spc)); wmb(); *(volatile uint32_t *)inl = - SET_BYTE_COUNT((1 << 31) | spc); + SET_BYTE_COUNT((1U << 31) | spc); } } @@ -885,7 +885,7 @@ dseg->addr = 0; dseg->lkey = 0; wmb(); - dseg->byte_count = SET_BYTE_COUNT((1 << 31)|0); + dseg->byte_count = SET_BYTE_COUNT((1U << 31)|0); } /* fill segment list */ @@ -895,7 +895,7 @@ dseg->addr = 0; dseg->lkey = 0; wmb(); - dseg->byte_count = SET_BYTE_COUNT((1 << 31)|0); + dseg->byte_count = SET_BYTE_COUNT((1U << 31)|0); } else { dseg--; dseg->addr = cpu_to_be64((uint64_t)segs[nr_segs].ds_addr); Index: sys/dev/mlx4/mlx4_ib/mlx4_ib.h =================================================================== --- sys/dev/mlx4/mlx4_ib/mlx4_ib.h +++ sys/dev/mlx4/mlx4_ib/mlx4_ib.h @@ -195,7 +195,7 @@ /* Mellanox specific flags start from IB_QP_CREATE_RESERVED_START */ MLX4_IB_ROCE_V2_GSI_QP = MLX4_IB_QP_CREATE_ROCE_V2_GSI, MLX4_IB_SRIOV_TUNNEL_QP = 1 << 30, - MLX4_IB_SRIOV_SQP = 1 << 31, + MLX4_IB_SRIOV_SQP = 1U << 31, }; struct mlx4_ib_gid_entry { Index: sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c =================================================================== --- sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c +++ sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c @@ -263,7 +263,7 @@ /* Pad the remainder of the WQE with an inline data segment. */ if (size > s) { inl = wqe + s; - inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl)); + inl->byte_count = cpu_to_be32(1U << 31 | (size - s - sizeof *inl)); } ctrl->srcrb_flags = 0; ctrl->fence_size = size / 16; @@ -274,7 +274,7 @@ wmb(); ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) | - (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0); + (n & qp->sq.wqe_cnt ? cpu_to_be32(1U << 31) : 0); stamp_send_wqe(qp, n + qp->sq_spare_wqes, size); } @@ -1992,7 +1992,7 @@ for (i = 0; i < qp->sq.wqe_cnt; ++i) { ctrl = get_send_wqe(qp, i); - ctrl->owner_opcode = cpu_to_be32(1 << 31); + ctrl->owner_opcode = cpu_to_be32(1U << 31); if (qp->sq_max_wqes_per_wr == 1) ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4); @@ -2653,11 +2653,11 @@ spc = MLX4_INLINE_ALIGN - ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); if (header_size <= spc) { - inl->byte_count = cpu_to_be32(1 << 31 | header_size); + inl->byte_count = cpu_to_be32(1U << 31 | header_size); memcpy(inl + 1, sqp->header_buf, header_size); i = 1; } else { - inl->byte_count = cpu_to_be32(1 << 31 | spc); + inl->byte_count = cpu_to_be32(1U << 31 | spc); memcpy(inl + 1, sqp->header_buf, spc); inl = (void *) (inl + 1) + spc; @@ -2676,7 +2676,7 @@ * of 16 mod 64. */ wmb(); - inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc)); + inl->byte_count = cpu_to_be32(1U << 31 | (header_size - spc)); i = 2; } @@ -3213,7 +3213,7 @@ } ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] | - (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh; + (ind & qp->sq.wqe_cnt ? cpu_to_be32(1U << 31) : 0) | blh; stamp = ind + qp->sq_spare_wqes; ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift); Index: sys/dev/mlx4/qp.h =================================================================== --- sys/dev/mlx4/qp.h +++ sys/dev/mlx4/qp.h @@ -283,7 +283,7 @@ #define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232) enum { - MLX4_WQE_CTRL_OWN = 1 << 31, + MLX4_WQE_CTRL_OWN = 1U << 31, MLX4_WQE_CTRL_NEC = 1 << 29, MLX4_WQE_CTRL_RR = 1 << 6, MLX4_WQE_CTRL_IIP = 1 << 28, @@ -371,7 +371,7 @@ enum mlx4_wqe_bind_seg_flags2 { MLX4_WQE_BIND_ZERO_BASED = (1 << 30), - MLX4_WQE_BIND_TYPE_2 = (1 << 31), + MLX4_WQE_BIND_TYPE_2 = (1U << 31), }; struct mlx4_wqe_bind_seg { @@ -388,7 +388,7 @@ MLX4_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28, MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ = 1 << 29, MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE = 1 << 30, - MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC = 1 << 31 + MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC = 1U << 31 }; struct mlx4_wqe_fmr_seg { @@ -445,7 +445,7 @@ enum { MLX4_INLINE_ALIGN = 64, - MLX4_INLINE_SEG = 1 << 31, + MLX4_INLINE_SEG = 1U << 31, }; struct mlx4_wqe_inline_seg { Index: sys/dev/mlx5/device.h =================================================================== --- sys/dev/mlx5/device.h +++ sys/dev/mlx5/device.h @@ -164,7 +164,7 @@ }; enum { - MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31 + MLX5_MKEY_INBOX_PG_ACCESS = 1U << 31 }; enum { @@ -188,7 +188,7 @@ MLX5_MKEY_REMOTE_INVAL = 1 << 24, MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, MLX5_MKEY_BSF_EN = 1 << 30, - MLX5_MKEY_LEN64 = 1 << 31, + MLX5_MKEY_LEN64 = 1U << 31, }; enum { Index: sys/dev/mlx5/qp.h =================================================================== --- sys/dev/mlx5/qp.h +++ sys/dev/mlx5/qp.h @@ -159,7 +159,7 @@ MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28, MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29, MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30, - MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31 + MLX5_WQE_FMR_PERM_ATOMIC = 1U << 31 }; enum { @@ -174,7 +174,7 @@ MLX5_QP_DRAIN_SIGERR = 1 << 26, MLX5_QP_LAT_SENSITIVE = 1 << 28, MLX5_QP_BLOCK_MCAST = 1 << 30, - MLX5_QP_ENABLE_SIG = 1 << 31, + MLX5_QP_ENABLE_SIG = 1U << 31, }; enum { Index: sys/dev/mmc/host/dwmmc.c =================================================================== --- sys/dev/mmc/host/dwmmc.c +++ sys/dev/mmc/host/dwmmc.c @@ -99,7 +99,7 @@ #define DES0_CH (1 << 4) #define DES0_ER (1 << 5) #define DES0_CES (1 << 30) -#define DES0_OWN (1 << 31) +#define DES0_OWN (1U << 31) #define DES1_BS1_MASK 0xfff #define DES1_BS1_SHIFT 0 Index: sys/dev/mmc/host/dwmmc_reg.h =================================================================== --- sys/dev/mmc/host/dwmmc_reg.h +++ sys/dev/mmc/host/dwmmc_reg.h @@ -73,7 +73,7 @@ #define SDMMC_INTMASK_CD (1 << 0) /* Card Detected */ #define SDMMC_CMDARG 0x28 /* Command Argument Register */ #define SDMMC_CMD 0x2C /* Command Register */ -#define SDMMC_CMD_START (1 << 31) +#define SDMMC_CMD_START (1U << 31) #define SDMMC_CMD_USE_HOLD_REG (1 << 29) #define SDMMC_CMD_UPD_CLK_ONLY (1 << 21) /* Update clk only */ #define SDMMC_CMD_SEND_INIT (1 << 15) /* Send initialization */ Index: sys/dev/mmc/mmc_ioctl.h =================================================================== --- sys/dev/mmc/mmc_ioctl.h +++ sys/dev/mmc/mmc_ioctl.h @@ -30,7 +30,7 @@ #define _DEV_MMC_MMC_IOCTL_H_ struct mmc_ioc_cmd { - int write_flag; /* 0: RD, 1: WR, (1 << 31): reliable WR */ + int write_flag; /* 0: RD, 1: WR, (1U << 31): reliable WR */ int is_acmd; /* 0: normal, 1: use CMD55 */ uint32_t opcode; uint32_t arg; Index: sys/dev/mmc/mmcsd.c =================================================================== --- sys/dev/mmc/mmcsd.c +++ sys/dev/mmc/mmcsd.c @@ -933,7 +933,7 @@ goto release; if (part->type == EXT_CSD_PART_CONFIG_ACC_RPMB) { err = mmcsd_set_blockcount(sc, mic->blocks, - mic->write_flag & (1 << 31)); + mic->write_flag & (1U << 31)); if (err != MMC_ERR_NONE) goto switch_back; } @@ -1052,7 +1052,7 @@ cmd.opcode = MMC_SET_BLOCK_COUNT; cmd.arg = count & 0x0000FFFF; if (reliable) - cmd.arg |= 1 << 31; + cmd.arg |= 1U << 31; cmd.flags = MMC_RSP_R1 | MMC_CMD_AC; MMCBUS_WAIT_FOR_REQUEST(sc->mmcbus, sc->dev, &req); return (cmd.error); Index: sys/dev/qlnx/qlnxe/spad_layout.h =================================================================== --- sys/dev/qlnx/qlnxe/spad_layout.h +++ sys/dev/qlnx/qlnxe/spad_layout.h @@ -185,7 +185,7 @@ #define FLAGS_POWER_TRANSITION (1 << 12) #define FLAGS_OS_DRV_LOADED (1 << 29) #define FLAGS_OVER_TEMP_OCCUR (1 << 30) -#define FLAGS_FAN_FAIL_OCCUR (1 << 31) +#define FLAGS_FAN_FAIL_OCCUR (1U << 31) u32 rsrv_persist[4]; /* Persist reserved for MFW upgrades */ /* 0xe20854 */ }; Index: sys/dev/qlxgb/qla_def.h =================================================================== --- sys/dev/qlxgb/qla_def.h +++ sys/dev/qlxgb/qla_def.h @@ -68,7 +68,7 @@ #define BIT_28 (0x1 << 28) #define BIT_29 (0x1 << 29) #define BIT_30 (0x1 << 30) -#define BIT_31 (0x1 << 31) +#define BIT_31 (0x1U << 31) struct qla_rx_buf { struct mbuf *m_head; Index: sys/dev/qlxgbe/ql_def.h =================================================================== --- sys/dev/qlxgbe/ql_def.h +++ sys/dev/qlxgbe/ql_def.h @@ -68,7 +68,7 @@ #define BIT_28 (0x1 << 28) #define BIT_29 (0x1 << 29) #define BIT_30 (0x1 << 30) -#define BIT_31 (0x1 << 31) +#define BIT_31 (0x1U << 31) struct qla_rx_buf { struct mbuf *m_head; Index: sys/dev/qlxge/qls_hw.h =================================================================== --- sys/dev/qlxge/qls_hw.h +++ sys/dev/qlxge/qls_hw.h @@ -84,7 +84,7 @@ #define BIT_28 (0x1 << 28) #define BIT_29 (0x1 << 29) #define BIT_30 (0x1 << 30) -#define BIT_31 (0x1 << 31) +#define BIT_31 (0x1U << 31) /* Index: sys/dev/sound/pci/hdspe.h =================================================================== --- sys/dev/sound/pci/hdspe.h +++ sys/dev/sound/pci/hdspe.h @@ -52,7 +52,7 @@ #define HDSPE_FREQ_0 (1 << 6) #define HDSPE_FREQ_1 (1 << 7) #define HDSPE_FREQ_DOUBLE (1 << 8) -#define HDSPE_FREQ_QUAD (1 << 31) +#define HDSPE_FREQ_QUAD (1U << 31) #define HDSPE_FREQ_32000 HDSPE_FREQ_0 #define HDSPE_FREQ_44100 HDSPE_FREQ_1 Index: sys/dev/uart/uart_dev_mvebu.c =================================================================== --- sys/dev/uart/uart_dev_mvebu.c +++ sys/dev/uart/uart_dev_mvebu.c @@ -53,7 +53,7 @@ #define UART_TSH 0x04 /* Transmitter Holding Register */ #define UART_CTRL 0x08 /* Control Register */ -#define CTRL_SOFT_RST (1 << 31) /* Soft Reset */ +#define CTRL_SOFT_RST (1U << 31) /* Soft Reset */ #define CTRL_TX_FIFO_RST (1 << 15) /* TX FIFO Reset */ #define CTRL_RX_FIFO_RST (1 << 14) /* RX FIFO Reset */ #define CTRL_ST_MIRR_EN (1 << 13) /* Status Mirror Enable */ Index: sys/dev/usb/controller/saf1761_otg.c =================================================================== --- sys/dev/usb/controller/saf1761_otg.c +++ sys/dev/usb/controller/saf1761_otg.c @@ -2499,9 +2499,9 @@ DPRINTF("USBCMD=0x%08x\n", SAF1761_READ_LE_4(sc, SOTG_USBCMD)); /* make HC scan all PTDs */ - SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_LAST_PTD, (1 << 31)); - SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_LAST_PTD, (1 << 31)); - SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_LAST_PTD, (1 << 31)); + SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_LAST_PTD, (1U << 31)); + SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_LAST_PTD, (1U << 31)); + SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_LAST_PTD, (1U << 31)); /* skip all PTDs by default */ SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD, -1U); Index: sys/dev/usb/controller/saf1761_otg_reg.h =================================================================== --- sys/dev/usb/controller/saf1761_otg_reg.h +++ sys/dev/usb/controller/saf1761_otg_reg.h @@ -109,7 +109,7 @@ #define SOTG_INTERRUPT_CFG_INTPOL (1 << 0) #define SOTG_DCINTERRUPT_EN 0x214 #define SOTG_HW_MODE_CTRL 0x300 -#define SOTG_HW_MODE_CTRL_ALL_ATX_RESET (1 << 31) +#define SOTG_HW_MODE_CTRL_ALL_ATX_RESET (1U << 31) #define SOTG_HW_MODE_CTRL_ANA_DIGI_OC (1 << 15) #define SOTG_HW_MODE_CTRL_DEV_DMA (1 << 11) #define SOTG_HW_MODE_CTRL_COMN_INT (1 << 10) Index: sys/dev/usb/net/if_urereg.h =================================================================== --- sys/dev/usb/net/if_urereg.h +++ sys/dev/usb/net/if_urereg.h @@ -403,7 +403,7 @@ struct ure_txpkt { uint32_t ure_pktlen; -#define URE_TKPKT_TX_FS (1 << 31) +#define URE_TKPKT_TX_FS (1U << 31) #define URE_TKPKT_TX_LS (1 << 30) #define URE_TXPKT_LEN_MASK 0xffff uint32_t ure_rsvd0; Index: sys/geom/raid/tr_raid1e.c =================================================================== --- sys/geom/raid/tr_raid1e.c +++ sys/geom/raid/tr_raid1e.c @@ -1044,7 +1044,7 @@ G_RAID_LOGREQ(2, cbp, "Retrying read from %d", nsd->sd_pos); if (do_write) - mask |= 1 << 31; + mask |= 1U << 31; if ((mask & (1U << 31)) != 0) sd->sd_recovery++; cbp->bio_caller2 = (void *)mask; Index: sys/mips/beri/beri_pic.c =================================================================== --- sys/mips/beri/beri_pic.c +++ sys/mips/beri/beri_pic.c @@ -69,7 +69,7 @@ #define BP_CFG_IRQ_M (0xf << BP_CFG_IRQ_S) #define BP_CFG_TID_S 8 #define BP_CFG_TID_M (0x7FFFFF << BP_CFG_TID_S) -#define BP_CFG_ENABLE (1 << 31) +#define BP_CFG_ENABLE (1U << 31) enum { BP_CFG, Index: sys/mips/ingenic/jz4780_codec.h =================================================================== --- sys/mips/ingenic/jz4780_codec.h +++ sys/mips/ingenic/jz4780_codec.h @@ -31,7 +31,7 @@ */ #define CODEC_RGADW 0x00 /* Address, data in and write command */ -#define RGADW_ICRST (1 << 31) /* Reset internal CODEC */ +#define RGADW_ICRST (1U << 31) /* Reset internal CODEC */ #define RGADW_RGWR (1 << 16) /* Issue a write command to CODEC */ #define RGADW_RGADDR_S 8 /* CODEC register's address. */ #define RGADW_RGADDR_M (0x7f << RGADW_RGADDR_S) Index: sys/mips/ingenic/jz4780_lcd.h =================================================================== --- sys/mips/ingenic/jz4780_lcd.h +++ sys/mips/ingenic/jz4780_lcd.h @@ -34,7 +34,7 @@ #define __JZ4780_LCD_H__ #define LCDCFG 0x0000 -#define LCDCFG_LCDPIN (1 << 31) +#define LCDCFG_LCDPIN (1U << 31) #define LCDCFG_TVEPEH (1 << 30) #define LCDCFG_NEWDES (1 << 28) #define LCDCFG_PALBP (1 << 27) @@ -60,7 +60,7 @@ #define LCDCFG_24 (1 << 6) #define LCDCFG_MODE (0xf << 0) #define LCDCTRL 0x0030 -#define LCDCTRL_PINMD (1 << 31) +#define LCDCTRL_PINMD (1U << 31) #define LCDCTRL_BST (0x7 << 28) #define LCDCTRL_BST_4 (0 << 28) #define LCDCTRL_BST_8 (1 << 28) @@ -139,7 +139,7 @@ #define LCDSA0 0x0044 #define LCDFID0 0x0048 #define LCDCMD0 0x004c -#define LCDCMD_SOFINT (1 << 31) +#define LCDCMD_SOFINT (1U << 31) #define LCDCMD_EOFINT (1 << 30) #define LCDCMD_CMD (1 << 29) #define LCDCMD_COMPE (1 << 27) @@ -151,7 +151,7 @@ #define LCDPW0 0x0064 #define LCDCNUM0 0x0068 #define LCDPOS0 LCDCNUM0 -#define LCDPOS_ALPHAMD1 (1 << 31) +#define LCDPOS_ALPHAMD1 (1U << 31) #define LCDPOS_RGB01 (1 << 30) #define LCDPOS_BPP01 (0x7 << 27) #define LCDPOS_BPP01_15_16 (4 << 27) Index: sys/mips/ingenic/jz4780_pdma.h =================================================================== --- sys/mips/ingenic/jz4780_pdma.h +++ sys/mips/ingenic/jz4780_pdma.h @@ -74,7 +74,7 @@ /* Global Control Registers */ #define PDMA_DMAC 0x1000 /* DMA Control */ -#define DMAC_FMSC (1 << 31) +#define DMAC_FMSC (1U << 31) #define DMAC_INTCC_S 17 #define DMAC_INTCC_M (0x1f << DMAC_INTCC_S) #define DMAC_INTCE (1 << 16) /* Permit INTC_IRQ to be bound to one of programmable channel. */ Index: sys/mips/ingenic/jz4780_regs.h =================================================================== --- sys/mips/ingenic/jz4780_regs.h +++ sys/mips/ingenic/jz4780_regs.h @@ -189,7 +189,7 @@ #define CLK_LCD (1 << 28) #define CLK_IPU (1 << 29) #define CLK_DDR0 (1 << 30) - #define CLK_DDR1 (1 << 31) + #define CLK_DDR1 (1U << 31) #define JZ_CLKGR1 0x00000028 /* Clock Gating Registers */ #define CLK_SMB3 (1 << 0) #define CLK_TSSI1 (1 << 1) Index: sys/mips/mediatek/mtk_intr_gic.c =================================================================== --- sys/mips/mediatek/mtk_intr_gic.c +++ sys/mips/mediatek/mtk_intr_gic.c @@ -72,7 +72,7 @@ #define MTK_INTPOL_NEG 0 #define MTK_INTTRIG_EDGE 1 #define MTK_INTTRIG_LEVEL 0 -#define MTK_PIN_BITS(_i) ((1 << 31) | (_i)) +#define MTK_PIN_BITS(_i) ((1U << 31) | (_i)) #define MTK_VPE_BITS(_v) (1 << ((_v) % 32)) static int mtk_gic_intr(void *); Index: sys/mips/mediatek/mtk_pcie.c =================================================================== --- sys/mips/mediatek/mtk_pcie.c +++ sys/mips/mediatek/mtk_pcie.c @@ -594,7 +594,7 @@ uint32_t addr; addr = ((((reg & 0xf00) >> 8) << 24) | (bus << 16) | (slot << 11) | - (func << 8) | (reg & 0xfc) | (1 << 31)); + (func << 8) | (reg & 0xfc) | (1U << 31)); return (addr); } Index: sys/mips/nlm/dev/net/sgmii.c =================================================================== --- sys/mips/nlm/dev/net/sgmii.c +++ sys/mips/nlm/dev/net/sgmii.c @@ -48,7 +48,7 @@ uint32_t data1, data2; /* Apply a soft reset */ - data1 = (0x1 << 31); /* soft reset */ + data1 = (0x1U << 31); /* soft reset */ if (loopback) data1 |= (0x01 << 8); data1 |= (0x01 << 2); /* Rx enable */ @@ -61,7 +61,7 @@ nlm_write_nae_reg(nae_base, NAE_REG(block, port, MAC_CONF2), data2); /* Remove a soft reset */ - data1 &= ~(0x01 << 31); + data1 &= ~(0x01U << 31); nlm_write_nae_reg(nae_base, NAE_REG(block, port, MAC_CONF1), data1); /* setup sgmii max frame length */ @@ -87,7 +87,7 @@ netwk_inf = nlm_read_nae_reg(nae_base, SGMII_NET_IFACE_CTRL(nblock, iface)); - mac_cfg1 &= ~(0x1 << 31); /* remove reset */ + mac_cfg1 &= ~(0x1U << 31); /* remove reset */ mac_cfg1 &= ~(0x1 << 2); /* remove rx */ mac_cfg1 &= ~(0x1); /* remove tx */ mac_cfg2 &= ~(0x3 << 8); /* remove interface mode bits */ @@ -111,7 +111,7 @@ } if (reset) - mac_cfg1 |= (0x1 << 31); /* set reset */ + mac_cfg1 |= (0x1U << 31); /* set reset */ if (rx_en) mac_cfg1 |= (0x1 << 2); /* set rx */ Index: sys/ofed/include/rdma/ib_verbs.h =================================================================== --- sys/ofed/include/rdma/ib_verbs.h +++ sys/ofed/include/rdma/ib_verbs.h @@ -1014,7 +1014,7 @@ IB_QP_CREATE_SCATTER_FCS = 1 << 8, /* reserve bits 26-31 for low level drivers' internal use */ IB_QP_CREATE_RESERVED_START = 1 << 26, - IB_QP_CREATE_RESERVED_END = 1 << 31, + IB_QP_CREATE_RESERVED_END = 1U << 31, }; /* @@ -1202,7 +1202,7 @@ /* reserve bits 26-31 for low level drivers' internal use */ IB_SEND_RESERVED_START = (1 << 26), - IB_SEND_RESERVED_END = (1 << 31), + IB_SEND_RESERVED_END = (1U << 31), }; struct ib_sge { Index: sys/powerpc/fpu/fpu_div.c =================================================================== --- sys/powerpc/fpu/fpu_div.c +++ sys/powerpc/fpu/fpu_div.c @@ -135,7 +135,7 @@ * } while ((bit >>= 1) != 0); * Q[0] = q; * for (i = 1; i < 4; i++) { - * q = 0, bit = 1 << 31; + * q = 0, bit = 1U << 31; * do { * D = R - Y; * if (D >= 0) { @@ -257,7 +257,7 @@ #define WORD(r, i) /* calculate r->fp_mant[i] */ \ q = 0; \ - bit = 1 << 31; \ + bit = 1U << 31; \ LOOP; \ (x)->fp_mant[i] = q Index: sys/powerpc/fpu/fpu_mul.c =================================================================== --- sys/powerpc/fpu/fpu_mul.c +++ sys/powerpc/fpu/fpu_mul.c @@ -172,7 +172,7 @@ #define SHR1 /* A >>= 1, with sticky */ \ sticky |= a3 & 1, a3 = (a3 >> 1) | (a2 << 31), \ - a2 = (a2 >> 1) | (a1 << 31), a1 = (a1 >> 1) | (a0 << 31), a0 >>= 1 + a2 = (a2 >> 1) | (a1U << 31), a1 = (a1 >> 1) | (a0 << 31), a0 >>= 1 #define SHR32 /* A >>= 32, with sticky */ \ sticky |= a3, a3 = a2, a2 = a1, a1 = a0, a0 = 0 Index: sys/powerpc/fpu/fpu_sqrt.c =================================================================== --- sys/powerpc/fpu/fpu_sqrt.c +++ sys/powerpc/fpu/fpu_sqrt.c @@ -314,7 +314,7 @@ #define t1 tt q = 0; y1 = 0; - bit = 1 << 31; + bit = 1U << 31; EVEN_DOUBLE; t1 = bit; FPU_SUBS(d1, x1, t1); @@ -345,7 +345,7 @@ #define t2 tt q = 0; y2 = 0; - bit = 1 << 31; + bit = 1U << 31; EVEN_DOUBLE; t2 = bit; FPU_SUBS(d2, x2, t2); @@ -378,7 +378,7 @@ #define t3 tt q = 0; y3 = 0; - bit = 1 << 31; + bit = 1U << 31; EVEN_DOUBLE; t3 = bit; FPU_SUBS(d3, x3, t3); Index: sys/powerpc/mpc85xx/fsl_diu.c =================================================================== --- sys/powerpc/mpc85xx/fsl_diu.c +++ sys/powerpc/mpc85xx/fsl_diu.c @@ -130,7 +130,7 @@ #define BPP_MASK 0xf /* Bit per pixel Mask */ #define BPP_SHIFT 16 /* Bit per pixel Shift */ #define BPP24 0x5 -#define EN_LAYER (1 << 31) /* Enable the layer */ +#define EN_LAYER (1U << 31) /* Enable the layer */ #define DIU_CTRLDESCLn_5(n) DIU_CTRLDESCL(n, 5) #define DIU_CTRLDESCLn_6(n) DIU_CTRLDESCL(n, 6) #define DIU_CTRLDESCLn_7(n) DIU_CTRLDESCL(n, 7) Index: sys/riscv/include/riscvreg.h =================================================================== --- sys/riscv/include/riscvreg.h +++ sys/riscv/include/riscvreg.h @@ -73,7 +73,7 @@ #define SSTATUS_XS_MASK (0x3 << SSTATUS_XS_SHIFT) #define SSTATUS_SUM (1 << 18) #define SSTATUS32_SD (1 << 63) -#define SSTATUS64_SD (1 << 31) +#define SSTATUS64_SD (1U << 31) #define MSTATUS_UIE (1 << 0) #define MSTATUS_SIE (1 << 1) @@ -108,7 +108,7 @@ #define MSTATUS_VM_SV57 11 #define MSTATUS_VM_SV64 12 #define MSTATUS32_SD (1 << 63) -#define MSTATUS64_SD (1 << 31) +#define MSTATUS64_SD (1U << 31) #define MSTATUS_PRV_U 0 /* user */ #define MSTATUS_PRV_S 1 /* supervisor */ Index: sys/ufs/ffs/ffs_vfsops.c =================================================================== --- sys/ufs/ffs/ffs_vfsops.c +++ sys/ufs/ffs/ffs_vfsops.c @@ -1174,7 +1174,7 @@ } if (fs->fs_magic == FS_UFS1_MAGIC && fs->fs_old_inodefmt < FS_44INODEFMT) { - fs->fs_maxfilesize = ((uint64_t)1 << 31) - 1; + fs->fs_maxfilesize = ((uint64_t)1U << 31) - 1; fs->fs_qbmask = ~fs->fs_bmask; fs->fs_qfmask = ~fs->fs_fmask; } Index: sys/vm/vm_mmap.c =================================================================== --- sys/vm/vm_mmap.c +++ sys/vm/vm_mmap.c @@ -100,7 +100,7 @@ "Do not apply RLIMIT_MEMLOCK on mlockall"); #ifdef MAP_32BIT -#define MAP_32BIT_MAX_ADDR ((vm_offset_t)1 << 31) +#define MAP_32BIT_MAX_ADDR ((vm_offset_t)1U << 31) #endif #ifndef _SYS_SYSPROTO_H_ Index: sys/x86/include/specialreg.h =================================================================== --- sys/x86/include/specialreg.h +++ sys/x86/include/specialreg.h @@ -206,7 +206,7 @@ #define CPUPT_TOPA_MULTI (1 << 1) /* ToPA Tables Allow Multiple Output Entries */ #define CPUPT_SINGLE (1 << 2) /* Single-Range Output Supported */ #define CPUPT_TT_OUT (1 << 3) /* Output to Trace Transport Subsystem Supported */ -#define CPUPT_LINEAR_IP (1 << 31) /* IP Payloads are Linear IP, otherwise IP is effective */ +#define CPUPT_LINEAR_IP (1U << 31) /* IP Payloads are Linear IP, otherwise IP is effective */ /* Leaf 1 eax. */ #define CPUPT_NADDR_S 0 /* Number of Address Ranges */ Index: sys/x86/include/vmware.h =================================================================== --- sys/x86/include/vmware.h +++ sys/x86/include/vmware.h @@ -37,7 +37,7 @@ #define VMW_HVCMD_GETVCPU_INFO 68 #define VMW_VCPUINFO_LEGACY_X2APIC (1 << 3) -#define VMW_VCPUINFO_VCPU_RESERVED (1 << 31) +#define VMW_VCPUINFO_VCPU_RESERVED (1U << 31) static __inline void vmware_hvcall(u_int cmd, u_int *p)