Index: sys/arm/allwinner/a10_mmc.c =================================================================== --- sys/arm/allwinner/a10_mmc.c +++ sys/arm/allwinner/a10_mmc.c @@ -65,6 +65,7 @@ {"allwinner,sun4i-a10-mmc", 1}, {"allwinner,sun5i-a13-mmc", 1}, {"allwinner,sun7i-a20-mmc", 1}, + {"allwinner,sun8i-a83t-mmc", 1}, {"allwinner,sun50i-a64-mmc", 1}, {NULL, 0} }; Index: sys/arm/allwinner/a83t/files.a83t =================================================================== --- sys/arm/allwinner/a83t/files.a83t +++ sys/arm/allwinner/a83t/files.a83t @@ -1,4 +1,6 @@ # $FreeBSD$ +arm/allwinner/clkng/ccu_a83t.c standard +arm/allwinner/clkng/ccu_sun8i_r.c standard arm/allwinner/a83t/a83t_padconf.c standard arm/allwinner/a83t/a83t_r_padconf.c standard Index: sys/arm/allwinner/clkng/aw_ccung.h =================================================================== --- sys/arm/allwinner/clkng/aw_ccung.h +++ sys/arm/allwinner/clkng/aw_ccung.h @@ -29,6 +29,29 @@ #ifndef __CCU_NG_H__ #define __CCU_NG_H__ +#ifdef __aarch64__ +#include "opt_soc.h" +#endif + +#if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5) +#define H3_CCU 1 +#define H3_R_CCU 2 +#endif + +#if defined(SOC_ALLWINNER_A31) +#define A31_CCU 3 +#endif + +#if defined(SOC_ALLWINNER_A64) +#define A64_CCU 4 +#define A64_R_CCU 5 +#endif + +#if defined(SOC_ALLWINNER_A83T) +#define A83T_CCU 6 +#define A83T_R_CCU 7 +#endif + struct aw_ccung_softc { device_t dev; struct resource *res; Index: sys/arm/allwinner/clkng/aw_ccung.c =================================================================== --- sys/arm/allwinner/clkng/aw_ccung.c +++ sys/arm/allwinner/clkng/aw_ccung.c @@ -54,10 +54,6 @@ #include #include -#ifdef __aarch64__ -#include "opt_soc.h" -#endif - #if defined(SOC_ALLWINNER_A31) #include #endif @@ -67,6 +63,11 @@ #include #endif +#if defined(SOC_ALLWINNER_A83T) +#include +#include +#endif + #if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5) #include #include @@ -80,20 +81,6 @@ { -1, 0 } }; -#if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5) -#define H3_CCU 1 -#define H3_R_CCU 2 -#endif - -#if defined(SOC_ALLWINNER_A31) -#define A31_CCU 3 -#endif - -#if defined(SOC_ALLWINNER_A64) -#define A64_CCU 4 -#define A64_R_CCU 5 -#endif - static struct ofw_compat_data compat_data[] = { #if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5) { "allwinner,sun8i-h3-ccu", H3_CCU }, @@ -105,6 +92,10 @@ #if defined(SOC_ALLWINNER_A64) { "allwinner,sun50i-a64-ccu", A64_CCU }, { "allwinner,sun50i-a64-r-ccu", A64_R_CCU }, +#endif +#if defined(SOC_ALLWINNER_A83T) + { "allwinner,sun8i-a83t-ccu", A83T_CCU }, + { "allwinner,sun8i-a83t-r-ccu", A83T_R_CCU }, #endif {NULL, 0 } }; @@ -342,6 +333,14 @@ case A64_R_CCU: ccu_sun8i_r_register_clocks(sc); break; +#endif +#if defined(SOC_ALLWINNER_A83T) + case A83T_CCU: + ccu_a83t_register_clocks(sc); + break; + case A83T_R_CCU: + ccu_sun8i_r_register_clocks(sc); + break; #endif } Index: sys/arm/allwinner/clkng/aw_clk.h =================================================================== --- sys/arm/allwinner/clkng/aw_clk.h +++ sys/arm/allwinner/clkng/aw_clk.h @@ -48,6 +48,7 @@ Clock Source/Divider N/Divider M Clock Source/Divider N/Divider M/2 +Clock Source * N/Divider M + 1/Divider P + 1 */ @@ -70,6 +71,8 @@ #define AW_CLK_FACTOR_ZERO_BASED 0x0002 #define AW_CLK_FACTOR_HAS_COND 0x0004 #define AW_CLK_FACTOR_FIXED 0x0008 +#define AW_CLK_FACTOR_POWER_OF_FOUR 0x0010 +#define AW_CLK_FACTOR_HAS_BIT_COND 0x0020 struct aw_clk_factor { uint32_t shift; /* Shift bits for the factor */ @@ -98,9 +101,14 @@ uint32_t factor_val; uint32_t cond; - if (factor->flags & AW_CLK_FACTOR_HAS_COND) { + if ((factor->flags & AW_CLK_FACTOR_HAS_COND) || + (factor->flags & AW_CLK_FACTOR_HAS_BIT_COND)) { cond = (val & factor->cond_mask) >> factor->cond_shift; - if (cond != factor->cond_value) + if (!(factor->flags & AW_CLK_FACTOR_HAS_BIT_COND) && + cond != factor->cond_value) + return (1); + if ((factor->flags & AW_CLK_FACTOR_HAS_BIT_COND) && + (cond & factor->cond_value) == 0) return (1); } @@ -112,10 +120,24 @@ factor_val += 1; else if (factor->flags & AW_CLK_FACTOR_POWER_OF_TWO) factor_val = 1 << factor_val; + else if (factor->flags & AW_CLK_FACTOR_POWER_OF_FOUR) + factor_val = 1 << (2 * factor_val); return (factor_val); } +static inline uint32_t +aw_clk_factor_get_incremented(uint32_t val, struct aw_clk_factor *factor) +{ + + if (factor->flags & AW_CLK_FACTOR_POWER_OF_TWO) + return (val << 1); + else if (factor->flags & AW_CLK_FACTOR_POWER_OF_FOUR) + return (val << 2); + else + return (val + 1); +} + static inline uint32_t aw_clk_factor_get_max(struct aw_clk_factor *factor) { @@ -125,6 +147,8 @@ max = factor->value; else if (factor->flags & AW_CLK_FACTOR_POWER_OF_TWO) max = 1 << ((1 << factor->width) - 1); + else if (factor->flags & AW_CLK_FACTOR_POWER_OF_FOUR) + max = 1 << (2 * ((1 << factor->width) - 1)); else { max = (1 << factor->width); } @@ -160,6 +184,9 @@ else if (factor->flags & AW_CLK_FACTOR_POWER_OF_TWO) { for (val = 0; raw != 1; val++) raw >>= 1; + } else if (factor->flags & AW_CLK_FACTOR_POWER_OF_FOUR) { + for (val = 0; raw != 1; val++) + raw >>= 2; } else val = raw - 1; Index: sys/arm/allwinner/clkng/aw_clk_nkmp.c =================================================================== --- sys/arm/allwinner/clkng/aw_clk_nkmp.c +++ sys/arm/allwinner/clkng/aw_clk_nkmp.c @@ -168,25 +168,13 @@ } if (best == *fout) return (best); - if ((sc->p.flags & AW_CLK_FACTOR_POWER_OF_TWO) != 0) - p <<= 1; - else - p++; + p = aw_clk_factor_get_incremented(p, &sc->p); } - if ((sc->m.flags & AW_CLK_FACTOR_POWER_OF_TWO) != 0) - m <<= 1; - else - m++; + m = aw_clk_factor_get_incremented(m, &sc->m); } - if ((sc->k.flags & AW_CLK_FACTOR_POWER_OF_TWO) != 0) - k <<= 1; - else - k++; + k = aw_clk_factor_get_incremented(k, &sc->k); } - if ((sc->n.flags & AW_CLK_FACTOR_POWER_OF_TWO) != 0) - n <<= 1; - else - n++; + n = aw_clk_factor_get_incremented(n, &sc->n); } return best; Index: sys/arm/allwinner/clkng/aw_clk_nm.c =================================================================== --- sys/arm/allwinner/clkng/aw_clk_nm.c +++ sys/arm/allwinner/clkng/aw_clk_nm.c @@ -160,15 +160,9 @@ *factor_m = m; } - if ((sc->n.flags & AW_CLK_FACTOR_POWER_OF_TWO) != 0) - n <<= 1; - else - n++; + n = aw_clk_factor_get_incremented(n, &sc->n); } - if ((sc->m.flags & AW_CLK_FACTOR_POWER_OF_TWO) != 0) - m <<= 1; - else - m++; + m = aw_clk_factor_get_incremented(m, &sc->m); } return (best); Index: sys/arm/allwinner/clkng/ccu_a83t.h =================================================================== --- sys/arm/allwinner/clkng/ccu_a83t.h +++ sys/arm/allwinner/clkng/ccu_a83t.h @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2017 Emmanuel Vadot + * Copyright (c) 2017 Kyle Evans * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -26,34 +26,9 @@ * $FreeBSD$ */ -#ifndef __CCU_NG_H__ -#define __CCU_NG_H__ +#ifndef __CCU_A83T_H__ +#define __CCU_A83T_H__ -struct aw_ccung_softc { - device_t dev; - struct resource *res; - struct clkdom *clkdom; - struct mtx mtx; - int type; - struct aw_ccung_reset *resets; - int nresets; - struct aw_ccung_gate *gates; - int ngates; - struct aw_clk_init *clk_init; - int n_clk_init; -}; +void ccu_a83t_register_clocks(struct aw_ccung_softc *sc); -struct aw_ccung_reset { - uint32_t offset; - uint32_t shift; -}; - -struct aw_ccung_gate { - const char *name; - const char *parent_name; - uint32_t id; - uint32_t offset; - uint32_t shift; -}; - -#endif /* __CCU_NG_H__ */ +#endif /* __CCU_A83T_H__ */ Index: sys/arm/allwinner/clkng/ccu_a83t.c =================================================================== --- /dev/null +++ sys/arm/allwinner/clkng/ccu_a83t.c @@ -0,0 +1,783 @@ +/*- + * Copyright (c) 2017 Kyle Evans + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "ccu_a83t.h" + +/* Non-exported resets */ +/* +#define RST_BUS_SCR 53 +*/ + +/* Non-exported clocks */ + +#define CLK_PLL_C0CPUX 0 +#define CLK_PLL_C1CPUX 1 +#define CLK_PLL_AUDIO 2 +#define CLK_PLL_VIDEO0 3 +#define CLK_PLL_VE 4 +#define CLK_PLL_DDR 5 + +#define CLK_PLL_GPU 7 +#define CLK_PLL_HSIC 8 +#define CLK_PLL_VIDEO1 10 + +#define CLK_AXI0 13 +#define CLK_AXI1 14 +#define CLK_AHB1 15 +#define CLK_APB1 16 +#define CLK_APB2 17 +#define CLK_AHB2 18 + +#define CLK_CCI400 58 + +#define CLK_DRAM 82 + +#define CLK_MBUS 95 + +/* Non-exported fixed clocks */ +#define CLK_OSC_12M 150 + + +static struct aw_ccung_reset a83t_ccu_resets[] = { + CCU_RESET(RST_USB_PHY0, 0xcc, 0) + CCU_RESET(RST_USB_PHY1, 0xcc, 1) + CCU_RESET(RST_USB_HSIC, 0xcc, 2) + + CCU_RESET(RST_DRAM, 0xf4, 31) + CCU_RESET(RST_MBUS, 0xfc, 31) + + CCU_RESET(RST_BUS_MIPI_DSI, 0x2c0, 1) + CCU_RESET(RST_BUS_SS, 0x2c0, 5) + CCU_RESET(RST_BUS_DMA, 0x2c0, 6) + CCU_RESET(RST_BUS_MMC0, 0x2c0, 8) + CCU_RESET(RST_BUS_MMC1, 0x2c0, 9) + CCU_RESET(RST_BUS_MMC2, 0x2c0, 10) + CCU_RESET(RST_BUS_NAND, 0x2c0, 13) + CCU_RESET(RST_BUS_DRAM, 0x2c0, 14) + CCU_RESET(RST_BUS_EMAC, 0x2c0, 17) + CCU_RESET(RST_BUS_HSTIMER, 0x2c0, 19) + CCU_RESET(RST_BUS_SPI0, 0x2c0, 20) + CCU_RESET(RST_BUS_SPI1, 0x2c0, 21) + CCU_RESET(RST_BUS_OTG, 0x2c0, 24) + CCU_RESET(RST_BUS_EHCI0, 0x2c0, 26) + CCU_RESET(RST_BUS_EHCI1, 0x2c0, 27) + CCU_RESET(RST_BUS_OHCI0, 0x2c0, 29) + + CCU_RESET(RST_BUS_VE, 0x2c4, 0) + CCU_RESET(RST_BUS_TCON0, 0x2c4, 4) + CCU_RESET(RST_BUS_TCON1, 0x2c4, 5) + CCU_RESET(RST_BUS_CSI, 0x2c4, 8) + CCU_RESET(RST_BUS_HDMI0, 0x2c4, 10) + CCU_RESET(RST_BUS_HDMI1, 0x2c4, 11) + CCU_RESET(RST_BUS_DE, 0x2c4, 12) + CCU_RESET(RST_BUS_GPU, 0x2c4, 20) + CCU_RESET(RST_BUS_MSGBOX, 0x2c4, 21) + CCU_RESET(RST_BUS_SPINLOCK, 0x2c4, 22) + + CCU_RESET(RST_BUS_LVDS, 0x2c8, 0) + + CCU_RESET(RST_BUS_SPDIF, 0x2d0, 1) + CCU_RESET(RST_BUS_I2S0, 0x2d0, 12) + CCU_RESET(RST_BUS_I2S1, 0x2d0, 13) + CCU_RESET(RST_BUS_I2S2, 0x2d0, 14) + CCU_RESET(RST_BUS_TDM, 0x2d0, 15) + + CCU_RESET(RST_BUS_I2C0, 0x2d8, 0) + CCU_RESET(RST_BUS_I2C1, 0x2d8, 1) + CCU_RESET(RST_BUS_I2C2, 0x2d8, 2) + CCU_RESET(RST_BUS_UART0, 0x2d8, 16) + CCU_RESET(RST_BUS_UART1, 0x2d8, 17) + CCU_RESET(RST_BUS_UART2, 0x2d8, 18) + CCU_RESET(RST_BUS_UART3, 0x2d8, 19) + CCU_RESET(RST_BUS_UART4, 0x2d8, 20) +}; + +static struct aw_ccung_gate a83t_ccu_gates[] = { + CCU_GATE(CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1", 0x60, 1) + CCU_GATE(CLK_BUS_SS, "bus-ss", "ahb1", 0x60, 5) + CCU_GATE(CLK_BUS_DMA, "bus-dma", "ahb1", 0x60, 6) + CCU_GATE(CLK_BUS_MMC0, "bus-mmc0", "ahb1", 0x60, 8) + CCU_GATE(CLK_BUS_MMC1, "bus-mmc1", "ahb1", 0x60, 9) + CCU_GATE(CLK_BUS_MMC2, "bus-mmc2", "ahb1", 0x60, 10) + CCU_GATE(CLK_BUS_NAND, "bus-nand", "ahb1", 0x60, 13) + CCU_GATE(CLK_BUS_DRAM, "bus-dram", "ahb1", 0x60, 14) + CCU_GATE(CLK_BUS_EMAC, "bus-emac", "ahb1", 0x60, 17) + CCU_GATE(CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 0x60, 19) + CCU_GATE(CLK_BUS_SPI0, "bus-spi0", "ahb1", 0x60, 20) + CCU_GATE(CLK_BUS_SPI1, "bus-spi1", "ahb1", 0x60, 21) + CCU_GATE(CLK_BUS_OTG, "bus-otg", "ahb1", 0x60, 24) + CCU_GATE(CLK_BUS_EHCI0, "bus-ehci0", "ahb2", 0x60, 26) + CCU_GATE(CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 0x60, 27) + CCU_GATE(CLK_BUS_OHCI0, "bus-ohci0", "ahb2", 0x60, 29) + + CCU_GATE(CLK_BUS_VE, "bus-ve", "ahb1", 0x64, 0) + CCU_GATE(CLK_BUS_TCON0, "bus-tcon0", "ahb1", 0x64, 4) + CCU_GATE(CLK_BUS_TCON1, "bus-tcon1", "ahb1", 0x64, 5) + CCU_GATE(CLK_BUS_CSI, "bus-csi", "ahb1", 0x64, 8) + CCU_GATE(CLK_BUS_HDMI, "bus-hdmi", "ahb1", 0x64, 11) + CCU_GATE(CLK_BUS_DE, "bus-de", "ahb1", 0x64, 12) + CCU_GATE(CLK_BUS_GPU, "bus-gpu", "ahb1", 0x64, 20) + CCU_GATE(CLK_BUS_MSGBOX, "bus-msgbox", "ahb1", 0x64, 21) + CCU_GATE(CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1", 0x64, 22) + + CCU_GATE(CLK_BUS_SPDIF, "bus-spdif", "apb1", 0x68, 1) + CCU_GATE(CLK_BUS_PIO, "bus-pio", "apb1", 0x68, 5) + CCU_GATE(CLK_BUS_I2S0, "bus-i2s0", "apb1", 0x68, 12) + CCU_GATE(CLK_BUS_I2S1, "bus-i2s1", "apb1", 0x68, 13) + CCU_GATE(CLK_BUS_I2S2, "bus-i2s2", "apb1", 0x68, 14) + CCU_GATE(CLK_BUS_TDM, "bus-tdm", "apb1", 0x68, 15) + + CCU_GATE(CLK_BUS_I2C0, "bus-i2c0", "apb2", 0x6c, 0) + CCU_GATE(CLK_BUS_I2C1, "bus-i2c1", "apb2", 0x6c, 1) + CCU_GATE(CLK_BUS_I2C2, "bus-i2c2", "apb2", 0x6c, 2) + CCU_GATE(CLK_BUS_UART0, "bus-uart0", "apb2", 0x6c, 16) + CCU_GATE(CLK_BUS_UART1, "bus-uart1", "apb2", 0x6c, 17) + CCU_GATE(CLK_BUS_UART2, "bus-uart2", "apb2", 0x6c, 18) + CCU_GATE(CLK_BUS_UART3, "bus-uart3", "apb2", 0x6c, 19) + CCU_GATE(CLK_BUS_UART4, "bus-uart4", "apb2", 0x6c, 20) + + CCU_GATE(CLK_USB_PHY0, "usb-phy0", "osc24M", 0xcc, 8) + CCU_GATE(CLK_USB_PHY1, "usb-phy1", "osc24M", 0xcc, 9) + CCU_GATE(CLK_USB_HSIC, "usb-hsic", "pll_hsic", 0xcc, 10) + CCU_GATE(CLK_USB_HSIC_12M, "usb-hsic-12M", "osc12M", 0xcc, 11) + CCU_GATE(CLK_USB_OHCI0, "usb-ohci0", "osc12M", 0xcc, 16) + + CCU_GATE(CLK_DRAM_VE, "dram-ve", "dram", 0x100, 0) + CCU_GATE(CLK_DRAM_CSI, "dram-csi", "dram", 0x100, 1) + + CCU_GATE(CLK_CSI_MISC, "csi-misc", "osc24M", 0x130, 16) + CCU_GATE(CLK_MIPI_CSI, "mipi-csi", "osc24M", 0x130, 31) + + CCU_GATE(CLK_AVS, "avs", "osc24M", 0x144, 31) + + CCU_GATE(CLK_HDMI_SLOW, "hdmi-ddc", "osc24M", 0x154, 31) +}; + +static const char *osc12m_parents[] = {"osc24M"}; +FIXED_CLK(osc12m_clk, + CLK_OSC_12M, /* id */ + "osc12M", osc12m_parents, /* name, parents */ + 0, /* freq */ + 1, /* mult */ + 2, /* div */ + 0); /* flags */ + +static const char *pll_c0cpux_parents[] = {"osc24M"}; +static const char *pll_c1cpux_parents[] = {"osc24M"}; +NKMP_CLK(pll_c0cpux_clk, + CLK_PLL_C0CPUX, /* id */ + "pll_c0cpux", pll_c0cpux_parents, /* name, parents */ + 0x00, /* offset */ + 8, 8, 0, 0, /* n factor */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ + 0, 2, 0, 0, /* m factor */ + 16, 1, 0, AW_CLK_FACTOR_POWER_OF_FOUR, /* p factor */ + 31, /* gate */ + 0, 0, /* lock */ + AW_CLK_HAS_GATE | AW_CLK_SCALE_CHANGE); /* flags */ +NKMP_CLK(pll_c1cpux_clk, + CLK_PLL_C1CPUX, /* id */ + "pll_c1cpux", pll_c1cpux_parents, /* name, parents */ + 0x04, /* offset */ + 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ + 0, 2, 0, 0, /* m factor */ + 16, 1, 0, AW_CLK_FACTOR_POWER_OF_FOUR, /* p factor */ + 31, /* gate */ + 0, 0, /* lock */ + AW_CLK_HAS_GATE | AW_CLK_SCALE_CHANGE); /* flags */ + +static const char *pll_audio_parents[] = {"osc24M"}; +NKMP_CLK(pll_audio_clk, + CLK_PLL_AUDIO, /* id */ + "pll_audio", pll_audio_parents, /* name, parents */ + 0x08, /* offset */ + 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ + 16, 1, 0, 0, /* m factor */ + 18, 1, 0, 0, /* p factor */ + 31, /* gate */ + 0, 0, /* lock */ + AW_CLK_HAS_GATE); /* flags */ + +static const char *pll_video0_parents[] = {"osc24M"}; +NKMP_CLK(pll_video0_clk, + CLK_PLL_VIDEO0, /* id */ + "pll_video0", pll_video0_parents, /* name, parents */ + 0x10, /* offset */ + 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ + 16, 1, 0, 0, /* m factor */ + 0, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* p factor */ + 31, /* gate */ + 0, 0, /* lock */ + AW_CLK_HAS_GATE); /* flags */ + +static const char *pll_ve_parents[] = {"osc24M"}; +NKMP_CLK(pll_ve_clk, + CLK_PLL_VE, /* id */ + "pll_ve", pll_ve_parents, /* name, parents */ + 0x18, /* offset */ + 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ + 16, 1, 0, 0, /* m factor */ + 18, 1, 0, 0, /* p factor */ + 31, /* gate */ + 0, 0, /* lock */ + AW_CLK_HAS_GATE); /* flags */ + +static const char *pll_ddr_parents[] = {"osc24M"}; +NKMP_CLK(pll_ddr_clk, + CLK_PLL_DDR, /* id */ + "pll_ddr", pll_ddr_parents, /* name, parents */ + 0x20, /* offset */ + 8, 5, 0, 0, /* n factor */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ + 16, 1, 0, 0, /* m factor */ + 18, 1, 0, 0, /* p factor */ + 31, /* gate */ + 0, 0, /* lock */ + AW_CLK_HAS_GATE); /* flags */ + +static const char *pll_periph_parents[] = {"osc24M"}; +NKMP_CLK(pll_periph_clk, + CLK_PLL_PERIPH, /* id */ + "pll_periph", pll_periph_parents, /* name, parents */ + 0x28, /* offset */ + 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ + 16, 1, 1, 0, /* m factor */ + 18, 1, 1, 0, /* p factor */ + 31, /* gate */ + 0, 0, /* lock */ + AW_CLK_HAS_GATE); /* flags */ + +static const char *pll_gpu_parents[] = {"osc24M"}; +NKMP_CLK(pll_gpu_clk, + CLK_PLL_GPU, /* id */ + "pll_gpu", pll_gpu_parents, /* name, parents */ + 0x38, /* offset */ + 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ + 16, 1, 1, 0, /* m factor */ + 18, 1, 1, 0, /* p factor */ + 31, /* gate */ + 0, 0, /* lock */ + AW_CLK_HAS_GATE); /* flags */ + +static const char *pll_hsic_parents[] = {"osc24M"}; +NKMP_CLK(pll_hsic_clk, + CLK_PLL_HSIC, /* id */ + "pll_hsic", pll_hsic_parents, /* name, parents */ + 0x44, /* offset */ + 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ + 16, 1, 1, 0, /* m factor */ + 18, 1, 1, 0, /* p factor */ + 31, /* gate */ + 0, 0, /* lock */ + AW_CLK_HAS_GATE); /* flags */ + +static const char *pll_de_parents[] = {"osc24M"}; +NKMP_CLK(pll_de_clk, + CLK_PLL_DE, /* id */ + "pll_de", pll_de_parents, /* name, parents */ + 0x48, /* offset */ + 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ + 16, 1, 1, 0, /* m factor */ + 18, 1, 1, 0, /* p factor */ + 31, /* gate */ + 0, 0, /* lock */ + AW_CLK_HAS_GATE); /* flags */ + +static const char *pll_video1_parents[] = {"osc24M"}; +NKMP_CLK(pll_video1_clk, + CLK_PLL_VIDEO1, /* id */ + "pll_video1", pll_video1_parents, /* name, parents */ + 0x4c, /* offset */ + 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ + 16, 1, 1, 0, /* m factor */ + 0, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* p factor */ + 31, /* gate */ + 0, 0, /* lock */ + AW_CLK_HAS_GATE); /* flags */ + +static const char *c0cpux_parents[] = {"osc24M", "pll_c0cpux"}; +MUX_CLK(c0cpux_clk, + CLK_C0CPUX, /* id */ + "c0cpux", c0cpux_parents, /* name, parents */ + 0x50, 12, 1); /* offset, shift, width */ + +static const char *c1cpux_parents[] = {"osc24M", "pll_c1cpux"}; +MUX_CLK(c1cpux_clk, + CLK_C1CPUX, /* id */ + "c1cpux", c1cpux_parents, /* name, parents */ + 0x50, 28, 1); /* offset, shift, width */ + +static const char *axi0_parents[] = {"c0cpux"}; +DIV_CLK(axi0_clk, + CLK_AXI0, /* id */ + "axi0", axi0_parents, /* name, parents */ + 0x50, /* offset */ + 0, 2, /* shift, width */ + 0, NULL); /* flags, div table */ + +static const char *axi1_parents[] = {"c1cpux"}; +DIV_CLK(axi1_clk, + CLK_AXI1, /* id */ + "axi1", axi1_parents, /* name, parents */ + 0x50, /* offset */ + 16, 2, /* shift, width */ + 0, NULL); /* flags, div table */ + +static const char *ahb1_parents[] = {"osc16M-d512", "osc24M", "pll_periph", "pll_periph"}; +PREDIV_CLK(ahb1_clk, + CLK_AHB1, /* id */ + "ahb1", ahb1_parents, /* name, parents */ + 0x54, /* offset */ + 12, 2, /* mux */ + 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */ + 6, 2, 0, AW_CLK_FACTOR_HAS_BIT_COND, /* prediv */ + 12, 2, 2); /* prediv bit condition */ + +static const char *apb1_parents[] = {"ahb1"}; +DIV_CLK(apb1_clk, + CLK_APB1, /* id */ + "apb1", apb1_parents, /* name, parents */ + 0x54, /* offset */ + 8, 2, /* shift, width */ + 0, NULL); /* flags, div table */ + +static const char *apb2_parents[] = {"osc16M-d512", "osc24M", "pll_periph", "pll_periph"}; +NM_CLK(apb2_clk, + CLK_APB2, /* id */ + "apb2", apb2_parents, /* name, parents */ + 0x58, /* offset */ + 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ + 0, 5, 0, 0, /* m factor */ + 24, 2, /* mux */ + 0, /* gate */ + AW_CLK_HAS_MUX); + +static const char *ahb2_parents[] = {"ahb1", "pll_periph"}; +PREDIV_CLK(ahb2_clk, + CLK_AHB2, /* id */ + "ahb2", ahb2_parents, /* name, parents */ + 0x5c, + 0, 2, /* mux */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* div (fake) */ + 0, 0, 2, AW_CLK_FACTOR_HAS_COND | AW_CLK_FACTOR_FIXED, /* prediv */ + 0, 2, 1); /* prediv cond */ + +/* Actually has a divider, but we don't use it */ +static const char *cci400_parents[] = {"osc24M", "pll_periph", "pll_hsic"}; +MUX_CLK(cci400_clk, + CLK_CCI400, /* id */ + "cci400", cci400_parents, /* name, parents */ + 0x78, 24, 2); /* offset, shift, width */ + +static const char *mod_parents[] = {"osc24M", "pll_periph"}; + +NM_CLK(nand_clk, + CLK_NAND, /* id */ + "nand", mod_parents, /* name, parents */ + 0x80, /* offset */ + 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ + 0, 4, 0, 0, /* m factor */ + 24, 2, /* mux */ + 31, /* gate */ + AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); + +NM_CLK(mmc0_clk, + CLK_MMC0, /* id */ + "mmc0", mod_parents, /* name, parents */ + 0x88, /* offset */ + 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ + 0, 4, 0, 0, /* m factor */ + 24, 2, /* mux */ + 31, /* gate */ + AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | + AW_CLK_REPARENT); +NM_CLK(mmc1_clk, + CLK_MMC1, /* id */ + "mmc1", mod_parents, /* name, parents */ + 0x8c, /* offset */ + 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ + 0, 4, 0, 0, /* m factor */ + 24, 2, /* mux */ + 31, /* gate */ + AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | + AW_CLK_REPARENT); +NM_CLK(mmc2_clk, + CLK_MMC2, /* id */ + "mmc2", mod_parents, /* name, parents */ + 0x90, /* offset */ + 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ + 0, 4, 0, 0, /* m factor */ + 24, 2, /* mux */ + 31, /* gate */ + AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | + AW_CLK_REPARENT); + +NM_CLK(ss_clk, + CLK_SS, /* id */ + "ss", mod_parents, /* name, parents */ + 0x9c, /* offset */ + 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ + 0, 4, 0, 0, /* m factor */ + 24, 2, /* mux */ + 31, /* gate */ + AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); + +NM_CLK(spi0_clk, + CLK_SPI0, /* id */ + "spi0", mod_parents, /* name, parents */ + 0xa0, /* offset */ + 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ + 0, 4, 0, 0, /* m factor */ + 24, 2, /* mux */ + 31, /* gate */ + AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); +NM_CLK(spi1_clk, + CLK_SPI1, /* id */ + "spi1", mod_parents, /* name, parents */ + 0xa4, /* offset */ + 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ + 0, 4, 0, 0, /* m factor */ + 24, 2, /* mux */ + 31, /* gate */ + AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); + +static const char *daudio_parents[] = {"pll_audio"}; +NM_CLK(i2s0_clk, + CLK_I2S0, /* id */ + "i2s0", daudio_parents, /* name, parents */ + 0xb0, /* offset */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ + 0, 4, 0, 0, /* m factor */ + 0, 0, /* mux */ + 31, /* gate */ + AW_CLK_HAS_GATE); +NM_CLK(i2s1_clk, + CLK_I2S1, /* id */ + "i2s1", daudio_parents, /* name, parents */ + 0xb4, /* offset */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ + 0, 4, 0, 0, /* m factor */ + 0, 0, /* mux */ + 31, /* gate */ + AW_CLK_HAS_GATE); +NM_CLK(i2s2_clk, + CLK_I2S2, /* id */ + "i2s2", daudio_parents, /* name, parents */ + 0xb8, /* offset */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ + 0, 4, 0, 0, /* m factor */ + 0, 0, /* mux */ + 31, /* gate */ + AW_CLK_HAS_GATE); + +static const char *tdm_parents[] = {"pll_audio"}; +NM_CLK(tdm_clk, + CLK_TDM, /* id */ + "tdm", tdm_parents, /* name, parents */ + 0xbc, /* offset */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ + 0, 4, 0, 0, /* m factor */ + 0, 0, /* mux */ + 31, /* gate */ + AW_CLK_HAS_GATE); + +static const char *spdif_parents[] = {"pll_audio"}; +NM_CLK(spdif_clk, + CLK_SPDIF, /* id */ + "spdif", spdif_parents, /* name, parents */ + 0xc0, /* offset */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ + 0, 4, 0, 0, /* m factor */ + 0, 0, /* mux */ + 31, /* gate */ + AW_CLK_HAS_GATE); + +static const char *dram_parents[] = {"pll_ddr"}; +NM_CLK(dram_clk, + CLK_DRAM, /* id */ + "dram", dram_parents, /* name, parents */ + 0xf4, /* offset */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ + 0, 4, 0, 0, /* m factor */ + 0, 0, /* mux */ + 0, /* gate */ + 0); + +static const char *tcon0_parents[] = {"pll_video0"}; +MUX_CLK(tcon0_clk, + CLK_TCON0, /* id */ + "tcon0", tcon0_parents, /* name, parents */ + 0x118, 24, 2); /* offset, shift, width */ + +static const char *tcon1_parents[] = {"pll_video1"}; +NM_CLK(tcon1_clk, + CLK_TCON1, /* id */ + "tcon1", tcon1_parents, /* name, parents */ + 0x11c, /* offset */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ + 0, 4, 0, 0, /* m factor */ + 0, 0, /* mux */ + 31, /* gate */ + AW_CLK_HAS_GATE); + +static const char *csi_mclk_parents[] = {"pll_de", "osc24M"}; +NM_CLK(csi_mclk_clk, + CLK_CSI_MCLK, /* id */ + "csi-mclk", csi_mclk_parents, /* name, parents */ + 0x134, /* offset */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ + 0, 4, 0, 0, /* m factor */ + 8, 3, /* mux */ + 15, /* gate */ + AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); + +static const char *csi_sclk_parents[] = {"pll_periph", "pll_ve"}; +NM_CLK(csi_sclk_clk, + CLK_CSI_SCLK, /* id */ + "csi-sclk", csi_sclk_parents, /* name, parents */ + 0x134, /* offset */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ + 16, 4, 0, 0, /* m factor */ + 24, 3, /* mux */ + 31, /* gate */ + AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); + +static const char *ve_parents[] = {"pll_ve"}; +NM_CLK(ve_clk, + CLK_VE, /* id */ + "ve", ve_parents, /* name, parents */ + 0x13c, /* offset */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ + 16, 3, 0, 0, /* m factor */ + 0, 0, /* mux */ + 31, /* gate */ + AW_CLK_HAS_GATE); + +static const char *hdmi_parents[] = {"pll_video1"}; +NM_CLK(hdmi_clk, + CLK_HDMI, /* id */ + "hdmi", hdmi_parents, /* name, parents */ + 0x150, /* offset */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ + 0, 4, 0, 0, /* m factor */ + 24, 2, /* mux */ + 31, /* gate */ + AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); + +static const char *mbus_parents[] = {"osc24M", "pll_periph", "pll_ddr"}; +NM_CLK(mbus_clk, + CLK_MBUS, /* id */ + "mbus", mbus_parents, /* name, parents */ + 0x15c, /* offset */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ + 0, 3, 0, 0, /* m factor */ + 24, 2, /* mux */ + 31, /* gate */ + AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); + +static const char *mipi_dsi0_parents[] = {"pll_video0"}; +NM_CLK(mipi_dsi0_clk, + CLK_MIPI_DSI0, /* id */ + "mipi-dsi0", mipi_dsi0_parents, /* name, parents */ + 0x168, /* offset */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ + 0, 4, 0, 0, /* m factor */ + 24, 4, /* mux */ + 31, /* gate */ + AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); + +static const char *mipi_dsi1_parents[] = {"osc24M", "pll_video0"}; +NM_CLK(mipi_dsi1_clk, + CLK_MIPI_DSI1, /* id */ + "mipi-dsi1", mipi_dsi1_parents, /* name, parents */ + 0x16c, /* offset */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ + 0, 4, 0, 0, /* m factor */ + 24, 4, /* mux */ + 31, /* gate */ + AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); + +static const char *gpu_core_parents[] = {"pll_gpu"}; +NM_CLK(gpu_core_clk, + CLK_GPU_CORE, /* id */ + "gpu-core", gpu_core_parents, /* name, parents */ + 0x1a0, /* offset */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ + 0, 3, 0, 0, /* m factor */ + 0, 0, /* mux */ + 31, /* gate */ + AW_CLK_HAS_GATE); + +static const char *gpu_memory_parents[] = {"pll_gpu", "pll_periph"}; +NM_CLK(gpu_memory_clk, + CLK_GPU_MEMORY, /* id */ + "gpu-memory", gpu_memory_parents, /* name, parents */ + 0x1a4, /* offset */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ + 0, 3, 0, 0, /* m factor */ + 24, 1, /* mux */ + 31, /* gate */ + AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); + +static const char *gpu_hyd_parents[] = {"pll_gpu"}; +NM_CLK(gpu_hyd_clk, + CLK_GPU_HYD, /* id */ + "gpu-hyd", gpu_hyd_parents, /* name, parents */ + 0x1a0, /* offset */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ + 0, 3, 0, 0, /* m factor */ + 0, 0, /* mux */ + 31, /* gate */ + AW_CLK_HAS_GATE); + + +static struct aw_clk_nkmp_def *nkmp_clks[] = { + &pll_c0cpux_clk, + &pll_c1cpux_clk, + &pll_audio_clk, + &pll_video0_clk, + &pll_ve_clk, + &pll_ddr_clk, + &pll_periph_clk, + &pll_gpu_clk, + &pll_hsic_clk, + &pll_de_clk, + &pll_video1_clk, +}; + +static struct aw_clk_nm_def *nm_clks[] = { + &apb2_clk, + &nand_clk, + &mmc0_clk, + &mmc1_clk, + &mmc2_clk, + &ss_clk, + &spi0_clk, + &spi1_clk, + &i2s0_clk, + &i2s1_clk, + &i2s2_clk, + &tdm_clk, + &spdif_clk, + &dram_clk, + &tcon1_clk, + &csi_mclk_clk, + &csi_sclk_clk, + &ve_clk, + &hdmi_clk, + &mbus_clk, + &mipi_dsi0_clk, + &mipi_dsi1_clk, + &gpu_core_clk, + &gpu_memory_clk, + &gpu_hyd_clk, +}; + +static struct aw_clk_prediv_mux_def *prediv_mux_clks[] = { + &ahb1_clk, + &ahb2_clk, +}; + +static struct clk_mux_def *mux_clks[] = { + &c0cpux_clk, + &c1cpux_clk, + &cci400_clk, + &tcon0_clk, +}; + +static struct clk_div_def *div_clks[] = { + &axi0_clk, + &axi1_clk, + &apb1_clk, +}; + +static struct clk_fixed_def *fixed_factor_clks[] = { + &osc12m_clk, +}; + +static struct aw_clk_init init_clks[] = { + {"ahb1", "pll_periph", 0, false}, + {"ahb2", "ahb1", 0, false}, + {"dram", "pll_ddr", 0, false}, +}; + +void +ccu_a83t_register_clocks(struct aw_ccung_softc *sc) +{ + int i; + + sc->resets = a83t_ccu_resets; + sc->nresets = nitems(a83t_ccu_resets); + sc->gates = a83t_ccu_gates; + sc->ngates = nitems(a83t_ccu_gates); + sc->clk_init = init_clks; + sc->n_clk_init = nitems(init_clks); + + for (i = 0; i < nitems(nkmp_clks); i++) + aw_clk_nkmp_register(sc->clkdom, nkmp_clks[i]); + for (i = 0; i < nitems(nm_clks); i++) + aw_clk_nm_register(sc->clkdom, nm_clks[i]); + for (i = 0; i < nitems(prediv_mux_clks); i++) + aw_clk_prediv_mux_register(sc->clkdom, prediv_mux_clks[i]); + + for (i = 0; i < nitems(mux_clks); i++) + clknode_mux_register(sc->clkdom, mux_clks[i]); + for (i = 0; i < nitems(div_clks); i++) + clknode_div_register(sc->clkdom, div_clks[i]); + for (i = 0; i < nitems(fixed_factor_clks); i++) + clknode_fixed_register(sc->clkdom, fixed_factor_clks[i]); +} Index: sys/arm/allwinner/clkng/ccu_sun8i_r.c =================================================================== --- sys/arm/allwinner/clkng/ccu_sun8i_r.c +++ sys/arm/allwinner/clkng/ccu_sun8i_r.c @@ -70,6 +70,7 @@ }; static const char *ar100_parents[] = {"osc32k", "osc24M", "pll_periph0", "iosc"}; +static const char *a83t_ar100_parents[] = {"osc16M-d512", "osc24M", "pll_periph", "osc16M"}; PREDIV_CLK(ar100_clk, CLK_AR100, /* id */ "ar100", ar100_parents, /* name, parents */ 0x00, /* offset */ @@ -77,6 +78,13 @@ 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */ 8, 5, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */ 16, 2, 2); /* prediv condition */ +PREDIV_CLK(a83t_ar100_clk, CLK_AR100, /* id */ + "ar100", a83t_ar100_parents, /* name, parents */ + 0x00, /* offset */ + 16, 2, /* mux */ + 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */ + 8, 5, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */ + 16, 2, 2); /* prediv condition */ static const char *ahb0_parents[] = {"ar100"}; FIXED_CLK(ahb0_clk, @@ -96,10 +104,6 @@ 0, 2, /* shift, width */ 0, NULL); /* flags, div table */ -static struct aw_clk_prediv_mux_def *prediv_mux_clks[] = { - &ar100_clk, -}; - static struct clk_div_def *div_clks[] = { &apb0_clk, }; @@ -118,8 +122,12 @@ sc->gates = ccu_sun8i_r_gates; sc->ngates = nitems(ccu_sun8i_r_gates); - for (i = 0; i < nitems(prediv_mux_clks); i++) - aw_clk_prediv_mux_register(sc->clkdom, prediv_mux_clks[i]); + /* The ar100 on the a83t has different parents than the others */ + if (sc->type == A83T_R_CCU) + aw_clk_prediv_mux_register(sc->clkdom, &a83t_ar100_clk); + else + aw_clk_prediv_mux_register(sc->clkdom, &ar100_clk); + for (i = 0; i < nitems(div_clks); i++) clknode_div_register(sc->clkdom, div_clks[i]); for (i = 0; i < nitems(fixed_factor_clks); i++) Index: sys/boot/fdt/dts/arm/a83t.dtsi =================================================================== --- sys/boot/fdt/dts/arm/a83t.dtsi +++ sys/boot/fdt/dts/arm/a83t.dtsi @@ -26,15 +26,17 @@ * $FreeBSD$ */ +#include + / { cpus { cpu@0 { - clocks = <&c0_cpux_clk>; + clocks = <&ccu CLK_C0CPUX>; clock-latency = <2000000>; }; cpu@100 { - clocks = <&c1_cpux_clk>; + clocks = <&ccu CLK_C1CPUX>; clock-latency = <2000000>; }; }; @@ -49,89 +51,6 @@ ; }; - clocks { - pll_c0cpux: clk@01c20000 { - #clock-cells = <0>; - compatible = "allwinner,sun8i-a83t-pllcpux-clk"; - reg = <0x01c20000 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll_c0cpux"; - }; - - pll_c1cpux: clk@01c20004 { - #clock-cells = <0>; - compatible = "allwinner,sun8i-a83t-pllcpux-clk"; - reg = <0x01c20004 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll_c1cpux"; - }; - - c0_cpux_clk: c0clk@01c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun8i-a83t-c0cpu-clk"; - reg = <0x01c20050 0x4>; - clocks = <&osc24M>, <&pll_c0cpux>; - clock-output-names = "c0_cpux"; - }; - - c1_cpux_clk: c1clk@01c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun8i-a83t-c1cpu-clk"; - reg = <0x01c20050 0x4>; - clocks = <&osc24M>, <&pll_c1cpux>; - clock-output-names = "c1_cpux"; - }; - - /* cpus_clk compatible in gnu dt is incorrect */ - cpus_clk: clk@01f01400 { - compatible = "allwinner,sun8i-a83t-cpus-clk"; - }; - - pll_hsic: clk@01c20044 { - #clock-cells = <0>; - compatible = "allwinner,sun9i-a80-pll4-clk"; - reg = <0x01c20044 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll_hsic"; - }; - - usb_clk: clk@01c200cc { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "allwinner,sun8i-a83t-usb-clk"; - reg = <0x01c200cc 0x4>; - clocks = <&osc24M>, <&pll_hsic>; - clock-indices = <8>, <9>, - <10>, <11>, - <16>; - clock-output-names = "usb_phy0", "usb_phy1", - "usb_hsic_pll", "usb_hsic_12m", - "usb_ohci0"; - }; - - mii_phy_tx_clk: clk@1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - clock-output-names = "mii_phy_tx"; - }; - - emac_int_tx_clk: clk@2 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "emac_int_tx"; - }; - - emac_tx_clk: clk@01c00030 { - #clock-cells = <0>; - compatible = "allwinner,sun8i-a83t-emac-clk"; - reg = <0x01c00030 0x4>; - clocks = <&mii_phy_tx_clk>, <&emac_int_tx_clk>; - clock-output-names = "emac_tx"; - }; - }; - soc { nmi_intc: interrupt-controller@01f00c0c { compatible = "allwinner,sun6i-a31-sc-nmi"; @@ -145,8 +64,8 @@ compatible = "allwinner,sun8i-a83t-i2c"; reg = <0x01c2ac00 0x400>; interrupts = ; - clocks = <&bus_gates 96>; - resets = <&apb2_reset 0>; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -156,8 +75,8 @@ compatible = "allwinner,sun8i-a83t-i2c"; reg = <0x01c2b000 0x400>; interrupts = ; - clocks = <&bus_gates 97>; - resets = <&apb2_reset 1>; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -167,66 +86,22 @@ compatible = "allwinner,sun8i-a83t-i2c"; reg = <0x01c2b400 0x400>; interrupts = ; - clocks = <&bus_gates 98>; - resets = <&apb2_reset 2>; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - usbphy: phy@01c19400 { - compatible = "allwinner,sun8i-a83t-usb-phy"; - reg = <0x01c19400 0x2c>, - <0x01c1a800 0x4>, - <0x01c1b800 0x4>; - clocks = <&usb_clk 8>, - <&usb_clk 9>, - <&usb_clk 10>, - <&usb_clk 11>; - clock-names = "usb0_phy", - "usb1_phy", - "hsic_pll", - "hsic_12m"; - resets = <&usb_clk 0>, - <&usb_clk 1>, - <&usb_clk 2>; - reset-names = "usb0_reset", - "usb1_reset", - "usb2_reset"; - status = "disabled"; - #phy-cells = <1>; - }; - - ehci0: usb@01c1a000 { - compatible = "allwinner,sun8i-a83t-ehci", "generic-ehci"; - reg = <0x01c1a000 0x100>; - interrupts = ; - clocks = <&bus_gates 26>; - resets = <&ahb_reset 26>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci1: usb@01c1b000 { - compatible = "allwinner,sun8i-a83t-ehci", "generic-ehci"; - reg = <0x01c1b000 0x100>; - interrupts = ; - clocks = <&bus_gates 27>; - resets = <&ahb_reset 27>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - emac: ethernet@01c30000 { compatible = "allwinner,sun8i-a83t-emac"; - reg = <0x01c30000 0x100>; + reg = <0x01c30000 0x104>, <0x01c00030 0x4>; + reg-names = "emac", "syscon"; interrupts = ; interrupt-names = "macirq"; - clocks = <&bus_gates 17>, <&emac_tx_clk>; - clock-names = "ahb", "tx"; - resets = <&ahb_reset 17>; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "ahb"; + resets = <&ccu RST_BUS_EMAC>; reset-names = "ahb"; status = "disabled"; #address-cells = <1>; @@ -248,16 +123,6 @@ }; &pio { - mmc2_8bit_pins: mmc2_8bit { - allwinner,pins = "PC5", "PC6", "PC8", - "PC9", "PC10", "PC11", - "PC12", "PC13", "PC14", - "PC15", "PC16"; - allwinner,function = "mmc2"; - allwinner,drive = ; - allwinner,pull = ; - }; - emac_pins_rgmii_a: emac_rgmii@0 { allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD11", "PD12", "PD13", "PD14", Index: sys/boot/fdt/dts/arm/sun8i-a83t.dtsi =================================================================== --- sys/boot/fdt/dts/arm/sun8i-a83t.dtsi +++ /dev/null @@ -1,510 +0,0 @@ -/* - * Copyright 2015 Vishnu Patekar - * - * Vishnu Patekar - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * $FreeBSD$ - */ - -#include "skeleton.dtsi" - -#include - -#include - -/ { - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - }; - - cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <1>; - }; - - cpu@2 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <2>; - }; - - cpu@3 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <3>; - }; - - cpu@100 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0x100>; - }; - - cpu@101 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0x101>; - }; - - cpu@102 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0x102>; - }; - - cpu@103 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0x103>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* TODO: PRCM block has a mux for this. */ - osc24M: osc24M_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - /* - * This is called "internal OSC" in some places. - * It is an internal RC-based oscillator. - * TODO: Its controls are in the PRCM block. - */ - osc16M: osc16M_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <16000000>; - clock-output-names = "osc16M"; - }; - - osc16Md512: osc16Md512_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <512>; - clock-mult = <1>; - clocks = <&osc16M>; - clock-output-names = "osc16M-d512"; - }; - - pll6: clk@01c20028 { - #clock-cells = <0>; - compatible = "allwinner,sun9i-a80-pll4-clk"; - reg = <0x01c20028 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll6"; - }; - - pll6d2: pll6d2_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <2>; - clock-mult = <1>; - clocks = <&pll6>; - clock-output-names = "pll6d2"; - }; - - ahb1: clk@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun8i-a83t-ahb1-clk"; - reg = <0x01c20054 0x4>; - clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&pll6>; - clock-output-names = "ahb1"; - }; - - apb1: apb1_clk@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun8i-a83t-apb1-clk"; - reg = <0x01c20054 0x4>; - clocks = <&ahb1>; - clock-output-names = "apb1"; - }; - - apb2: clk@01c20058 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb1-clk"; - reg = <0x01c20058 0x4>; - clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&pll6>; - clock-output-names = "apb2"; - }; - - ahb2: clk@01c2005c { - #clock-cells = <0>; - compatible = "allwinner,sun8i-h3-ahb2-clk"; - reg = <0x01c2005c 0x4>; - clocks = <&ahb1>, <&pll6d2>; - clock-output-names = "ahb2"; - }; - - bus_gates: clk@01c20060 { - #clock-cells = <1>; - compatible = "allwinner,sun8i-a83t-bus-gates-clk"; - reg = <0x01c20060 0x10>; - clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>; - clock-names = "ahb1", "ahb2", "apb1", "apb2"; - clock-indices = <1>, <5>, <6>, - <8>, <9>, <10>, - <13>, <14>, <17>, - <19>, <20>, - <21>, <24>, - <26>, <27>, - <29>, <32>, - <36>, <37>, - <40>, <43>, - <44>, <52>, <53>, - <54>, <65>, - <69>, <76>, <77>, - <78>, <79>, <96>, - <97>, <98>, - <112>, <113>, - <114>, <115>, - <116>; - clock-output-names = "bus_mipidsi", "bus_ss", "bus_dma", - "bus_mmc0", "bus_mmc1", "bus_mmc2", - "bus_nand", "bus_sdram", "bus_emac", - "bus_hstimer", "bus_spi0", - "bus_spi1", "bus_usb_otg", - "bus_ehci0", "bus_ehci1", - "bus_ohci0", "bus_ve", - "bus_lcd0", "bus_lcd1", - "bus_csi", "bus_hdmi", - "bus_de", "bus_gpu", "bus_msgbox", - "bus_spinlock", "bus_spdif", - "bus_pio", "bus_i2s0", "bus_i2s1", - "bus_i2s2", "bus_tdm", "bus_i2c0", - "bus_i2c1", "bus_i2c2", - "bus_uart0", "bus_uart1", - "bus_uart2", "bus_uart3", - "bus_uart4"; - }; - - mmc0_clk: clk@01c20088 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6>; - clock-output-names = "mmc0", - "mmc0_output", - "mmc0_sample"; - }; - - mmc1_clk: clk@01c2008c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c2008c 0x4>; - clocks = <&osc24M>, <&pll6>; - clock-output-names = "mmc1", - "mmc1_output", - "mmc1_sample"; - }; - - mmc2_clk: clk@01c20090 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20090 0x4>; - clocks = <&osc24M>, <&pll6>; - clock-output-names = "mmc2", - "mmc2_output", - "mmc2_sample"; - }; - - cpus_clk: clk@01f01400 { - compatible = "allwinner,sun9i-a80-cpus-clk"; - reg = <0x01f01400 0x4>; - #clock-cells = <0>; - clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&osc16M>; - clock-output-names = "cpus"; - }; - - ahb0: ahb0_clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clocks = <&cpus_clk>; - clock-output-names = "ahb0"; - }; - - apb0: clk@01f0140c { - compatible = "allwinner,sun8i-a23-apb0-clk"; - reg = <0x01f0140c 0x4>; - #clock-cells = <0>; - clocks = <&ahb0>; - clock-output-names = "apb0"; - }; - - apb0_gates: clk@01f01428 { - compatible = "allwinner,sun8i-a83t-apb0-gates-clk"; - reg = <0x01f01428 0x4>; - #clock-cells = <1>; - clocks = <&apb0>; - clock-indices = <0>, <1>, - <2>, <3>, - <4>, <6>, <7>; - clock-output-names = "apb0_pio", "apb0_ir", - "apb0_timer", "apb0_rsb", - "apb0_uart", "apb0_i2c0", "apb0_twd"; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mmc0: mmc@01c0f000 { - compatible = "allwinner,sun5i-a13-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&bus_gates 8>, - <&mmc0_clk 0>, - <&mmc0_clk 1>, - <&mmc0_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ahb_reset 8>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@01c10000 { - compatible = "allwinner,sun5i-a13-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&bus_gates 9>, - <&mmc1_clk 0>, - <&mmc1_clk 1>, - <&mmc1_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ahb_reset 9>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@01c11000 { - compatible = "allwinner,sun5i-a13-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&bus_gates 10>, - <&mmc2_clk 0>, - <&mmc2_clk 1>, - <&mmc2_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ahb_reset 10>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - pio: pinctrl@01c20800 { - compatible = "allwinner,sun8i-a83t-pinctrl"; - interrupts = , - , - ; - reg = <0x01c20800 0x400>; - clocks = <&bus_gates 69>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - mmc0_pins_a: mmc0@0 { - allwinner,pins = "PF0", "PF1", "PF2", - "PF3", "PF4", "PF5"; - allwinner,function = "mmc0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { - allwinner,pins = "PF6"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart0_pins_a: uart0@0 { - allwinner,pins = "PF2", "PF4"; - allwinner,function = "uart0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart0_pins_b: uart0@1 { - allwinner,pins = "PB9", "PB10"; - allwinner,function = "uart0"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; - - ahb_reset: reset@01c202c0 { - reg = <0x01c202c0 0xc>; - compatible = "allwinner,sun6i-a31-clock-reset"; - #reset-cells = <1>; - }; - - apb1_reset: reset@01c202d0 { - reg = <0x01c202d0 0x4>; - compatible = "allwinner,sun6i-a31-clock-reset"; - #reset-cells = <1>; - }; - - apb2_reset: reset@01c202d8 { - reg = <0x01c202d8 0x4>; - compatible = "allwinner,sun6i-a31-clock-reset"; - #reset-cells = <1>; - }; - - timer@01c20c00 { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x01c20c00 0xa0>; - interrupts = , - ; - clocks = <&osc24M>; - }; - - watchdog@01c20ca0 { - compatible = "allwinner,sun6i-a31-wdt"; - reg = <0x01c20ca0 0x20>; - interrupts = ; - clocks = <&osc24M>; - }; - - uart0: serial@01c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&bus_gates 112>; - resets = <&apb2_reset 16>; - status = "disabled"; - }; - - gic: interrupt-controller@01c81000 { - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; - reg = <0x01c81000 0x1000>, - <0x01c82000 0x1000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - }; - - apb0_reset: reset@01f014b0 { - reg = <0x01f014b0 0x4>; - compatible = "allwinner,sun6i-a31-clock-reset"; - #reset-cells = <1>; - }; - - r_pio: pinctrl@01f02c00 { - compatible = "allwinner,sun8i-a83t-r-pinctrl"; - reg = <0x01f02c00 0x400>; - interrupts = ; - clocks = <&apb0_gates 0>; - resets = <&apb0_reset 0>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - r_rsb_pins: r_rsb { - allwinner,pins = "PL0", "PL1"; - allwinner,function = "s_rsb"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; - - r_rsb: i2c@01f03400 { - compatible = "allwinner,sun8i-a23-rsb"; - reg = <0x01f03400 0x400>; - interrupts = ; - clocks = <&apb0_gates 3>; - clock-frequency = <3000000>; - resets = <&apb0_reset 3>; - pinctrl-names = "default"; - pinctrl-0 = <&r_rsb_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; Index: sys/conf/files.arm64 =================================================================== --- sys/conf/files.arm64 +++ sys/conf/files.arm64 @@ -42,6 +42,7 @@ arm/allwinner/clkng/aw_clk_nm.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_prediv_mux.c optional aw_ccu fdt arm/allwinner/clkng/ccu_a64.c optional aw_ccu fdt +arm/allwinner/clkng/ccu_a83t.c optional aw_ccu fdt arm/allwinner/clkng/ccu_h3.c optional aw_ccu fdt arm/allwinner/clkng/ccu_sun8i_r.c optional aw_ccu fdt Index: sys/gnu/dts/arm/sun8i-a83t.dtsi =================================================================== --- sys/gnu/dts/arm/sun8i-a83t.dtsi +++ sys/gnu/dts/arm/sun8i-a83t.dtsi @@ -47,6 +47,7 @@ #include #include #include +#include / { interrupt-parent = <&gic>; @@ -182,6 +183,141 @@ #dma-cells = <1>; }; + mmc0: mmc@1c0f000 { + compatible = "allwinner,sun8i-a83t-mmc", + "allwinner,sun7i-a20-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ccu CLK_BUS_MMC0>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@1c10000 { + compatible = "allwinner,sun8i-a83t-mmc", + "allwinner,sun7i-a20-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ccu CLK_BUS_MMC1>, + <&ccu CLK_MMC1>, + <&ccu CLK_MMC1_OUTPUT>, + <&ccu CLK_MMC1_SAMPLE>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@1c11000 { + compatible = "allwinner,sun8i-a83t-emmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ccu CLK_BUS_MMC2>, + <&ccu CLK_MMC2>, + <&ccu CLK_MMC2_OUTPUT>, + <&ccu CLK_MMC2_SAMPLE>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ccu RST_BUS_MMC2>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + usb_otg: usb@01c19000 { + compatible = "allwinner,sun8i-a83t-musb", + "allwinner,sun8i-a33-musb"; + reg = <0x01c19000 0x0400>; + clocks = <&ccu CLK_BUS_OTG>; + resets = <&ccu RST_BUS_OTG>; + interrupts = ; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + status = "disabled"; + }; + + usbphy: phy@1c19400 { + compatible = "allwinner,sun8i-a83t-usb-phy"; + reg = <0x01c19400 0x10>, + <0x01c1a800 0x14>, + <0x01c1b800 0x14>; + reg-names = "phy_ctrl", + "pmu1", + "pmu2"; + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>, + <&ccu CLK_USB_HSIC>, + <&ccu CLK_USB_HSIC_12M>; + clock-names = "usb0_phy", + "usb1_phy", + "usb2_phy", + "usb2_hsic_12M"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_HSIC>; + reset-names = "usb0_reset", + "usb1_reset", + "usb2_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci0: usb@1c1a000 { + compatible = "allwinner,sun8i-a83t-ehci", + "generic-ehci"; + reg = <0x01c1a000 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_EHCI0>; + resets = <&ccu RST_BUS_EHCI0>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@1c1a400 { + compatible = "allwinner,sun8i-a83t-ohci", + "generic-ohci"; + reg = <0x01c1a400 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_OHCI0>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci1: usb@1c1b000 { + compatible = "allwinner,sun8i-a83t-ehci", + "generic-ehci"; + reg = <0x01c1b000 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_EHCI1>; + resets = <&ccu RST_BUS_EHCI1>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + ccu: clock@1c20000 { compatible = "allwinner,sun8i-a83t-ccu"; reg = <0x01c20000 0x400>; @@ -212,6 +348,15 @@ bias-pull-up; }; + mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins { + pins = "PC5", "PC6", "PC8", "PC9", + "PC10", "PC11", "PC12", "PC13", + "PC14", "PC15", "PC16"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; + spdif_tx_pin: spdif-tx-pin { pins = "PE18"; function = "spdif"; @@ -281,6 +426,15 @@ interrupts = ; }; + r_intc: interrupt-controller@1f00c00 { + compatible = "allwinner,sun8i-a83t-r-intc", + "allwinner,sun6i-a31-r-intc"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01f00c00 0x400>; + interrupts = ; + }; + r_ccu: clock@1f01400 { compatible = "allwinner,sun8i-a83t-r-ccu"; reg = <0x01f01400 0x400>; @@ -302,6 +456,28 @@ #gpio-cells = <3>; interrupt-controller; #interrupt-cells = <3>; + + r_rsb_pins: r-rsb-pins { + pins = "PL0", "PL1"; + function = "s_rsb"; + drive-strength = <20>; + bias-pull-up; + }; + }; + + r_rsb: rsb@1f03400 { + compatible = "allwinner,sun8i-a83t-rsb", + "allwinner,sun8i-a23-rsb"; + reg = <0x01f03400 0x400>; + interrupts = ; + clocks = <&r_ccu CLK_APB0_RSB>; + clock-frequency = <3000000>; + resets = <&r_ccu RST_APB0_RSB>; + pinctrl-names = "default"; + pinctrl-0 = <&r_rsb_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; }; }; Index: sys/modules/dtb/allwinner/Makefile =================================================================== --- sys/modules/dtb/allwinner/Makefile +++ sys/modules/dtb/allwinner/Makefile @@ -3,6 +3,7 @@ DTS= \ nanopi-neo.dts \ orangepi-plus-2e.dts \ + sinovoip-bpi-m3.dts \ sun4i-a10-cubieboard.dts \ sun4i-a10-olinuxino-lime.dts \ sun6i-a31s-sinovoip-bpi-m2.dts \