Index: lib/clang/include/llvm/Config/AsmParsers.def =================================================================== --- lib/clang/include/llvm/Config/AsmParsers.def +++ lib/clang/include/llvm/Config/AsmParsers.def @@ -4,11 +4,35 @@ # error Please define the macro LLVM_ASM_PARSER(TargetName) #endif +#ifdef LLVM_TARGET_ENABLE_AARCH64 LLVM_ASM_PARSER(AArch64) +#endif +#ifdef LLVM_TARGET_ENABLE_AMDGPU +LLVM_ASM_PARSER(AMDGPU) +#endif +#ifdef LLVM_TARGET_ENABLE_ARM LLVM_ASM_PARSER(ARM) +#endif +#ifdef LLVM_TARGET_ENABLE_HEXAGON +LLVM_ASM_PARSER(Hexagon) +#endif +#ifdef LLVM_TARGET_ENABLE_LANAI +LLVM_ASM_PARSER(Lanai) +#endif +#ifdef LLVM_TARGET_ENABLE_MIPS LLVM_ASM_PARSER(Mips) +#endif +#ifdef LLVM_TARGET_ENABLE_POWERPC LLVM_ASM_PARSER(PowerPC) +#endif +#ifdef LLVM_TARGET_ENABLE_SPARC LLVM_ASM_PARSER(Sparc) +#endif +#ifdef LLVM_TARGET_ENABLE_SYSTEMZ +LLVM_ASM_PARSER(SystemZ) +#endif +#ifdef LLVM_TARGET_ENABLE_X86 LLVM_ASM_PARSER(X86) +#endif #undef LLVM_ASM_PARSER Index: lib/clang/include/llvm/Config/AsmPrinters.def =================================================================== --- lib/clang/include/llvm/Config/AsmPrinters.def +++ lib/clang/include/llvm/Config/AsmPrinters.def @@ -4,11 +4,47 @@ # error Please define the macro LLVM_ASM_PRINTER(TargetName) #endif +#ifdef LLVM_TARGET_ENABLE_AARCH64 LLVM_ASM_PRINTER(AArch64) +#endif +#ifdef LLVM_TARGET_ENABLE_AMDGPU +LLVM_ASM_PRINTER(AMDGPU) +#endif +#ifdef LLVM_TARGET_ENABLE_ARM LLVM_ASM_PRINTER(ARM) +#endif +#ifdef LLVM_TARGET_ENABLE_BPF +LLVM_ASM_PRINTER(BPF) +#endif +#ifdef LLVM_TARGET_ENABLE_HEXAGON +LLVM_ASM_PRINTER(Hexagon) +#endif +#ifdef LLVM_TARGET_ENABLE_LANAI +LLVM_ASM_PRINTER(Lanai) +#endif +#ifdef LLVM_TARGET_ENABLE_MIPS LLVM_ASM_PRINTER(Mips) +#endif +#ifdef LLVM_TARGET_ENABLE_MSP430 +LLVM_ASM_PRINTER(MSP430) +#endif +#ifdef LLVM_TARGET_ENABLE_NVPTX +LLVM_ASM_PRINTER(NVPTX) +#endif +#ifdef LLVM_TARGET_ENABLE_POWERPC LLVM_ASM_PRINTER(PowerPC) +#endif +#ifdef LLVM_TARGET_ENABLE_SPARC LLVM_ASM_PRINTER(Sparc) +#endif +#ifdef LLVM_TARGET_ENABLE_SYSTEMZ +LLVM_ASM_PRINTER(SystemZ) +#endif +#ifdef LLVM_TARGET_ENABLE_X86 LLVM_ASM_PRINTER(X86) +#endif +#ifdef LLVM_TARGET_ENABLE_XCORE +LLVM_ASM_PRINTER(XCore) +#endif #undef LLVM_ASM_PRINTER Index: lib/clang/include/llvm/Config/Disassemblers.def =================================================================== --- lib/clang/include/llvm/Config/Disassemblers.def +++ lib/clang/include/llvm/Config/Disassemblers.def @@ -4,11 +4,41 @@ # error Please define the macro LLVM_DISASSEMBLER(TargetName) #endif +#ifdef LLVM_TARGET_ENABLE_AARCH64 LLVM_DISASSEMBLER(AArch64) +#endif +#ifdef LLVM_TARGET_ENABLE_AMDGPU +LLVM_DISASSEMBLER(AMDGPU) +#endif +#ifdef LLVM_TARGET_ENABLE_ARM LLVM_DISASSEMBLER(ARM) +#endif +#ifdef LLVM_TARGET_ENABLE_BPF +LLVM_DISASSEMBLER(BPF) +#endif +#ifdef LLVM_TARGET_ENABLE_HEXAGON +LLVM_DISASSEMBLER(Hexagon) +#endif +#ifdef LLVM_TARGET_ENABLE_LANAI +LLVM_DISASSEMBLER(Lanai) +#endif +#ifdef LLVM_TARGET_ENABLE_MIPS LLVM_DISASSEMBLER(Mips) +#endif +#ifdef LLVM_TARGET_ENABLE_POWERPC LLVM_DISASSEMBLER(PowerPC) +#endif +#ifdef LLVM_TARGET_ENABLE_SPARC LLVM_DISASSEMBLER(Sparc) +#endif +#ifdef LLVM_TARGET_ENABLE_SYSTEMZ +LLVM_DISASSEMBLER(SystemZ) +#endif +#ifdef LLVM_TARGET_ENABLE_X86 LLVM_DISASSEMBLER(X86) +#endif +#ifdef LLVM_TARGET_ENABLE_XCORE +LLVM_DISASSEMBLER(XCore) +#endif #undef LLVM_DISASSEMBLER Index: lib/clang/include/llvm/Config/Targets.def =================================================================== --- lib/clang/include/llvm/Config/Targets.def +++ lib/clang/include/llvm/Config/Targets.def @@ -4,11 +4,50 @@ # error Please define the macro LLVM_TARGET(TargetName) #endif +#ifdef LLVM_TARGET_ENABLE_AARCH64 LLVM_TARGET(AArch64) +#endif +#ifdef LLVM_TARGET_ENABLE_AMDGPU +LLVM_TARGET(AMDGPU) +#endif +#ifdef LLVM_TARGET_ENABLE_ARM LLVM_TARGET(ARM) +#endif +#ifdef LLVM_TARGET_ENABLE_BPF +LLVM_TARGET(BPF) +#endif +#ifdef LLVM_TARGET_ENABLE_HEXAGON +LLVM_TARGET(Hexagon) +#endif +#ifdef LLVM_TARGET_ENABLE_LANAI +LLVM_TARGET(Lanai) +#endif +#ifdef LLVM_TARGET_ENABLE_MIPS LLVM_TARGET(Mips) +#endif +#ifdef LLVM_TARGET_ENABLE_MSP430 +LLVM_TARGET(MSP430) +#endif +#ifdef LLVM_TARGET_ENABLE_NVPTX +LLVM_TARGET(NVPTX) +#endif +#ifdef LLVM_TARGET_ENABLE_POWERPC LLVM_TARGET(PowerPC) +#endif +#ifdef LLVM_TARGET_ENABLE_RISCV +LLVM_TARGET(RISCV) +#endif +#ifdef LLVM_TARGET_ENABLE_SPARC LLVM_TARGET(Sparc) +#endif +#ifdef LLVM_TARGET_ENABLE_SYSTEMZ +LLVM_TARGET(SystemZ) +#endif +#ifdef LLVM_TARGET_ENABLE_X86 LLVM_TARGET(X86) +#endif +#ifdef LLVM_TARGET_ENABLE_XCORE +LLVM_TARGET(XCore) +#endif #undef LLVM_TARGET Index: lib/clang/include/llvm/Config/config.h =================================================================== --- lib/clang/include/llvm/Config/config.h +++ lib/clang/include/llvm/Config/config.h @@ -357,25 +357,25 @@ /* #undef LLVM_HOST_TRIPLE */ /* LLVM architecture name for the native architecture, if available */ -#define LLVM_NATIVE_ARCH X86 +/* #undef LLVM_NATIVE_ARCH */ /* LLVM name for the native AsmParser init function, if available */ -#define LLVM_NATIVE_ASMPARSER LLVMInitializeX86AsmParser +/* #undef LLVM_NATIVE_ASMPARSER */ /* LLVM name for the native AsmPrinter init function, if available */ -#define LLVM_NATIVE_ASMPRINTER LLVMInitializeX86AsmPrinter +/* #undef LLVM_NATIVE_ASMPRINTER */ /* LLVM name for the native Disassembler init function, if available */ -#define LLVM_NATIVE_DISASSEMBLER LLVMInitializeX86Disassembler +/* #undef LLVM_NATIVE_DISASSEMBLER */ /* LLVM name for the native Target init function, if available */ -#define LLVM_NATIVE_TARGET LLVMInitializeX86Target +/* #undef LLVM_NATIVE_TARGET */ /* LLVM name for the native TargetInfo init function, if available */ -#define LLVM_NATIVE_TARGETINFO LLVMInitializeX86TargetInfo +/* #undef LLVM_NATIVE_TARGETINFO */ /* LLVM name for the native target MC init function, if available */ -#define LLVM_NATIVE_TARGETMC LLVMInitializeX86TargetMC +/* #undef LLVM_NATIVE_TARGETMC */ /* Define if this is Unixish platform */ #define LLVM_ON_UNIX 1 Index: lib/clang/include/llvm/Config/llvm-config.h =================================================================== --- lib/clang/include/llvm/Config/llvm-config.h +++ lib/clang/include/llvm/Config/llvm-config.h @@ -31,25 +31,25 @@ /* #undef LLVM_HOST_TRIPLE */ /* LLVM architecture name for the native architecture, if available */ -#define LLVM_NATIVE_ARCH X86 +/* #undef LLVM_NATIVE_ARCH */ /* LLVM name for the native AsmParser init function, if available */ -#define LLVM_NATIVE_ASMPARSER LLVMInitializeX86AsmParser +/* #undef LLVM_NATIVE_ASMPARSER */ /* LLVM name for the native AsmPrinter init function, if available */ -#define LLVM_NATIVE_ASMPRINTER LLVMInitializeX86AsmPrinter +/* #undef LLVM_NATIVE_ASMPRINTER */ /* LLVM name for the native Disassembler init function, if available */ -#define LLVM_NATIVE_DISASSEMBLER LLVMInitializeX86Disassembler +/* #undef LLVM_NATIVE_DISASSEMBLER */ /* LLVM name for the native Target init function, if available */ -#define LLVM_NATIVE_TARGET LLVMInitializeX86Target +/* #undef LLVM_NATIVE_TARGET */ /* LLVM name for the native TargetInfo init function, if available */ -#define LLVM_NATIVE_TARGETINFO LLVMInitializeX86TargetInfo +/* #undef LLVM_NATIVE_TARGETINFO */ /* LLVM name for the native target MC init function, if available */ -#define LLVM_NATIVE_TARGETMC LLVMInitializeX86TargetMC +/* #undef LLVM_NATIVE_TARGETMC */ /* Define if this is Unixish platform */ #define LLVM_ON_UNIX 1 Index: lib/clang/libllvm/Makefile =================================================================== --- lib/clang/libllvm/Makefile +++ lib/clang/libllvm/Makefile @@ -7,9 +7,51 @@ INTERNALLIB= CFLAGS+= -I${.OBJDIR} -.for arch in AArch64 ARM Mips PowerPC Sparc X86 -CFLAGS+= -I${LLVM_SRCS}/lib/Target/${arch} -.endfor +.if ${MK_LLVM_TARGET_AARCH64} != "no" +CFLAGS+= -I${LLVM_SRCS}/lib/Target/AArch64 +.endif +.if ${MK_LLVM_TARGET_AMDGPU} != "no" +CFLAGS+= -I${LLVM_SRCS}/lib/Target/AMDGPU +.endif +.if ${MK_LLVM_TARGET_ARM} != "no" +CFLAGS+= -I${LLVM_SRCS}/lib/Target/ARM +.endif +.if ${MK_LLVM_TARGET_BPF} != "no" +CFLAGS+= -I${LLVM_SRCS}/lib/Target/BPF +.endif +.if ${MK_LLVM_TARGET_HEXAGON} != "no" +CFLAGS+= -I${LLVM_SRCS}/lib/Target/Hexagon +.endif +.if ${MK_LLVM_TARGET_LANAI} != "no" +CFLAGS+= -I${LLVM_SRCS}/lib/Target/Lanai +.endif +.if ${MK_LLVM_TARGET_MIPS} != "no" +CFLAGS+= -I${LLVM_SRCS}/lib/Target/Mips +.endif +.if ${MK_LLVM_TARGET_MSP430} != "no" +CFLAGS+= -I${LLVM_SRCS}/lib/Target/MSP430 +.endif +.if ${MK_LLVM_TARGET_NVPTX} != "no" +CFLAGS+= -I${LLVM_SRCS}/lib/Target/NVPTX +.endif +.if ${MK_LLVM_TARGET_POWERPC} != "no" +CFLAGS+= -I${LLVM_SRCS}/lib/Target/PowerPC +.endif +.if ${MK_LLVM_TARGET_RISCV} != "no" +CFLAGS+= -I${LLVM_SRCS}/lib/Target/RISCV +.endif +.if ${MK_LLVM_TARGET_SPARC} != "no" +CFLAGS+= -I${LLVM_SRCS}/lib/Target/Sparc +.endif +.if ${MK_LLVM_TARGET_SYSTEMZ} != "no" +CFLAGS+= -I${LLVM_SRCS}/lib/Target/SystemZ +.endif +.if ${MK_LLVM_TARGET_X86} != "no" +CFLAGS+= -I${LLVM_SRCS}/lib/Target/X86 +.endif +.if ${MK_LLVM_TARGET_XCORE} != "no" +CFLAGS+= -I${LLVM_SRCS}/lib/Target/XCore +.endif SRCDIR= lib @@ -700,6 +742,7 @@ SRCS_MIN+= TableGen/TGLexer.cpp SRCS_MIN+= TableGen/TGParser.cpp SRCS_MIN+= TableGen/TableGenBackend.cpp +.if ${MK_LLVM_TARGET_AARCH64} != "no" SRCS_MIN+= Target/AArch64/AArch64A53Fix835769.cpp SRCS_MIN+= Target/AArch64/AArch64A57FPLoadBalancing.cpp SRCS_MIN+= Target/AArch64/AArch64AddressTypePromotion.cpp @@ -744,6 +787,82 @@ SRCS_MIN+= Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp SRCS_MIN+= Target/AArch64/TargetInfo/AArch64TargetInfo.cpp SRCS_MIN+= Target/AArch64/Utils/AArch64BaseInfo.cpp +.endif # MK_LLVM_TARGET_AARCH64 +.if ${MK_LLVM_TARGET_AMDGPU} != "no" +SRCS_MIN+= Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp +SRCS_MIN+= Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp +SRCS_MIN+= Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp +SRCS_MIN+= Target/AMDGPU/AMDGPUAsmPrinter.cpp +SRCS_MIN+= Target/AMDGPU/AMDGPUCodeGenPrepare.cpp +SRCS_MIN+= Target/AMDGPU/AMDGPUFrameLowering.cpp +SRCS_MIN+= Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +SRCS_MIN+= Target/AMDGPU/AMDGPUISelLowering.cpp +SRCS_MIN+= Target/AMDGPU/AMDGPUInstrInfo.cpp +SRCS_MIN+= Target/AMDGPU/AMDGPUIntrinsicInfo.cpp +SRCS_MIN+= Target/AMDGPU/AMDGPUMCInstLower.cpp +SRCS_MIN+= Target/AMDGPU/AMDGPUMachineFunction.cpp +SRCS_MIN+= Target/AMDGPU/AMDGPUOpenCLImageTypeLoweringPass.cpp +SRCS_MIN+= Target/AMDGPU/AMDGPUPromoteAlloca.cpp +SRCS_MIN+= Target/AMDGPU/AMDGPURegisterInfo.cpp +SRCS_MIN+= Target/AMDGPU/AMDGPUSubtarget.cpp +SRCS_MIN+= Target/AMDGPU/AMDGPUTargetMachine.cpp +SRCS_MIN+= Target/AMDGPU/AMDGPUTargetObjectFile.cpp +SRCS_MIN+= Target/AMDGPU/AMDGPUTargetTransformInfo.cpp +SRCS_MIN+= Target/AMDGPU/AMDGPUUnifyMetadata.cpp +SRCS_MIN+= Target/AMDGPU/AMDILCFGStructurizer.cpp +SRCS_MIN+= Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +SRCS_XDW+= Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +SRCS_MIN+= Target/AMDGPU/GCNHazardRecognizer.cpp +SRCS_MIN+= Target/AMDGPU/GCNSchedStrategy.cpp +SRCS_MIN+= Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp +SRCS_MIN+= Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp +SRCS_MIN+= Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp +SRCS_MIN+= Target/AMDGPU/MCTargetDesc/AMDGPUELFStreamer.cpp +SRCS_MIN+= Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp +SRCS_MIN+= Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp +SRCS_MIN+= Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp +SRCS_MIN+= Target/AMDGPU/MCTargetDesc/AMDGPURuntimeMD.cpp +SRCS_MIN+= Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp +SRCS_MIN+= Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp +SRCS_MIN+= Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp +SRCS_MIN+= Target/AMDGPU/R600ClauseMergePass.cpp +SRCS_MIN+= Target/AMDGPU/R600ControlFlowFinalizer.cpp +SRCS_MIN+= Target/AMDGPU/R600EmitClauseMarkers.cpp +SRCS_MIN+= Target/AMDGPU/R600ExpandSpecialInstrs.cpp +SRCS_MIN+= Target/AMDGPU/R600FrameLowering.cpp +SRCS_MIN+= Target/AMDGPU/R600ISelLowering.cpp +SRCS_MIN+= Target/AMDGPU/R600InstrInfo.cpp +SRCS_MIN+= Target/AMDGPU/R600MachineFunctionInfo.cpp +SRCS_MIN+= Target/AMDGPU/R600MachineScheduler.cpp +SRCS_MIN+= Target/AMDGPU/R600OptimizeVectorRegisters.cpp +SRCS_MIN+= Target/AMDGPU/R600Packetizer.cpp +SRCS_MIN+= Target/AMDGPU/R600RegisterInfo.cpp +SRCS_MIN+= Target/AMDGPU/SIAnnotateControlFlow.cpp +SRCS_MIN+= Target/AMDGPU/SIDebuggerInsertNops.cpp +SRCS_MIN+= Target/AMDGPU/SIFixControlFlowLiveIntervals.cpp +SRCS_MIN+= Target/AMDGPU/SIFixSGPRCopies.cpp +SRCS_MIN+= Target/AMDGPU/SIFoldOperands.cpp +SRCS_MIN+= Target/AMDGPU/SIFrameLowering.cpp +SRCS_MIN+= Target/AMDGPU/SIISelLowering.cpp +SRCS_MIN+= Target/AMDGPU/SIInsertSkips.cpp +SRCS_MIN+= Target/AMDGPU/SIInsertWaits.cpp +SRCS_MIN+= Target/AMDGPU/SIInstrInfo.cpp +SRCS_MIN+= Target/AMDGPU/SILoadStoreOptimizer.cpp +SRCS_MIN+= Target/AMDGPU/SILowerControlFlow.cpp +SRCS_MIN+= Target/AMDGPU/SILowerI1Copies.cpp +SRCS_MIN+= Target/AMDGPU/SIMachineFunctionInfo.cpp +SRCS_MIN+= Target/AMDGPU/SIMachineScheduler.cpp +SRCS_MIN+= Target/AMDGPU/SIOptimizeExecMasking.cpp +SRCS_MIN+= Target/AMDGPU/SIRegisterInfo.cpp +SRCS_MIN+= Target/AMDGPU/SIShrinkInstructions.cpp +SRCS_MIN+= Target/AMDGPU/SITypeRewriter.cpp +SRCS_MIN+= Target/AMDGPU/SIWholeQuadMode.cpp +SRCS_MIN+= Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp +SRCS_MIN+= Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp +SRCS_MIN+= Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +SRCS_MIN+= Target/AMDGPU/Utils/AMDKernelCodeTUtils.cpp +.endif # MK_LLVM_TARGET_AMDGPU +.if ${MK_LLVM_TARGET_ARM} != "no" SRCS_MIN+= Target/ARM/A15SDOptimizer.cpp SRCS_MIN+= Target/ARM/ARMAsmPrinter.cpp SRCS_MIN+= Target/ARM/ARMBaseInstrInfo.cpp @@ -792,6 +911,117 @@ SRCS_MIN+= Target/ARM/Thumb2InstrInfo.cpp SRCS_MIN+= Target/ARM/Thumb2SizeReduction.cpp SRCS_MIN+= Target/ARM/ThumbRegisterInfo.cpp +.endif # MK_LLVM_TARGET_ARM +.if ${MK_LLVM_TARGET_BPF} != "no" +SRCS_MIN+= Target/BPF/BPFAsmPrinter.cpp +SRCS_MIN+= Target/BPF/BPFFrameLowering.cpp +SRCS_MIN+= Target/BPF/BPFISelDAGToDAG.cpp +SRCS_MIN+= Target/BPF/BPFISelLowering.cpp +SRCS_MIN+= Target/BPF/BPFInstrInfo.cpp +SRCS_MIN+= Target/BPF/BPFMCInstLower.cpp +SRCS_MIN+= Target/BPF/BPFRegisterInfo.cpp +SRCS_MIN+= Target/BPF/BPFSubtarget.cpp +SRCS_MIN+= Target/BPF/BPFTargetMachine.cpp +SRCS_XDW+= Target/BPF/Disassembler/BPFDisassembler.cpp +SRCS_MIN+= Target/BPF/InstPrinter/BPFInstPrinter.cpp +SRCS_MIN+= Target/BPF/MCTargetDesc/BPFAsmBackend.cpp +SRCS_MIN+= Target/BPF/MCTargetDesc/BPFELFObjectWriter.cpp +SRCS_MIN+= Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp +SRCS_MIN+= Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp +SRCS_MIN+= Target/BPF/TargetInfo/BPFTargetInfo.cpp +.endif # MK_LLVM_TARGET_BPF +.if ${MK_LLVM_TARGET_HEXAGON} != "no" +SRCS_MIN+= Target/Hexagon/AsmParser/HexagonAsmParser.cpp +SRCS_MIN+= Target/Hexagon/BitTracker.cpp +SRCS_XDW+= Target/Hexagon/Disassembler/HexagonDisassembler.cpp +SRCS_MIN+= Target/Hexagon/HexagonAsmPrinter.cpp +SRCS_MIN+= Target/Hexagon/HexagonBitSimplify.cpp +SRCS_MIN+= Target/Hexagon/HexagonBitTracker.cpp +SRCS_MIN+= Target/Hexagon/HexagonBlockRanges.cpp +SRCS_MIN+= Target/Hexagon/HexagonBranchRelaxation.cpp +SRCS_MIN+= Target/Hexagon/HexagonCFGOptimizer.cpp +SRCS_MIN+= Target/Hexagon/HexagonCommonGEP.cpp +SRCS_MIN+= Target/Hexagon/HexagonConstPropagation.cpp +SRCS_MIN+= Target/Hexagon/HexagonCopyToCombine.cpp +SRCS_MIN+= Target/Hexagon/HexagonEarlyIfConv.cpp +SRCS_MIN+= Target/Hexagon/HexagonExpandCondsets.cpp +SRCS_MIN+= Target/Hexagon/HexagonFixupHwLoops.cpp +SRCS_MIN+= Target/Hexagon/HexagonFrameLowering.cpp +SRCS_MIN+= Target/Hexagon/HexagonGenExtract.cpp +SRCS_MIN+= Target/Hexagon/HexagonGenInsert.cpp +SRCS_MIN+= Target/Hexagon/HexagonGenMux.cpp +SRCS_MIN+= Target/Hexagon/HexagonGenPredicate.cpp +SRCS_MIN+= Target/Hexagon/HexagonHardwareLoops.cpp +SRCS_MIN+= Target/Hexagon/HexagonHazardRecognizer.cpp +SRCS_MIN+= Target/Hexagon/HexagonISelDAGToDAG.cpp +SRCS_MIN+= Target/Hexagon/HexagonISelLowering.cpp +SRCS_MIN+= Target/Hexagon/HexagonInstrInfo.cpp +SRCS_MIN+= Target/Hexagon/HexagonMCInstLower.cpp +SRCS_MIN+= Target/Hexagon/HexagonMachineFunctionInfo.cpp +SRCS_MIN+= Target/Hexagon/HexagonMachineScheduler.cpp +SRCS_MIN+= Target/Hexagon/HexagonNewValueJump.cpp +SRCS_MIN+= Target/Hexagon/HexagonOptAddrMode.cpp +SRCS_MIN+= Target/Hexagon/HexagonOptimizeSZextends.cpp +SRCS_MIN+= Target/Hexagon/HexagonPeephole.cpp +SRCS_MIN+= Target/Hexagon/HexagonRDFOpt.cpp +SRCS_MIN+= Target/Hexagon/HexagonRegisterInfo.cpp +SRCS_MIN+= Target/Hexagon/HexagonSelectionDAGInfo.cpp +SRCS_MIN+= Target/Hexagon/HexagonSplitConst32AndConst64.cpp +SRCS_MIN+= Target/Hexagon/HexagonSplitDouble.cpp +SRCS_MIN+= Target/Hexagon/HexagonStoreWidening.cpp +SRCS_MIN+= Target/Hexagon/HexagonSubtarget.cpp +SRCS_MIN+= Target/Hexagon/HexagonTargetMachine.cpp +SRCS_MIN+= Target/Hexagon/HexagonTargetObjectFile.cpp +SRCS_MIN+= Target/Hexagon/HexagonTargetTransformInfo.cpp +SRCS_MIN+= Target/Hexagon/HexagonVLIWPacketizer.cpp +SRCS_MIN+= Target/Hexagon/HexagonVectorPrint.cpp +SRCS_MIN+= Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp +SRCS_MIN+= Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp +SRCS_MIN+= Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp +SRCS_MIN+= Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp +SRCS_MIN+= Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp +SRCS_MIN+= Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp +SRCS_MIN+= Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp +SRCS_MIN+= Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp +SRCS_MIN+= Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp +SRCS_MIN+= Target/Hexagon/MCTargetDesc/HexagonMCExpr.cpp +SRCS_MIN+= Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp +SRCS_MIN+= Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp +SRCS_MIN+= Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +SRCS_MIN+= Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp +SRCS_MIN+= Target/Hexagon/RDFCopy.cpp +SRCS_MIN+= Target/Hexagon/RDFDeadCode.cpp +SRCS_MIN+= Target/Hexagon/RDFGraph.cpp +SRCS_MIN+= Target/Hexagon/RDFLiveness.cpp +SRCS_MIN+= Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp +.endif # MK_LLVM_TARGET_HEXAGON +.if ${MK_LLVM_TARGET_LANAI} != "no" +SRCS_MIN+= Target/Lanai/AsmParser/LanaiAsmParser.cpp +SRCS_XDW+= Target/Lanai/Disassembler/LanaiDisassembler.cpp +SRCS_MIN+= Target/Lanai/InstPrinter/LanaiInstPrinter.cpp +SRCS_MIN+= Target/Lanai/LanaiAsmPrinter.cpp +SRCS_MIN+= Target/Lanai/LanaiDelaySlotFiller.cpp +SRCS_MIN+= Target/Lanai/LanaiFrameLowering.cpp +SRCS_MIN+= Target/Lanai/LanaiISelDAGToDAG.cpp +SRCS_MIN+= Target/Lanai/LanaiISelLowering.cpp +SRCS_MIN+= Target/Lanai/LanaiInstrInfo.cpp +SRCS_MIN+= Target/Lanai/LanaiMCInstLower.cpp +SRCS_MIN+= Target/Lanai/LanaiMachineFunctionInfo.cpp +SRCS_MIN+= Target/Lanai/LanaiMemAluCombiner.cpp +SRCS_MIN+= Target/Lanai/LanaiRegisterInfo.cpp +SRCS_MIN+= Target/Lanai/LanaiSelectionDAGInfo.cpp +SRCS_MIN+= Target/Lanai/LanaiSubtarget.cpp +SRCS_MIN+= Target/Lanai/LanaiTargetMachine.cpp +SRCS_MIN+= Target/Lanai/LanaiTargetObjectFile.cpp +SRCS_MIN+= Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp +SRCS_MIN+= Target/Lanai/MCTargetDesc/LanaiELFObjectWriter.cpp +SRCS_MIN+= Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.cpp +SRCS_MIN+= Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp +SRCS_MIN+= Target/Lanai/MCTargetDesc/LanaiMCExpr.cpp +SRCS_MIN+= Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp +SRCS_MIN+= Target/Lanai/TargetInfo/LanaiTargetInfo.cpp +.endif # MK_LLVM_TARGET_LANAI +.if ${MK_LLVM_TARGET_MIPS} != "no" SRCS_MIN+= Target/Mips/AsmParser/MipsAsmParser.cpp SRCS_XDW+= Target/Mips/Disassembler/MipsDisassembler.cpp SRCS_MIN+= Target/Mips/InstPrinter/MipsInstPrinter.cpp @@ -841,6 +1071,55 @@ SRCS_MIN+= Target/Mips/MipsTargetMachine.cpp SRCS_MIN+= Target/Mips/MipsTargetObjectFile.cpp SRCS_MIN+= Target/Mips/TargetInfo/MipsTargetInfo.cpp +.endif # MK_LLVM_TARGET_MIPS +.if ${MK_LLVM_TARGET_MSP430} != "no" +SRCS_MIN+= Target/MSP430/InstPrinter/MSP430InstPrinter.cpp +SRCS_MIN+= Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp +SRCS_MIN+= Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp +SRCS_MIN+= Target/MSP430/MSP430AsmPrinter.cpp +SRCS_MIN+= Target/MSP430/MSP430BranchSelector.cpp +SRCS_MIN+= Target/MSP430/MSP430FrameLowering.cpp +SRCS_MIN+= Target/MSP430/MSP430ISelDAGToDAG.cpp +SRCS_MIN+= Target/MSP430/MSP430ISelLowering.cpp +SRCS_MIN+= Target/MSP430/MSP430InstrInfo.cpp +SRCS_MIN+= Target/MSP430/MSP430MCInstLower.cpp +SRCS_MIN+= Target/MSP430/MSP430MachineFunctionInfo.cpp +SRCS_MIN+= Target/MSP430/MSP430RegisterInfo.cpp +SRCS_MIN+= Target/MSP430/MSP430Subtarget.cpp +SRCS_MIN+= Target/MSP430/MSP430TargetMachine.cpp +SRCS_MIN+= Target/MSP430/TargetInfo/MSP430TargetInfo.cpp +.endif # MK_LLVM_TARGET_MSP430 +.if ${MK_LLVM_TARGET_NVPTX} != "no" +SRCS_MIN+= Target/NVPTX/InstPrinter/NVPTXInstPrinter.cpp +SRCS_MIN+= Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp +SRCS_MIN+= Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp +SRCS_MIN+= Target/NVPTX/NVPTXAllocaHoisting.cpp +SRCS_MIN+= Target/NVPTX/NVPTXAsmPrinter.cpp +SRCS_MIN+= Target/NVPTX/NVPTXAssignValidGlobalNames.cpp +SRCS_MIN+= Target/NVPTX/NVPTXFrameLowering.cpp +SRCS_MIN+= Target/NVPTX/NVPTXGenericToNVVM.cpp +SRCS_MIN+= Target/NVPTX/NVPTXISelDAGToDAG.cpp +SRCS_MIN+= Target/NVPTX/NVPTXISelLowering.cpp +SRCS_MIN+= Target/NVPTX/NVPTXImageOptimizer.cpp +SRCS_MIN+= Target/NVPTX/NVPTXInferAddressSpaces.cpp +SRCS_MIN+= Target/NVPTX/NVPTXInstrInfo.cpp +SRCS_MIN+= Target/NVPTX/NVPTXLowerAggrCopies.cpp +SRCS_MIN+= Target/NVPTX/NVPTXLowerAlloca.cpp +SRCS_MIN+= Target/NVPTX/NVPTXLowerArgs.cpp +SRCS_MIN+= Target/NVPTX/NVPTXMCExpr.cpp +SRCS_MIN+= Target/NVPTX/NVPTXPeephole.cpp +SRCS_MIN+= Target/NVPTX/NVPTXPrologEpilogPass.cpp +SRCS_MIN+= Target/NVPTX/NVPTXRegisterInfo.cpp +SRCS_MIN+= Target/NVPTX/NVPTXReplaceImageHandles.cpp +SRCS_MIN+= Target/NVPTX/NVPTXSubtarget.cpp +SRCS_MIN+= Target/NVPTX/NVPTXTargetMachine.cpp +SRCS_MIN+= Target/NVPTX/NVPTXTargetTransformInfo.cpp +SRCS_MIN+= Target/NVPTX/NVPTXUtilities.cpp +SRCS_MIN+= Target/NVPTX/NVVMIntrRange.cpp +SRCS_MIN+= Target/NVPTX/NVVMReflect.cpp +SRCS_MIN+= Target/NVPTX/TargetInfo/NVPTXTargetInfo.cpp +.endif # MK_LLVM_TARGET_NVPTX +.if ${MK_LLVM_TARGET_POWERPC} != "no" SRCS_MIN+= Target/PowerPC/AsmParser/PPCAsmParser.cpp SRCS_MIN+= Target/PowerPC/Disassembler/PPCDisassembler.cpp SRCS_MIN+= Target/PowerPC/InstPrinter/PPCInstPrinter.cpp @@ -880,6 +1159,17 @@ SRCS_MIN+= Target/PowerPC/PPCVSXFMAMutate.cpp SRCS_MIN+= Target/PowerPC/PPCVSXSwapRemoval.cpp SRCS_MIN+= Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp +.endif # MK_LLVM_TARGET_POWERPC +.if ${MK_LLVM_TARGET_RISCV} != "no" +SRCS_MIN+= Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp +SRCS_MIN+= Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp +SRCS_MIN+= Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp +SRCS_MIN+= Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp +SRCS_MIN+= Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp +SRCS_MIN+= Target/RISCV/RISCVTargetMachine.cpp +SRCS_MIN+= Target/RISCV/TargetInfo/RISCVTargetInfo.cpp +.endif # MK_LLVM_TARGET_RISCV +.if ${MK_LLVM_TARGET_SPARC} != "no" SRCS_MIN+= Target/Sparc/AsmParser/SparcAsmParser.cpp SRCS_MIN+= Target/Sparc/DelaySlotFiller.cpp SRCS_XDW+= Target/Sparc/Disassembler/SparcDisassembler.cpp @@ -904,11 +1194,46 @@ SRCS_MIN+= Target/Sparc/SparcTargetMachine.cpp SRCS_MIN+= Target/Sparc/SparcTargetObjectFile.cpp SRCS_MIN+= Target/Sparc/TargetInfo/SparcTargetInfo.cpp +.endif # MK_LLVM_TARGET_SPARC +.if ${MK_LLVM_TARGET_SYSTEMZ} != "no" +SRCS_MIN+= Target/SystemZ/AsmParser/SystemZAsmParser.cpp +SRCS_XDW+= Target/SystemZ/Disassembler/SystemZDisassembler.cpp +SRCS_MIN+= Target/SystemZ/InstPrinter/SystemZInstPrinter.cpp +SRCS_MIN+= Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp +SRCS_MIN+= Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp +SRCS_MIN+= Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp +SRCS_MIN+= Target/SystemZ/MCTargetDesc/SystemZMCObjectWriter.cpp +SRCS_MIN+= Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp +SRCS_MIN+= Target/SystemZ/SystemZAsmPrinter.cpp +SRCS_MIN+= Target/SystemZ/SystemZCallingConv.cpp +SRCS_MIN+= Target/SystemZ/SystemZConstantPoolValue.cpp +SRCS_MIN+= Target/SystemZ/SystemZElimCompare.cpp +SRCS_MIN+= Target/SystemZ/SystemZExpandPseudo.cpp +SRCS_MIN+= Target/SystemZ/SystemZFrameLowering.cpp +SRCS_MIN+= Target/SystemZ/SystemZHazardRecognizer.cpp +SRCS_MIN+= Target/SystemZ/SystemZISelDAGToDAG.cpp +SRCS_MIN+= Target/SystemZ/SystemZISelLowering.cpp +SRCS_MIN+= Target/SystemZ/SystemZInstrInfo.cpp +SRCS_MIN+= Target/SystemZ/SystemZLDCleanup.cpp +SRCS_MIN+= Target/SystemZ/SystemZLongBranch.cpp +SRCS_MIN+= Target/SystemZ/SystemZMCInstLower.cpp +SRCS_MIN+= Target/SystemZ/SystemZMachineFunctionInfo.cpp +SRCS_MIN+= Target/SystemZ/SystemZMachineScheduler.cpp +SRCS_MIN+= Target/SystemZ/SystemZRegisterInfo.cpp +SRCS_MIN+= Target/SystemZ/SystemZSelectionDAGInfo.cpp +SRCS_MIN+= Target/SystemZ/SystemZShortenInst.cpp +SRCS_MIN+= Target/SystemZ/SystemZSubtarget.cpp +SRCS_MIN+= Target/SystemZ/SystemZTDC.cpp +SRCS_MIN+= Target/SystemZ/SystemZTargetMachine.cpp +SRCS_MIN+= Target/SystemZ/SystemZTargetTransformInfo.cpp +SRCS_MIN+= Target/SystemZ/TargetInfo/SystemZTargetInfo.cpp +.endif # MK_LLVM_TARGET_SYSTEMZ SRCS_MIN+= Target/Target.cpp SRCS_MIN+= Target/TargetIntrinsicInfo.cpp SRCS_MIN+= Target/TargetLoweringObjectFile.cpp SRCS_MIN+= Target/TargetMachine.cpp SRCS_MIN+= Target/TargetMachineC.cpp +.if ${MK_LLVM_TARGET_X86} != "no" SRCS_MIN+= Target/X86/AsmParser/X86AsmInstrumentation.cpp SRCS_MIN+= Target/X86/AsmParser/X86AsmParser.cpp SRCS_XDW+= Target/X86/Disassembler/X86Disassembler.cpp @@ -956,6 +1281,28 @@ SRCS_MIN+= Target/X86/X86VZeroUpper.cpp SRCS_MIN+= Target/X86/X86WinAllocaExpander.cpp SRCS_MIN+= Target/X86/X86WinEHState.cpp +.endif # MK_LLVM_TARGET_X86 +.if ${MK_LLVM_TARGET_XCORE} != "no" +SRCS_XDW+= Target/XCore/Disassembler/XCoreDisassembler.cpp +SRCS_MIN+= Target/XCore/InstPrinter/XCoreInstPrinter.cpp +SRCS_MIN+= Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp +SRCS_MIN+= Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp +SRCS_MIN+= Target/XCore/TargetInfo/XCoreTargetInfo.cpp +SRCS_MIN+= Target/XCore/XCoreAsmPrinter.cpp +SRCS_MIN+= Target/XCore/XCoreFrameLowering.cpp +SRCS_MIN+= Target/XCore/XCoreFrameToArgsOffsetElim.cpp +SRCS_MIN+= Target/XCore/XCoreISelDAGToDAG.cpp +SRCS_MIN+= Target/XCore/XCoreISelLowering.cpp +SRCS_MIN+= Target/XCore/XCoreInstrInfo.cpp +SRCS_MIN+= Target/XCore/XCoreLowerThreadLocal.cpp +SRCS_MIN+= Target/XCore/XCoreMCInstLower.cpp +SRCS_MIN+= Target/XCore/XCoreMachineFunctionInfo.cpp +SRCS_MIN+= Target/XCore/XCoreRegisterInfo.cpp +SRCS_MIN+= Target/XCore/XCoreSelectionDAGInfo.cpp +SRCS_MIN+= Target/XCore/XCoreSubtarget.cpp +SRCS_MIN+= Target/XCore/XCoreTargetMachine.cpp +SRCS_MIN+= Target/XCore/XCoreTargetObjectFile.cpp +.endif # MK_LLVM_TARGET_XCORE SRCS_MIN+= Transforms/Coroutines/CoroCleanup.cpp SRCS_MIN+= Transforms/Coroutines/CoroEarly.cpp SRCS_MIN+= Transforms/Coroutines/CoroElide.cpp @@ -1198,7 +1545,8 @@ # Note: some rules are superfluous, not every combination is valid. .for arch in \ - AArch64/AArch64 ARM/ARM Mips/Mips PowerPC/PPC Sparc/Sparc X86/X86 + AArch64 AMDGPU ARM BPF Hexagon Lanai Mips MSP430 NVPTX PowerPC RISCV \ + Sparc SystemZ X86 XCore . for hdr in \ AsmMatcher/-gen-asm-matcher \ AsmWriter1/-gen-asm-writer,-asmwriternum=1 \ @@ -1206,21 +1554,25 @@ CallingConv/-gen-callingconv \ CodeEmitter/-gen-emitter \ DAGISel/-gen-dag-isel \ + DFAPacketizer/-gen-dfa-packetizer \ DisassemblerTables/-gen-disassembler \ FastISel/-gen-fast-isel \ InstrInfo/-gen-instr-info \ + Intrinsics/-gen-tgt-intrinsic \ MCCodeEmitter/-gen-emitter \ MCPseudoLowering/-gen-pseudo-lowering \ RegisterInfo/-gen-register-info \ SubtargetInfo/-gen-subtarget \ SystemOperands/-gen-searchable-tables -${arch:T}Gen${hdr:H}.inc: ${LLVM_SRCS}/lib/Target/${arch:H}/${arch:T}.td +${arch:C/PowerPC/PPC/}Gen${hdr:H}.inc: \ + ${LLVM_SRCS}/lib/Target/${arch}/${arch:C/PowerPC/PPC/}.td ${LLVM_TBLGEN} ${hdr:T:C/,/ /g} \ - -I ${LLVM_SRCS}/include -I ${LLVM_SRCS}/lib/Target/${arch:H} \ + -I ${LLVM_SRCS}/include -I ${LLVM_SRCS}/lib/Target/${arch} \ -d ${.TARGET:C/$/.d/} -o ${.TARGET} \ - ${LLVM_SRCS}/lib/Target/${arch:H}/${arch:T}.td + ${LLVM_SRCS}/lib/Target/${arch}/${arch:C/PowerPC/PPC/}.td . endfor .endfor +.if ${MK_LLVM_TARGET_AARCH64} != "no" TGHDRS+= AArch64GenAsmMatcher.inc TGHDRS+= AArch64GenAsmWriter.inc TGHDRS+= AArch64GenAsmWriter1.inc @@ -1234,6 +1586,22 @@ TGHDRS+= AArch64GenRegisterInfo.inc TGHDRS+= AArch64GenSubtargetInfo.inc TGHDRS+= AArch64GenSystemOperands.inc +.endif # MK_LLVM_TARGET_AARCH64 +.if ${MK_LLVM_TARGET_AMDGPU} != "no" +TGHDRS+= AMDGPUGenAsmMatcher.inc +TGHDRS+= AMDGPUGenAsmWriter.inc +TGHDRS+= AMDGPUGenCallingConv.inc +TGHDRS+= AMDGPUGenDAGISel.inc +TGHDRS+= AMDGPUGenDFAPacketizer.inc +TGHDRS+= AMDGPUGenDisassemblerTables.inc +TGHDRS+= AMDGPUGenInstrInfo.inc +TGHDRS+= AMDGPUGenIntrinsics.inc +TGHDRS+= AMDGPUGenMCCodeEmitter.inc +TGHDRS+= AMDGPUGenMCPseudoLowering.inc +TGHDRS+= AMDGPUGenRegisterInfo.inc +TGHDRS+= AMDGPUGenSubtargetInfo.inc +.endif # MK_LLVM_TARGET_AMDGPU +.if ${MK_LLVM_TARGET_ARM} != "no" TGHDRS+= ARMGenAsmMatcher.inc TGHDRS+= ARMGenAsmWriter.inc TGHDRS+= ARMGenCallingConv.inc @@ -1245,6 +1613,40 @@ TGHDRS+= ARMGenMCPseudoLowering.inc TGHDRS+= ARMGenRegisterInfo.inc TGHDRS+= ARMGenSubtargetInfo.inc +.endif # MK_LLVM_TARGET_ARM +.if ${MK_LLVM_TARGET_BPF} != "no" +TGHDRS+= BPFGenAsmWriter.inc +TGHDRS+= BPFGenCallingConv.inc +TGHDRS+= BPFGenDAGISel.inc +TGHDRS+= BPFGenDisassemblerTables.inc +TGHDRS+= BPFGenInstrInfo.inc +TGHDRS+= BPFGenMCCodeEmitter.inc +TGHDRS+= BPFGenRegisterInfo.inc +TGHDRS+= BPFGenSubtargetInfo.inc +.endif # MK_LLVM_TARGET_BPF +.if ${MK_LLVM_TARGET_HEXAGON} != "no" +TGHDRS+= HexagonGenAsmMatcher.inc +TGHDRS+= HexagonGenAsmWriter.inc +TGHDRS+= HexagonGenDAGISel.inc +TGHDRS+= HexagonGenDFAPacketizer.inc +TGHDRS+= HexagonGenDisassemblerTables.inc +TGHDRS+= HexagonGenInstrInfo.inc +TGHDRS+= HexagonGenMCCodeEmitter.inc +TGHDRS+= HexagonGenRegisterInfo.inc +TGHDRS+= HexagonGenSubtargetInfo.inc +.endif # MK_LLVM_TARGET_HEXAGON +.if ${MK_LLVM_TARGET_LANAI} != "no" +TGHDRS+= LanaiGenAsmMatcher.inc +TGHDRS+= LanaiGenAsmWriter.inc +TGHDRS+= LanaiGenCallingConv.inc +TGHDRS+= LanaiGenDAGISel.inc +TGHDRS+= LanaiGenDisassemblerTables.inc +TGHDRS+= LanaiGenInstrInfo.inc +TGHDRS+= LanaiGenMCCodeEmitter.inc +TGHDRS+= LanaiGenRegisterInfo.inc +TGHDRS+= LanaiGenSubtargetInfo.inc +.endif # MK_LLVM_TARGET_LANAI +.if ${MK_LLVM_TARGET_MIPS} != "no" TGHDRS+= MipsGenAsmMatcher.inc TGHDRS+= MipsGenAsmWriter.inc TGHDRS+= MipsGenCallingConv.inc @@ -1256,6 +1658,23 @@ TGHDRS+= MipsGenMCPseudoLowering.inc TGHDRS+= MipsGenRegisterInfo.inc TGHDRS+= MipsGenSubtargetInfo.inc +.endif # MK_LLVM_TARGET_MIPS +.if ${MK_LLVM_TARGET_MSP430} != "no" +TGHDRS+= MSP430GenAsmWriter.inc +TGHDRS+= MSP430GenCallingConv.inc +TGHDRS+= MSP430GenDAGISel.inc +TGHDRS+= MSP430GenInstrInfo.inc +TGHDRS+= MSP430GenRegisterInfo.inc +TGHDRS+= MSP430GenSubtargetInfo.inc +.endif # MK_LLVM_TARGET_MSP430 +.if ${MK_LLVM_TARGET_NVPTX} != "no" +TGHDRS+= NVPTXGenAsmWriter.inc +TGHDRS+= NVPTXGenDAGISel.inc +TGHDRS+= NVPTXGenInstrInfo.inc +TGHDRS+= NVPTXGenRegisterInfo.inc +TGHDRS+= NVPTXGenSubtargetInfo.inc +.endif # MK_LLVM_TARGET_NVPTX +.if ${MK_LLVM_TARGET_POWERPC} != "no" TGHDRS+= PPCGenAsmMatcher.inc TGHDRS+= PPCGenAsmWriter.inc TGHDRS+= PPCGenCallingConv.inc @@ -1266,6 +1685,13 @@ TGHDRS+= PPCGenMCCodeEmitter.inc TGHDRS+= PPCGenRegisterInfo.inc TGHDRS+= PPCGenSubtargetInfo.inc +.endif # MK_LLVM_TARGET_POWERPC +.if ${MK_LLVM_TARGET_RISCV} != "no" +TGHDRS+= RISCVGenInstrInfo.inc +TGHDRS+= RISCVGenMCCodeEmitter.inc +TGHDRS+= RISCVGenRegisterInfo.inc +.endif # MK_LLVM_TARGET_RISCV +.if ${MK_LLVM_TARGET_SPARC} != "no" TGHDRS+= SparcGenAsmMatcher.inc TGHDRS+= SparcGenAsmWriter.inc TGHDRS+= SparcGenCallingConv.inc @@ -1275,6 +1701,19 @@ TGHDRS+= SparcGenMCCodeEmitter.inc TGHDRS+= SparcGenRegisterInfo.inc TGHDRS+= SparcGenSubtargetInfo.inc +.endif # MK_LLVM_TARGET_SPARC +.if ${MK_LLVM_TARGET_SYSTEMZ} != "no" +TGHDRS+= SystemZGenAsmMatcher.inc +TGHDRS+= SystemZGenAsmWriter.inc +TGHDRS+= SystemZGenCallingConv.inc +TGHDRS+= SystemZGenDAGISel.inc +TGHDRS+= SystemZGenDisassemblerTables.inc +TGHDRS+= SystemZGenInstrInfo.inc +TGHDRS+= SystemZGenMCCodeEmitter.inc +TGHDRS+= SystemZGenRegisterInfo.inc +TGHDRS+= SystemZGenSubtargetInfo.inc +.endif # MK_LLVM_TARGET_SYSTEMZ +.if ${MK_LLVM_TARGET_X86} != "no" TGHDRS+= X86GenAsmMatcher.inc TGHDRS+= X86GenAsmWriter.inc TGHDRS+= X86GenAsmWriter1.inc @@ -1285,6 +1724,16 @@ TGHDRS+= X86GenInstrInfo.inc TGHDRS+= X86GenRegisterInfo.inc TGHDRS+= X86GenSubtargetInfo.inc +.endif # MK_LLVM_TARGET_X86 +.if ${MK_LLVM_TARGET_XCORE} != "no" +TGHDRS+= XCoreGenAsmWriter.inc +TGHDRS+= XCoreGenCallingConv.inc +TGHDRS+= XCoreGenDAGISel.inc +TGHDRS+= XCoreGenDisassemblerTables.inc +TGHDRS+= XCoreGenInstrInfo.inc +TGHDRS+= XCoreGenRegisterInfo.inc +TGHDRS+= XCoreGenSubtargetInfo.inc +.endif # MK_LLVM_TARGET_XCORE .for dep in ${TGHDRS:C/$/.d/} . if ${MAKE_VERSION} < 20160220 Index: lib/clang/llvm.build.mk =================================================================== --- lib/clang/llvm.build.mk +++ lib/clang/llvm.build.mk @@ -1,5 +1,7 @@ # $FreeBSD$ +.include + .ifndef LLVM_SRCS .error Please define LLVM_SRCS before including this file .endif @@ -41,6 +43,82 @@ CFLAGS+= -DLLVM_HOST_TRIPLE=\"${BUILD_TRIPLE}\" CFLAGS+= -DDEFAULT_SYSROOT=\"${TOOLS_PREFIX}\" +.if ${MK_LLVM_TARGET_AARCH64} != "no" +CFLAGS+= -DLLVM_TARGET_ENABLE_AARCH64 +. if ${MACHINE_CPUARCH} == "aarch64" +LLVM_NATIVE_ARCH= AArch64 +. endif +.endif +.if ${MK_LLVM_TARGET_AMDGPU} != "no" +CFLAGS+= -DLLVM_TARGET_ENABLE_AMDGPU +.endif +.if ${MK_LLVM_TARGET_ARM} != "no" +CFLAGS+= -DLLVM_TARGET_ENABLE_ARM +. if ${MACHINE_CPUARCH} == "arm" +LLVM_NATIVE_ARCH= ARM +. endif +.endif +.if ${MK_LLVM_TARGET_BPF} != "no" +CFLAGS+= -DLLVM_TARGET_ENABLE_BPF +.endif +.if ${MK_LLVM_TARGET_HEXAGON} != "no" +CFLAGS+= -DLLVM_TARGET_ENABLE_HEXAGON +.endif +.if ${MK_LLVM_TARGET_LANAI} != "no" +CFLAGS+= -DLLVM_TARGET_ENABLE_LANAI +.endif +.if ${MK_LLVM_TARGET_MIPS} != "no" +CFLAGS+= -DLLVM_TARGET_ENABLE_MIPS +. if ${MACHINE_CPUARCH} == "mips" +LLVM_NATIVE_ARCH= Mips +. endif +.endif +.if ${MK_LLVM_TARGET_MSP430} != "no" +CFLAGS+= -DLLVM_TARGET_ENABLE_MSP430 +.endif +.if ${MK_LLVM_TARGET_NVPTX} != "no" +CFLAGS+= -DLLVM_TARGET_ENABLE_NVPTX +.endif +.if ${MK_LLVM_TARGET_POWERPC} != "no" +CFLAGS+= -DLLVM_TARGET_ENABLE_POWERPC +. if ${MACHINE_CPUARCH} == "powerpc" +LLVM_NATIVE_ARCH= PowerPC +. endif +.endif +.if ${MK_LLVM_TARGET_RISCV} != "no" +CFLAGS+= -DLLVM_TARGET_ENABLE_RISCV +. if ${MACHINE_CPUARCH} == "riscv" +LLVM_NATIVE_ARCH= RISCV +. endif +.endif +.if ${MK_LLVM_TARGET_SPARC} != "no" +CFLAGS+= -DLLVM_TARGET_ENABLE_SPARC +. if ${MACHINE_CPUARCH} == "sparc64" +LLVM_NATIVE_ARCH= Sparc +. endif +.endif +.if ${MK_LLVM_TARGET_SYSTEMZ} != "no" +CFLAGS+= -DLLVM_TARGET_ENABLE_SYSTEMZ +.endif +.if ${MK_LLVM_TARGET_X86} != "no" +CFLAGS+= -DLLVM_TARGET_ENABLE_X86 +. if ${MACHINE_CPUARCH} == "i386" || ${MACHINE_CPUARCH} == "amd64" +LLVM_NATIVE_ARCH= X86 +. endif +.endif +.if ${MK_LLVM_TARGET_XCORE} != "no" +CFLAGS+= -DLLVM_TARGET_ENABLE_XCORE +.endif + +.ifdef LLVM_NATIVE_ARCH +CFLAGS+= -DLLVM_NATIVE_ASMPARSER=LLVMInitialize${LLVM_NATIVE_ARCH}AsmParser +CFLAGS+= -DLLVM_NATIVE_ASMPRINTER=LLVMInitialize${LLVM_NATIVE_ARCH}AsmPrinter +CFLAGS+= -DLLVM_NATIVE_DISASSEMBLER=LLVMInitialize${LLVM_NATIVE_ARCH}Disassembler +CFLAGS+= -DLLVM_NATIVE_TARGET=LLVMInitialize${LLVM_NATIVE_ARCH}Target +CFLAGS+= -DLLVM_NATIVE_TARGETINFO=LLVMInitialize${LLVM_NATIVE_ARCH}TargetInfo +CFLAGS+= -DLLVM_NATIVE_TARGETMC=LLVMInitialize${LLVM_NATIVE_ARCH}TargetMC +.endif + CFLAGS+= -ffunction-sections CFLAGS+= -fdata-sections LDFLAGS+= -Wl,--gc-sections Index: share/mk/src.opts.mk =================================================================== --- share/mk/src.opts.mk +++ share/mk/src.opts.mk @@ -222,18 +222,28 @@ ${__T} == "amd64" || ${__TT} == "arm" || ${__T} == "i386") # Clang is enabled, and will be installed as the default /usr/bin/cc. __DEFAULT_YES_OPTIONS+=CLANG CLANG_BOOTSTRAP CLANG_FULL CLANG_IS_CC LLD +__DEFAULT_YES_OPTIONS+=LLVM_TARGET_AARCH64 LLVM_TARGET_ARM LLVM_TARGET_MIPS +__DEFAULT_YES_OPTIONS+=LLVM_TARGET_POWERPC LLVM_TARGET_SPARC LLVM_TARGET_X86 __DEFAULT_NO_OPTIONS+=GCC GCC_BOOTSTRAP GNUCXX .elif ${COMPILER_FEATURES:Mc++11} && ${__T} != "riscv64" && ${__T} != "sparc64" # If an external compiler that supports C++11 is used as ${CC} and Clang # supports the target, then Clang is enabled but GCC is installed as the # default /usr/bin/cc. __DEFAULT_YES_OPTIONS+=CLANG CLANG_FULL GCC GCC_BOOTSTRAP GNUCXX +__DEFAULT_YES_OPTIONS+=LLVM_TARGET_AARCH64 LLVM_TARGET_ARM LLVM_TARGET_MIPS +__DEFAULT_YES_OPTIONS+=LLVM_TARGET_POWERPC LLVM_TARGET_SPARC LLVM_TARGET_X86 __DEFAULT_NO_OPTIONS+=CLANG_BOOTSTRAP CLANG_IS_CC LLD .else # Everything else disables Clang, and uses GCC instead. __DEFAULT_YES_OPTIONS+=GCC GCC_BOOTSTRAP GNUCXX __DEFAULT_NO_OPTIONS+=CLANG CLANG_BOOTSTRAP CLANG_FULL CLANG_IS_CC LLD +__DEFAULT_NO_OPTIONS+=LLVM_TARGET_AARCH64 LLVM_TARGET_ARM LLVM_TARGET_MIPS +__DEFAULT_NO_OPTIONS+=LLVM_TARGET_POWERPC LLVM_TARGET_SPARC LLVM_TARGET_X86 .endif +# Other LLVM targets, disabled by default. +__DEFAULT_YES_OPTIONS+=LLVM_TARGET_AMDGPU LLVM_TARGET_BPF LLVM_TARGET_HEXAGON +__DEFAULT_YES_OPTIONS+=LLVM_TARGET_LANAI LLVM_TARGET_MSP430 LLVM_TARGET_NVPTX +__DEFAULT_YES_OPTIONS+=LLVM_TARGET_RISCV LLVM_TARGET_SYSTEMZ LLVM_TARGET_XCORE # In-tree binutils/gcc are older versions without modern architecture support. .if ${__T} == "aarch64" || ${__T:Mriscv*} != "" BROKEN_OPTIONS+=BINUTILS BINUTILS_BOOTSTRAP GCC GCC_BOOTSTRAP GDB