Index: sys/dev/bhnd/cores/chipc/chipcreg.h
===================================================================
--- sys/dev/bhnd/cores/chipc/chipcreg.h
+++ sys/dev/bhnd/cores/chipc/chipcreg.h
@@ -280,7 +280,7 @@
 #define	CHIPC_PLL_TYPE1		0x2	/* 48MHz base, 3 dividers */
 #define	CHIPC_PLL_TYPE2		0x4	/* 48MHz, 4 dividers */
 #define	CHIPC_PLL_TYPE3		0x6	/* 25MHz, 2 dividers */
-#define	CHIPC_PLL_TYPE4		0x8	/* 48MHz, 4 dividers */
+#define	CHIPC_PLL_TYPE4		0x1	/* 48MHz, 4 dividers */
 #define	CHIPC_PLL_TYPE5		0x3	/* 25MHz, 4 dividers */
 #define	CHIPC_PLL_TYPE6		0x5	/* 100/200 or 120/240 only */
 #define	CHIPC_PLL_TYPE7		0x7	/* 25MHz, 4 dividers */
Index: sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c
===================================================================
--- sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c
+++ sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c
@@ -374,7 +374,7 @@
 	} else if (PWRCTL_QUIRK(sc, SLOWCLK_CTL)) {
 		div = bhnd_bus_read_4(sc->res, CHIPC_PLL_SLOWCLK_CTL);
 		div = CHIPC_GET_BITS(div, CHIPC_SCC_CD);
-		div *= 4;
+		div = 4 * (div + 1);
 	} else if (PWRCTL_QUIRK(sc, INSTACLK_CTL)) {
 		if (max_freq) {
 			div = 1;