Change Details

While version 2 adds the SITEs to enable to TMSR in bits 0..<n>, version 1 (e.g., LS1028, LS1046, LS1088) add MSITEs to TMR bits 16..31 or rather 15..0(16-<n>). While we assume we enable all available sites and they are contiguous we can just shift the sites bitfield up to the right start (still in opposite order). MFC after: 2 weeks

For version 2 extend the TMUV2_TMSAR() write loop over all site_ids registered for a particular SoC and actually use the site_id rather than always just the first [0] (which for the LX2080 would be a problem given there is no site0). Later, while version 2 adds the SITEs to enable to TMSR in bits 0..<n>, version 1 (e.g., LS1028, LS1046, LS1088) add MSITEs to TMR bits 16..31 or rather 15..0(16-<n>). Adjust the loops to only enable the site_ids listed for the particular SoC for monitoring. This now also deals with sparse site_ids (not starting at 0, or not being contiguous). MFC after: 2 weeks

WhileFor version 2 addsextend the SITEs to enable to TMSR in bits 0..<n>,TMUV2_TMSAR() write loop over all site_ids registered for a particular SoC and actually use the site_id rather than always just the first [0] (which for the LX2080 would be a problem given there is no site0). Later, while version 2 adds the SITEs to enable to TMSR in bits 0..<n>, version 1 (e.g., LS1028, LS1046, LS1088) add MSITEs to TMR bits 16..31 or rather 15..0(16-<n>). While we assume we enable all available sites and they are contiguous Adjust the loops to only enable we can just shift the sites bitfield up to the right start (still inthe site_ids listed for the particular SoC for monitoring. This now opposite orderalso deals with sparse site_ids (not starting at 0, or not being contiguous). MFC after: 2 weeks