diff --git a/sys/arm/nvidia/tegra124/tegra124_clk_per.c b/sys/arm/nvidia/tegra124/tegra124_clk_per.c index 4d68e8b22daf..b555a15786a4 100644 --- a/sys/arm/nvidia/tegra124/tegra124_clk_per.c +++ b/sys/arm/nvidia/tegra124/tegra124_clk_per.c @@ -1,825 +1,844 @@ /*- * Copyright (c) 2016 Michal Meloun * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include "tegra124_car.h" /* The TEGRA124_CLK_XUSB_GATE is missing in current * DT bindings, define it localy */ #ifdef TEGRA124_CLK_XUSB_GATE #error "TEGRA124_CLK_XUSB_GATE is now defined, revisit XUSB code!" #else #define TEGRA124_CLK_XUSB_GATE 143 #endif /* Bits in base register. */ #define PERLCK_AMUX_MASK 0x0F #define PERLCK_AMUX_SHIFT 16 #define PERLCK_AMUX_DIS (1 << 20) #define PERLCK_UDIV_DIS (1 << 24) #define PERLCK_ENA_MASK (1 << 28) #define PERLCK_MUX_SHIFT 29 #define PERLCK_MUX_MASK 0x07 struct periph_def { struct clknode_init_def clkdef; uint32_t base_reg; uint32_t div_width; uint32_t div_mask; uint32_t div_f_width; uint32_t div_f_mask; uint32_t flags; }; struct pgate_def { struct clknode_init_def clkdef; uint32_t idx; uint32_t flags; }; #define PLIST(x) static const char *x[] #define GATE(_id, cname, plist, _idx) \ { \ .clkdef.id = TEGRA124_CLK_##_id, \ .clkdef.name = cname, \ .clkdef.parent_names = (const char *[]){plist}, \ .clkdef.parent_cnt = 1, \ .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ .idx = _idx, \ .flags = 0, \ } /* Sources for multiplexors. */ PLIST(mux_a_N_audio_N_p_N_clkm) = {"pllA_out0", NULL, "audio", NULL, "pllP_out0", NULL, "clk_m"}; PLIST(mux_a_N_audio0_N_p_N_clkm) = {"pllA_out0", NULL, "audio0", NULL, "pllP_out0", NULL, "clk_m"}; PLIST(mux_a_N_audio1_N_p_N_clkm) = {"pllA_out0", NULL, "audio1", NULL, "pllP_out0", NULL, "clk_m"}; PLIST(mux_a_N_audio2_N_p_N_clkm) = {"pllA_out0", NULL, "audio2", NULL, "pllP_out0", NULL, "clk_m"}; PLIST(mux_a_N_audio3_N_p_N_clkm) = {"pllA_out0", NULL, "audio3", NULL, "pllP_out0", NULL, "clk_m"}; PLIST(mux_a_N_audio4_N_p_N_clkm) = {"pllA_out0", NULL, "audio4", NULL, "pllP_out0", NULL, "clk_m"}; PLIST(mux_a_clks_p_clkm_e) = {"pllA_out0", "clk_s", "pllP_out0", "clk_m", "pllE_out0"}; PLIST(mux_a_c2_c_c3_p_N_clkm) = {"pllA_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", "pllP_out0", NULL, "clk_m"}; PLIST(mux_m_c_p_a_c2_c3) = {"pllM_out0", "pllC_out0", "pllP_out0", "pllA_out0", "pllC2_out0", "pllC3_out0"}; PLIST(mux_m_c_p_a_c2_c3_clkm) = {"pllM_out0", "pllC_out0", "pllP_out0", "pllA_out0", "pllC2_out0", "pllC3_out0", "clk_m"}; PLIST(mux_m_c_p_a_c2_c3_clkm_c4) = {"pllM_out0", "pllC_out0", "pllP_out0", "pllA_out0", "pllC2_out0", "pllC3_out0", "clk_m", "pllC4_out0"}; PLIST(mux_m_c_p_clkm_mud_c2_c3) = {"pllM_out0", "pllC_out0", "pllP_out0", "clk_m", "pllM_UD", "pllC2_out0", "pllC3_out0"}; PLIST(mux_m_c_p_clkm_mud_c2_c3_cud) = {"pllM_out0", "pllC_out0", "pllP_out0", "clk_m", "pllM_UD", "pllC2_out0", "pllC3_out0", "pllC_UD"}; PLIST(mux_m_c2_c_c3_p_N_a) = {"pllM_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", "pllP_out0", NULL, "pllA_out0"}; PLIST(mux_m_c2_c_c3_p_N_a_c4) = {"pllM_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", NULL, "pllA_out0", "pllC4_out0"}; PLIST(mux_p_N_c_N_N_N_clkm) = {"pllP_out0", NULL, "pllC_out0", NULL, NULL, NULL, "clk_m"}; PLIST(mux_p_N_c_N_m_N_clkm) = {"pllP_out0", NULL, "pllC_out0", NULL, "pllM_out0", NULL, "clk_m"}; PLIST(mux_p_c_c2_clkm) = {"pllP_out0", "pllC_out0", "pllC2_out0", "clk_m"}; PLIST(mux_p_c2_c_c3_m) = {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", "pllM_out0"}; PLIST(mux_p_c2_c_c3_m_N_clkm) = {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", "pllM_out0", NULL, "clk_m"}; PLIST(mux_p_c2_c_c3_m_e_clkm) = {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", "pllM_out0", "pllE_out0", "clk_m"}; PLIST(mux_p_c2_c_c3_m_a_clkm) = {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", "pllM_out0", "pllA_out0", "clk_m"}; PLIST(mux_p_c2_c_c3_m_clks_clkm) = {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", "pllM_out0", "clk_s", "clk_m"}; PLIST(mux_p_c2_c_c3_clks_N_clkm) = {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", "clk_s", NULL, "clk_m"}; PLIST(mux_p_c2_c_c3_clkm_N_clks) = {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", "clk_m", NULL, "clk_s"}; PLIST(mux_p_clkm_clks_E) = {"pllP_out0", "clk_m", "clk_s", "pllE_out0"}; PLIST(mux_p_m_d_a_c_d2_clkm) = {"pllP_out0", "pllM_out0", "pllD_out0", "pllA_out0", "pllC_out0", "pllD2_out0", "clk_m"}; PLIST(mux_clkm_N_u48_N_p_N_u480) = {"clk_m", NULL, "pllU_48", NULL, "pllP_out0", NULL, "pllU_480"}; PLIST(mux_clkm_p_c2_c_c3_refre) = {"clk_m", "pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", "pllREFE_out"}; PLIST(mux_clkm_refe_clks_u480_c_c2_c3_oscdiv) = {"clk_m", "pllREFE_out", "clk_s", "pllU_480", "pllC_out0", "pllC2_out0", "pllC3_out0", "osc_div_clk"}; PLIST(mux_sep_audio) = {"pllA_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", "pllP_out0", NULL, "clk_m", NULL, "spdif_in", "i2s0", "i2s1", "i2s2", "i2s4", "pllA_out0", "ext_vimclk"}; static uint32_t clk_enable_reg[] = { CLK_OUT_ENB_L, CLK_OUT_ENB_H, CLK_OUT_ENB_U, CLK_OUT_ENB_V, CLK_OUT_ENB_W, CLK_OUT_ENB_X, }; static uint32_t clk_reset_reg[] = { RST_DEVICES_L, RST_DEVICES_H, RST_DEVICES_U, RST_DEVICES_V, RST_DEVICES_W, RST_DEVICES_X, }; #define L(n) ((0 * 32) + (n)) #define H(n) ((1 * 32) + (n)) #define U(n) ((2 * 32) + (n)) #define V(n) ((3 * 32) + (n)) #define W(n) ((4 * 32) + (n)) #define X(n) ((5 * 32) + (n)) static struct pgate_def pgate_def[] = { /* bank L -> 0-31 */ /* GATE(CPU, "cpu", "clk_m", L(0)), */ GATE(ISPB, "ispb", "clk_m", L(3)), GATE(RTC, "rtc", "clk_s", L(4)), GATE(TIMER, "timer", "clk_m", L(5)), GATE(UARTA, "uarta", "pc_uarta" , L(6)), GATE(UARTB, "uartb", "pc_uartb", L(7)), GATE(VFIR, "vfir", "pc_vfir", L(7)), /* GATE(GPIO, "gpio", "clk_m", L(8)), */ GATE(SDMMC2, "sdmmc2", "pc_sdmmc2", L(9)), GATE(SPDIF_OUT, "spdif_out", "pc_spdif_out", L(10)), GATE(SPDIF_IN, "spdif_in", "pc_spdif_in", L(10)), GATE(I2S1, "i2s1", "pc_i2s1", L(11)), GATE(I2C1, "i2c1", "pc_i2c1", L(12)), GATE(SDMMC1, "sdmmc1", "pc_sdmmc1", L(14)), GATE(SDMMC4, "sdmmc4", "pc_sdmmc4", L(15)), GATE(PWM, "pwm", "pc_pwm", L(17)), GATE(I2S2, "i2s2", "pc_i2s2", L(18)), GATE(VI, "vi", "pc_vi", L(20)), GATE(USBD, "usbd", "clk_m", L(22)), GATE(ISP, "isp", "pc_isp", L(23)), GATE(DISP2, "disp2", "pc_disp2", L(26)), GATE(DISP1, "disp1", "pc_disp1", L(27)), GATE(HOST1X, "host1x", "pc_host1x", L(28)), GATE(VCP, "vcp", "clk_m", L(29)), GATE(I2S0, "i2s0", "pc_i2s0", L(30)), /* GATE(CACHE2, "ccache2", "clk_m", L(31)), */ /* bank H -> 32-63 */ GATE(MC, "mem", "clk_m", H(0)), /* GATE(AHBDMA, "ahbdma", "clk_m", H(1)), */ GATE(APBDMA, "apbdma", "clk_m", H(2)), GATE(KBC, "kbc", "clk_s", H(4)), /* GATE(STAT_MON, "stat_mon", "clk_s", H(5)), */ /* GATE(PMC, "pmc", "clk_s", H(6)), */ GATE(FUSE, "fuse", "clk_m", H(7)), GATE(KFUSE, "kfuse", "clk_m", H(8)), GATE(SBC1, "spi1", "pc_spi1", H(9)), GATE(NOR, "snor", "pc_snor", H(10)), /* GATE(JTAG2TBC, "jtag2tbc", "clk_m", H(11)), */ GATE(SBC2, "spi2", "pc_spi2", H(12)), GATE(SBC3, "spi3", "pc_spi3", H(14)), GATE(I2C5, "i2c5", "pc_i2c5", H(15)), GATE(DSIA, "dsia", "dsia_mux", H(16)), GATE(MIPI, "hsi", "pc_hsi", H(18)), GATE(HDMI, "hdmi", "pc_hdmi", H(19)), GATE(CSI, "csi", "pllP_out3", H(20)), GATE(I2C2, "i2c2", "pc_i2c2", H(22)), GATE(UARTC, "uartc", "pc_uartc", H(23)), GATE(MIPI_CAL, "mipi_cal", "clk_m", H(24)), GATE(EMC, "emc", "pc_emc_2x", H(25)), GATE(USB2, "usb2", "clk_m", H(26)), GATE(USB3, "usb3", "clk_m", H(27)), GATE(VDE, "vde", "pc_vde", H(29)), GATE(BSEA, "bsea", "clk_m", H(30)), GATE(BSEV, "bsev", "clk_m", H(31)), /* bank U -> 64-95 */ GATE(UARTD, "uartd", "pc_uartd", U(1)), GATE(I2C3, "i2c3", "pc_i2c3", U(3)), GATE(SBC4, "spi4", "pc_spi4", U(4)), GATE(SDMMC3, "sdmmc3", "pc_sdmmc3", U(5)), GATE(PCIE, "pcie", "clk_m", U(6)), GATE(OWR, "owr", "pc_owr", U(7)), GATE(AFI, "afi", "clk_m", U(8)), GATE(CSITE, "csite", "pc_csite", U(9)), /* GATE(AVPUCQ, "avpucq", clk_m, U(11)), */ GATE(TRACE, "traceclkin", "pc_traceclkin", U(13)), GATE(SOC_THERM, "soc_therm", "pc_soc_therm", U(14)), GATE(DTV, "dtv", "clk_m", U(15)), GATE(I2CSLOW, "i2c_slow", "pc_i2c_slow", U(17)), GATE(DSIB, "dsib", "dsib_mux", U(18)), GATE(TSEC, "tsec", "pc_tsec", U(19)), /* GATE(IRAMA, "irama", "clk_m", U(20)), */ /* GATE(IRAMB, "iramb", "clk_m", U(21)), */ /* GATE(IRAMC, "iramc", "clk_m", U(22)), */ /* GATE(IRAMD, "iramd", "clk_m", U(23)), */ /* GATE(CRAM2, "cram2", "clk_m", U(24)), */ GATE(XUSB_HOST, "xusb_core_host", "pc_xusb_core_host", U(25)), /* GATE(M_DOUBLER, "m_doubler", "clk_m", U(26)), */ GATE(MSENC, "msenc", "pc_msenc", U(27)), GATE(CSUS, "sus_out", "clk_m", U(28)), /* GATE(DEVD2_OUT, "devd2_out", "clk_m", U(29)), */ /* GATE(DEVD1_OUT, "devd1_out", "clk_m", U(30)), */ GATE(XUSB_DEV, "xusb_core_dev", "pc_xusb_core_dev", U(31)), /* bank V -> 96-127 */ /* GATE(CPUG, "cpug", "clk_m", V(0)), */ /* GATE(CPULP, "cpuLP", "clk_m", V(1)), */ GATE(MSELECT, "mselect", "pc_mselect", V(3)), GATE(TSENSOR, "tsensor", "pc_tsensor", V(4)), GATE(I2S3, "i2s3", "pc_i2s3", V(5)), GATE(I2S4, "i2s4", "pc_i2s4", V(6)), GATE(I2C4, "i2c4", "pc_i2c4", V(7)), GATE(SBC5, "spi5", "pc_spi5", V(8)), GATE(SBC6, "spi6", "pc_spi6", V(9)), GATE(D_AUDIO, "audio", "pc_audio", V(10)), GATE(APBIF, "apbif", "clk_m", V(11)), GATE(DAM0, "dam0", "pc_dam0", V(12)), GATE(DAM1, "dam1", "pc_dam1", V(13)), GATE(DAM2, "dam2", "pc_dam2", V(14)), GATE(HDA2CODEC_2X, "hda2codec_2x", "pc_hda2codec_2x", V(15)), /* GATE(ATOMICS, "atomics", "clk_m", V(16)), */ /* GATE(SPDIF_DOUBLER, "spdif_doubler", "clk_m", V(22)), */ GATE(ACTMON, "actmon", "pc_actmon", V(23)), GATE(EXTERN1, "extperiph1", "pc_extperiph1", V(24)), GATE(EXTERN2, "extperiph2", "pc_extperiph2", V(25)), GATE(EXTERN3, "extperiph3", "pc_extperiph3", V(26)), GATE(SATA_OOB, "sata_oob", "pc_sata_oob", V(27)), GATE(SATA, "sata", "pc_sata", V(28)), GATE(HDA, "hda", "pc_hda", V(29)), /* bank W -> 128-159*/ GATE(HDA2HDMI, "hda2hdmi", "clk_m", W(0)), GATE(SATA_COLD, "sata_cold", "clk_m", W(1)), /* Reset only */ /* GATE(PCIERX0, "pcierx0", "clk_m", W(2)), */ /* GATE(PCIERX1, "pcierx1", "clk_m", W(3)), */ /* GATE(PCIERX2, "pcierx2", "clk_m", W(4)), */ /* GATE(PCIERX3, "pcierx3", "clk_m", W(5)), */ /* GATE(PCIERX4, "pcierx4", "clk_m", W(6)), */ /* GATE(PCIERX5, "pcierx5", "clk_m", W(7)), */ /* GATE(CEC, "cec", "clk_m", W(8)), */ /* GATE(PCIE2_IOBIST, "pcie2_iobist", "clk_m", W(9)), */ /* GATE(EMC_IOBIST, "emc_iobist", "clk_m", W(10)), */ /* GATE(HDMI_IOBIST, "hdmi_iobist", "clk_m", W(11)), */ /* GATE(SATA_IOBIST, "sata_iobist", "clk_m", W(12)), */ /* GATE(MIPI_IOBIST, "mipi_iobist", "clk_m", W(13)), */ GATE(XUSB_GATE, "xusb_gate", "clk_m", W(15)), GATE(CILAB, "cilab", "pc_cilab", W(16)), GATE(CILCD, "cilcd", "pc_cilcd", W(17)), GATE(CILE, "cile", "pc_cile", W(18)), GATE(DSIALP, "dsia_lp", "pc_dsia_lp", W(19)), GATE(DSIBLP, "dsib_lp", "pc_dsib_lp", W(20)), GATE(ENTROPY, "entropy", "pc_entropy", W(21)), GATE(AMX, "amx", "pc_amx", W(25)), GATE(ADX, "adx", "pc_adx", W(26)), GATE(DFLL_REF, "dvfs_ref", "pc_dvfs_ref", W(27)), GATE(DFLL_SOC, "dvfs_soc", "pc_dvfs_soc", W(27)), GATE(XUSB_SS, "xusb_ss", "xusb_ss_mux", W(28)), /* GATE(EMC_LATENCY, "emc_latency", "pc_emc_latency", W(29)), */ /* bank X -> 160-191*/ /* GATE(SPARE, "spare", "clk_m", X(0)), */ /* GATE(CAM_MCLK, "CAM_MCLK", "clk_m", X(4)), */ /* GATE(CAM_MCLK2, "CAM_MCLK2", "clk_m", X(5)), */ GATE(I2C6, "i2c6", "pc_i2c6", X(6)), GATE(VIM2_CLK, "vim2_clk", "clk_m", X(11)), /* GATE(EMC_DLL, "emc_dll", "pc_emc_dll", X(14)), */ GATE(HDMI_AUDIO, "hdmi_audio", "pc_hdmi_audio", X(16)), GATE(CLK72MHZ, "clk72mhz", "pc_clk72mhz", X(17)), GATE(VIC03, "vic", "pc_vic", X(18)), GATE(ADX1, "adx1", "pc_adx1", X(20)), GATE(DPAUX, "dpaux", "clk_m", X(21)), GATE(SOR0_LVDS, "sor0", "pc_sor0", X(22)), GATE(GPU, "gpu", "osc_div_clk", X(24)), GATE(AMX1, "amx1", "pc_amx1", X(26)), }; /* Peripheral clock clock */ #define DCF_HAVE_MUX 0x0100 /* Block with multipexor */ #define DCF_HAVE_ENA 0x0200 /* Block with enable bit */ #define DCF_HAVE_DIV 0x0400 /* Block with divider */ /* Mark block with additional bits / functionality. */ #define DCF_IS_MASK 0x00FF #define DCF_IS_UART 0x0001 #define DCF_IS_VI 0x0002 #define DCF_IS_HOST1X 0x0003 #define DCF_IS_XUSB_SS 0x0004 #define DCF_IS_EMC_DLL 0x0005 #define DCF_IS_SATA 0x0006 #define DCF_IS_VIC 0x0007 #define DCF_IS_AUDIO 0x0008 #define DCF_IS_SOR0 0x0009 #define DCF_IS_EMC 0x000A /* Basic pheripheral clock */ #define PER_CLK(_id, cn, pl, r, diw, fiw, f) \ { \ .clkdef.id = _id, \ .clkdef.name = cn, \ .clkdef.parent_names = pl, \ .clkdef.parent_cnt = nitems(pl), \ .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ .base_reg = r, \ .div_width = diw, \ .div_f_width = fiw, \ .flags = f, \ } /* Mux with fractional 8.1 divider. */ #define CLK_8_1(id, cn, pl, r, f) \ PER_CLK(id, cn, pl, r, 8, 1, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV) /* Mux with fractional 16.1 divider. */ #define CLK16_1(id, cn, pl, r, f) \ PER_CLK(id, cn, pl, r, 16, 1, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV) /* Mux with integer 16bits divider. */ #define CLK16_0(id, cn, pl, r, f) \ PER_CLK(id, cn, pl, r, 16, 0, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV) /* Mux wihout divider. */ #define CLK_0_0(id, cn, pl, r, f) \ PER_CLK(id, cn, pl, r, 0, 0, (f) | DCF_HAVE_MUX) static struct periph_def periph_def[] = { CLK_8_1(0, "pc_i2s1", mux_a_N_audio1_N_p_N_clkm, CLK_SOURCE_I2S1, DCF_HAVE_ENA), CLK_8_1(0, "pc_i2s2", mux_a_N_audio2_N_p_N_clkm, CLK_SOURCE_I2S2, DCF_HAVE_ENA), CLK_8_1(0, "pc_spdif_out", mux_a_N_audio_N_p_N_clkm, CLK_SOURCE_SPDIF_OUT, 0), CLK_8_1(0, "pc_spdif_in", mux_p_c2_c_c3_m, CLK_SOURCE_SPDIF_IN, 0), CLK_8_1(0, "pc_pwm", mux_p_c2_c_c3_clks_N_clkm, CLK_SOURCE_PWM, 0), CLK_8_1(0, "pc_spi2", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI2, 0), CLK_8_1(0, "pc_spi3", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI3, 0), CLK16_0(0, "pc_i2c5", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C5, 0), CLK16_0(0, "pc_i2c1", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C1, 0), CLK_8_1(0, "pc_spi1", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI1, 0), CLK_0_0(0, "pc_disp1", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_DISP1, 0), CLK_0_0(0, "pc_disp2", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_DISP2, 0), CLK_8_1(0, "pc_isp", mux_m_c_p_a_c2_c3_clkm_c4, CLK_SOURCE_ISP, 0), CLK_8_1(0, "pc_vi", mux_m_c2_c_c3_p_N_a_c4, CLK_SOURCE_VI, DCF_IS_VI), CLK_8_1(0, "pc_sdmmc1", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC1, 0), CLK_8_1(0, "pc_sdmmc2", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC2, 0), CLK_8_1(0, "pc_sdmmc4", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC4, 0), CLK_8_1(0, "pc_vfir", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_VFIR, 0), CLK_8_1(0, "pc_hsi", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HSI, 0), CLK16_1(0, "pc_uarta", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTA, DCF_IS_UART), CLK16_1(0, "pc_uartb", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTB, DCF_IS_UART), CLK_8_1(0, "pc_host1x", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HOST1X, DCF_IS_HOST1X), CLK_8_1(0, "pc_hdmi", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_HDMI, 0), CLK16_0(0, "pc_i2c2", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C2, 0), CLK_8_1(0, "pc_emc_2x", mux_m_c_p_clkm_mud_c2_c3_cud, CLK_SOURCE_EMC, DCF_IS_EMC), CLK16_1(0, "pc_uartc", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTC, DCF_IS_UART), CLK_8_1(0, "pc_vi_sensor", mux_m_c2_c_c3_p_N_a, CLK_SOURCE_VI_SENSOR, 0), CLK_8_1(0, "pc_spi4", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI4, 0), CLK16_0(0, "pc_i2c3", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C3, 0), CLK_8_1(0, "pc_sdmmc3", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC3, 0), CLK16_1(0, "pc_uartd", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTD, DCF_IS_UART), CLK_8_1(0, "pc_vde", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_VDE, 0), CLK_8_1(0, "pc_owr", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_OWR, 0), CLK_8_1(0, "pc_snor", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_NOR, 0), CLK_8_1(0, "pc_csite", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_CSITE, 0), CLK_8_1(0, "pc_i2s0", mux_a_N_audio0_N_p_N_clkm, CLK_SOURCE_I2S0, 0), /* DTV xxx */ CLK_8_1(0, "pc_msenc", mux_m_c2_c_c3_p_N_a, CLK_SOURCE_MSENC, 0), CLK_8_1(0, "pc_tsec", mux_p_c2_c_c3_m_a_clkm, CLK_SOURCE_TSEC, 0), /* SPARE2 */ CLK_8_1(0, "pc_mselect", mux_p_c2_c_c3_m_clks_clkm, CLK_SOURCE_MSELECT, 0), CLK_8_1(0, "pc_tsensor", mux_p_c2_c_c3_clkm_N_clks, CLK_SOURCE_TSENSOR, 0), CLK_8_1(0, "pc_i2s3", mux_a_N_audio3_N_p_N_clkm, CLK_SOURCE_I2S3, DCF_HAVE_ENA), CLK_8_1(0, "pc_i2s4", mux_a_N_audio4_N_p_N_clkm, CLK_SOURCE_I2S4, DCF_HAVE_ENA), CLK16_0(0, "pc_i2c4", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C4, 0), CLK_8_1(0, "pc_spi5", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI5, 0), CLK_8_1(0, "pc_spi6", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI6, 0), CLK_8_1(0, "pc_audio", mux_sep_audio, CLK_SOURCE_AUDIO, DCF_IS_AUDIO), CLK_8_1(0, "pc_dam0", mux_sep_audio, CLK_SOURCE_DAM0, DCF_IS_AUDIO), CLK_8_1(0, "pc_dam1", mux_sep_audio, CLK_SOURCE_DAM1, DCF_IS_AUDIO), CLK_8_1(0, "pc_dam2", mux_sep_audio, CLK_SOURCE_DAM2, DCF_IS_AUDIO), CLK_8_1(0, "pc_hda2codec_2x", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HDA2CODEC_2X, 0), CLK_8_1(0, "pc_actmon", mux_p_c2_c_c3_clks_N_clkm, CLK_SOURCE_ACTMON, 0), CLK_8_1(0, "pc_extperiph1", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH1, 0), CLK_8_1(0, "pc_extperiph2", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH2, 0), CLK_8_1(0, "pc_extperiph3", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH3, 0), CLK_8_1(0, "pc_i2c_slow", mux_p_c2_c_c3_clks_N_clkm, CLK_SOURCE_I2C_SLOW, 0), /* SYS */ CLK_8_1(0, "pc_sor0", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_SOR0, DCF_IS_SOR0), CLK_8_1(0, "pc_sata_oob", mux_p_N_c_N_m_N_clkm, CLK_SOURCE_SATA_OOB, 0), CLK_8_1(0, "pc_sata", mux_p_N_c_N_m_N_clkm, CLK_SOURCE_SATA, DCF_IS_SATA), CLK_8_1(0, "pc_hda", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HDA, 0), CLK_8_1(TEGRA124_CLK_XUSB_HOST_SRC, "pc_xusb_core_host", mux_clkm_p_c2_c_c3_refre, CLK_SOURCE_XUSB_CORE_HOST, 0), CLK_8_1(TEGRA124_CLK_XUSB_FALCON_SRC, "pc_xusb_falcon", mux_clkm_p_c2_c_c3_refre, CLK_SOURCE_XUSB_FALCON, 0), CLK_8_1(TEGRA124_CLK_XUSB_FS_SRC, "pc_xusb_fs", mux_clkm_N_u48_N_p_N_u480, CLK_SOURCE_XUSB_FS, 0), CLK_8_1(TEGRA124_CLK_XUSB_DEV_SRC, "pc_xusb_core_dev", mux_clkm_p_c2_c_c3_refre, CLK_SOURCE_XUSB_CORE_DEV, 0), CLK_8_1(TEGRA124_CLK_XUSB_SS_SRC, "pc_xusb_ss", mux_clkm_refe_clks_u480_c_c2_c3_oscdiv, CLK_SOURCE_XUSB_SS, DCF_IS_XUSB_SS), CLK_8_1(0, "pc_cilab", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_CILAB, 0), CLK_8_1(0, "pc_cilcd", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_CILCD, 0), CLK_8_1(0, "pc_cile", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_CILE, 0), CLK_8_1(0, "pc_dsia_lp", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_DSIA_LP, 0), CLK_8_1(0, "pc_dsib_lp", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_DSIB_LP, 0), CLK_8_1(0, "pc_entropy", mux_p_clkm_clks_E, CLK_SOURCE_ENTROPY, 0), CLK_8_1(0, "pc_dvfs_ref", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_DVFS_REF, DCF_HAVE_ENA), CLK_8_1(0, "pc_dvfs_soc", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_DVFS_SOC, DCF_HAVE_ENA), CLK_8_1(0, "pc_traceclkin", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_TRACECLKIN, 0), CLK_8_1(0, "pc_adx", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_ADX, DCF_HAVE_ENA), CLK_8_1(0, "pc_amx", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_AMX, DCF_HAVE_ENA), CLK_8_1(0, "pc_emc_latency", mux_m_c_p_clkm_mud_c2_c3, CLK_SOURCE_EMC_LATENCY, 0), CLK_8_1(0, "pc_soc_therm", mux_m_c_p_a_c2_c3, CLK_SOURCE_SOC_THERM, 0), CLK_8_1(0, "pc_vi_sensor2", mux_m_c2_c_c3_p_N_a, CLK_SOURCE_VI_SENSOR2, 0), CLK16_0(0, "pc_i2c6", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C6, 0), CLK_8_1(0, "pc_emc_dll", mux_m_c_p_clkm_mud_c2_c3, CLK_SOURCE_EMC_DLL, DCF_IS_EMC_DLL), CLK_8_1(0, "pc_hdmi_audio", mux_p_c_c2_clkm, CLK_SOURCE_HDMI_AUDIO, 0), CLK_8_1(0, "pc_clk72mhz", mux_p_c_c2_clkm, CLK_SOURCE_CLK72MHZ, 0), CLK_8_1(0, "pc_adx1", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_ADX1, DCF_HAVE_ENA), CLK_8_1(0, "pc_amx1", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_AMX1, DCF_HAVE_ENA), CLK_8_1(0, "pc_vic", mux_m_c_p_a_c2_c3_clkm, CLK_SOURCE_VIC, DCF_IS_VIC), }; static int periph_init(struct clknode *clk, device_t dev); static int periph_recalc(struct clknode *clk, uint64_t *freq); static int periph_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout, int flags, int *stop); static int periph_set_mux(struct clknode *clk, int idx); struct periph_sc { device_t clkdev; uint32_t base_reg; uint32_t div_shift; uint32_t div_width; uint32_t div_mask; uint32_t div_f_width; uint32_t div_f_mask; uint32_t flags; uint32_t divider; int mux; }; static clknode_method_t periph_methods[] = { /* Device interface */ CLKNODEMETHOD(clknode_init, periph_init), CLKNODEMETHOD(clknode_recalc_freq, periph_recalc), CLKNODEMETHOD(clknode_set_freq, periph_set_freq), CLKNODEMETHOD(clknode_set_mux, periph_set_mux), CLKNODEMETHOD_END }; DEFINE_CLASS_1(tegra124_periph, tegra124_periph_class, periph_methods, sizeof(struct periph_sc), clknode_class); static int periph_init(struct clknode *clk, device_t dev) { struct periph_sc *sc; uint32_t reg; sc = clknode_get_softc(clk); DEVICE_LOCK(sc); if (sc->flags & DCF_HAVE_ENA) MD4(sc, sc->base_reg, PERLCK_ENA_MASK, PERLCK_ENA_MASK); RD4(sc, sc->base_reg, ®); DEVICE_UNLOCK(sc); /* Stnadard mux. */ if (sc->flags & DCF_HAVE_MUX) sc->mux = (reg >> PERLCK_MUX_SHIFT) & PERLCK_MUX_MASK; else sc->mux = 0; if (sc->flags & DCF_HAVE_DIV) sc->divider = (reg & sc->div_mask) + 2; else sc->divider = 1; if ((sc->flags & DCF_IS_MASK) == DCF_IS_UART) { if (!(reg & PERLCK_UDIV_DIS)) sc->divider = 2; } /* AUDIO MUX */ if ((sc->flags & DCF_IS_MASK) == DCF_IS_AUDIO) { if (!(reg & PERLCK_AMUX_DIS) && (sc->mux == 7)) { sc->mux = 8 + ((reg >> PERLCK_AMUX_SHIFT) & PERLCK_MUX_MASK); } } clknode_init_parent_idx(clk, sc->mux); return(0); } static int periph_set_mux(struct clknode *clk, int idx) { struct periph_sc *sc; uint32_t reg; sc = clknode_get_softc(clk); if (!(sc->flags & DCF_HAVE_MUX)) return (ENXIO); sc->mux = idx; DEVICE_LOCK(sc); RD4(sc, sc->base_reg, ®); reg &= ~(PERLCK_MUX_MASK << PERLCK_MUX_SHIFT); if ((sc->flags & DCF_IS_MASK) == DCF_IS_AUDIO) { reg &= ~PERLCK_AMUX_DIS; reg &= ~(PERLCK_MUX_MASK << PERLCK_AMUX_SHIFT); if (idx <= 7) { reg |= idx << PERLCK_MUX_SHIFT; } else { reg |= 7 << PERLCK_MUX_SHIFT; reg |= (idx - 8) << PERLCK_AMUX_SHIFT; } } else { reg |= idx << PERLCK_MUX_SHIFT; } WR4(sc, sc->base_reg, reg); DEVICE_UNLOCK(sc); return(0); } static int periph_recalc(struct clknode *clk, uint64_t *freq) { struct periph_sc *sc; uint32_t reg; sc = clknode_get_softc(clk); if (sc->flags & DCF_HAVE_DIV) { DEVICE_LOCK(sc); RD4(sc, sc->base_reg, ®); DEVICE_UNLOCK(sc); *freq = (*freq << sc->div_f_width) / sc->divider; } return (0); } static int periph_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout, int flags, int *stop) { struct periph_sc *sc; uint64_t tmp, divider; sc = clknode_get_softc(clk); if (!(sc->flags & DCF_HAVE_DIV)) { *stop = 0; return (0); } tmp = fin << sc->div_f_width; divider = tmp / *fout; if ((tmp % *fout) != 0) divider++; if (divider < (1 << sc->div_f_width)) divider = 1 << (sc->div_f_width - 1); if (flags & CLK_SET_DRYRUN) { if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) && (*fout != (tmp / divider))) return (ERANGE); } else { DEVICE_LOCK(sc); MD4(sc, sc->base_reg, sc->div_mask, (divider - (1 << sc->div_f_width))); DEVICE_UNLOCK(sc); sc->divider = divider; } *fout = tmp / divider; *stop = 1; return (0); } static int periph_register(struct clkdom *clkdom, struct periph_def *clkdef) { struct clknode *clk; struct periph_sc *sc; clk = clknode_create(clkdom, &tegra124_periph_class, &clkdef->clkdef); if (clk == NULL) return (1); sc = clknode_get_softc(clk); sc->clkdev = clknode_get_device(clk); sc->base_reg = clkdef->base_reg; sc->div_width = clkdef->div_width; sc->div_mask = (1 <div_width) - 1; sc->div_f_width = clkdef->div_f_width; sc->div_f_mask = (1 <div_f_width) - 1; sc->flags = clkdef->flags; clknode_register(clkdom, clk); return (0); } /* -------------------------------------------------------------------------- */ static int pgate_init(struct clknode *clk, device_t dev); static int pgate_set_gate(struct clknode *clk, bool enable); +static int pgate_get_gate(struct clknode *clk, bool *enableD); struct pgate_sc { device_t clkdev; uint32_t idx; uint32_t flags; uint32_t enabled; }; static clknode_method_t pgate_methods[] = { /* Device interface */ CLKNODEMETHOD(clknode_init, pgate_init), CLKNODEMETHOD(clknode_set_gate, pgate_set_gate), + CLKNODEMETHOD(clknode_get_gate, pgate_get_gate), CLKNODEMETHOD_END }; DEFINE_CLASS_1(tegra124_pgate, tegra124_pgate_class, pgate_methods, sizeof(struct pgate_sc), clknode_class); static uint32_t get_enable_reg(int idx) { KASSERT(idx / 32 < nitems(clk_enable_reg), ("Invalid clock index for enable: %d", idx)); return (clk_enable_reg[idx / 32]); } static uint32_t get_reset_reg(int idx) { KASSERT(idx / 32 < nitems(clk_reset_reg), ("Invalid clock index for reset: %d", idx)); return (clk_reset_reg[idx / 32]); } static int pgate_init(struct clknode *clk, device_t dev) { struct pgate_sc *sc; uint32_t ena_reg, rst_reg, mask; sc = clknode_get_softc(clk); mask = 1 << (sc->idx % 32); DEVICE_LOCK(sc); RD4(sc, get_enable_reg(sc->idx), &ena_reg); RD4(sc, get_reset_reg(sc->idx), &rst_reg); DEVICE_UNLOCK(sc); sc->enabled = ena_reg & mask ? 1 : 0; clknode_init_parent_idx(clk, 0); return(0); } static int pgate_set_gate(struct clknode *clk, bool enable) { struct pgate_sc *sc; uint32_t reg, mask, base_reg; sc = clknode_get_softc(clk); mask = 1 << (sc->idx % 32); sc->enabled = enable; base_reg = get_enable_reg(sc->idx); DEVICE_LOCK(sc); MD4(sc, base_reg, mask, enable ? mask : 0); RD4(sc, base_reg, ®); DEVICE_UNLOCK(sc); DELAY(2); return(0); } +static int +pgate_get_gate(struct clknode *clk, bool *enabled) +{ + struct pgate_sc *sc; + uint32_t reg, mask, base_reg; + + sc = clknode_get_softc(clk); + mask = 1 << (sc->idx % 32); + base_reg = get_enable_reg(sc->idx); + + DEVICE_LOCK(sc); + RD4(sc, base_reg, ®); + DEVICE_UNLOCK(sc); + *enabled = reg & mask ? true: false; + + return(0); +} int tegra124_hwreset_by_idx(struct tegra124_car_softc *sc, intptr_t idx, bool reset) { uint32_t reg, mask, reset_reg; mask = 1 << (idx % 32); reset_reg = get_reset_reg(idx); CLKDEV_DEVICE_LOCK(sc->dev); CLKDEV_MODIFY_4(sc->dev, reset_reg, mask, reset ? mask : 0); CLKDEV_READ_4(sc->dev, reset_reg, ®); CLKDEV_DEVICE_UNLOCK(sc->dev); return(0); } static int pgate_register(struct clkdom *clkdom, struct pgate_def *clkdef) { struct clknode *clk; struct pgate_sc *sc; clk = clknode_create(clkdom, &tegra124_pgate_class, &clkdef->clkdef); if (clk == NULL) return (1); sc = clknode_get_softc(clk); sc->clkdev = clknode_get_device(clk); sc->idx = clkdef->idx; sc->flags = clkdef->flags; clknode_register(clkdom, clk); return (0); } void tegra124_periph_clock(struct tegra124_car_softc *sc) { int i, rv; for (i = 0; i < nitems(periph_def); i++) { rv = periph_register(sc->clkdom, &periph_def[i]); if (rv != 0) panic("tegra124_periph_register failed"); } for (i = 0; i < nitems(pgate_def); i++) { rv = pgate_register(sc->clkdom, &pgate_def[i]); if (rv != 0) panic("tegra124_pgate_register failed"); } } diff --git a/sys/arm/nvidia/tegra124/tegra124_clk_pll.c b/sys/arm/nvidia/tegra124/tegra124_clk_pll.c index 82b34fd71203..d6aa55f8efe0 100644 --- a/sys/arm/nvidia/tegra124/tegra124_clk_pll.c +++ b/sys/arm/nvidia/tegra124/tegra124_clk_pll.c @@ -1,1143 +1,1158 @@ /*- * Copyright (c) 2016 Michal Meloun * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include "tegra124_car.h" /* #define TEGRA_PLL_DEBUG */ #ifdef TEGRA_PLL_DEBUG #define dprintf(...) printf(__VA_ARGS__) #else #define dprintf(...) #endif /* All PLLs. */ enum pll_type { PLL_M, PLL_X, PLL_C, PLL_C2, PLL_C3, PLL_C4, PLL_P, PLL_A, PLL_U, PLL_D, PLL_D2, PLL_DP, PLL_E, PLL_REFE}; /* Common base register bits. */ #define PLL_BASE_BYPASS (1U << 31) #define PLL_BASE_ENABLE (1 << 30) #define PLL_BASE_REFDISABLE (1 << 29) #define PLL_BASE_LOCK (1 << 27) #define PLL_BASE_DIVM_SHIFT 0 #define PLL_BASE_DIVN_SHIFT 8 #define PLLRE_MISC_LOCK (1 << 24) #define PLL_MISC_LOCK_ENABLE (1 << 18) #define PLLC_MISC_LOCK_ENABLE (1 << 24) #define PLLDU_MISC_LOCK_ENABLE (1 << 22) #define PLLRE_MISC_LOCK_ENABLE (1 << 30) #define PLLSS_MISC_LOCK_ENABLE (1 << 30) #define PLLC_IDDQ_BIT 26 #define PLLX_IDDQ_BIT 3 #define PLLRE_IDDQ_BIT 16 #define PLLSS_IDDQ_BIT 19 #define PLL_LOCK_TIMEOUT 5000 /* Post divider <-> register value mapping. */ struct pdiv_table { uint32_t divider; /* real divider */ uint32_t value; /* register value */ }; /* Bits definition of M, N and P fields. */ struct mnp_bits { uint32_t m_width; uint32_t n_width; uint32_t p_width; uint32_t p_shift; }; struct clk_pll_def { struct clknode_init_def clkdef; enum pll_type type; uint32_t base_reg; uint32_t misc_reg; uint32_t lock_mask; uint32_t lock_enable; uint32_t iddq_reg; uint32_t iddq_mask; uint32_t flags; struct pdiv_table *pdiv_table; struct mnp_bits mnp_bits; }; #define PLL(_id, cname, pname) \ .clkdef.id = _id, \ .clkdef.name = cname, \ .clkdef.parent_names = (const char *[]){pname}, \ .clkdef.parent_cnt = 1, \ .clkdef.flags = CLK_NODE_STATIC_STRINGS /* Tegra K1 PLLs PLLM: Clock source for EMC 2x clock PLLX: Clock source for the fast CPU cluster and the shadow CPU PLLC: Clock source for general use PLLC2: Clock source for engine scaling PLLC3: Clock source for engine scaling PLLC4: Clock source for ISP/VI units PLLP: Clock source for most peripherals PLLA: Audio clock sources: (11.2896 MHz, 12.288 MHz, 24.576 MHz) PLLU: Clock source for USB PHY, provides 12/60/480 MHz PLLD: Clock sources for the DSI and display subsystem PLLD2: Clock sources for the DSI and display subsystem refPLLe: PLLE: generate the 100 MHz reference clock for USB 3.0 (spread spectrum) PLLDP: Clock source for eDP/LVDS (spread spectrum) DFLLCPU: DFLL clock source for the fast CPU cluster GPCPLL: Clock source for the GPU */ static struct pdiv_table pllm_map[] = { {1, 0}, {2, 1}, {0, 0} }; static struct pdiv_table pllxc_map[] = { { 1, 0}, { 2, 1}, { 3, 2}, { 4, 3}, { 5, 4}, { 6, 5}, { 8, 6}, {10, 7}, {12, 8}, {16, 9}, {12, 10}, {16, 11}, {20, 12}, {24, 13}, {32, 14}, { 0, 0} }; static struct pdiv_table pllc_map[] = { { 1, 0}, { 2, 1}, { 3, 2}, { 4, 3}, { 6, 4}, { 8, 5}, {12, 6}, {16, 7}, { 0, 0} }; static struct pdiv_table pll12g_ssd_esd_map[] = { { 1, 0}, { 2, 1}, { 3, 2}, { 4, 3}, { 5, 4}, { 6, 5}, { 8, 6}, {10, 7}, {12, 8}, {16, 9}, {12, 10}, {16, 11}, {20, 12}, {24, 13}, {32, 14}, { 0, 0} }; static struct pdiv_table pllu_map[] = { {1, 1}, {2, 0}, {0, 0} }; static struct pdiv_table pllrefe_map[] = { {1, 0}, {2, 1}, {3, 2}, {4, 3}, {5, 4}, {6, 5}, {0, 0}, }; static struct clk_pll_def pll_clks[] = { /* PLLM: 880 MHz Clock source for EMC 2x clock */ { PLL(TEGRA124_CLK_PLL_M, "pllM_out0", "osc_div_clk"), .type = PLL_M, .base_reg = PLLM_BASE, .misc_reg = PLLM_MISC, .lock_mask = PLL_BASE_LOCK, .lock_enable = PLL_MISC_LOCK_ENABLE, .pdiv_table = pllm_map, .mnp_bits = {8, 8, 1, 20}, }, /* PLLX: 1GHz Clock source for the fast CPU cluster and the shadow CPU */ { PLL(TEGRA124_CLK_PLL_X, "pllX_out", "osc_div_clk"), .type = PLL_X, .base_reg = PLLX_BASE, .misc_reg = PLLX_MISC, .lock_mask = PLL_BASE_LOCK, .lock_enable = PLL_MISC_LOCK_ENABLE, .iddq_reg = PLLX_MISC3, .iddq_mask = 1 << PLLX_IDDQ_BIT, .pdiv_table = pllxc_map, .mnp_bits = {8, 8, 4, 20}, }, /* PLLC: 600 MHz Clock source for general use */ { PLL(TEGRA124_CLK_PLL_C, "pllC_out0", "osc_div_clk"), .type = PLL_C, .base_reg = PLLC_BASE, .misc_reg = PLLC_MISC, .lock_mask = PLL_BASE_LOCK, .lock_enable = PLLC_MISC_LOCK_ENABLE, .iddq_reg = PLLC_MISC, .iddq_mask = 1 << PLLC_IDDQ_BIT, .pdiv_table = pllc_map, .mnp_bits = {8, 8, 4, 20}, }, /* PLLC2: 600 MHz Clock source for engine scaling */ { PLL(TEGRA124_CLK_PLL_C2, "pllC2_out0", "osc_div_clk"), .type = PLL_C2, .base_reg = PLLC2_BASE, .misc_reg = PLLC2_MISC, .lock_mask = PLL_BASE_LOCK, .lock_enable = PLL_MISC_LOCK_ENABLE, .pdiv_table = pllc_map, .mnp_bits = {2, 8, 3, 20}, }, /* PLLC3: 600 MHz Clock source for engine scaling */ { PLL(TEGRA124_CLK_PLL_C3, "pllC3_out0", "osc_div_clk"), .type = PLL_C3, .base_reg = PLLC3_BASE, .misc_reg = PLLC3_MISC, .lock_mask = PLL_BASE_LOCK, .lock_enable = PLL_MISC_LOCK_ENABLE, .pdiv_table = pllc_map, .mnp_bits = {2, 8, 3, 20}, }, /* PLLC4: 600 MHz Clock source for ISP/VI units */ { PLL(TEGRA124_CLK_PLL_C4, "pllC4_out0", "pllC4_src"), .type = PLL_C4, .base_reg = PLLC4_BASE, .misc_reg = PLLC4_MISC, .lock_mask = PLL_BASE_LOCK, .lock_enable = PLLSS_MISC_LOCK_ENABLE, .iddq_reg = PLLC4_BASE, .iddq_mask = 1 << PLLSS_IDDQ_BIT, .pdiv_table = pll12g_ssd_esd_map, .mnp_bits = {8, 8, 4, 20}, }, /* PLLP: 408 MHz Clock source for most peripherals */ { PLL(TEGRA124_CLK_PLL_P, "pllP_out0", "osc_div_clk"), .type = PLL_P, .base_reg = PLLP_BASE, .misc_reg = PLLP_MISC, .lock_mask = PLL_BASE_LOCK, .lock_enable = PLL_MISC_LOCK_ENABLE, .mnp_bits = {5, 10, 3, 20}, }, /* PLLA: Audio clock sources: (11.2896 MHz, 12.288 MHz, 24.576 MHz) */ { PLL(TEGRA124_CLK_PLL_A, "pllA_out", "pllP_out1"), .type = PLL_A, .base_reg = PLLA_BASE, .misc_reg = PLLA_MISC, .lock_mask = PLL_BASE_LOCK, .lock_enable = PLL_MISC_LOCK_ENABLE, .mnp_bits = {5, 10, 3, 20}, }, /* PLLU: 480 MHz Clock source for USB PHY, provides 12/60/480 MHz */ { PLL(TEGRA124_CLK_PLL_U, "pllU_out", "osc_div_clk"), .type = PLL_U, .base_reg = PLLU_BASE, .misc_reg = PLLU_MISC, .lock_mask = PLL_BASE_LOCK, .lock_enable = PLLDU_MISC_LOCK_ENABLE, .pdiv_table = pllu_map, .mnp_bits = {5, 10, 1, 20}, }, /* PLLD: 600 MHz Clock sources for the DSI and display subsystem */ { PLL(TEGRA124_CLK_PLL_D, "pllD_out", "osc_div_clk"), .type = PLL_D, .base_reg = PLLD_BASE, .misc_reg = PLLD_MISC, .lock_mask = PLL_BASE_LOCK, .lock_enable = PLL_MISC_LOCK_ENABLE, .mnp_bits = {5, 11, 3, 20}, }, /* PLLD2: 600 MHz Clock sources for the DSI and display subsystem */ { PLL(TEGRA124_CLK_PLL_D2, "pllD2_out", "pllD2_src"), .type = PLL_D2, .base_reg = PLLD2_BASE, .misc_reg = PLLD2_MISC, .lock_mask = PLL_BASE_LOCK, .lock_enable = PLLSS_MISC_LOCK_ENABLE, .iddq_reg = PLLD2_BASE, .iddq_mask = 1 << PLLSS_IDDQ_BIT, .pdiv_table = pll12g_ssd_esd_map, .mnp_bits = {8, 8, 4, 20}, }, /* refPLLe: */ { PLL(0, "pllREFE_out", "osc_div_clk"), .type = PLL_REFE, .base_reg = PLLRE_BASE, .misc_reg = PLLRE_MISC, .lock_mask = PLLRE_MISC_LOCK, .lock_enable = PLLRE_MISC_LOCK_ENABLE, .iddq_reg = PLLRE_MISC, .iddq_mask = 1 << PLLRE_IDDQ_BIT, .pdiv_table = pllrefe_map, .mnp_bits = {8, 8, 4, 16}, }, /* PLLE: generate the 100 MHz reference clock for USB 3.0 (spread spectrum) */ { PLL(TEGRA124_CLK_PLL_E, "pllE_out0", "pllE_src"), .type = PLL_E, .base_reg = PLLE_BASE, .misc_reg = PLLE_MISC, .lock_mask = PLLE_MISC_LOCK, .lock_enable = PLLE_MISC_LOCK_ENABLE, .mnp_bits = {8, 8, 4, 24}, }, /* PLLDP: 600 MHz Clock source for eDP/LVDS (spread spectrum) */ { PLL(0, "pllDP_out0", "pllDP_src"), .type = PLL_DP, .base_reg = PLLDP_BASE, .misc_reg = PLLDP_MISC, .lock_mask = PLL_BASE_LOCK, .lock_enable = PLLSS_MISC_LOCK_ENABLE, .iddq_reg = PLLDP_BASE, .iddq_mask = 1 << PLLSS_IDDQ_BIT, .pdiv_table = pll12g_ssd_esd_map, .mnp_bits = {8, 8, 4, 20}, }, }; static int tegra124_pll_init(struct clknode *clk, device_t dev); static int tegra124_pll_set_gate(struct clknode *clk, bool enable); +static int tegra124_pll_get_gate(struct clknode *clk, bool *enabled); static int tegra124_pll_recalc(struct clknode *clk, uint64_t *freq); static int tegra124_pll_set_freq(struct clknode *clknode, uint64_t fin, uint64_t *fout, int flags, int *stop); struct pll_sc { device_t clkdev; enum pll_type type; uint32_t base_reg; uint32_t misc_reg; uint32_t lock_mask; uint32_t lock_enable; uint32_t iddq_reg; uint32_t iddq_mask; uint32_t flags; struct pdiv_table *pdiv_table; struct mnp_bits mnp_bits; }; static clknode_method_t tegra124_pll_methods[] = { /* Device interface */ CLKNODEMETHOD(clknode_init, tegra124_pll_init), CLKNODEMETHOD(clknode_set_gate, tegra124_pll_set_gate), + CLKNODEMETHOD(clknode_get_gate, tegra124_pll_get_gate), CLKNODEMETHOD(clknode_recalc_freq, tegra124_pll_recalc), CLKNODEMETHOD(clknode_set_freq, tegra124_pll_set_freq), CLKNODEMETHOD_END }; DEFINE_CLASS_1(tegra124_pll, tegra124_pll_class, tegra124_pll_methods, sizeof(struct pll_sc), clknode_class); static int pll_enable(struct pll_sc *sc) { uint32_t reg; RD4(sc, sc->base_reg, ®); if (sc->type != PLL_E) reg &= ~PLL_BASE_BYPASS; reg |= PLL_BASE_ENABLE; WR4(sc, sc->base_reg, reg); return (0); } static int pll_disable(struct pll_sc *sc) { uint32_t reg; RD4(sc, sc->base_reg, ®); if (sc->type != PLL_E) reg |= PLL_BASE_BYPASS; reg &= ~PLL_BASE_ENABLE; WR4(sc, sc->base_reg, reg); return (0); } static uint32_t pdiv_to_reg(struct pll_sc *sc, uint32_t p_div) { struct pdiv_table *tbl; tbl = sc->pdiv_table; if (tbl == NULL) return (ffs(p_div) - 1); while (tbl->divider != 0) { if (p_div <= tbl->divider) return (tbl->value); tbl++; } return (0xFFFFFFFF); } static uint32_t reg_to_pdiv(struct pll_sc *sc, uint32_t reg) { struct pdiv_table *tbl; tbl = sc->pdiv_table; if (tbl == NULL) return (1 << reg); while (tbl->divider) { if (reg == tbl->value) return (tbl->divider); tbl++; } return (0); } static uint32_t get_masked(uint32_t val, uint32_t shift, uint32_t width) { return ((val >> shift) & ((1 << width) - 1)); } static uint32_t set_masked(uint32_t val, uint32_t v, uint32_t shift, uint32_t width) { val &= ~(((1 << width) - 1) << shift); val |= (v & ((1 << width) - 1)) << shift; return (val); } static void get_divisors(struct pll_sc *sc, uint32_t *m, uint32_t *n, uint32_t *p) { uint32_t val; struct mnp_bits *mnp_bits; mnp_bits = &sc->mnp_bits; RD4(sc, sc->base_reg, &val); *m = get_masked(val, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); *n = get_masked(val, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); *p = get_masked(val, mnp_bits->p_shift, mnp_bits->p_width); } static uint32_t set_divisors(struct pll_sc *sc, uint32_t val, uint32_t m, uint32_t n, uint32_t p) { struct mnp_bits *mnp_bits; mnp_bits = &sc->mnp_bits; val = set_masked(val, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); val = set_masked(val, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); val = set_masked(val, p, mnp_bits->p_shift, mnp_bits->p_width); return (val); } static bool is_locked(struct pll_sc *sc) { uint32_t reg; switch (sc->type) { case PLL_REFE: RD4(sc, sc->misc_reg, ®); reg &= PLLRE_MISC_LOCK; break; case PLL_E: RD4(sc, sc->misc_reg, ®); reg &= PLLE_MISC_LOCK; break; default: RD4(sc, sc->base_reg, ®); reg &= PLL_BASE_LOCK; break; } return (reg != 0); } static int wait_for_lock(struct pll_sc *sc) { int i; for (i = PLL_LOCK_TIMEOUT / 10; i > 0; i--) { if (is_locked(sc)) break; DELAY(10); } if (i <= 0) { printf("PLL lock timeout\n"); return (ETIMEDOUT); } return (0); } static int plle_enable(struct pll_sc *sc) { uint32_t reg; int rv; struct mnp_bits *mnp_bits; uint32_t pll_m = 1; uint32_t pll_n = 200; uint32_t pll_p = 13; uint32_t pll_cml = 13; mnp_bits = &sc->mnp_bits; /* Disable lock override. */ RD4(sc, sc->base_reg, ®); reg &= ~PLLE_BASE_LOCK_OVERRIDE; WR4(sc, sc->base_reg, reg); RD4(sc, PLLE_AUX, ®); reg |= PLLE_AUX_ENABLE_SWCTL; reg &= ~PLLE_AUX_SEQ_ENABLE; WR4(sc, PLLE_AUX, reg); DELAY(10); RD4(sc, sc->misc_reg, ®); reg |= PLLE_MISC_LOCK_ENABLE; reg |= PLLE_MISC_IDDQ_SWCTL; reg &= ~PLLE_MISC_IDDQ_OVERRIDE_VALUE; reg |= PLLE_MISC_PTS; reg |= PLLE_MISC_VREG_BG_CTRL_MASK; reg |= PLLE_MISC_VREG_CTRL_MASK; WR4(sc, sc->misc_reg, reg); DELAY(10); RD4(sc, PLLE_SS_CNTL, ®); reg |= PLLE_SS_CNTL_DISABLE; WR4(sc, PLLE_SS_CNTL, reg); RD4(sc, sc->base_reg, ®); reg = set_divisors(sc, reg, pll_m, pll_n, pll_p); reg &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); reg |= pll_cml << PLLE_BASE_DIVCML_SHIFT; WR4(sc, sc->base_reg, reg); DELAY(10); pll_enable(sc); rv = wait_for_lock(sc); if (rv != 0) return (rv); RD4(sc, PLLE_SS_CNTL, ®); reg &= ~PLLE_SS_CNTL_SSCCENTER; reg &= ~PLLE_SS_CNTL_SSCINVERT; reg &= ~PLLE_SS_CNTL_COEFFICIENTS_MASK; reg |= PLLE_SS_CNTL_COEFFICIENTS_VAL; WR4(sc, PLLE_SS_CNTL, reg); reg &= ~PLLE_SS_CNTL_SSCBYP; reg &= ~PLLE_SS_CNTL_BYPASS_SS; WR4(sc, PLLE_SS_CNTL, reg); DELAY(10); reg &= ~PLLE_SS_CNTL_INTERP_RESET; WR4(sc, PLLE_SS_CNTL, reg); DELAY(10); /* HW control of brick pll. */ RD4(sc, sc->misc_reg, ®); reg &= ~PLLE_MISC_IDDQ_SWCTL; WR4(sc, sc->misc_reg, reg); RD4(sc, PLLE_AUX, ®); reg |= PLLE_AUX_USE_LOCKDET; reg |= PLLE_AUX_SEQ_START_STATE; reg &= ~PLLE_AUX_ENABLE_SWCTL; reg &= ~PLLE_AUX_SS_SWCTL; WR4(sc, PLLE_AUX, reg); reg |= PLLE_AUX_SEQ_START_STATE; DELAY(10); reg |= PLLE_AUX_SEQ_ENABLE; WR4(sc, PLLE_AUX, reg); RD4(sc, XUSBIO_PLL_CFG0, ®); reg |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET; reg |= XUSBIO_PLL_CFG0_SEQ_START_STATE; reg &= ~XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL; reg &= ~XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL; WR4(sc, XUSBIO_PLL_CFG0, reg); DELAY(10); reg |= XUSBIO_PLL_CFG0_SEQ_ENABLE; WR4(sc, XUSBIO_PLL_CFG0, reg); /* Enable HW control and unreset SATA PLL. */ RD4(sc, SATA_PLL_CFG0, ®); reg &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; reg &= ~SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE; reg |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET; reg &= ~SATA_PLL_CFG0_SEQ_IN_SWCTL; reg &= ~SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE; reg &= ~SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE; reg &= ~SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE; reg &= ~SATA_PLL_CFG0_SEQ_ENABLE; reg |= SATA_PLL_CFG0_SEQ_START_STATE; WR4(sc, SATA_PLL_CFG0, reg); DELAY(10); reg |= SATA_PLL_CFG0_SEQ_ENABLE; WR4(sc, SATA_PLL_CFG0, reg); /* Enable HW control of PCIe PLL. */ RD4(sc, PCIE_PLL_CFG0, ®); reg |= PCIE_PLL_CFG0_SEQ_ENABLE; WR4(sc, PCIE_PLL_CFG0, reg); return (0); } static int tegra124_pll_set_gate(struct clknode *clknode, bool enable) { int rv; struct pll_sc *sc; sc = clknode_get_softc(clknode); if (enable == 0) { rv = pll_disable(sc); return(rv); } if (sc->type == PLL_E) rv = plle_enable(sc); else rv = pll_enable(sc); return (rv); } +static int +tegra124_pll_get_gate(struct clknode *clknode, bool *enabled) +{ + uint32_t reg; + struct pll_sc *sc; + + sc = clknode_get_softc(clknode); + RD4(sc, sc->base_reg, ®); + *enabled = reg & PLL_BASE_ENABLE ? true: false; + WR4(sc, sc->base_reg, reg); + return (0); +} + static int pll_set_std(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags, uint32_t m, uint32_t n, uint32_t p) { uint32_t reg; struct mnp_bits *mnp_bits; int rv; mnp_bits = &sc->mnp_bits; if (m >= (1 << mnp_bits->m_width)) return (ERANGE); if (n >= (1 << mnp_bits->n_width)) return (ERANGE); if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width)) return (ERANGE); if (flags & CLK_SET_DRYRUN) { if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) && (*fout != (((fin / m) * n) /p))) return (ERANGE); *fout = ((fin / m) * n) /p; return (0); } pll_disable(sc); /* take pll out of IDDQ */ if (sc->iddq_reg != 0) MD4(sc, sc->iddq_reg, sc->iddq_mask, 0); RD4(sc, sc->base_reg, ®); reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, mnp_bits->p_width); WR4(sc, sc->base_reg, reg); /* Enable PLL. */ RD4(sc, sc->base_reg, ®); reg |= PLL_BASE_ENABLE; WR4(sc, sc->base_reg, reg); /* Enable lock detection. */ RD4(sc, sc->misc_reg, ®); reg |= sc->lock_enable; WR4(sc, sc->misc_reg, reg); rv = wait_for_lock(sc); if (rv != 0) { /* Disable PLL */ RD4(sc, sc->base_reg, ®); reg &= ~PLL_BASE_ENABLE; WR4(sc, sc->base_reg, reg); return (rv); } RD4(sc, sc->misc_reg, ®); pll_enable(sc); *fout = ((fin / m) * n) / p; return 0; } static int plla_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) { uint32_t m, n, p; p = 1; m = 5; n = (*fout * p * m + fin / 2)/ fin; dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); return (pll_set_std(sc, fin, fout, flags, m, n, p)); } static int pllc_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) { uint32_t m, n, p; p = 2; m = 1; n = (*fout * p * m + fin / 2)/ fin; dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); return (pll_set_std( sc, fin, fout, flags, m, n, p)); } /* * PLLD2 is used as source for pixel clock for HDMI. * We must be able to set it frequency very flexibly and * precisely (within 5% tolerance limit allowed by HDMI specs). * * For this reason, it is necessary to search the full state space. * Fortunately, thanks to early cycle terminations, performance * is within acceptable limits. */ #define PLLD2_PFD_MIN 12000000 /* 12 MHz */ #define PLLD2_PFD_MAX 38000000 /* 38 MHz */ #define PLLD2_VCO_MIN 600000000 /* 600 MHz */ #define PLLD2_VCO_MAX 1200000000 /* 1.2 GHz */ static int plld2_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) { uint32_t m, n, p; uint32_t best_m, best_n, best_p; uint64_t vco, pfd; int64_t err, best_err; struct mnp_bits *mnp_bits; struct pdiv_table *tbl; int p_idx, rv; mnp_bits = &sc->mnp_bits; tbl = sc->pdiv_table; best_err = INT64_MAX; for (p_idx = 0; tbl[p_idx].divider != 0; p_idx++) { p = tbl[p_idx].divider; /* Check constraints */ vco = *fout * p; if (vco < PLLD2_VCO_MIN) continue; if (vco > PLLD2_VCO_MAX) break; for (m = 1; m < (1 << mnp_bits->m_width); m++) { n = (*fout * p * m + fin / 2) / fin; /* Check constraints */ if (n == 0) continue; if (n >= (1 << mnp_bits->n_width)) break; vco = (fin * n) / m; if (vco > PLLD2_VCO_MAX || vco < PLLD2_VCO_MIN) continue; pfd = fin / m; if (pfd > PLLD2_PFD_MAX || vco < PLLD2_PFD_MIN) continue; /* Constraints passed, save best result */ err = *fout - vco / p; if (err < 0) err = -err; if (err < best_err) { best_err = err; best_p = p; best_m = m; best_n = n; } if (err == 0) goto done; } } done: /* * HDMI specification allows 5% pixel clock tolerance, * we will by a slightly stricter */ if (best_err > ((*fout * 100) / 4)) return (ERANGE); if (flags & CLK_SET_DRYRUN) return (0); rv = pll_set_std(sc, fin, fout, flags, best_m, best_n, best_p); /* XXXX Panic for rv == ERANGE ? */ return (rv); } static int pllrefe_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) { uint32_t m, n, p; m = 1; p = 1; n = *fout * p * m / fin; dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); return (pll_set_std(sc, fin, fout, flags, m, n, p)); } static int pllx_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) { uint32_t reg; uint32_t m, n, p; struct mnp_bits *mnp_bits; int rv; mnp_bits = &sc->mnp_bits; p = 1; m = 1; n = (*fout * p * m + fin / 2)/ fin; dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); if (m >= (1 << mnp_bits->m_width)) return (ERANGE); if (n >= (1 << mnp_bits->n_width)) return (ERANGE); if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width)) return (ERANGE); if (flags & CLK_SET_DRYRUN) { if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) && (*fout != (((fin / m) * n) /p))) return (ERANGE); *fout = ((fin / m) * n) /p; return (0); } /* PLLX doesn't have bypass, disable it first. */ RD4(sc, sc->base_reg, ®); reg &= ~PLL_BASE_ENABLE; WR4(sc, sc->base_reg, reg); /* Set PLL. */ RD4(sc, sc->base_reg, ®); reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, mnp_bits->p_width); WR4(sc, sc->base_reg, reg); RD4(sc, sc->base_reg, ®); DELAY(100); /* Enable lock detection. */ RD4(sc, sc->misc_reg, ®); reg |= sc->lock_enable; WR4(sc, sc->misc_reg, reg); /* Enable PLL. */ RD4(sc, sc->base_reg, ®); reg |= PLL_BASE_ENABLE; WR4(sc, sc->base_reg, reg); rv = wait_for_lock(sc); if (rv != 0) { /* Disable PLL */ RD4(sc, sc->base_reg, ®); reg &= ~PLL_BASE_ENABLE; WR4(sc, sc->base_reg, reg); return (rv); } RD4(sc, sc->misc_reg, ®); *fout = ((fin / m) * n) / p; return (0); } static int tegra124_pll_set_freq(struct clknode *clknode, uint64_t fin, uint64_t *fout, int flags, int *stop) { *stop = 1; int rv; struct pll_sc *sc; sc = clknode_get_softc(clknode); dprintf("%s: %s requested freq: %llu, input freq: %llu\n", __func__, clknode_get_name(clknode), *fout, fin); switch (sc->type) { case PLL_A: rv = plla_set_freq(sc, fin, fout, flags); break; case PLL_C: rv = pllc_set_freq(sc, fin, fout, flags); break; case PLL_D2: rv = plld2_set_freq(sc, fin, fout, flags); break; case PLL_REFE: rv = pllrefe_set_freq(sc, fin, fout, flags); break; case PLL_X: rv = pllx_set_freq(sc, fin, fout, flags); break; case PLL_U: if (*fout == 480000000) /* PLLU is fixed to 480 MHz */ rv = 0; else rv = ERANGE; break; default: rv = ENXIO; break; } return (rv); } static int tegra124_pll_init(struct clknode *clk, device_t dev) { struct pll_sc *sc; uint32_t reg; sc = clknode_get_softc(clk); /* If PLL is enabled, enable lock detect too. */ RD4(sc, sc->base_reg, ®); if (reg & PLL_BASE_ENABLE) { RD4(sc, sc->misc_reg, ®); reg |= sc->lock_enable; WR4(sc, sc->misc_reg, reg); } if (sc->type == PLL_REFE) { RD4(sc, sc->misc_reg, ®); reg &= ~(1 << 29); /* Diasble lock override */ WR4(sc, sc->misc_reg, reg); } clknode_init_parent_idx(clk, 0); return(0); } static int tegra124_pll_recalc(struct clknode *clk, uint64_t *freq) { struct pll_sc *sc; uint32_t m, n, p, pr; uint32_t reg, misc_reg; int locked; sc = clknode_get_softc(clk); RD4(sc, sc->base_reg, ®); RD4(sc, sc->misc_reg, &misc_reg); get_divisors(sc, &m, &n, &pr); if (sc->type != PLL_E) p = reg_to_pdiv(sc, pr); else p = 2 * (pr - 1); locked = is_locked(sc); dprintf("%s: %s (0x%08x, 0x%08x) - m: %d, n: %d, p: %d (%d): " "e: %d, r: %d, o: %d - %s\n", __func__, clknode_get_name(clk), reg, misc_reg, m, n, p, pr, (reg >> 30) & 1, (reg >> 29) & 1, (reg >> 28) & 1, locked ? "locked" : "unlocked"); if ((m == 0) || (n == 0) || (p == 0)) { *freq = 0; return (EINVAL); } *freq = ((*freq / m) * n) / p; return (0); } static int pll_register(struct clkdom *clkdom, struct clk_pll_def *clkdef) { struct clknode *clk; struct pll_sc *sc; clk = clknode_create(clkdom, &tegra124_pll_class, &clkdef->clkdef); if (clk == NULL) return (ENXIO); sc = clknode_get_softc(clk); sc->clkdev = clknode_get_device(clk); sc->type = clkdef->type; sc->base_reg = clkdef->base_reg; sc->misc_reg = clkdef->misc_reg; sc->lock_mask = clkdef->lock_mask; sc->lock_enable = clkdef->lock_enable; sc->iddq_reg = clkdef->iddq_reg; sc->iddq_mask = clkdef->iddq_mask; sc->flags = clkdef->flags; sc->pdiv_table = clkdef->pdiv_table; sc->mnp_bits = clkdef->mnp_bits; clknode_register(clkdom, clk); return (0); } static void config_utmi_pll(struct tegra124_car_softc *sc) { uint32_t reg; /* * XXX Simplified UTMIP settings for 12MHz base clock. */ #define ENABLE_DELAY_COUNT 0x02 #define STABLE_COUNT 0x2F #define ACTIVE_DELAY_COUNT 0x04 #define XTAL_FREQ_COUNT 0x76 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG2, ®); reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); reg |= UTMIP_PLL_CFG2_STABLE_COUNT(STABLE_COUNT); reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(ACTIVE_DELAY_COUNT); reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN; CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG2, reg); CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, ®); reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(ENABLE_DELAY_COUNT); reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(XTAL_FREQ_COUNT); reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN; reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP; reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg); /* Prepare UTMIP requencer. */ CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®); reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET; reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL; reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE; CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); /* Powerup UTMIP. */ CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, ®); reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg); DELAY(10); /* SW override for UTMIPLL */ CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®); reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL; reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); DELAY(10); /* HW control of UTMIPLL. */ CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®); reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE; CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); } void tegra124_init_plls(struct tegra124_car_softc *sc) { int i, rv; for (i = 0; i < nitems(pll_clks); i++) { rv = pll_register(sc->clkdom, pll_clks + i); if (rv != 0) panic("pll_register failed"); } config_utmi_pll(sc); }